2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
32 #include <drm/amdgpu_drm.h>
36 #include "amdgpu_trace.h"
38 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000)
39 #define AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT msecs_to_jiffies(2000)
43 * IBs (Indirect Buffers) and areas of GPU accessible memory where
44 * commands are stored. You can put a pointer to the IB in the
45 * command ring and the hw will fetch the commands from the IB
46 * and execute them. Generally userspace acceleration drivers
47 * produce command buffers which are send to the kernel and
48 * put in IBs for execution by the requested ring.
52 * amdgpu_ib_get - request an IB (Indirect Buffer)
54 * @adev: amdgpu_device pointer
55 * @vm: amdgpu_vm pointer
56 * @size: requested IB size
57 * @pool_type: IB pool type (delayed, immediate, direct)
58 * @ib: IB object returned
60 * Request an IB (all asics). IBs are allocated using the
62 * Returns 0 on success, error on failure.
64 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
65 unsigned size, enum amdgpu_ib_pool_type pool_type,
71 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type],
72 &ib->sa_bo, size, 256);
74 dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
78 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
79 /* flush the cache before commit the IB */
80 ib->flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC;
83 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
90 * amdgpu_ib_free - free an IB (Indirect Buffer)
92 * @adev: amdgpu_device pointer
93 * @ib: IB object to free
94 * @f: the fence SA bo need wait on for the ib alloation
96 * Free an IB (all asics).
98 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
101 amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
105 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
107 * @ring: ring index the IB is associated with
108 * @num_ibs: number of IBs to schedule
109 * @ibs: IB objects to schedule
110 * @job: job to schedule
111 * @f: fence created during this submission
113 * Schedule an IB on the associated ring (all asics).
114 * Returns 0 on success, error on failure.
116 * On SI, there are two parallel engines fed from the primary ring,
117 * the CE (Constant Engine) and the DE (Drawing Engine). Since
118 * resource descriptors have moved to memory, the CE allows you to
119 * prime the caches while the DE is updating register state so that
120 * the resource descriptors will be already in cache when the draw is
121 * processed. To accomplish this, the userspace driver submits two
122 * IBs, one for the CE and one for the DE. If there is a CE IB (called
123 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
124 * to SI there was just a DE IB.
126 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
127 struct amdgpu_ib *ibs, struct amdgpu_job *job,
128 struct dma_fence **f)
130 struct amdgpu_device *adev = ring->adev;
131 struct amdgpu_ib *ib = &ibs[0];
132 struct dma_fence *tmp = NULL;
133 bool need_ctx_switch;
134 unsigned patch_offset = ~0;
135 struct amdgpu_vm *vm;
137 uint32_t status = 0, alloc_size;
138 unsigned fence_flags = 0;
143 bool need_pipe_sync = false;
148 /* ring tests don't use a job */
151 fence_ctx = job->base.s_fence ?
152 job->base.s_fence->scheduled.context : 0;
158 if (!ring->sched.ready) {
159 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
163 if (vm && !job->vmid) {
164 dev_err(adev->dev, "VM IB without ID\n");
168 if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) &&
169 (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)) {
170 dev_err(adev->dev, "secure submissions not supported on compute rings\n");
174 alloc_size = ring->funcs->emit_frame_size + num_ibs *
175 ring->funcs->emit_ib_size;
177 r = amdgpu_ring_alloc(ring, alloc_size);
179 dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
183 need_ctx_switch = ring->current_ctx != fence_ctx;
184 if (ring->funcs->emit_pipeline_sync && job &&
185 ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) ||
186 (amdgpu_sriov_vf(adev) && need_ctx_switch) ||
187 amdgpu_vm_need_pipeline_sync(ring, job))) {
188 need_pipe_sync = true;
191 trace_amdgpu_ib_pipe_sync(job, tmp);
196 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
197 ring->funcs->emit_mem_sync(ring);
199 if (ring->funcs->emit_wave_limit &&
200 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
201 ring->funcs->emit_wave_limit(ring, true);
203 if (ring->funcs->insert_start)
204 ring->funcs->insert_start(ring);
207 r = amdgpu_vm_flush(ring, job, need_pipe_sync);
209 amdgpu_ring_undo(ring);
214 if (job && ring->funcs->init_cond_exec)
215 patch_offset = amdgpu_ring_init_cond_exec(ring);
217 amdgpu_device_flush_hdp(adev, ring);
220 status |= AMDGPU_HAVE_CTX_SWITCH;
222 if (job && ring->funcs->emit_cntxcntl) {
223 status |= job->preamble_status;
224 status |= job->preemption_status;
225 amdgpu_ring_emit_cntxcntl(ring, status);
228 /* Setup initial TMZiness and send it off.
231 if (job && ring->funcs->emit_frame_cntl) {
232 secure = ib->flags & AMDGPU_IB_FLAGS_SECURE;
233 amdgpu_ring_emit_frame_cntl(ring, true, secure);
236 for (i = 0; i < num_ibs; ++i) {
239 if (job && ring->funcs->emit_frame_cntl) {
240 if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) {
241 amdgpu_ring_emit_frame_cntl(ring, false, secure);
243 amdgpu_ring_emit_frame_cntl(ring, true, secure);
247 amdgpu_ring_emit_ib(ring, job, ib, status);
248 status &= ~AMDGPU_HAVE_CTX_SWITCH;
251 if (job && ring->funcs->emit_frame_cntl)
252 amdgpu_ring_emit_frame_cntl(ring, false, secure);
254 amdgpu_device_invalidate_hdp(adev, ring);
256 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
257 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
259 /* wrap the last IB with fence */
260 if (job && job->uf_addr) {
261 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
262 fence_flags | AMDGPU_FENCE_FLAG_64BIT);
265 r = amdgpu_fence_emit(ring, f, job, fence_flags);
267 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
268 if (job && job->vmid)
269 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid);
270 amdgpu_ring_undo(ring);
274 if (ring->funcs->insert_end)
275 ring->funcs->insert_end(ring);
277 if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
278 amdgpu_ring_patch_cond_exec(ring, patch_offset);
280 ring->current_ctx = fence_ctx;
281 if (vm && ring->funcs->emit_switch_buffer)
282 amdgpu_ring_emit_switch_buffer(ring);
284 if (ring->funcs->emit_wave_limit &&
285 ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
286 ring->funcs->emit_wave_limit(ring, false);
288 amdgpu_ring_commit(ring);
293 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
295 * @adev: amdgpu_device pointer
297 * Initialize the suballocator to manage a pool of memory
298 * for use as IBs (all asics).
299 * Returns 0 on success, error on failure.
301 int amdgpu_ib_pool_init(struct amdgpu_device *adev)
305 if (adev->ib_pool_ready)
308 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
309 r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i],
311 AMDGPU_GPU_PAGE_SIZE,
312 AMDGPU_GEM_DOMAIN_GTT);
316 adev->ib_pool_ready = true;
322 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]);
327 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
329 * @adev: amdgpu_device pointer
331 * Tear down the suballocator managing the pool of memory
332 * for use as IBs (all asics).
334 void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
338 if (!adev->ib_pool_ready)
341 for (i = 0; i < AMDGPU_IB_POOL_MAX; i++)
342 amdgpu_sa_bo_manager_fini(adev, &adev->ib_pools[i]);
343 adev->ib_pool_ready = false;
347 * amdgpu_ib_ring_tests - test IBs on the rings
349 * @adev: amdgpu_device pointer
351 * Test an IB (Indirect Buffer) on each ring.
352 * If the test fails, disable the ring.
353 * Returns 0 on success, error if the primary GFX ring
356 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
358 long tmo_gfx, tmo_mm;
362 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT;
363 if (amdgpu_sriov_vf(adev)) {
364 /* for MM engines in hypervisor side they are not scheduled together
365 * with CP and SDMA engines, so even in exclusive mode MM engine could
366 * still running on other VF thus the IB TEST TIMEOUT for MM engines
367 * under SR-IOV should be set to a long time. 8 sec should be enough
368 * for the MM comes back to this VF.
370 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT;
373 if (amdgpu_sriov_runtime(adev)) {
374 /* for CP & SDMA engines since they are scheduled together so
375 * need to make the timeout width enough to cover the time
376 * cost waiting for it coming back under RUNTIME only
378 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT;
379 } else if (adev->gmc.xgmi.hive_id) {
380 tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT;
383 for (i = 0; i < adev->num_rings; ++i) {
384 struct amdgpu_ring *ring = adev->rings[i];
387 /* KIQ rings don't have an IB test because we never submit IBs
388 * to them and they have no interrupt support.
390 if (!ring->sched.ready || !ring->funcs->test_ib)
393 /* MM engine need more time */
394 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
395 ring->funcs->type == AMDGPU_RING_TYPE_VCE ||
396 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||
397 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||
398 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
399 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
404 r = amdgpu_ring_test_ib(ring, tmo);
406 DRM_DEV_DEBUG(adev->dev, "ib test on %s succeeded\n",
411 ring->sched.ready = false;
412 DRM_DEV_ERROR(adev->dev, "IB test failed on %s (%d).\n",
415 if (ring == &adev->gfx.gfx_ring[0]) {
416 /* oh, oh, that's really bad */
417 adev->accel_working = false;
430 #if defined(CONFIG_DEBUG_FS)
432 static int amdgpu_debugfs_sa_info_show(struct seq_file *m, void *unused)
434 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
436 seq_printf(m, "--------------------- DELAYED --------------------- \n");
437 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED],
439 seq_printf(m, "-------------------- IMMEDIATE -------------------- \n");
440 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE],
442 seq_printf(m, "--------------------- DIRECT ---------------------- \n");
443 amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT], m);
448 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_sa_info);
452 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
454 #if defined(CONFIG_DEBUG_FS)
455 struct drm_minor *minor = adev_to_drm(adev)->primary;
456 struct dentry *root = minor->debugfs_root;
458 debugfs_create_file("amdgpu_sa_info", 0444, root, adev,
459 &amdgpu_debugfs_sa_info_fops);