2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
32 #include <drm/amdgpu_drm.h>
36 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000)
40 * IBs (Indirect Buffers) and areas of GPU accessible memory where
41 * commands are stored. You can put a pointer to the IB in the
42 * command ring and the hw will fetch the commands from the IB
43 * and execute them. Generally userspace acceleration drivers
44 * produce command buffers which are send to the kernel and
45 * put in IBs for execution by the requested ring.
47 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
50 * amdgpu_ib_get - request an IB (Indirect Buffer)
52 * @ring: ring index the IB is associated with
53 * @size: requested IB size
54 * @ib: IB object returned
56 * Request an IB (all asics). IBs are allocated using the
58 * Returns 0 on success, error on failure.
60 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
61 unsigned size, struct amdgpu_ib *ib)
66 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
67 &ib->sa_bo, size, 256);
69 dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
73 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
76 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
83 * amdgpu_ib_free - free an IB (Indirect Buffer)
85 * @adev: amdgpu_device pointer
86 * @ib: IB object to free
87 * @f: the fence SA bo need wait on for the ib alloation
89 * Free an IB (all asics).
91 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
94 amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
98 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
100 * @adev: amdgpu_device pointer
101 * @num_ibs: number of IBs to schedule
102 * @ibs: IB objects to schedule
103 * @f: fence created during this submission
105 * Schedule an IB on the associated ring (all asics).
106 * Returns 0 on success, error on failure.
108 * On SI, there are two parallel engines fed from the primary ring,
109 * the CE (Constant Engine) and the DE (Drawing Engine). Since
110 * resource descriptors have moved to memory, the CE allows you to
111 * prime the caches while the DE is updating register state so that
112 * the resource descriptors will be already in cache when the draw is
113 * processed. To accomplish this, the userspace driver submits two
114 * IBs, one for the CE and one for the DE. If there is a CE IB (called
115 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
116 * to SI there was just a DE IB.
118 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
119 struct amdgpu_ib *ibs, struct amdgpu_job *job,
120 struct dma_fence **f)
122 struct amdgpu_device *adev = ring->adev;
123 struct amdgpu_ib *ib = &ibs[0];
124 struct dma_fence *tmp = NULL;
125 bool skip_preamble, need_ctx_switch;
126 unsigned patch_offset = ~0;
127 struct amdgpu_vm *vm;
129 uint32_t status = 0, alloc_size;
133 bool need_pipe_sync = false;
138 /* ring tests don't use a job */
141 fence_ctx = job->fence_ctx;
148 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
152 if (vm && !job->vmid) {
153 dev_err(adev->dev, "VM IB without ID\n");
157 alloc_size = ring->funcs->emit_frame_size + num_ibs *
158 ring->funcs->emit_ib_size;
160 r = amdgpu_ring_alloc(ring, alloc_size);
162 dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
166 if (ring->funcs->emit_pipeline_sync && job &&
167 ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
168 amdgpu_vm_need_pipeline_sync(ring, job))) {
169 need_pipe_sync = true;
173 if (ring->funcs->insert_start)
174 ring->funcs->insert_start(ring);
177 r = amdgpu_vm_flush(ring, job, need_pipe_sync);
179 amdgpu_ring_undo(ring);
184 if (job && ring->funcs->init_cond_exec)
185 patch_offset = amdgpu_ring_init_cond_exec(ring);
188 if (!(adev->flags & AMD_IS_APU))
191 if (ring->funcs->emit_hdp_flush)
192 amdgpu_ring_emit_hdp_flush(ring);
194 amdgpu_asic_flush_hdp(adev, ring);
197 skip_preamble = ring->current_ctx == fence_ctx;
198 need_ctx_switch = ring->current_ctx != fence_ctx;
199 if (job && ring->funcs->emit_cntxcntl) {
201 status |= AMDGPU_HAVE_CTX_SWITCH;
202 status |= job->preamble_status;
204 amdgpu_ring_emit_cntxcntl(ring, status);
207 for (i = 0; i < num_ibs; ++i) {
210 /* drop preamble IBs if we don't have a context switch */
211 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
213 !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
214 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
217 amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0,
219 need_ctx_switch = false;
222 if (ring->funcs->emit_tmz)
223 amdgpu_ring_emit_tmz(ring, false);
226 if (!(adev->flags & AMD_IS_APU))
228 amdgpu_asic_invalidate_hdp(adev, ring);
230 r = amdgpu_fence_emit(ring, f);
232 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
233 if (job && job->vmid)
234 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid);
235 amdgpu_ring_undo(ring);
239 if (ring->funcs->insert_end)
240 ring->funcs->insert_end(ring);
242 /* wrap the last IB with fence */
243 if (job && job->uf_addr) {
244 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
245 AMDGPU_FENCE_FLAG_64BIT);
248 if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
249 amdgpu_ring_patch_cond_exec(ring, patch_offset);
251 ring->current_ctx = fence_ctx;
252 if (vm && ring->funcs->emit_switch_buffer)
253 amdgpu_ring_emit_switch_buffer(ring);
254 amdgpu_ring_commit(ring);
259 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
261 * @adev: amdgpu_device pointer
263 * Initialize the suballocator to manage a pool of memory
264 * for use as IBs (all asics).
265 * Returns 0 on success, error on failure.
267 int amdgpu_ib_pool_init(struct amdgpu_device *adev)
271 if (adev->ib_pool_ready) {
274 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
275 AMDGPU_IB_POOL_SIZE*64*1024,
276 AMDGPU_GPU_PAGE_SIZE,
277 AMDGPU_GEM_DOMAIN_GTT);
282 adev->ib_pool_ready = true;
283 if (amdgpu_debugfs_sa_init(adev)) {
284 dev_err(adev->dev, "failed to register debugfs file for SA\n");
290 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
292 * @adev: amdgpu_device pointer
294 * Tear down the suballocator managing the pool of memory
295 * for use as IBs (all asics).
297 void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
299 if (adev->ib_pool_ready) {
300 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
301 adev->ib_pool_ready = false;
306 * amdgpu_ib_ring_tests - test IBs on the rings
308 * @adev: amdgpu_device pointer
310 * Test an IB (Indirect Buffer) on each ring.
311 * If the test fails, disable the ring.
312 * Returns 0 on success, error if the primary GFX ring
315 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
319 long tmo_gfx, tmo_mm;
321 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT;
322 if (amdgpu_sriov_vf(adev)) {
323 /* for MM engines in hypervisor side they are not scheduled together
324 * with CP and SDMA engines, so even in exclusive mode MM engine could
325 * still running on other VF thus the IB TEST TIMEOUT for MM engines
326 * under SR-IOV should be set to a long time. 8 sec should be enough
327 * for the MM comes back to this VF.
329 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT;
332 if (amdgpu_sriov_runtime(adev)) {
333 /* for CP & SDMA engines since they are scheduled together so
334 * need to make the timeout width enough to cover the time
335 * cost waiting for it coming back under RUNTIME only
337 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT;
340 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
341 struct amdgpu_ring *ring = adev->rings[i];
344 if (!ring || !ring->ready)
347 /* MM engine need more time */
348 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
349 ring->funcs->type == AMDGPU_RING_TYPE_VCE ||
350 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||
351 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||
352 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
357 r = amdgpu_ring_test_ib(ring, tmo);
361 if (ring == &adev->gfx.gfx_ring[0]) {
362 /* oh, oh, that's really bad */
363 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
364 adev->accel_working = false;
368 /* still not good, but we can live with it */
369 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
380 #if defined(CONFIG_DEBUG_FS)
382 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
384 struct drm_info_node *node = (struct drm_info_node *) m->private;
385 struct drm_device *dev = node->minor->dev;
386 struct amdgpu_device *adev = dev->dev_private;
388 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
394 static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
395 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
400 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
402 #if defined(CONFIG_DEBUG_FS)
403 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);