2 * Copyright 2018 Advanced Micro Devices, Inc.
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27 #include <linux/io-64-nonatomic-lo-hi.h>
29 #include <asm/hypervisor.h>
33 #include "amdgpu_gmc.h"
34 #include "amdgpu_ras.h"
35 #include "amdgpu_xgmi.h"
37 #include <drm/drm_drv.h>
40 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0
42 * @adev: amdgpu_device pointer
44 * Allocate video memory for pdb0 and map it for CPU access
45 * Returns 0 for success, error for failure.
47 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev)
50 struct amdgpu_bo_param bp;
51 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
52 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21;
53 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift;
55 memset(&bp, 0, sizeof(bp));
56 bp.size = PAGE_ALIGN((npdes + 1) * 8);
57 bp.byte_align = PAGE_SIZE;
58 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
59 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
60 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
61 bp.type = ttm_bo_type_kernel;
63 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
65 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo);
69 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false);
71 goto bo_reserve_failure;
73 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM);
76 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0);
80 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
84 amdgpu_bo_unpin(adev->gmc.pdb0_bo);
86 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
88 amdgpu_bo_unref(&adev->gmc.pdb0_bo);
93 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
95 * @bo: the BO to get the PDE for
96 * @level: the level in the PD hirarchy
97 * @addr: resulting addr
98 * @flags: resulting flags
100 * Get the address and flags to be used for a PDE (Page Directory Entry).
102 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
103 uint64_t *addr, uint64_t *flags)
105 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
107 switch (bo->tbo.resource->mem_type) {
109 *addr = bo->tbo.ttm->dma_address[0];
112 *addr = amdgpu_bo_gpu_offset(bo);
118 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource);
119 amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
123 * amdgpu_gmc_pd_addr - return the address of the root directory
125 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
127 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
130 /* TODO: move that into ASIC specific code */
131 if (adev->asic_type >= CHIP_VEGA10) {
132 uint64_t flags = AMDGPU_PTE_VALID;
134 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
137 pd_addr = amdgpu_bo_gpu_offset(bo);
143 * amdgpu_gmc_set_pte_pde - update the page tables using CPU
145 * @adev: amdgpu_device pointer
146 * @cpu_pt_addr: cpu address of the page table
147 * @gpu_page_idx: entry in the page table to update
148 * @addr: dst addr to write into pte/pde
149 * @flags: access flags
151 * Update the page tables using CPU.
153 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
154 uint32_t gpu_page_idx, uint64_t addr,
157 void __iomem *ptr = (void *)cpu_pt_addr;
161 * The following is for PTE only. GART does not have PDEs.
163 value = addr & 0x0000FFFFFFFFF000ULL;
165 writeq(value, ptr + (gpu_page_idx * 8));
171 * amdgpu_gmc_agp_addr - return the address in the AGP address space
173 * @bo: TTM BO which needs the address, must be in GTT domain
175 * Tries to figure out how to access the BO through the AGP aperture. Returns
176 * AMDGPU_BO_INVALID_OFFSET if that is not possible.
178 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
180 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
182 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)
183 return AMDGPU_BO_INVALID_OFFSET;
185 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
186 return AMDGPU_BO_INVALID_OFFSET;
188 return adev->gmc.agp_start + bo->ttm->dma_address[0];
192 * amdgpu_gmc_vram_location - try to find VRAM location
194 * @adev: amdgpu device structure holding all necessary information
195 * @mc: memory controller structure holding memory information
196 * @base: base address at which to put VRAM
198 * Function will try to place VRAM at base address provided
201 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
204 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
206 mc->vram_start = base;
207 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
208 if (limit && limit < mc->real_vram_size)
209 mc->real_vram_size = limit;
211 if (mc->xgmi.num_physical_nodes == 0) {
212 mc->fb_start = mc->vram_start;
213 mc->fb_end = mc->vram_end;
215 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
216 mc->mc_vram_size >> 20, mc->vram_start,
217 mc->vram_end, mc->real_vram_size >> 20);
220 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture
222 * @adev: amdgpu device structure holding all necessary information
223 * @mc: memory controller structure holding memory information
225 * This function is only used if use GART for FB translation. In such
226 * case, we use sysvm aperture (vmid0 page tables) for both vram
227 * and gart (aka system memory) access.
229 * GPUVM (and our organization of vmid0 page tables) require sysvm
230 * aperture to be placed at a location aligned with 8 times of native
231 * page size. For example, if vm_context0_cntl.page_table_block_size
232 * is 12, then native page size is 8G (2M*2^12), sysvm should start
233 * with a 64G aligned address. For simplicity, we just put sysvm at
234 * address 0. So vram start at address 0 and gart is right after vram.
236 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
238 u64 hive_vram_start = 0;
239 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1;
240 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id;
241 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1;
242 mc->gart_start = hive_vram_end + 1;
243 mc->gart_end = mc->gart_start + mc->gart_size - 1;
244 mc->fb_start = hive_vram_start;
245 mc->fb_end = hive_vram_end;
246 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
247 mc->mc_vram_size >> 20, mc->vram_start,
248 mc->vram_end, mc->real_vram_size >> 20);
249 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
250 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
254 * amdgpu_gmc_gart_location - try to find GART location
256 * @adev: amdgpu device structure holding all necessary information
257 * @mc: memory controller structure holding memory information
259 * Function will place try to place GART before or after VRAM.
260 * If GART size is bigger than space left then we ajust GART size.
261 * Thus function will never fails.
263 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
265 const uint64_t four_gb = 0x100000000ULL;
266 u64 size_af, size_bf;
267 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
268 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
270 /* VCE doesn't like it when BOs cross a 4GB segment, so align
271 * the GART base on a 4GB boundary as well.
273 size_bf = mc->fb_start;
274 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
276 if (mc->gart_size > max(size_bf, size_af)) {
277 dev_warn(adev->dev, "limiting GART\n");
278 mc->gart_size = max(size_bf, size_af);
281 if ((size_bf >= mc->gart_size && size_bf < size_af) ||
282 (size_af < mc->gart_size))
285 mc->gart_start = max_mc_address - mc->gart_size + 1;
287 mc->gart_start &= ~(four_gb - 1);
288 mc->gart_end = mc->gart_start + mc->gart_size - 1;
289 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
290 mc->gart_size >> 20, mc->gart_start, mc->gart_end);
294 * amdgpu_gmc_agp_location - try to find AGP location
295 * @adev: amdgpu device structure holding all necessary information
296 * @mc: memory controller structure holding memory information
298 * Function will place try to find a place for the AGP BAR in the MC address
301 * AGP BAR will be assigned the largest available hole in the address space.
302 * Should be called after VRAM and GART locations are setup.
304 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
306 const uint64_t sixteen_gb = 1ULL << 34;
307 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
308 u64 size_af, size_bf;
310 if (amdgpu_sriov_vf(adev)) {
311 mc->agp_start = 0xffffffffffff;
318 if (mc->fb_start > mc->gart_start) {
319 size_bf = (mc->fb_start & sixteen_gb_mask) -
320 ALIGN(mc->gart_end + 1, sixteen_gb);
321 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb);
323 size_bf = mc->fb_start & sixteen_gb_mask;
324 size_af = (mc->gart_start & sixteen_gb_mask) -
325 ALIGN(mc->fb_end + 1, sixteen_gb);
328 if (size_bf > size_af) {
329 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask;
330 mc->agp_size = size_bf;
332 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb);
333 mc->agp_size = size_af;
336 mc->agp_end = mc->agp_start + mc->agp_size - 1;
337 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
338 mc->agp_size >> 20, mc->agp_start, mc->agp_end);
342 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid
344 * @addr: 48 bit physical address, page aligned (36 significant bits)
345 * @pasid: 16 bit process address space identifier
347 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid)
349 return addr << 4 | pasid;
353 * amdgpu_gmc_filter_faults - filter VM faults
355 * @adev: amdgpu device structure
356 * @ih: interrupt ring that the fault received from
357 * @addr: address of the VM fault
358 * @pasid: PASID of the process causing the fault
359 * @timestamp: timestamp of the fault
362 * True if the fault was filtered and should not be processed further.
363 * False if the fault is a new one and needs to be handled.
365 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
366 struct amdgpu_ih_ring *ih, uint64_t addr,
367 uint16_t pasid, uint64_t timestamp)
369 struct amdgpu_gmc *gmc = &adev->gmc;
370 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid);
371 struct amdgpu_gmc_fault *fault;
374 /* Stale retry fault if timestamp goes backward */
375 if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp))
378 /* If we don't have space left in the ring buffer return immediately */
379 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
380 AMDGPU_GMC_FAULT_TIMEOUT;
381 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
384 /* Try to find the fault in the hash */
385 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
386 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
387 while (fault->timestamp >= stamp) {
390 if (atomic64_read(&fault->key) == key)
393 tmp = fault->timestamp;
394 fault = &gmc->fault_ring[fault->next];
396 /* Check if the entry was reused */
397 if (fault->timestamp >= tmp)
401 /* Add the fault to the ring */
402 fault = &gmc->fault_ring[gmc->last_fault];
403 atomic64_set(&fault->key, key);
404 fault->timestamp = timestamp;
406 /* And update the hash */
407 fault->next = gmc->fault_hash[hash].idx;
408 gmc->fault_hash[hash].idx = gmc->last_fault++;
413 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
415 * @adev: amdgpu device structure
416 * @addr: address of the VM fault
417 * @pasid: PASID of the process causing the fault
419 * Remove the address from fault filter, then future vm fault on this address
420 * will pass to retry fault handler to recover.
422 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
425 struct amdgpu_gmc *gmc = &adev->gmc;
426 uint64_t key = amdgpu_gmc_fault_key(addr, pasid);
427 struct amdgpu_gmc_fault *fault;
431 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
432 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
434 if (atomic64_cmpxchg(&fault->key, key, 0) == key)
437 tmp = fault->timestamp;
438 fault = &gmc->fault_ring[fault->next];
439 } while (fault->timestamp < tmp);
442 int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev)
444 if (!adev->gmc.xgmi.connected_to_cpu) {
445 adev->gmc.xgmi.ras = &xgmi_ras;
446 amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block);
447 adev->gmc.xgmi.ras_if = &adev->gmc.xgmi.ras->ras_block.ras_comm;
453 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
458 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
464 * The latest engine allocation on gfx9/10 is:
465 * Engine 2, 3: firmware
466 * Engine 0, 1, 4~16: amdgpu ring,
467 * subject to change when ring number changes
468 * Engine 17: Gart flushes
470 #define GFXHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3
471 #define MMHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3
473 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
475 struct amdgpu_ring *ring;
476 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
477 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
478 GFXHUB_FREE_VM_INV_ENGS_BITMAP};
480 unsigned vmhub, inv_eng;
482 for (i = 0; i < adev->num_rings; ++i) {
483 ring = adev->rings[i];
484 vmhub = ring->funcs->vmhub;
486 if (ring == &adev->mes.ring)
489 inv_eng = ffs(vm_inv_engs[vmhub]);
491 dev_err(adev->dev, "no VM inv eng for ring %s\n",
496 ring->vm_inv_eng = inv_eng - 1;
497 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
499 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
500 ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
507 * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ
508 * @adev: amdgpu_device pointer
510 * Check and set if an the device @adev supports Trusted Memory
513 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
515 switch (adev->ip_versions[GC_HWIP][0]) {
517 case IP_VERSION(9, 2, 2):
518 case IP_VERSION(9, 1, 0):
519 /* RENOIR looks like RAVEN */
520 case IP_VERSION(9, 3, 0):
522 case IP_VERSION(10, 3, 7):
523 if (amdgpu_tmz == 0) {
524 adev->gmc.tmz_enabled = false;
526 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n");
528 adev->gmc.tmz_enabled = true;
530 "Trusted Memory Zone (TMZ) feature enabled\n");
533 case IP_VERSION(10, 1, 10):
534 case IP_VERSION(10, 1, 1):
535 case IP_VERSION(10, 1, 2):
536 case IP_VERSION(10, 1, 3):
537 case IP_VERSION(10, 3, 0):
538 case IP_VERSION(10, 3, 2):
539 case IP_VERSION(10, 3, 4):
540 case IP_VERSION(10, 3, 5):
542 case IP_VERSION(10, 3, 1):
544 case IP_VERSION(10, 3, 3):
545 /* Don't enable it by default yet.
547 if (amdgpu_tmz < 1) {
548 adev->gmc.tmz_enabled = false;
550 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n");
552 adev->gmc.tmz_enabled = true;
554 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n");
558 adev->gmc.tmz_enabled = false;
560 "Trusted Memory Zone (TMZ) feature not supported\n");
566 * amdgpu_gmc_noretry_set -- set per asic noretry defaults
567 * @adev: amdgpu_device pointer
569 * Set a per asic default for the no-retry parameter.
572 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)
574 struct amdgpu_gmc *gmc = &adev->gmc;
576 switch (adev->ip_versions[GC_HWIP][0]) {
577 case IP_VERSION(9, 0, 1):
578 case IP_VERSION(9, 3, 0):
579 case IP_VERSION(9, 4, 0):
580 case IP_VERSION(9, 4, 1):
581 case IP_VERSION(9, 4, 2):
582 case IP_VERSION(10, 3, 3):
583 case IP_VERSION(10, 3, 4):
584 case IP_VERSION(10, 3, 5):
585 case IP_VERSION(10, 3, 6):
586 case IP_VERSION(10, 3, 7):
588 * noretry = 0 will cause kfd page fault tests fail
589 * for some ASICs, so set default to 1 for these ASICs.
591 if (amdgpu_noretry == -1)
594 gmc->noretry = amdgpu_noretry;
597 /* Raven currently has issues with noretry
598 * regardless of what we decide for other
599 * asics, we should leave raven with
600 * noretry = 0 until we root cause the
603 * default this to 0 for now, but we may want
604 * to change this in the future for certain
605 * GPUs as it can increase performance in
608 if (amdgpu_noretry == -1)
611 gmc->noretry = amdgpu_noretry;
616 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
619 struct amdgpu_vmhub *hub;
622 hub = &adev->vmhub[hub_type];
623 for (i = 0; i < 16; i++) {
624 reg = hub->vm_context0_cntl + hub->ctx_distance * i;
626 tmp = (hub_type == AMDGPU_GFXHUB_0) ?
627 RREG32_SOC15_IP(GC, reg) :
628 RREG32_SOC15_IP(MMHUB, reg);
631 tmp |= hub->vm_cntx_cntl_vm_fault;
633 tmp &= ~hub->vm_cntx_cntl_vm_fault;
635 (hub_type == AMDGPU_GFXHUB_0) ?
636 WREG32_SOC15_IP(GC, reg, tmp) :
637 WREG32_SOC15_IP(MMHUB, reg, tmp);
641 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
646 * Some ASICs need to reserve a region of video memory to avoid access
649 adev->mman.stolen_reserved_offset = 0;
650 adev->mman.stolen_reserved_size = 0;
654 * Currently there is a bug where some memory client outside
655 * of the driver writes to first 8M of VRAM on S3 resume,
656 * this overrides GART which by default gets placed in first 8M and
657 * causes VM_FAULTS once GTT is accessed.
658 * Keep the stolen memory reservation until the while this is not solved.
660 switch (adev->asic_type) {
662 adev->mman.keep_stolen_vga_memory = true;
664 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area.
667 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) {
668 adev->mman.stolen_reserved_offset = 0x500000;
669 adev->mman.stolen_reserved_size = 0x200000;
675 adev->mman.keep_stolen_vga_memory = true;
677 case CHIP_YELLOW_CARP:
678 if (amdgpu_discovery == 0) {
679 adev->mman.stolen_reserved_offset = 0x1ffb0000;
680 adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;
684 adev->mman.keep_stolen_vga_memory = false;
688 if (amdgpu_sriov_vf(adev) ||
689 !amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE)) {
692 size = amdgpu_gmc_get_vbios_fb_size(adev);
694 if (adev->mman.keep_stolen_vga_memory)
695 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION);
698 /* set to 0 if the pre-OS buffer uses up most of vram */
699 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
702 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) {
703 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION;
704 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size;
706 adev->mman.stolen_vga_size = size;
707 adev->mman.stolen_extended_size = 0;
712 * amdgpu_gmc_init_pdb0 - initialize PDB0
714 * @adev: amdgpu_device pointer
716 * This function is only used when GART page table is used
717 * for FB address translatioin. In such a case, we construct
718 * a 2-level system VM page table: PDB0->PTB, to cover both
719 * VRAM of the hive and system memory.
721 * PDB0 is static, initialized once on driver initialization.
722 * The first n entries of PDB0 are used as PTE by setting
723 * P bit to 1, pointing to VRAM. The n+1'th entry points
724 * to a big PTB covering system memory.
727 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
730 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW?
731 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M
733 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
734 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;
735 u64 vram_addr = adev->vm_manager.vram_base_offset -
736 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
737 u64 vram_end = vram_addr + vram_size;
738 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);
741 if (!drm_dev_enter(adev_to_drm(adev), &idx))
744 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
745 flags |= AMDGPU_PTE_WRITEABLE;
746 flags |= AMDGPU_PTE_SNOOPED;
747 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));
748 flags |= AMDGPU_PDE_PTE;
750 /* The first n PDE0 entries are used as PTE,
753 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size)
754 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags);
756 /* The n+1'th PDE0 entry points to a huge
757 * PTB who has more than 512 entries each
758 * pointing to a 4K system page
760 flags = AMDGPU_PTE_VALID;
761 flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED;
762 /* Requires gart_ptb_gpu_pa to be 4K aligned */
763 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);
768 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC
771 * @adev: amdgpu_device pointer
772 * @mc_addr: MC address of buffer
774 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr)
776 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
780 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from
783 * @adev: amdgpu_device pointer
784 * @bo: amdgpu buffer object
786 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
788 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo));
792 * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address
795 * @adev: amdgpu_device pointer
796 * @bo: amdgpu buffer object
798 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
800 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
803 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
805 struct amdgpu_bo *vram_bo = NULL;
806 uint64_t vram_gpu = 0;
807 void *vram_ptr = NULL;
809 int ret, size = 0x100000;
812 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
813 AMDGPU_GEM_DOMAIN_VRAM,
820 memset(vram_ptr, 0x86, size);
821 memset(cptr, 0x86, 10);
824 * Check the start, the mid, and the end of the memory if the content of
825 * each byte is the pattern "0x86". If yes, we suppose the vram bo is
828 * Note: If check the each byte of whole 1M bo, it will cost too many
829 * seconds, so here, we just pick up three parts for emulation.
831 ret = memcmp(vram_ptr, cptr, 10);
835 ret = memcmp(vram_ptr + (size / 2), cptr, 10);
839 ret = memcmp(vram_ptr + size - 10, cptr, 10);
843 amdgpu_bo_free_kernel(&vram_bo, &vram_gpu,