2 * Copyright 2014 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amdgpu_gfx.h"
28 #include "amdgpu_rlc.h"
29 #include "amdgpu_ras.h"
31 /* delay 0.1 second to enable gfx off feature */
32 #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
35 * GPU GFX IP block helpers function.
38 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
43 bit += mec * adev->gfx.mec.num_pipe_per_mec
44 * adev->gfx.mec.num_queue_per_pipe;
45 bit += pipe * adev->gfx.mec.num_queue_per_pipe;
51 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
52 int *mec, int *pipe, int *queue)
54 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
55 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
56 % adev->gfx.mec.num_pipe_per_mec;
57 *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
58 / adev->gfx.mec.num_pipe_per_mec;
62 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
63 int mec, int pipe, int queue)
65 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
66 adev->gfx.mec.queue_bitmap);
69 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
70 int me, int pipe, int queue)
74 bit += me * adev->gfx.me.num_pipe_per_me
75 * adev->gfx.me.num_queue_per_pipe;
76 bit += pipe * adev->gfx.me.num_queue_per_pipe;
82 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
83 int *me, int *pipe, int *queue)
85 *queue = bit % adev->gfx.me.num_queue_per_pipe;
86 *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
87 % adev->gfx.me.num_pipe_per_me;
88 *me = (bit / adev->gfx.me.num_queue_per_pipe)
89 / adev->gfx.me.num_pipe_per_me;
92 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
93 int me, int pipe, int queue)
95 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
96 adev->gfx.me.queue_bitmap);
100 * amdgpu_gfx_scratch_get - Allocate a scratch register
102 * @adev: amdgpu_device pointer
103 * @reg: scratch register mmio offset
105 * Allocate a CP scratch register for use by the driver (all asics).
106 * Returns 0 on success or -EINVAL on failure.
108 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
112 i = ffs(adev->gfx.scratch.free_mask);
113 if (i != 0 && i <= adev->gfx.scratch.num_reg) {
115 adev->gfx.scratch.free_mask &= ~(1u << i);
116 *reg = adev->gfx.scratch.reg_base + i;
123 * amdgpu_gfx_scratch_free - Free a scratch register
125 * @adev: amdgpu_device pointer
126 * @reg: scratch register mmio offset
128 * Free a CP scratch register allocated for use by the driver (all asics)
130 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
132 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
136 * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
138 * @mask: array in which the per-shader array disable masks will be stored
139 * @max_se: number of SEs
140 * @max_sh: number of SHs
142 * The bitmask of CUs to be disabled in the shader array determined by se and
143 * sh is stored in mask[se * max_sh + sh].
145 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
150 memset(mask, 0, sizeof(*mask) * max_se * max_sh);
152 if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
155 p = amdgpu_disable_cu;
158 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
160 DRM_ERROR("amdgpu: could not parse disable_cu\n");
164 if (se < max_se && sh < max_sh && cu < 16) {
165 DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
166 mask[se * max_sh + sh] |= 1u << cu;
168 DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
172 next = strchr(p, ',');
179 static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
181 if (amdgpu_compute_multipipe != -1) {
182 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
183 amdgpu_compute_multipipe);
184 return amdgpu_compute_multipipe == 1;
187 /* FIXME: spreading the queues across pipes causes perf regressions
188 * on POLARIS11 compute workloads */
189 if (adev->asic_type == CHIP_POLARIS11)
192 return adev->gfx.mec.num_mec > 1;
195 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
196 struct amdgpu_ring *ring)
198 /* Policy: use 1st queue as high priority compute queue if we
199 * have more than one compute queue.
201 if (adev->gfx.num_compute_rings > 1 &&
202 ring == &adev->gfx.compute_ring[0])
208 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
211 bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
212 int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
213 adev->gfx.mec.num_queue_per_pipe,
214 adev->gfx.num_compute_rings);
216 if (multipipe_policy) {
217 /* policy: make queues evenly cross all pipes on MEC1 only */
218 for (i = 0; i < max_queues_per_mec; i++) {
219 pipe = i % adev->gfx.mec.num_pipe_per_mec;
220 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
221 adev->gfx.mec.num_queue_per_pipe;
223 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
224 adev->gfx.mec.queue_bitmap);
227 /* policy: amdgpu owns all queues in the given pipe */
228 for (i = 0; i < max_queues_per_mec; ++i)
229 set_bit(i, adev->gfx.mec.queue_bitmap);
232 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n", bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
235 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
239 for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
240 queue = i % adev->gfx.me.num_queue_per_pipe;
241 me = (i / adev->gfx.me.num_queue_per_pipe)
242 / adev->gfx.me.num_pipe_per_me;
244 if (me >= adev->gfx.me.num_me)
246 /* policy: amdgpu owns the first queue per pipe at this stage
247 * will extend to mulitple queues per pipe later */
248 if (me == 0 && queue < 1)
249 set_bit(i, adev->gfx.me.queue_bitmap);
252 /* update the number of active graphics rings */
253 adev->gfx.num_gfx_rings =
254 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
257 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
258 struct amdgpu_ring *ring)
261 int mec, pipe, queue;
263 queue_bit = adev->gfx.mec.num_mec
264 * adev->gfx.mec.num_pipe_per_mec
265 * adev->gfx.mec.num_queue_per_pipe;
267 while (queue_bit-- >= 0) {
268 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
271 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
274 * 1. Using pipes 2/3 from MEC 2 seems cause problems.
275 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
276 * only can be issued on queue 0.
278 if ((mec == 1 && pipe > 1) || queue != 0)
288 dev_err(adev->dev, "Failed to find a queue for KIQ\n");
292 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
293 struct amdgpu_ring *ring,
294 struct amdgpu_irq_src *irq)
296 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
299 spin_lock_init(&kiq->ring_lock);
302 ring->ring_obj = NULL;
303 ring->use_doorbell = true;
304 ring->doorbell_index = adev->doorbell_index.kiq;
306 r = amdgpu_gfx_kiq_acquire(adev, ring);
310 ring->eop_gpu_addr = kiq->eop_gpu_addr;
311 ring->no_scheduler = true;
312 sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);
313 r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
314 AMDGPU_RING_PRIO_DEFAULT, NULL);
316 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
321 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
323 amdgpu_ring_fini(ring);
326 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev)
328 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
330 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
333 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
338 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
340 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
341 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
342 &kiq->eop_gpu_addr, (void **)&hpd);
344 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
348 memset(hpd, 0, hpd_size);
350 r = amdgpu_bo_reserve(kiq->eop_obj, true);
351 if (unlikely(r != 0))
352 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
353 amdgpu_bo_kunmap(kiq->eop_obj);
354 amdgpu_bo_unreserve(kiq->eop_obj);
359 /* create MQD for each compute/gfx queue */
360 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
363 struct amdgpu_ring *ring = NULL;
366 /* create MQD for KIQ */
367 ring = &adev->gfx.kiq.ring;
368 if (!ring->mqd_obj) {
369 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
370 * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
371 * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
372 * KIQ MQD no matter SRIOV or Bare-metal
374 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
375 AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
376 &ring->mqd_gpu_addr, &ring->mqd_ptr);
378 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
382 /* prepare MQD backup */
383 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL);
384 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
385 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
388 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
389 /* create MQD for each KGQ */
390 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
391 ring = &adev->gfx.gfx_ring[i];
392 if (!ring->mqd_obj) {
393 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
394 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
395 &ring->mqd_gpu_addr, &ring->mqd_ptr);
397 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
401 /* prepare MQD backup */
402 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
403 if (!adev->gfx.me.mqd_backup[i])
404 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
409 /* create MQD for each KCQ */
410 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
411 ring = &adev->gfx.compute_ring[i];
412 if (!ring->mqd_obj) {
413 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
414 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
415 &ring->mqd_gpu_addr, &ring->mqd_ptr);
417 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
421 /* prepare MQD backup */
422 adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
423 if (!adev->gfx.mec.mqd_backup[i])
424 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
431 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
433 struct amdgpu_ring *ring = NULL;
436 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
437 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
438 ring = &adev->gfx.gfx_ring[i];
439 kfree(adev->gfx.me.mqd_backup[i]);
440 amdgpu_bo_free_kernel(&ring->mqd_obj,
446 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
447 ring = &adev->gfx.compute_ring[i];
448 kfree(adev->gfx.mec.mqd_backup[i]);
449 amdgpu_bo_free_kernel(&ring->mqd_obj,
454 ring = &adev->gfx.kiq.ring;
455 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
456 amdgpu_bo_free_kernel(&ring->mqd_obj,
461 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
463 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
464 struct amdgpu_ring *kiq_ring = &kiq->ring;
467 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
470 spin_lock(&adev->gfx.kiq.ring_lock);
471 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
472 adev->gfx.num_compute_rings)) {
473 spin_unlock(&adev->gfx.kiq.ring_lock);
477 for (i = 0; i < adev->gfx.num_compute_rings; i++)
478 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
480 r = amdgpu_ring_test_helper(kiq_ring);
481 spin_unlock(&adev->gfx.kiq.ring_lock);
486 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
489 int mec, pipe, queue;
490 int set_resource_bit = 0;
492 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
494 set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
496 return set_resource_bit;
499 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
501 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
502 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
503 uint64_t queue_mask = 0;
506 if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
509 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
510 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
513 /* This situation may be hit in the future if a new HW
514 * generation exposes more than 64 queues. If so, the
515 * definition of queue_mask needs updating */
516 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
517 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
521 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
524 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
526 spin_lock(&adev->gfx.kiq.ring_lock);
527 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
528 adev->gfx.num_compute_rings +
529 kiq->pmf->set_resources_size);
531 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
532 spin_unlock(&adev->gfx.kiq.ring_lock);
536 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
537 for (i = 0; i < adev->gfx.num_compute_rings; i++)
538 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]);
540 r = amdgpu_ring_test_helper(kiq_ring);
541 spin_unlock(&adev->gfx.kiq.ring_lock);
543 DRM_ERROR("KCQ enable failed\n");
548 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
550 * @adev: amdgpu_device pointer
551 * @bool enable true: enable gfx off feature, false: disable gfx off feature
553 * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
554 * 2. other client can send request to disable gfx off feature, the request should be honored.
555 * 3. other client can cancel their request of disable gfx off feature
556 * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
559 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
561 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
564 mutex_lock(&adev->gfx.gfx_off_mutex);
567 /* If the count is already 0, it means there's an imbalance bug somewhere.
568 * Note that the bug may be in a different caller than the one which triggers the
571 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
574 adev->gfx.gfx_off_req_count--;
576 if (adev->gfx.gfx_off_req_count == 0 && !adev->gfx.gfx_off_state)
577 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE);
579 if (adev->gfx.gfx_off_req_count == 0) {
580 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
582 if (adev->gfx.gfx_off_state &&
583 !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
584 adev->gfx.gfx_off_state = false;
586 if (adev->gfx.funcs->init_spm_golden) {
588 "GFXOFF is disabled, re-init SPM golden settings\n");
589 amdgpu_gfx_init_spm_golden(adev);
594 adev->gfx.gfx_off_req_count++;
598 mutex_unlock(&adev->gfx.gfx_off_mutex);
601 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
606 mutex_lock(&adev->gfx.gfx_off_mutex);
608 r = smu_get_status_gfxoff(adev, value);
610 mutex_unlock(&adev->gfx.gfx_off_mutex);
615 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
618 struct ras_fs_if fs_info = {
619 .sysfs_name = "gfx_err_count",
621 struct ras_ih_if ih_info = {
622 .cb = amdgpu_gfx_process_ras_data_cb,
625 if (!adev->gfx.ras_if) {
626 adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
627 if (!adev->gfx.ras_if)
629 adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
630 adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
631 adev->gfx.ras_if->sub_block_index = 0;
632 strcpy(adev->gfx.ras_if->name, "gfx");
634 fs_info.head = ih_info.head = *adev->gfx.ras_if;
635 r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
640 if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
641 if (!amdgpu_persistent_edc_harvesting_supported(adev))
642 amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
644 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
648 /* free gfx ras_if if ras is not supported */
655 amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
657 kfree(adev->gfx.ras_if);
658 adev->gfx.ras_if = NULL;
662 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev)
664 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
666 struct ras_common_if *ras_if = adev->gfx.ras_if;
667 struct ras_ih_if ih_info = {
669 .cb = amdgpu_gfx_process_ras_data_cb,
672 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
677 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
679 struct amdgpu_iv_entry *entry)
681 /* TODO ue will trigger an interrupt.
683 * When “Full RAS” is enabled, the per-IP interrupt sources should
684 * be disabled and the driver should only look for the aggregated
685 * interrupt via sync flood
687 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
688 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
689 if (adev->gfx.ras_funcs &&
690 adev->gfx.ras_funcs->query_ras_error_count)
691 adev->gfx.ras_funcs->query_ras_error_count(adev, err_data);
692 amdgpu_ras_reset_gpu(adev);
694 return AMDGPU_RAS_SUCCESS;
697 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
698 struct amdgpu_irq_src *source,
699 struct amdgpu_iv_entry *entry)
701 struct ras_common_if *ras_if = adev->gfx.ras_if;
702 struct ras_dispatch_if ih_data = {
709 ih_data.head = *ras_if;
711 DRM_ERROR("CP ECC ERROR IRQ\n");
712 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
716 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
718 signed long r, cnt = 0;
720 uint32_t seq, reg_val_offs = 0, value = 0;
721 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
722 struct amdgpu_ring *ring = &kiq->ring;
724 if (amdgpu_device_skip_hw_access(adev))
727 BUG_ON(!ring->funcs->emit_rreg);
729 spin_lock_irqsave(&kiq->ring_lock, flags);
730 if (amdgpu_device_wb_get(adev, ®_val_offs)) {
731 pr_err("critical bug! too many kiq readers\n");
734 amdgpu_ring_alloc(ring, 32);
735 amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
736 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
740 amdgpu_ring_commit(ring);
741 spin_unlock_irqrestore(&kiq->ring_lock, flags);
743 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
745 /* don't wait anymore for gpu reset case because this way may
746 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
747 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
748 * never return if we keep waiting in virt_kiq_rreg, which cause
749 * gpu_recover() hang there.
751 * also don't wait anymore for IRQ context
753 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
754 goto failed_kiq_read;
757 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
758 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
759 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
762 if (cnt > MAX_KIQ_REG_TRY)
763 goto failed_kiq_read;
766 value = adev->wb.wb[reg_val_offs];
767 amdgpu_device_wb_free(adev, reg_val_offs);
771 amdgpu_ring_undo(ring);
773 spin_unlock_irqrestore(&kiq->ring_lock, flags);
776 amdgpu_device_wb_free(adev, reg_val_offs);
777 dev_err(adev->dev, "failed to read reg:%x\n", reg);
781 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
783 signed long r, cnt = 0;
786 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
787 struct amdgpu_ring *ring = &kiq->ring;
789 BUG_ON(!ring->funcs->emit_wreg);
791 if (amdgpu_device_skip_hw_access(adev))
794 spin_lock_irqsave(&kiq->ring_lock, flags);
795 amdgpu_ring_alloc(ring, 32);
796 amdgpu_ring_emit_wreg(ring, reg, v);
797 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
801 amdgpu_ring_commit(ring);
802 spin_unlock_irqrestore(&kiq->ring_lock, flags);
804 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
806 /* don't wait anymore for gpu reset case because this way may
807 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
808 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
809 * never return if we keep waiting in virt_kiq_rreg, which cause
810 * gpu_recover() hang there.
812 * also don't wait anymore for IRQ context
814 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
815 goto failed_kiq_write;
818 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
820 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
821 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
824 if (cnt > MAX_KIQ_REG_TRY)
825 goto failed_kiq_write;
830 amdgpu_ring_undo(ring);
831 spin_unlock_irqrestore(&kiq->ring_lock, flags);
833 dev_err(adev->dev, "failed to write reg:%x\n", reg);
836 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
838 if (amdgpu_num_kcq == -1) {
840 } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
841 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
844 return amdgpu_num_kcq;
847 /* amdgpu_gfx_state_change_set - Handle gfx power state change set
848 * @adev: amdgpu_device pointer
849 * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry)
853 void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state)
855 mutex_lock(&adev->pm.mutex);
856 if (adev->powerplay.pp_funcs &&
857 adev->powerplay.pp_funcs->gfx_state_change_set)
858 ((adev)->powerplay.pp_funcs->gfx_state_change_set(
859 (adev)->powerplay.pp_handle, state));
860 mutex_unlock(&adev->pm.mutex);