2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
29 #include <linux/pagemap.h>
31 #include <drm/amdgpu_drm.h>
33 #include "amdgpu_display.h"
35 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
37 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
40 amdgpu_mn_unregister(robj);
41 amdgpu_bo_unref(&robj);
45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
46 int alignment, u32 initial_domain,
47 u64 flags, enum ttm_bo_type type,
48 struct reservation_object *resv,
49 struct drm_gem_object **obj)
52 struct amdgpu_bo_param bp;
55 memset(&bp, 0, sizeof(bp));
57 /* At least align on page size */
58 if (alignment < PAGE_SIZE) {
59 alignment = PAGE_SIZE;
63 bp.byte_align = alignment;
66 bp.preferred_domain = initial_domain;
69 bp.domain = initial_domain;
70 r = amdgpu_bo_create(adev, &bp, &bo);
72 if (r != -ERESTARTSYS) {
73 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
74 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
78 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
79 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
82 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
83 size, initial_domain, alignment, r);
92 void amdgpu_gem_force_release(struct amdgpu_device *adev)
94 struct drm_device *ddev = adev->ddev;
95 struct drm_file *file;
97 mutex_lock(&ddev->filelist_mutex);
99 list_for_each_entry(file, &ddev->filelist, lhead) {
100 struct drm_gem_object *gobj;
103 WARN_ONCE(1, "Still active user space clients!\n");
104 spin_lock(&file->table_lock);
105 idr_for_each_entry(&file->object_idr, gobj, handle) {
106 WARN_ONCE(1, "And also active allocations!\n");
107 drm_gem_object_put_unlocked(gobj);
109 idr_destroy(&file->object_idr);
110 spin_unlock(&file->table_lock);
113 mutex_unlock(&ddev->filelist_mutex);
117 * Call from drm_gem_handle_create which appear in both new and open ioctl
120 int amdgpu_gem_object_open(struct drm_gem_object *obj,
121 struct drm_file *file_priv)
123 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
124 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
125 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
126 struct amdgpu_vm *vm = &fpriv->vm;
127 struct amdgpu_bo_va *bo_va;
128 struct mm_struct *mm;
131 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
132 if (mm && mm != current->mm)
135 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
136 abo->tbo.resv != vm->root.base.bo->tbo.resv)
139 r = amdgpu_bo_reserve(abo, false);
143 bo_va = amdgpu_vm_bo_find(vm, abo);
145 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
149 amdgpu_bo_unreserve(abo);
153 void amdgpu_gem_object_close(struct drm_gem_object *obj,
154 struct drm_file *file_priv)
156 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
157 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
158 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
159 struct amdgpu_vm *vm = &fpriv->vm;
161 struct amdgpu_bo_list_entry vm_pd;
162 struct list_head list, duplicates;
163 struct ttm_validate_buffer tv;
164 struct ww_acquire_ctx ticket;
165 struct amdgpu_bo_va *bo_va;
168 INIT_LIST_HEAD(&list);
169 INIT_LIST_HEAD(&duplicates);
173 list_add(&tv.head, &list);
175 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
177 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
179 dev_err(adev->dev, "leaking bo va because "
180 "we fail to reserve bo (%d)\n", r);
183 bo_va = amdgpu_vm_bo_find(vm, bo);
184 if (bo_va && --bo_va->ref_count == 0) {
185 amdgpu_vm_bo_rmv(adev, bo_va);
187 if (amdgpu_vm_ready(vm)) {
188 struct dma_fence *fence = NULL;
190 r = amdgpu_vm_clear_freed(adev, vm, &fence);
192 dev_err(adev->dev, "failed to clear page "
193 "tables on GEM object close (%d)\n", r);
197 amdgpu_bo_fence(bo, fence, true);
198 dma_fence_put(fence);
202 ttm_eu_backoff_reservation(&ticket, &list);
208 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
209 struct drm_file *filp)
211 struct amdgpu_device *adev = dev->dev_private;
212 struct amdgpu_fpriv *fpriv = filp->driver_priv;
213 struct amdgpu_vm *vm = &fpriv->vm;
214 union drm_amdgpu_gem_create *args = data;
215 uint64_t flags = args->in.domain_flags;
216 uint64_t size = args->in.bo_size;
217 struct reservation_object *resv = NULL;
218 struct drm_gem_object *gobj;
222 /* reject invalid gem flags */
223 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
224 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
225 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
226 AMDGPU_GEM_CREATE_VRAM_CLEARED |
227 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
228 AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
232 /* reject invalid gem domains */
233 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
236 /* create a gem object to contain this object in */
237 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
238 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
239 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
240 /* if gds bo is created from user space, it must be
243 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
246 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
247 /* GDS allocations must be DW aligned */
248 if (args->in.domains & AMDGPU_GEM_DOMAIN_GDS)
249 size = ALIGN(size, 4);
252 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
253 r = amdgpu_bo_reserve(vm->root.base.bo, false);
257 resv = vm->root.base.bo->tbo.resv;
260 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
261 (u32)(0xffffffff & args->in.domains),
262 flags, ttm_bo_type_device, resv, &gobj);
263 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
265 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
267 abo->parent = amdgpu_bo_ref(vm->root.base.bo);
269 amdgpu_bo_unreserve(vm->root.base.bo);
274 r = drm_gem_handle_create(filp, gobj, &handle);
275 /* drop reference from allocate - handle holds it now */
276 drm_gem_object_put_unlocked(gobj);
280 memset(args, 0, sizeof(*args));
281 args->out.handle = handle;
285 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
286 struct drm_file *filp)
288 struct ttm_operation_ctx ctx = { true, false };
289 struct amdgpu_device *adev = dev->dev_private;
290 struct drm_amdgpu_gem_userptr *args = data;
291 struct drm_gem_object *gobj;
292 struct amdgpu_bo *bo;
296 if (offset_in_page(args->addr | args->size))
299 /* reject unknown flag values */
300 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
301 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
302 AMDGPU_GEM_USERPTR_REGISTER))
305 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
306 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
308 /* if we want to write to it we must install a MMU notifier */
312 /* create a gem object to contain this object in */
313 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
314 0, ttm_bo_type_device, NULL, &gobj);
318 bo = gem_to_amdgpu_bo(gobj);
319 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
320 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
321 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
325 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
326 r = amdgpu_mn_register(bo, args->addr);
331 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
332 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
337 r = amdgpu_bo_reserve(bo, true);
341 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
342 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
343 amdgpu_bo_unreserve(bo);
348 r = drm_gem_handle_create(filp, gobj, &handle);
349 /* drop reference from allocate - handle holds it now */
350 drm_gem_object_put_unlocked(gobj);
354 args->handle = handle;
358 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
361 drm_gem_object_put_unlocked(gobj);
366 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
367 struct drm_device *dev,
368 uint32_t handle, uint64_t *offset_p)
370 struct drm_gem_object *gobj;
371 struct amdgpu_bo *robj;
373 gobj = drm_gem_object_lookup(filp, handle);
377 robj = gem_to_amdgpu_bo(gobj);
378 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
379 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
380 drm_gem_object_put_unlocked(gobj);
383 *offset_p = amdgpu_bo_mmap_offset(robj);
384 drm_gem_object_put_unlocked(gobj);
388 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
389 struct drm_file *filp)
391 union drm_amdgpu_gem_mmap *args = data;
392 uint32_t handle = args->in.handle;
393 memset(args, 0, sizeof(*args));
394 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
398 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
400 * @timeout_ns: timeout in ns
402 * Calculate the timeout in jiffies from an absolute timeout in ns.
404 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
406 unsigned long timeout_jiffies;
409 /* clamp timeout if it's to large */
410 if (((int64_t)timeout_ns) < 0)
411 return MAX_SCHEDULE_TIMEOUT;
413 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
414 if (ktime_to_ns(timeout) < 0)
417 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
418 /* clamp timeout to avoid unsigned-> signed overflow */
419 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
420 return MAX_SCHEDULE_TIMEOUT - 1;
422 return timeout_jiffies;
425 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
426 struct drm_file *filp)
428 union drm_amdgpu_gem_wait_idle *args = data;
429 struct drm_gem_object *gobj;
430 struct amdgpu_bo *robj;
431 uint32_t handle = args->in.handle;
432 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
436 gobj = drm_gem_object_lookup(filp, handle);
440 robj = gem_to_amdgpu_bo(gobj);
441 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
444 /* ret == 0 means not signaled,
445 * ret > 0 means signaled
446 * ret < 0 means interrupted before timeout
449 memset(args, 0, sizeof(*args));
450 args->out.status = (ret == 0);
454 drm_gem_object_put_unlocked(gobj);
458 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
459 struct drm_file *filp)
461 struct drm_amdgpu_gem_metadata *args = data;
462 struct drm_gem_object *gobj;
463 struct amdgpu_bo *robj;
466 DRM_DEBUG("%d \n", args->handle);
467 gobj = drm_gem_object_lookup(filp, args->handle);
470 robj = gem_to_amdgpu_bo(gobj);
472 r = amdgpu_bo_reserve(robj, false);
473 if (unlikely(r != 0))
476 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
477 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
478 r = amdgpu_bo_get_metadata(robj, args->data.data,
479 sizeof(args->data.data),
480 &args->data.data_size_bytes,
482 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
483 if (args->data.data_size_bytes > sizeof(args->data.data)) {
487 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
489 r = amdgpu_bo_set_metadata(robj, args->data.data,
490 args->data.data_size_bytes,
495 amdgpu_bo_unreserve(robj);
497 drm_gem_object_put_unlocked(gobj);
502 * amdgpu_gem_va_update_vm -update the bo_va in its VM
504 * @adev: amdgpu_device pointer
506 * @bo_va: bo_va to update
507 * @operation: map, unmap or clear
509 * Update the bo_va directly after setting its address. Errors are not
510 * vital here, so they are not reported back to userspace.
512 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
513 struct amdgpu_vm *vm,
514 struct amdgpu_bo_va *bo_va,
519 if (!amdgpu_vm_ready(vm))
522 r = amdgpu_vm_clear_freed(adev, vm, NULL);
526 if (operation == AMDGPU_VA_OP_MAP ||
527 operation == AMDGPU_VA_OP_REPLACE) {
528 r = amdgpu_vm_bo_update(adev, bo_va, false);
533 r = amdgpu_vm_update_directories(adev, vm);
536 if (r && r != -ERESTARTSYS)
537 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
540 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
541 struct drm_file *filp)
543 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
544 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
545 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
546 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
549 struct drm_amdgpu_gem_va *args = data;
550 struct drm_gem_object *gobj;
551 struct amdgpu_device *adev = dev->dev_private;
552 struct amdgpu_fpriv *fpriv = filp->driver_priv;
553 struct amdgpu_bo *abo;
554 struct amdgpu_bo_va *bo_va;
555 struct amdgpu_bo_list_entry vm_pd;
556 struct ttm_validate_buffer tv;
557 struct ww_acquire_ctx ticket;
558 struct list_head list, duplicates;
562 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
563 dev_dbg(&dev->pdev->dev,
564 "va_address 0x%LX is in reserved area 0x%LX\n",
565 args->va_address, AMDGPU_VA_RESERVED_SIZE);
569 if (args->va_address >= AMDGPU_GMC_HOLE_START &&
570 args->va_address < AMDGPU_GMC_HOLE_END) {
571 dev_dbg(&dev->pdev->dev,
572 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
573 args->va_address, AMDGPU_GMC_HOLE_START,
574 AMDGPU_GMC_HOLE_END);
578 args->va_address &= AMDGPU_GMC_HOLE_MASK;
580 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
581 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
586 switch (args->operation) {
587 case AMDGPU_VA_OP_MAP:
588 case AMDGPU_VA_OP_UNMAP:
589 case AMDGPU_VA_OP_CLEAR:
590 case AMDGPU_VA_OP_REPLACE:
593 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
598 INIT_LIST_HEAD(&list);
599 INIT_LIST_HEAD(&duplicates);
600 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
601 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
602 gobj = drm_gem_object_lookup(filp, args->handle);
605 abo = gem_to_amdgpu_bo(gobj);
607 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
611 list_add(&tv.head, &list);
617 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
619 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
624 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
629 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
630 bo_va = fpriv->prt_va;
635 switch (args->operation) {
636 case AMDGPU_VA_OP_MAP:
637 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
642 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
643 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
644 args->offset_in_bo, args->map_size,
647 case AMDGPU_VA_OP_UNMAP:
648 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
651 case AMDGPU_VA_OP_CLEAR:
652 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
656 case AMDGPU_VA_OP_REPLACE:
657 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
662 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
663 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
664 args->offset_in_bo, args->map_size,
670 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
671 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
675 ttm_eu_backoff_reservation(&ticket, &list);
678 drm_gem_object_put_unlocked(gobj);
682 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
683 struct drm_file *filp)
685 struct amdgpu_device *adev = dev->dev_private;
686 struct drm_amdgpu_gem_op *args = data;
687 struct drm_gem_object *gobj;
688 struct amdgpu_bo *robj;
691 gobj = drm_gem_object_lookup(filp, args->handle);
695 robj = gem_to_amdgpu_bo(gobj);
697 r = amdgpu_bo_reserve(robj, false);
702 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
703 struct drm_amdgpu_gem_create_in info;
704 void __user *out = u64_to_user_ptr(args->value);
706 info.bo_size = robj->gem_base.size;
707 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
708 info.domains = robj->preferred_domains;
709 info.domain_flags = robj->flags;
710 amdgpu_bo_unreserve(robj);
711 if (copy_to_user(out, &info, sizeof(info)))
715 case AMDGPU_GEM_OP_SET_PLACEMENT:
716 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
718 amdgpu_bo_unreserve(robj);
721 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
723 amdgpu_bo_unreserve(robj);
726 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
727 AMDGPU_GEM_DOMAIN_GTT |
728 AMDGPU_GEM_DOMAIN_CPU);
729 robj->allowed_domains = robj->preferred_domains;
730 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
731 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
733 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
734 amdgpu_vm_bo_invalidate(adev, robj, true);
736 amdgpu_bo_unreserve(robj);
739 amdgpu_bo_unreserve(robj);
744 drm_gem_object_put_unlocked(gobj);
748 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
749 struct drm_device *dev,
750 struct drm_mode_create_dumb *args)
752 struct amdgpu_device *adev = dev->dev_private;
753 struct drm_gem_object *gobj;
758 args->pitch = amdgpu_align_pitch(adev, args->width,
759 DIV_ROUND_UP(args->bpp, 8), 0);
760 args->size = (u64)args->pitch * args->height;
761 args->size = ALIGN(args->size, PAGE_SIZE);
762 domain = amdgpu_bo_get_preferred_pin_domain(adev,
763 amdgpu_display_supported_domains(adev));
764 r = amdgpu_gem_object_create(adev, args->size, 0, domain,
765 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
766 ttm_bo_type_device, NULL, &gobj);
770 r = drm_gem_handle_create(file_priv, gobj, &handle);
771 /* drop reference from allocate - handle holds it now */
772 drm_gem_object_put_unlocked(gobj);
776 args->handle = handle;
780 #if defined(CONFIG_DEBUG_FS)
782 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \
783 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
784 seq_printf((m), " " #flag); \
787 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
789 struct drm_gem_object *gobj = ptr;
790 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
791 struct seq_file *m = data;
793 struct dma_buf_attachment *attachment;
794 struct dma_buf *dma_buf;
796 const char *placement;
799 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
801 case AMDGPU_GEM_DOMAIN_VRAM:
804 case AMDGPU_GEM_DOMAIN_GTT:
807 case AMDGPU_GEM_DOMAIN_CPU:
812 seq_printf(m, "\t0x%08x: %12ld byte %s",
813 id, amdgpu_bo_size(bo), placement);
815 pin_count = READ_ONCE(bo->pin_count);
817 seq_printf(m, " pin count %d", pin_count);
819 dma_buf = READ_ONCE(bo->gem_base.dma_buf);
820 attachment = READ_ONCE(bo->gem_base.import_attach);
823 seq_printf(m, " imported from %p", dma_buf);
825 seq_printf(m, " exported as %p", dma_buf);
827 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
828 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS);
829 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC);
830 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED);
831 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW);
832 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
833 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID);
834 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC);
841 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
843 struct drm_info_node *node = (struct drm_info_node *)m->private;
844 struct drm_device *dev = node->minor->dev;
845 struct drm_file *file;
848 r = mutex_lock_interruptible(&dev->filelist_mutex);
852 list_for_each_entry(file, &dev->filelist, lhead) {
853 struct task_struct *task;
856 * Although we have a valid reference on file->pid, that does
857 * not guarantee that the task_struct who called get_pid() is
858 * still alive (e.g. get_pid(current) => fork() => exit()).
859 * Therefore, we need to protect this ->comm access using RCU.
862 task = pid_task(file->pid, PIDTYPE_PID);
863 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
864 task ? task->comm : "<unknown>");
867 spin_lock(&file->table_lock);
868 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
869 spin_unlock(&file->table_lock);
872 mutex_unlock(&dev->filelist_mutex);
876 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
877 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
881 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
883 #if defined(CONFIG_DEBUG_FS)
884 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);