2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
29 #include <linux/module.h>
30 #include <linux/pagemap.h>
31 #include <linux/pci.h>
32 #include <linux/dma-buf.h>
34 #include <drm/amdgpu_drm.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_exec.h>
37 #include <drm/drm_gem_ttm_helper.h>
38 #include <drm/ttm/ttm_tt.h>
41 #include "amdgpu_display.h"
42 #include "amdgpu_dma_buf.h"
43 #include "amdgpu_hmm.h"
44 #include "amdgpu_xgmi.h"
46 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
48 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
50 struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
51 struct drm_device *ddev = bo->base.dev;
55 ret = ttm_bo_vm_reserve(bo, vmf);
59 if (drm_dev_enter(ddev, &idx)) {
60 ret = amdgpu_bo_fault_reserve_notify(bo);
66 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
67 TTM_BO_VM_NUM_PREFAULT);
71 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
73 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
77 dma_resv_unlock(bo->base.resv);
81 static const struct vm_operations_struct amdgpu_gem_vm_ops = {
82 .fault = amdgpu_gem_fault,
83 .open = ttm_bo_vm_open,
84 .close = ttm_bo_vm_close,
85 .access = ttm_bo_vm_access
88 static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
90 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
93 amdgpu_hmm_unregister(robj);
94 amdgpu_bo_unref(&robj);
98 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
99 int alignment, u32 initial_domain,
100 u64 flags, enum ttm_bo_type type,
101 struct dma_resv *resv,
102 struct drm_gem_object **obj, int8_t xcp_id_plus1)
104 struct amdgpu_bo *bo;
105 struct amdgpu_bo_user *ubo;
106 struct amdgpu_bo_param bp;
109 memset(&bp, 0, sizeof(bp));
113 bp.byte_align = alignment;
116 bp.preferred_domain = initial_domain;
118 bp.domain = initial_domain;
119 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
120 bp.xcp_id_plus1 = xcp_id_plus1;
122 r = amdgpu_bo_create_user(adev, &bp, &ubo);
127 *obj = &bo->tbo.base;
128 (*obj)->funcs = &amdgpu_gem_object_funcs;
133 void amdgpu_gem_force_release(struct amdgpu_device *adev)
135 struct drm_device *ddev = adev_to_drm(adev);
136 struct drm_file *file;
138 mutex_lock(&ddev->filelist_mutex);
140 list_for_each_entry(file, &ddev->filelist, lhead) {
141 struct drm_gem_object *gobj;
144 WARN_ONCE(1, "Still active user space clients!\n");
145 spin_lock(&file->table_lock);
146 idr_for_each_entry(&file->object_idr, gobj, handle) {
147 WARN_ONCE(1, "And also active allocations!\n");
148 drm_gem_object_put(gobj);
150 idr_destroy(&file->object_idr);
151 spin_unlock(&file->table_lock);
154 mutex_unlock(&ddev->filelist_mutex);
158 * Call from drm_gem_handle_create which appear in both new and open ioctl
161 static int amdgpu_gem_object_open(struct drm_gem_object *obj,
162 struct drm_file *file_priv)
164 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
165 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
166 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
167 struct amdgpu_vm *vm = &fpriv->vm;
168 struct amdgpu_bo_va *bo_va;
169 struct mm_struct *mm;
172 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
173 if (mm && mm != current->mm)
176 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
177 abo->tbo.base.resv != vm->root.bo->tbo.base.resv)
180 r = amdgpu_bo_reserve(abo, false);
184 bo_va = amdgpu_vm_bo_find(vm, abo);
186 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
189 amdgpu_bo_unreserve(abo);
193 static void amdgpu_gem_object_close(struct drm_gem_object *obj,
194 struct drm_file *file_priv)
196 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
197 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
198 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
199 struct amdgpu_vm *vm = &fpriv->vm;
201 struct dma_fence *fence = NULL;
202 struct amdgpu_bo_va *bo_va;
203 struct drm_exec exec;
206 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
207 drm_exec_until_all_locked(&exec) {
208 r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1);
209 drm_exec_retry_on_contention(&exec);
213 r = amdgpu_vm_lock_pd(vm, &exec, 0);
214 drm_exec_retry_on_contention(&exec);
219 bo_va = amdgpu_vm_bo_find(vm, bo);
220 if (!bo_va || --bo_va->ref_count)
223 amdgpu_vm_bo_del(adev, bo_va);
224 if (!amdgpu_vm_ready(vm))
227 r = amdgpu_vm_clear_freed(adev, vm, &fence);
229 dev_err(adev->dev, "failed to clear page "
230 "tables on GEM object close (%ld)\n", r);
234 amdgpu_bo_fence(bo, fence, true);
235 dma_fence_put(fence);
239 dev_err(adev->dev, "leaking bo va (%ld)\n", r);
240 drm_exec_fini(&exec);
243 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
245 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
247 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
249 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
252 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
253 * for debugger access to invisible VRAM. Should have used MAP_SHARED
254 * instead. Clearing VM_MAYWRITE prevents the mapping from ever
255 * becoming writable and makes is_cow_mapping(vm_flags) false.
257 if (is_cow_mapping(vma->vm_flags) &&
258 !(vma->vm_flags & VM_ACCESS_FLAGS))
259 vm_flags_clear(vma, VM_MAYWRITE);
261 return drm_gem_ttm_mmap(obj, vma);
264 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
265 .free = amdgpu_gem_object_free,
266 .open = amdgpu_gem_object_open,
267 .close = amdgpu_gem_object_close,
268 .export = amdgpu_gem_prime_export,
269 .vmap = drm_gem_ttm_vmap,
270 .vunmap = drm_gem_ttm_vunmap,
271 .mmap = amdgpu_gem_object_mmap,
272 .vm_ops = &amdgpu_gem_vm_ops,
278 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
279 struct drm_file *filp)
281 struct amdgpu_device *adev = drm_to_adev(dev);
282 struct amdgpu_fpriv *fpriv = filp->driver_priv;
283 struct amdgpu_vm *vm = &fpriv->vm;
284 union drm_amdgpu_gem_create *args = data;
285 uint64_t flags = args->in.domain_flags;
286 uint64_t size = args->in.bo_size;
287 struct dma_resv *resv = NULL;
288 struct drm_gem_object *gobj;
289 uint32_t handle, initial_domain;
292 /* reject DOORBELLs until userspace code to use it is available */
293 if (args->in.domains & AMDGPU_GEM_DOMAIN_DOORBELL)
296 /* reject invalid gem flags */
297 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
298 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
299 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
300 AMDGPU_GEM_CREATE_VRAM_CLEARED |
301 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
302 AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
303 AMDGPU_GEM_CREATE_ENCRYPTED |
304 AMDGPU_GEM_CREATE_DISCARDABLE))
307 /* reject invalid gem domains */
308 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
311 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
312 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
316 /* create a gem object to contain this object in */
317 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
318 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
319 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
320 /* if gds bo is created from user space, it must be
323 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
326 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
329 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
330 r = amdgpu_bo_reserve(vm->root.bo, false);
334 resv = vm->root.bo->tbo.base.resv;
337 initial_domain = (u32)(0xffffffff & args->in.domains);
339 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
341 flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1);
342 if (r && r != -ERESTARTSYS) {
343 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
344 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
348 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
349 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
352 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
353 size, initial_domain, args->in.alignment, r);
356 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
358 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
360 abo->parent = amdgpu_bo_ref(vm->root.bo);
362 amdgpu_bo_unreserve(vm->root.bo);
367 r = drm_gem_handle_create(filp, gobj, &handle);
368 /* drop reference from allocate - handle holds it now */
369 drm_gem_object_put(gobj);
373 memset(args, 0, sizeof(*args));
374 args->out.handle = handle;
378 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
379 struct drm_file *filp)
381 struct ttm_operation_ctx ctx = { true, false };
382 struct amdgpu_device *adev = drm_to_adev(dev);
383 struct drm_amdgpu_gem_userptr *args = data;
384 struct amdgpu_fpriv *fpriv = filp->driver_priv;
385 struct drm_gem_object *gobj;
386 struct hmm_range *range;
387 struct amdgpu_bo *bo;
391 args->addr = untagged_addr(args->addr);
393 if (offset_in_page(args->addr | args->size))
396 /* reject unknown flag values */
397 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
398 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
399 AMDGPU_GEM_USERPTR_REGISTER))
402 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
403 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
405 /* if we want to write to it we must install a MMU notifier */
409 /* create a gem object to contain this object in */
410 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
411 0, ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
415 bo = gem_to_amdgpu_bo(gobj);
416 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
417 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
418 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags);
422 r = amdgpu_hmm_register(bo, args->addr);
426 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
427 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
432 r = amdgpu_bo_reserve(bo, true);
434 goto user_pages_done;
436 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
437 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
438 amdgpu_bo_unreserve(bo);
440 goto user_pages_done;
443 r = drm_gem_handle_create(filp, gobj, &handle);
445 goto user_pages_done;
447 args->handle = handle;
450 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
451 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
454 drm_gem_object_put(gobj);
459 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
460 struct drm_device *dev,
461 uint32_t handle, uint64_t *offset_p)
463 struct drm_gem_object *gobj;
464 struct amdgpu_bo *robj;
466 gobj = drm_gem_object_lookup(filp, handle);
470 robj = gem_to_amdgpu_bo(gobj);
471 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
472 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
473 drm_gem_object_put(gobj);
476 *offset_p = amdgpu_bo_mmap_offset(robj);
477 drm_gem_object_put(gobj);
481 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
482 struct drm_file *filp)
484 union drm_amdgpu_gem_mmap *args = data;
485 uint32_t handle = args->in.handle;
487 memset(args, 0, sizeof(*args));
488 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
492 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
494 * @timeout_ns: timeout in ns
496 * Calculate the timeout in jiffies from an absolute timeout in ns.
498 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
500 unsigned long timeout_jiffies;
503 /* clamp timeout if it's to large */
504 if (((int64_t)timeout_ns) < 0)
505 return MAX_SCHEDULE_TIMEOUT;
507 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
508 if (ktime_to_ns(timeout) < 0)
511 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
512 /* clamp timeout to avoid unsigned-> signed overflow */
513 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT)
514 return MAX_SCHEDULE_TIMEOUT - 1;
516 return timeout_jiffies;
519 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
520 struct drm_file *filp)
522 union drm_amdgpu_gem_wait_idle *args = data;
523 struct drm_gem_object *gobj;
524 struct amdgpu_bo *robj;
525 uint32_t handle = args->in.handle;
526 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
530 gobj = drm_gem_object_lookup(filp, handle);
534 robj = gem_to_amdgpu_bo(gobj);
535 ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ,
538 /* ret == 0 means not signaled,
539 * ret > 0 means signaled
540 * ret < 0 means interrupted before timeout
543 memset(args, 0, sizeof(*args));
544 args->out.status = (ret == 0);
548 drm_gem_object_put(gobj);
552 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
553 struct drm_file *filp)
555 struct drm_amdgpu_gem_metadata *args = data;
556 struct drm_gem_object *gobj;
557 struct amdgpu_bo *robj;
560 DRM_DEBUG("%d\n", args->handle);
561 gobj = drm_gem_object_lookup(filp, args->handle);
564 robj = gem_to_amdgpu_bo(gobj);
566 r = amdgpu_bo_reserve(robj, false);
567 if (unlikely(r != 0))
570 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
571 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
572 r = amdgpu_bo_get_metadata(robj, args->data.data,
573 sizeof(args->data.data),
574 &args->data.data_size_bytes,
576 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
577 if (args->data.data_size_bytes > sizeof(args->data.data)) {
581 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
583 r = amdgpu_bo_set_metadata(robj, args->data.data,
584 args->data.data_size_bytes,
589 amdgpu_bo_unreserve(robj);
591 drm_gem_object_put(gobj);
596 * amdgpu_gem_va_update_vm -update the bo_va in its VM
598 * @adev: amdgpu_device pointer
600 * @bo_va: bo_va to update
601 * @operation: map, unmap or clear
603 * Update the bo_va directly after setting its address. Errors are not
604 * vital here, so they are not reported back to userspace.
606 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
607 struct amdgpu_vm *vm,
608 struct amdgpu_bo_va *bo_va,
613 if (!amdgpu_vm_ready(vm))
616 r = amdgpu_vm_clear_freed(adev, vm, NULL);
620 if (operation == AMDGPU_VA_OP_MAP ||
621 operation == AMDGPU_VA_OP_REPLACE) {
622 r = amdgpu_vm_bo_update(adev, bo_va, false);
627 r = amdgpu_vm_update_pdes(adev, vm, false);
630 if (r && r != -ERESTARTSYS)
631 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
635 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
637 * @adev: amdgpu_device pointer
638 * @flags: GEM UAPI flags
640 * Returns the GEM UAPI flags mapped into hardware for the ASIC.
642 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
644 uint64_t pte_flag = 0;
646 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
647 pte_flag |= AMDGPU_PTE_EXECUTABLE;
648 if (flags & AMDGPU_VM_PAGE_READABLE)
649 pte_flag |= AMDGPU_PTE_READABLE;
650 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
651 pte_flag |= AMDGPU_PTE_WRITEABLE;
652 if (flags & AMDGPU_VM_PAGE_PRT)
653 pte_flag |= AMDGPU_PTE_PRT;
654 if (flags & AMDGPU_VM_PAGE_NOALLOC)
655 pte_flag |= AMDGPU_PTE_NOALLOC;
657 if (adev->gmc.gmc_funcs->map_mtype)
658 pte_flag |= amdgpu_gmc_map_mtype(adev,
659 flags & AMDGPU_VM_MTYPE_MASK);
664 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
665 struct drm_file *filp)
667 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
668 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
669 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
670 AMDGPU_VM_PAGE_NOALLOC;
671 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
674 struct drm_amdgpu_gem_va *args = data;
675 struct drm_gem_object *gobj;
676 struct amdgpu_device *adev = drm_to_adev(dev);
677 struct amdgpu_fpriv *fpriv = filp->driver_priv;
678 struct amdgpu_bo *abo;
679 struct amdgpu_bo_va *bo_va;
680 struct drm_exec exec;
685 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
687 "va_address 0x%llx is in reserved area 0x%llx\n",
688 args->va_address, AMDGPU_VA_RESERVED_SIZE);
692 if (args->va_address >= AMDGPU_GMC_HOLE_START &&
693 args->va_address < AMDGPU_GMC_HOLE_END) {
695 "va_address 0x%llx is in VA hole 0x%llx-0x%llx\n",
696 args->va_address, AMDGPU_GMC_HOLE_START,
697 AMDGPU_GMC_HOLE_END);
701 args->va_address &= AMDGPU_GMC_HOLE_MASK;
703 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
704 vm_size -= AMDGPU_VA_RESERVED_SIZE;
705 if (args->va_address + args->map_size > vm_size) {
707 "va_address 0x%llx is in top reserved area 0x%llx\n",
708 args->va_address + args->map_size, vm_size);
712 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
713 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
718 switch (args->operation) {
719 case AMDGPU_VA_OP_MAP:
720 case AMDGPU_VA_OP_UNMAP:
721 case AMDGPU_VA_OP_CLEAR:
722 case AMDGPU_VA_OP_REPLACE:
725 dev_dbg(dev->dev, "unsupported operation %d\n",
730 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
731 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
732 gobj = drm_gem_object_lookup(filp, args->handle);
735 abo = gem_to_amdgpu_bo(gobj);
741 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
742 DRM_EXEC_IGNORE_DUPLICATES, 0);
743 drm_exec_until_all_locked(&exec) {
745 r = drm_exec_lock_obj(&exec, gobj);
746 drm_exec_retry_on_contention(&exec);
751 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
752 drm_exec_retry_on_contention(&exec);
758 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
763 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
764 bo_va = fpriv->prt_va;
769 switch (args->operation) {
770 case AMDGPU_VA_OP_MAP:
771 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
772 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
773 args->offset_in_bo, args->map_size,
776 case AMDGPU_VA_OP_UNMAP:
777 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
780 case AMDGPU_VA_OP_CLEAR:
781 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
785 case AMDGPU_VA_OP_REPLACE:
786 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
787 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
788 args->offset_in_bo, args->map_size,
794 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm)
795 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
799 drm_exec_fini(&exec);
800 drm_gem_object_put(gobj);
804 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
805 struct drm_file *filp)
807 struct amdgpu_device *adev = drm_to_adev(dev);
808 struct drm_amdgpu_gem_op *args = data;
809 struct drm_gem_object *gobj;
810 struct amdgpu_vm_bo_base *base;
811 struct amdgpu_bo *robj;
814 gobj = drm_gem_object_lookup(filp, args->handle);
818 robj = gem_to_amdgpu_bo(gobj);
820 r = amdgpu_bo_reserve(robj, false);
825 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
826 struct drm_amdgpu_gem_create_in info;
827 void __user *out = u64_to_user_ptr(args->value);
829 info.bo_size = robj->tbo.base.size;
830 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
831 info.domains = robj->preferred_domains;
832 info.domain_flags = robj->flags;
833 amdgpu_bo_unreserve(robj);
834 if (copy_to_user(out, &info, sizeof(info)))
838 case AMDGPU_GEM_OP_SET_PLACEMENT:
839 if (robj->tbo.base.import_attach &&
840 args->value & AMDGPU_GEM_DOMAIN_VRAM) {
842 amdgpu_bo_unreserve(robj);
845 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
847 amdgpu_bo_unreserve(robj);
850 for (base = robj->vm_bo; base; base = base->next)
851 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
852 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
854 amdgpu_bo_unreserve(robj);
859 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
860 AMDGPU_GEM_DOMAIN_GTT |
861 AMDGPU_GEM_DOMAIN_CPU);
862 robj->allowed_domains = robj->preferred_domains;
863 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
864 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
866 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
867 amdgpu_vm_bo_invalidate(adev, robj, true);
869 amdgpu_bo_unreserve(robj);
872 amdgpu_bo_unreserve(robj);
877 drm_gem_object_put(gobj);
881 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
902 aligned += pitch_mask;
903 aligned &= ~pitch_mask;
904 return aligned * cpp;
907 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
908 struct drm_device *dev,
909 struct drm_mode_create_dumb *args)
911 struct amdgpu_device *adev = drm_to_adev(dev);
912 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
913 struct drm_gem_object *gobj;
915 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
916 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
917 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
922 * The buffer returned from this function should be cleared, but
923 * it can only be done if the ring is enabled or we'll fail to
926 if (adev->mman.buffer_funcs_enabled)
927 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
929 args->pitch = amdgpu_gem_align_pitch(adev, args->width,
930 DIV_ROUND_UP(args->bpp, 8), 0);
931 args->size = (u64)args->pitch * args->height;
932 args->size = ALIGN(args->size, PAGE_SIZE);
933 domain = amdgpu_bo_get_preferred_domain(adev,
934 amdgpu_display_supported_domains(adev, flags));
935 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
936 ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
940 r = drm_gem_handle_create(file_priv, gobj, &handle);
941 /* drop reference from allocate - handle holds it now */
942 drm_gem_object_put(gobj);
946 args->handle = handle;
950 #if defined(CONFIG_DEBUG_FS)
951 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
953 struct amdgpu_device *adev = m->private;
954 struct drm_device *dev = adev_to_drm(adev);
955 struct drm_file *file;
958 r = mutex_lock_interruptible(&dev->filelist_mutex);
962 list_for_each_entry(file, &dev->filelist, lhead) {
963 struct task_struct *task;
964 struct drm_gem_object *gobj;
969 * Although we have a valid reference on file->pid, that does
970 * not guarantee that the task_struct who called get_pid() is
971 * still alive (e.g. get_pid(current) => fork() => exit()).
972 * Therefore, we need to protect this ->comm access using RCU.
975 pid = rcu_dereference(file->pid);
976 task = pid_task(pid, PIDTYPE_TGID);
977 seq_printf(m, "pid %8d command %s:\n", pid_nr(pid),
978 task ? task->comm : "<unknown>");
981 spin_lock(&file->table_lock);
982 idr_for_each_entry(&file->object_idr, gobj, id) {
983 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
985 amdgpu_bo_print_info(id, bo, m);
987 spin_unlock(&file->table_lock);
990 mutex_unlock(&dev->filelist_mutex);
994 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
998 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
1000 #if defined(CONFIG_DEBUG_FS)
1001 struct drm_minor *minor = adev_to_drm(adev)->primary;
1002 struct dentry *root = minor->debugfs_root;
1004 debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
1005 &amdgpu_debugfs_gem_info_fops);