2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
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9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_drv.h>
27 #include <drm/drm_gem.h>
28 #include <drm/drm_vblank.h>
29 #include <drm/drm_managed.h>
30 #include "amdgpu_drv.h"
32 #include <drm/drm_pciids.h>
33 #include <linux/console.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/mmu_notifier.h>
41 #include "amdgpu_irq.h"
42 #include "amdgpu_dma_buf.h"
43 #include "amdgpu_sched.h"
45 #include "amdgpu_amdkfd.h"
47 #include "amdgpu_ras.h"
48 #include "amdgpu_xgmi.h"
52 * - 3.0.0 - initial driver
53 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
54 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
56 * - 3.3.0 - Add VM support for UVD on supported hardware.
57 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
58 * - 3.5.0 - Add support for new UVD_NO_OP register.
59 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
60 * - 3.7.0 - Add support for VCE clock list packet
61 * - 3.8.0 - Add support raster config init in the kernel
62 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
63 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
64 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
65 * - 3.12.0 - Add query for double offchip LDS buffers
66 * - 3.13.0 - Add PRT support
67 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
68 * - 3.15.0 - Export more gpu info for gfx9
69 * - 3.16.0 - Add reserved vmid support
70 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
71 * - 3.18.0 - Export gpu always on cu bitmap
72 * - 3.19.0 - Add support for UVD MJPEG decode
73 * - 3.20.0 - Add support for local BOs
74 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
75 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
76 * - 3.23.0 - Add query for VRAM lost counter
77 * - 3.24.0 - Add high priority compute support for gfx9
78 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
79 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
80 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
81 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
82 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
83 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
84 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
85 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
86 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
87 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
88 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
89 * - 3.36.0 - Allow reading more status registers on si/cik
90 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
91 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
92 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
93 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
94 * - 3.41.0 - Add video codec query
96 #define KMS_DRIVER_MAJOR 3
97 #define KMS_DRIVER_MINOR 41
98 #define KMS_DRIVER_PATCHLEVEL 0
100 int amdgpu_vram_limit;
101 int amdgpu_vis_vram_limit;
102 int amdgpu_gart_size = -1; /* auto */
103 int amdgpu_gtt_size = -1; /* auto */
104 int amdgpu_moverate = -1; /* auto */
105 int amdgpu_benchmarking;
107 int amdgpu_audio = -1;
108 int amdgpu_disp_priority;
110 int amdgpu_pcie_gen2 = -1;
112 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
114 int amdgpu_fw_load_type = -1;
115 int amdgpu_aspm = -1;
116 int amdgpu_runtime_pm = -1;
117 uint amdgpu_ip_block_mask = 0xffffffff;
118 int amdgpu_bapm = -1;
119 int amdgpu_deep_color;
120 int amdgpu_vm_size = -1;
121 int amdgpu_vm_fragment_size = -1;
122 int amdgpu_vm_block_size = -1;
123 int amdgpu_vm_fault_stop;
125 int amdgpu_vm_update_mode = -1;
126 int amdgpu_exp_hw_support;
128 int amdgpu_sched_jobs = 32;
129 int amdgpu_sched_hw_submission = 2;
130 uint amdgpu_pcie_gen_cap;
131 uint amdgpu_pcie_lane_cap;
132 uint amdgpu_cg_mask = 0xffffffff;
133 uint amdgpu_pg_mask = 0xffffffff;
134 uint amdgpu_sdma_phase_quantum = 32;
135 char *amdgpu_disable_cu = NULL;
136 char *amdgpu_virtual_display = NULL;
139 * OverDrive(bit 14) disabled by default
140 * GFX DCS(bit 19) disabled by default
142 uint amdgpu_pp_feature_mask = 0xfff7bfff;
143 uint amdgpu_force_long_training;
144 int amdgpu_job_hang_limit;
145 int amdgpu_lbpw = -1;
146 int amdgpu_compute_multipipe = -1;
147 int amdgpu_gpu_recovery = -1; /* auto */
149 uint amdgpu_smu_memory_pool_size;
150 int amdgpu_smu_pptable_id = -1;
152 * FBC (bit 0) disabled by default
153 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
154 * - With this, for multiple monitors in sync(e.g. with the same model),
155 * mclk switching will be allowed. And the mclk will be not foced to the
156 * highest. That helps saving some idle power.
157 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
158 * PSR (bit 3) disabled by default
160 uint amdgpu_dc_feature_mask = 2;
161 uint amdgpu_dc_debug_mask;
162 int amdgpu_async_gfx_ring = 1;
164 int amdgpu_discovery = -1;
166 int amdgpu_noretry = -1;
167 int amdgpu_force_asic_type = -1;
168 int amdgpu_tmz = -1; /* auto */
169 uint amdgpu_freesync_vid_mode;
170 int amdgpu_reset_method = -1; /* auto */
171 int amdgpu_num_kcq = -1;
173 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
175 struct amdgpu_mgpu_info mgpu_info = {
176 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
177 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
178 mgpu_info.delayed_reset_work,
179 amdgpu_drv_delayed_reset_work_handler, 0),
181 int amdgpu_ras_enable = -1;
182 uint amdgpu_ras_mask = 0xffffffff;
183 int amdgpu_bad_page_threshold = -1;
184 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
185 .timeout_fatal_disable = false,
186 .period = 0x23, /* default to max. timeout = 1 << 0x23 cycles */
190 * DOC: vramlimit (int)
191 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
193 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
194 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
197 * DOC: vis_vramlimit (int)
198 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
200 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
201 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
204 * DOC: gartsize (uint)
205 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
207 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
208 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
212 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
213 * otherwise 3/4 RAM size).
215 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
216 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
219 * DOC: moverate (int)
220 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
222 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
223 module_param_named(moverate, amdgpu_moverate, int, 0600);
226 * DOC: benchmark (int)
227 * Run benchmarks. The default is 0 (Skip benchmarks).
229 MODULE_PARM_DESC(benchmark, "Run benchmark");
230 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
234 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
236 MODULE_PARM_DESC(test, "Run tests");
237 module_param_named(test, amdgpu_testing, int, 0444);
241 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
243 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
244 module_param_named(audio, amdgpu_audio, int, 0444);
247 * DOC: disp_priority (int)
248 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
250 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
251 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
255 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
257 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
258 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
261 * DOC: pcie_gen2 (int)
262 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
264 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
265 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
269 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
271 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
272 module_param_named(msi, amdgpu_msi, int, 0444);
275 * DOC: lockup_timeout (string)
276 * Set GPU scheduler timeout value in ms.
278 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
279 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
280 * to the default timeout.
282 * - With one value specified, the setting will apply to all non-compute jobs.
283 * - With multiple values specified, the first one will be for GFX.
284 * The second one is for Compute. The third and fourth ones are
285 * for SDMA and Video.
287 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
288 * jobs is 10000. And there is no timeout enforced on compute jobs.
290 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; "
291 "for passthrough or sriov, 10000 for all jobs."
292 " 0: keep default value. negative: infinity timeout), "
293 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
294 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
295 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
299 * Override for dynamic power management setting
300 * (0 = disable, 1 = enable)
301 * The default is -1 (auto).
303 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
304 module_param_named(dpm, amdgpu_dpm, int, 0444);
307 * DOC: fw_load_type (int)
308 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
310 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
311 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
315 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
317 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
318 module_param_named(aspm, amdgpu_aspm, int, 0444);
322 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
323 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
325 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)");
326 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
329 * DOC: ip_block_mask (uint)
330 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
331 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
332 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
333 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
335 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
336 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
340 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
341 * The default -1 (auto, enabled)
343 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
344 module_param_named(bapm, amdgpu_bapm, int, 0444);
347 * DOC: deep_color (int)
348 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
350 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
351 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
355 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
357 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
358 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
361 * DOC: vm_fragment_size (int)
362 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
364 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
365 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
368 * DOC: vm_block_size (int)
369 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
371 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
372 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
375 * DOC: vm_fault_stop (int)
376 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
378 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
379 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
382 * DOC: vm_debug (int)
383 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
385 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
386 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
389 * DOC: vm_update_mode (int)
390 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
391 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
393 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
394 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
397 * DOC: exp_hw_support (int)
398 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
400 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
401 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
405 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
407 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
408 module_param_named(dc, amdgpu_dc, int, 0444);
411 * DOC: sched_jobs (int)
412 * Override the max number of jobs supported in the sw queue. The default is 32.
414 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
415 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
418 * DOC: sched_hw_submission (int)
419 * Override the max number of HW submissions. The default is 2.
421 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
422 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
425 * DOC: ppfeaturemask (hexint)
426 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
427 * The default is the current set of stable power features.
429 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
430 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
433 * DOC: forcelongtraining (uint)
434 * Force long memory training in resume.
435 * The default is zero, indicates short training in resume.
437 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
438 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
441 * DOC: pcie_gen_cap (uint)
442 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
443 * The default is 0 (automatic for each asic).
445 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
446 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
449 * DOC: pcie_lane_cap (uint)
450 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
451 * The default is 0 (automatic for each asic).
453 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
454 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
457 * DOC: cg_mask (uint)
458 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
459 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
461 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
462 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
465 * DOC: pg_mask (uint)
466 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
467 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
469 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
470 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
473 * DOC: sdma_phase_quantum (uint)
474 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
476 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
477 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
480 * DOC: disable_cu (charp)
481 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
483 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
484 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
487 * DOC: virtual_display (charp)
488 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
489 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
490 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
491 * device at 26:00.0. The default is NULL.
493 MODULE_PARM_DESC(virtual_display,
494 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
495 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
498 * DOC: job_hang_limit (int)
499 * Set how much time allow a job hang and not drop it. The default is 0.
501 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
502 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
506 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
508 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
509 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
511 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
512 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
515 * DOC: gpu_recovery (int)
516 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
518 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
519 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
522 * DOC: emu_mode (int)
523 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
525 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
526 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
529 * DOC: ras_enable (int)
530 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
532 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
533 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
536 * DOC: ras_mask (uint)
537 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
538 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
540 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
541 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
544 * DOC: timeout_fatal_disable (bool)
545 * Disable Watchdog timeout fatal error event
547 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
548 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
551 * DOC: timeout_period (uint)
552 * Modify the watchdog timeout max_cycles as (1 << period)
554 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (1 to 0x23(default), timeout maxCycles = (1 << period)");
555 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
558 * DOC: si_support (int)
559 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
560 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
561 * otherwise using amdgpu driver.
563 #ifdef CONFIG_DRM_AMDGPU_SI
565 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
566 int amdgpu_si_support = 0;
567 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
569 int amdgpu_si_support = 1;
570 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
573 module_param_named(si_support, amdgpu_si_support, int, 0444);
577 * DOC: cik_support (int)
578 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
579 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
580 * otherwise using amdgpu driver.
582 #ifdef CONFIG_DRM_AMDGPU_CIK
584 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
585 int amdgpu_cik_support = 0;
586 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
588 int amdgpu_cik_support = 1;
589 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
592 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
596 * DOC: smu_memory_pool_size (uint)
597 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
598 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
600 MODULE_PARM_DESC(smu_memory_pool_size,
601 "reserve gtt for smu debug usage, 0 = disable,"
602 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
603 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
606 * DOC: async_gfx_ring (int)
607 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
609 MODULE_PARM_DESC(async_gfx_ring,
610 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
611 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
615 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
617 MODULE_PARM_DESC(mcbp,
618 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
619 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
622 * DOC: discovery (int)
623 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
624 * (-1 = auto (default), 0 = disabled, 1 = enabled)
626 MODULE_PARM_DESC(discovery,
627 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
628 module_param_named(discovery, amdgpu_discovery, int, 0444);
632 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
633 * (0 = disabled (default), 1 = enabled)
635 MODULE_PARM_DESC(mes,
636 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
637 module_param_named(mes, amdgpu_mes, int, 0444);
641 * Disable retry faults in the GPU memory controller.
642 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
644 MODULE_PARM_DESC(noretry,
645 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
646 module_param_named(noretry, amdgpu_noretry, int, 0644);
649 * DOC: force_asic_type (int)
650 * A non negative value used to specify the asic type for all supported GPUs.
652 MODULE_PARM_DESC(force_asic_type,
653 "A non negative value used to specify the asic type for all supported GPUs");
654 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
658 #ifdef CONFIG_HSA_AMD
660 * DOC: sched_policy (int)
661 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
662 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
663 * assigns queues to HQDs.
665 int sched_policy = KFD_SCHED_POLICY_HWS;
666 module_param(sched_policy, int, 0444);
667 MODULE_PARM_DESC(sched_policy,
668 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
671 * DOC: hws_max_conc_proc (int)
672 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
673 * number of VMIDs assigned to the HWS, which is also the default.
675 int hws_max_conc_proc = 8;
676 module_param(hws_max_conc_proc, int, 0444);
677 MODULE_PARM_DESC(hws_max_conc_proc,
678 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
681 * DOC: cwsr_enable (int)
682 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
683 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
687 module_param(cwsr_enable, int, 0444);
688 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
691 * DOC: max_num_of_queues_per_device (int)
692 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
695 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
696 module_param(max_num_of_queues_per_device, int, 0444);
697 MODULE_PARM_DESC(max_num_of_queues_per_device,
698 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
701 * DOC: send_sigterm (int)
702 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
703 * but just print errors on dmesg. Setting 1 enables sending sigterm.
706 module_param(send_sigterm, int, 0444);
707 MODULE_PARM_DESC(send_sigterm,
708 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
711 * DOC: debug_largebar (int)
712 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
713 * system. This limits the VRAM size reported to ROCm applications to the visible
714 * size, usually 256MB.
715 * Default value is 0, diabled.
718 module_param(debug_largebar, int, 0444);
719 MODULE_PARM_DESC(debug_largebar,
720 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
723 * DOC: ignore_crat (int)
724 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
725 * table to get information about AMD APUs. This option can serve as a workaround on
726 * systems with a broken CRAT table.
728 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
732 module_param(ignore_crat, int, 0444);
733 MODULE_PARM_DESC(ignore_crat,
734 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
737 * DOC: halt_if_hws_hang (int)
738 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
739 * Setting 1 enables halt on hang.
741 int halt_if_hws_hang;
742 module_param(halt_if_hws_hang, int, 0644);
743 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
746 * DOC: hws_gws_support(bool)
747 * Assume that HWS supports GWS barriers regardless of what firmware version
748 * check says. Default value: false (rely on MEC2 firmware version check).
750 bool hws_gws_support;
751 module_param(hws_gws_support, bool, 0444);
752 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
755 * DOC: queue_preemption_timeout_ms (int)
756 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
758 int queue_preemption_timeout_ms = 9000;
759 module_param(queue_preemption_timeout_ms, int, 0644);
760 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
763 * DOC: debug_evictions(bool)
764 * Enable extra debug messages to help determine the cause of evictions
766 bool debug_evictions;
767 module_param(debug_evictions, bool, 0644);
768 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
771 * DOC: no_system_mem_limit(bool)
772 * Disable system memory limit, to support multiple process shared memory
774 bool no_system_mem_limit;
775 module_param(no_system_mem_limit, bool, 0644);
776 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
779 * DOC: no_queue_eviction_on_vm_fault (int)
780 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
782 int amdgpu_no_queue_eviction_on_vm_fault = 0;
783 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
784 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
788 * DOC: dcfeaturemask (uint)
789 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
790 * The default is the current set of stable display features.
792 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
793 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
796 * DOC: dcdebugmask (uint)
797 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
799 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
800 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
803 * DOC: abmlevel (uint)
804 * Override the default ABM (Adaptive Backlight Management) level used for DC
805 * enabled hardware. Requires DMCU to be supported and loaded.
806 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
807 * default. Values 1-4 control the maximum allowable brightness reduction via
808 * the ABM algorithm, with 1 being the least reduction and 4 being the most
811 * Defaults to 0, or disabled. Userspace can still override this level later
814 uint amdgpu_dm_abm_level;
815 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
816 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
818 int amdgpu_backlight = -1;
819 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
820 module_param_named(backlight, amdgpu_backlight, bint, 0444);
824 * Trusted Memory Zone (TMZ) is a method to protect data being written
825 * to or read from memory.
827 * The default value: 0 (off). TODO: change to auto till it is completed.
829 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
830 module_param_named(tmz, amdgpu_tmz, int, 0444);
833 * DOC: freesync_video (uint)
834 * Enabled the optimization to adjust front porch timing to achieve seamless mode change experience
835 * when setting a freesync supported mode for which full modeset is not needed.
836 * The default value: 0 (off).
840 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
841 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
844 * DOC: reset_method (int)
845 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci)
847 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)");
848 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
851 * DOC: bad_page_threshold (int)
852 * Bad page threshold is to specify the threshold value of faulty pages
853 * detected by RAS ECC, that may result in GPU entering bad status if total
854 * faulty pages by ECC exceed threshold value and leave it for user's further
857 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)");
858 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
860 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
861 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
864 * DOC: smu_pptable_id (int)
865 * Used to override pptable id. id = 0 use VBIOS pptable.
866 * id > 0 use the soft pptable with specicfied id.
868 MODULE_PARM_DESC(smu_pptable_id,
869 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
870 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
872 static const struct pci_device_id pciidlist[] = {
873 #ifdef CONFIG_DRM_AMDGPU_SI
874 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
875 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
876 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
877 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
878 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
879 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
880 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
881 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
882 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
883 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
884 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
885 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
886 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
887 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
888 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
889 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
890 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
891 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
892 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
893 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
894 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
895 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
896 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
897 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
898 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
899 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
900 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
901 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
902 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
903 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
904 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
905 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
906 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
907 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
908 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
909 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
910 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
911 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
912 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
913 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
914 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
915 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
916 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
917 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
918 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
919 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
920 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
921 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
922 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
923 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
924 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
925 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
926 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
927 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
928 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
929 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
930 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
931 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
932 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
933 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
934 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
935 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
936 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
937 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
938 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
939 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
940 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
941 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
942 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
943 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
944 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
945 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
947 #ifdef CONFIG_DRM_AMDGPU_CIK
949 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
950 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
951 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
952 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
953 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
954 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
955 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
956 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
957 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
958 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
959 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
960 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
961 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
962 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
963 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
964 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
965 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
966 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
967 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
968 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
969 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
970 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
972 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
973 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
974 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
975 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
976 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
977 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
978 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
979 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
980 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
981 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
982 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
984 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
985 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
986 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
987 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
988 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
989 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
990 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
991 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
992 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
993 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
994 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
995 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
997 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
998 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
999 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1000 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1001 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1002 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1003 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1004 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1005 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1006 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1007 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1008 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1009 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1010 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1011 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1012 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1014 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1015 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1016 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1017 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1018 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1019 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1020 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1021 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1022 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1023 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1024 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1025 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1026 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1027 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1028 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1029 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1032 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1033 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1034 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1035 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1036 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1038 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1039 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1040 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1041 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1042 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1043 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1044 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1045 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1046 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1048 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1049 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1051 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1052 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1053 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1054 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1055 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1057 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1059 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1060 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1061 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1062 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1063 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1064 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1065 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1066 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1067 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1069 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1070 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1071 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1072 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1073 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1074 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1075 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1076 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1077 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1078 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1079 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1080 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1081 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1083 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1084 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1085 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1086 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1087 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1088 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1089 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1090 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1092 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1093 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1094 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1096 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1097 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1098 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1099 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1100 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1101 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1102 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1103 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1104 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1105 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1106 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1107 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1108 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1109 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1110 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1112 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1113 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1114 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1115 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1116 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1118 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1119 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1120 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1121 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1122 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1123 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1124 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1126 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1127 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1129 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1130 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1131 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1132 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1134 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1135 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1136 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1137 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1138 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1139 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1140 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1141 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1143 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1144 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1145 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1146 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1149 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1150 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1151 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1154 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1155 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1157 /* Sienna_Cichlid */
1158 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1159 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1160 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1161 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1162 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1163 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1164 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1165 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1168 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1171 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1172 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1173 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1174 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1176 /* DIMGREY_CAVEFISH */
1177 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1178 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1179 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1180 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1183 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1184 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1185 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1190 MODULE_DEVICE_TABLE(pci, pciidlist);
1192 static const struct drm_driver amdgpu_kms_driver;
1194 static int amdgpu_pci_probe(struct pci_dev *pdev,
1195 const struct pci_device_id *ent)
1197 struct drm_device *ddev;
1198 struct amdgpu_device *adev;
1199 unsigned long flags = ent->driver_data;
1201 bool supports_atomic = false;
1203 if (!amdgpu_virtual_display &&
1204 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
1205 supports_atomic = true;
1207 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
1208 DRM_INFO("This hardware requires experimental hardware support.\n"
1209 "See modparam exp_hw_support\n");
1213 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
1214 * however, SME requires an indirect IOMMU mapping because the encryption
1215 * bit is beyond the DMA mask of the chip.
1217 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
1218 dev_info(&pdev->dev,
1219 "SME is not compatible with RAVEN\n");
1223 #ifdef CONFIG_DRM_AMDGPU_SI
1224 if (!amdgpu_si_support) {
1225 switch (flags & AMD_ASIC_MASK) {
1231 dev_info(&pdev->dev,
1232 "SI support provided by radeon.\n");
1233 dev_info(&pdev->dev,
1234 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
1240 #ifdef CONFIG_DRM_AMDGPU_CIK
1241 if (!amdgpu_cik_support) {
1242 switch (flags & AMD_ASIC_MASK) {
1248 dev_info(&pdev->dev,
1249 "CIK support provided by radeon.\n");
1250 dev_info(&pdev->dev,
1251 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
1258 /* Get rid of things like offb */
1259 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb");
1263 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
1265 return PTR_ERR(adev);
1267 adev->dev = &pdev->dev;
1269 ddev = adev_to_drm(adev);
1271 if (!supports_atomic)
1272 ddev->driver_features &= ~DRIVER_ATOMIC;
1274 ret = pci_enable_device(pdev);
1278 pci_set_drvdata(pdev, ddev);
1280 ret = amdgpu_driver_load_kms(adev, ent->driver_data);
1285 ret = drm_dev_register(ddev, ent->driver_data);
1286 if (ret == -EAGAIN && ++retry <= 3) {
1287 DRM_INFO("retry init %d\n", retry);
1288 /* Don't request EX mode too frequently which is attacking */
1295 ret = amdgpu_debugfs_init(adev);
1297 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
1302 pci_disable_device(pdev);
1307 amdgpu_pci_remove(struct pci_dev *pdev)
1309 struct drm_device *dev = pci_get_drvdata(pdev);
1312 if (THIS_MODULE->state != MODULE_STATE_GOING)
1314 DRM_ERROR("Hotplug removal is not supported\n");
1315 drm_dev_unplug(dev);
1316 amdgpu_driver_unload_kms(dev);
1317 pci_disable_device(pdev);
1318 pci_set_drvdata(pdev, NULL);
1322 amdgpu_pci_shutdown(struct pci_dev *pdev)
1324 struct drm_device *dev = pci_get_drvdata(pdev);
1325 struct amdgpu_device *adev = drm_to_adev(dev);
1327 if (amdgpu_ras_intr_triggered())
1330 /* if we are running in a VM, make sure the device
1331 * torn down properly on reboot/shutdown.
1332 * unfortunately we can't detect certain
1333 * hypervisors so just do this all the time.
1335 if (!amdgpu_passthrough(adev))
1336 adev->mp1_state = PP_MP1_STATE_UNLOAD;
1337 adev->in_poweroff_reboot_com = true;
1338 amdgpu_device_ip_suspend(adev);
1339 adev->in_poweroff_reboot_com = false;
1340 adev->mp1_state = PP_MP1_STATE_NONE;
1344 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
1346 * @work: work_struct.
1348 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
1350 struct list_head device_list;
1351 struct amdgpu_device *adev;
1353 bool need_full_reset = true;
1355 mutex_lock(&mgpu_info.mutex);
1356 if (mgpu_info.pending_reset == true) {
1357 mutex_unlock(&mgpu_info.mutex);
1360 mgpu_info.pending_reset = true;
1361 mutex_unlock(&mgpu_info.mutex);
1363 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1364 adev = mgpu_info.gpu_ins[i].adev;
1365 r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset);
1367 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
1368 r, adev_to_drm(adev)->unique);
1370 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
1373 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1374 adev = mgpu_info.gpu_ins[i].adev;
1375 flush_work(&adev->xgmi_reset_work);
1376 adev->gmc.xgmi.pending_reset = false;
1379 /* reset function will rebuild the xgmi hive info , clear it now */
1380 for (i = 0; i < mgpu_info.num_dgpu; i++)
1381 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
1383 INIT_LIST_HEAD(&device_list);
1385 for (i = 0; i < mgpu_info.num_dgpu; i++)
1386 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
1388 /* unregister the GPU first, reset function will add them back */
1389 list_for_each_entry(adev, &device_list, reset_list)
1390 amdgpu_unregister_gpu_instance(adev);
1392 r = amdgpu_do_asic_reset(NULL, &device_list, &need_full_reset, true);
1394 DRM_ERROR("reinit gpus failure");
1397 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1398 adev = mgpu_info.gpu_ins[i].adev;
1399 if (!adev->kfd.init_complete)
1400 amdgpu_amdkfd_device_init(adev);
1401 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1406 static int amdgpu_pmops_suspend(struct device *dev)
1408 struct drm_device *drm_dev = dev_get_drvdata(dev);
1410 return amdgpu_device_suspend(drm_dev, true);
1413 static int amdgpu_pmops_resume(struct device *dev)
1415 struct drm_device *drm_dev = dev_get_drvdata(dev);
1417 return amdgpu_device_resume(drm_dev, true);
1420 static int amdgpu_pmops_freeze(struct device *dev)
1422 struct drm_device *drm_dev = dev_get_drvdata(dev);
1423 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1426 adev->in_hibernate = true;
1427 r = amdgpu_device_suspend(drm_dev, true);
1428 adev->in_hibernate = false;
1431 return amdgpu_asic_reset(adev);
1434 static int amdgpu_pmops_thaw(struct device *dev)
1436 struct drm_device *drm_dev = dev_get_drvdata(dev);
1438 return amdgpu_device_resume(drm_dev, true);
1441 static int amdgpu_pmops_poweroff(struct device *dev)
1443 struct drm_device *drm_dev = dev_get_drvdata(dev);
1444 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1447 adev->in_poweroff_reboot_com = true;
1448 r = amdgpu_device_suspend(drm_dev, true);
1449 adev->in_poweroff_reboot_com = false;
1453 static int amdgpu_pmops_restore(struct device *dev)
1455 struct drm_device *drm_dev = dev_get_drvdata(dev);
1457 return amdgpu_device_resume(drm_dev, true);
1460 static int amdgpu_pmops_runtime_suspend(struct device *dev)
1462 struct pci_dev *pdev = to_pci_dev(dev);
1463 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1464 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1468 pm_runtime_forbid(dev);
1472 /* wait for all rings to drain before suspending */
1473 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1474 struct amdgpu_ring *ring = adev->rings[i];
1475 if (ring && ring->sched.ready) {
1476 ret = amdgpu_fence_wait_empty(ring);
1482 adev->in_runpm = true;
1483 if (amdgpu_device_supports_atpx(drm_dev))
1484 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1486 ret = amdgpu_device_suspend(drm_dev, false);
1488 adev->in_runpm = false;
1492 if (amdgpu_device_supports_atpx(drm_dev)) {
1493 /* Only need to handle PCI state in the driver for ATPX
1494 * PCI core handles it for _PR3.
1496 if (!amdgpu_is_atpx_hybrid()) {
1497 amdgpu_device_cache_pci_state(pdev);
1498 pci_disable_device(pdev);
1499 pci_ignore_hotplug(pdev);
1500 pci_set_power_state(pdev, PCI_D3cold);
1502 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1503 } else if (amdgpu_device_supports_baco(drm_dev)) {
1504 amdgpu_device_baco_enter(drm_dev);
1510 static int amdgpu_pmops_runtime_resume(struct device *dev)
1512 struct pci_dev *pdev = to_pci_dev(dev);
1513 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1514 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1520 if (amdgpu_device_supports_atpx(drm_dev)) {
1521 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1523 /* Only need to handle PCI state in the driver for ATPX
1524 * PCI core handles it for _PR3.
1526 if (!amdgpu_is_atpx_hybrid()) {
1527 pci_set_power_state(pdev, PCI_D0);
1528 amdgpu_device_load_pci_state(pdev);
1529 ret = pci_enable_device(pdev);
1533 pci_set_master(pdev);
1534 } else if (amdgpu_device_supports_boco(drm_dev)) {
1535 /* Only need to handle PCI state in the driver for ATPX
1536 * PCI core handles it for _PR3.
1538 pci_set_master(pdev);
1539 } else if (amdgpu_device_supports_baco(drm_dev)) {
1540 amdgpu_device_baco_exit(drm_dev);
1542 ret = amdgpu_device_resume(drm_dev, false);
1543 if (amdgpu_device_supports_atpx(drm_dev))
1544 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1545 adev->in_runpm = false;
1549 static int amdgpu_pmops_runtime_idle(struct device *dev)
1551 struct drm_device *drm_dev = dev_get_drvdata(dev);
1552 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1553 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1557 pm_runtime_forbid(dev);
1561 if (amdgpu_device_has_dc_support(adev)) {
1562 struct drm_crtc *crtc;
1564 drm_modeset_lock_all(drm_dev);
1566 drm_for_each_crtc(crtc, drm_dev) {
1567 if (crtc->state->active) {
1573 drm_modeset_unlock_all(drm_dev);
1576 struct drm_connector *list_connector;
1577 struct drm_connector_list_iter iter;
1579 mutex_lock(&drm_dev->mode_config.mutex);
1580 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
1582 drm_connector_list_iter_begin(drm_dev, &iter);
1583 drm_for_each_connector_iter(list_connector, &iter) {
1584 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
1590 drm_connector_list_iter_end(&iter);
1592 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
1593 mutex_unlock(&drm_dev->mode_config.mutex);
1597 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1599 pm_runtime_mark_last_busy(dev);
1600 pm_runtime_autosuspend(dev);
1604 long amdgpu_drm_ioctl(struct file *filp,
1605 unsigned int cmd, unsigned long arg)
1607 struct drm_file *file_priv = filp->private_data;
1608 struct drm_device *dev;
1610 dev = file_priv->minor->dev;
1611 ret = pm_runtime_get_sync(dev->dev);
1615 ret = drm_ioctl(filp, cmd, arg);
1617 pm_runtime_mark_last_busy(dev->dev);
1619 pm_runtime_put_autosuspend(dev->dev);
1623 static const struct dev_pm_ops amdgpu_pm_ops = {
1624 .suspend = amdgpu_pmops_suspend,
1625 .resume = amdgpu_pmops_resume,
1626 .freeze = amdgpu_pmops_freeze,
1627 .thaw = amdgpu_pmops_thaw,
1628 .poweroff = amdgpu_pmops_poweroff,
1629 .restore = amdgpu_pmops_restore,
1630 .runtime_suspend = amdgpu_pmops_runtime_suspend,
1631 .runtime_resume = amdgpu_pmops_runtime_resume,
1632 .runtime_idle = amdgpu_pmops_runtime_idle,
1635 static int amdgpu_flush(struct file *f, fl_owner_t id)
1637 struct drm_file *file_priv = f->private_data;
1638 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1639 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
1641 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
1642 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
1644 return timeout >= 0 ? 0 : timeout;
1647 static const struct file_operations amdgpu_driver_kms_fops = {
1648 .owner = THIS_MODULE,
1650 .flush = amdgpu_flush,
1651 .release = drm_release,
1652 .unlocked_ioctl = amdgpu_drm_ioctl,
1653 .mmap = amdgpu_mmap,
1656 #ifdef CONFIG_COMPAT
1657 .compat_ioctl = amdgpu_kms_compat_ioctl,
1661 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
1663 struct drm_file *file;
1668 if (filp->f_op != &amdgpu_driver_kms_fops) {
1672 file = filp->private_data;
1673 *fpriv = file->driver_priv;
1677 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1678 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1679 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1680 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1681 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1682 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1683 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1685 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1686 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1687 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1688 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1689 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1690 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1691 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1692 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1693 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1694 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1697 static const struct drm_driver amdgpu_kms_driver = {
1701 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
1702 DRIVER_SYNCOBJ_TIMELINE,
1703 .open = amdgpu_driver_open_kms,
1704 .postclose = amdgpu_driver_postclose_kms,
1705 .lastclose = amdgpu_driver_lastclose_kms,
1706 .irq_handler = amdgpu_irq_handler,
1707 .ioctls = amdgpu_ioctls_kms,
1708 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
1709 .dumb_create = amdgpu_mode_dumb_create,
1710 .dumb_map_offset = amdgpu_mode_dumb_mmap,
1711 .fops = &amdgpu_driver_kms_fops,
1713 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1714 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1715 .gem_prime_import = amdgpu_gem_prime_import,
1716 .gem_prime_mmap = amdgpu_gem_prime_mmap,
1718 .name = DRIVER_NAME,
1719 .desc = DRIVER_DESC,
1720 .date = DRIVER_DATE,
1721 .major = KMS_DRIVER_MAJOR,
1722 .minor = KMS_DRIVER_MINOR,
1723 .patchlevel = KMS_DRIVER_PATCHLEVEL,
1726 static struct pci_error_handlers amdgpu_pci_err_handler = {
1727 .error_detected = amdgpu_pci_error_detected,
1728 .mmio_enabled = amdgpu_pci_mmio_enabled,
1729 .slot_reset = amdgpu_pci_slot_reset,
1730 .resume = amdgpu_pci_resume,
1733 static struct pci_driver amdgpu_kms_pci_driver = {
1734 .name = DRIVER_NAME,
1735 .id_table = pciidlist,
1736 .probe = amdgpu_pci_probe,
1737 .remove = amdgpu_pci_remove,
1738 .shutdown = amdgpu_pci_shutdown,
1739 .driver.pm = &amdgpu_pm_ops,
1740 .err_handler = &amdgpu_pci_err_handler,
1743 static int __init amdgpu_init(void)
1747 if (vgacon_text_force()) {
1748 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1752 r = amdgpu_sync_init();
1756 r = amdgpu_fence_slab_init();
1760 DRM_INFO("amdgpu kernel modesetting enabled.\n");
1761 amdgpu_register_atpx_handler();
1763 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
1764 amdgpu_amdkfd_init();
1766 /* let modprobe override vga console setting */
1767 return pci_register_driver(&amdgpu_kms_pci_driver);
1776 static void __exit amdgpu_exit(void)
1778 amdgpu_amdkfd_fini();
1779 pci_unregister_driver(&amdgpu_kms_pci_driver);
1780 amdgpu_unregister_atpx_handler();
1782 amdgpu_fence_slab_fini();
1783 mmu_notifier_synchronize();
1786 module_init(amdgpu_init);
1787 module_exit(amdgpu_exit);
1789 MODULE_AUTHOR(DRIVER_AUTHOR);
1790 MODULE_DESCRIPTION(DRIVER_DESC);
1791 MODULE_LICENSE("GPL and additional rights");