2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_aperture.h>
27 #include <drm/drm_drv.h>
28 #include <drm/drm_gem.h>
29 #include <drm/drm_vblank.h>
30 #include <drm/drm_managed.h>
31 #include "amdgpu_drv.h"
33 #include <drm/drm_pciids.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/suspend.h>
40 #include <linux/cc_platform.h>
44 #include "amdgpu_irq.h"
45 #include "amdgpu_dma_buf.h"
46 #include "amdgpu_sched.h"
47 #include "amdgpu_fdinfo.h"
48 #include "amdgpu_amdkfd.h"
50 #include "amdgpu_ras.h"
51 #include "amdgpu_xgmi.h"
52 #include "amdgpu_reset.h"
56 * - 3.0.0 - initial driver
57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
60 * - 3.3.0 - Add VM support for UVD on supported hardware.
61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
62 * - 3.5.0 - Add support for new UVD_NO_OP register.
63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
64 * - 3.7.0 - Add support for VCE clock list packet
65 * - 3.8.0 - Add support raster config init in the kernel
66 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
69 * - 3.12.0 - Add query for double offchip LDS buffers
70 * - 3.13.0 - Add PRT support
71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
72 * - 3.15.0 - Export more gpu info for gfx9
73 * - 3.16.0 - Add reserved vmid support
74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
75 * - 3.18.0 - Export gpu always on cu bitmap
76 * - 3.19.0 - Add support for UVD MJPEG decode
77 * - 3.20.0 - Add support for local BOs
78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
80 * - 3.23.0 - Add query for VRAM lost counter
81 * - 3.24.0 - Add high priority compute support for gfx9
82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
93 * - 3.36.0 - Allow reading more status registers on si/cik
94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
98 * - 3.41.0 - Add video codec query
99 * - 3.42.0 - Add 16bpc fixed point display support
100 * - 3.43.0 - Add device hot plug/unplug support
101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
102 * - 3.45.0 - Add context ioctl stable pstate interface
104 #define KMS_DRIVER_MAJOR 3
105 #define KMS_DRIVER_MINOR 45
106 #define KMS_DRIVER_PATCHLEVEL 0
108 int amdgpu_vram_limit;
109 int amdgpu_vis_vram_limit;
110 int amdgpu_gart_size = -1; /* auto */
111 int amdgpu_gtt_size = -1; /* auto */
112 int amdgpu_moverate = -1; /* auto */
113 int amdgpu_benchmarking;
115 int amdgpu_audio = -1;
116 int amdgpu_disp_priority;
118 int amdgpu_pcie_gen2 = -1;
120 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
122 int amdgpu_fw_load_type = -1;
123 int amdgpu_aspm = -1;
124 int amdgpu_runtime_pm = -1;
125 uint amdgpu_ip_block_mask = 0xffffffff;
126 int amdgpu_bapm = -1;
127 int amdgpu_deep_color;
128 int amdgpu_vm_size = -1;
129 int amdgpu_vm_fragment_size = -1;
130 int amdgpu_vm_block_size = -1;
131 int amdgpu_vm_fault_stop;
133 int amdgpu_vm_update_mode = -1;
134 int amdgpu_exp_hw_support;
136 int amdgpu_sched_jobs = 32;
137 int amdgpu_sched_hw_submission = 2;
138 uint amdgpu_pcie_gen_cap;
139 uint amdgpu_pcie_lane_cap;
140 uint amdgpu_cg_mask = 0xffffffff;
141 uint amdgpu_pg_mask = 0xffffffff;
142 uint amdgpu_sdma_phase_quantum = 32;
143 char *amdgpu_disable_cu = NULL;
144 char *amdgpu_virtual_display = NULL;
147 * OverDrive(bit 14) disabled by default
148 * GFX DCS(bit 19) disabled by default
150 uint amdgpu_pp_feature_mask = 0xfff7bfff;
151 uint amdgpu_force_long_training;
152 int amdgpu_job_hang_limit;
153 int amdgpu_lbpw = -1;
154 int amdgpu_compute_multipipe = -1;
155 int amdgpu_gpu_recovery = -1; /* auto */
157 uint amdgpu_smu_memory_pool_size;
158 int amdgpu_smu_pptable_id = -1;
160 * FBC (bit 0) disabled by default
161 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
162 * - With this, for multiple monitors in sync(e.g. with the same model),
163 * mclk switching will be allowed. And the mclk will be not foced to the
164 * highest. That helps saving some idle power.
165 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
166 * PSR (bit 3) disabled by default
167 * EDP NO POWER SEQUENCING (bit 4) disabled by default
169 uint amdgpu_dc_feature_mask = 2;
170 uint amdgpu_dc_debug_mask;
171 int amdgpu_async_gfx_ring = 1;
173 int amdgpu_discovery = -1;
175 int amdgpu_noretry = -1;
176 int amdgpu_force_asic_type = -1;
177 int amdgpu_tmz = -1; /* auto */
178 int amdgpu_reset_method = -1; /* auto */
179 int amdgpu_num_kcq = -1;
180 int amdgpu_smartshift_bias;
182 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
184 struct amdgpu_mgpu_info mgpu_info = {
185 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
186 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
187 mgpu_info.delayed_reset_work,
188 amdgpu_drv_delayed_reset_work_handler, 0),
190 int amdgpu_ras_enable = -1;
191 uint amdgpu_ras_mask = 0xffffffff;
192 int amdgpu_bad_page_threshold = -1;
193 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
194 .timeout_fatal_disable = false,
195 .period = 0x0, /* default to 0x0 (timeout disable) */
199 * DOC: vramlimit (int)
200 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
202 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
203 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
206 * DOC: vis_vramlimit (int)
207 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
209 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
210 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
213 * DOC: gartsize (uint)
214 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
216 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
217 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
221 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
222 * otherwise 3/4 RAM size).
224 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
225 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
228 * DOC: moverate (int)
229 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
231 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
232 module_param_named(moverate, amdgpu_moverate, int, 0600);
235 * DOC: benchmark (int)
236 * Run benchmarks. The default is 0 (Skip benchmarks).
238 MODULE_PARM_DESC(benchmark, "Run benchmark");
239 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
243 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
245 MODULE_PARM_DESC(test, "Run tests");
246 module_param_named(test, amdgpu_testing, int, 0444);
250 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
252 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
253 module_param_named(audio, amdgpu_audio, int, 0444);
256 * DOC: disp_priority (int)
257 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
259 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
260 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
264 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
266 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
267 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
270 * DOC: pcie_gen2 (int)
271 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
273 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
274 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
278 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
280 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
281 module_param_named(msi, amdgpu_msi, int, 0444);
284 * DOC: lockup_timeout (string)
285 * Set GPU scheduler timeout value in ms.
287 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
288 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
289 * to the default timeout.
291 * - With one value specified, the setting will apply to all non-compute jobs.
292 * - With multiple values specified, the first one will be for GFX.
293 * The second one is for Compute. The third and fourth ones are
294 * for SDMA and Video.
296 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
297 * jobs is 10000. The timeout for compute is 60000.
299 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
300 "for passthrough or sriov, 10000 for all jobs."
301 " 0: keep default value. negative: infinity timeout), "
302 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
303 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
304 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
308 * Override for dynamic power management setting
309 * (0 = disable, 1 = enable)
310 * The default is -1 (auto).
312 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
313 module_param_named(dpm, amdgpu_dpm, int, 0444);
316 * DOC: fw_load_type (int)
317 * Set different firmware loading type for debugging, if supported.
318 * Set to 0 to force direct loading if supported by the ASIC. Set
319 * to -1 to select the default loading mode for the ASIC, as defined
320 * by the driver. The default is -1 (auto).
322 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = force direct if supported, -1 = auto)");
323 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
327 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
329 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
330 module_param_named(aspm, amdgpu_aspm, int, 0444);
334 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
335 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
336 * Setting the value to 0 disables this functionality.
338 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
339 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
342 * DOC: ip_block_mask (uint)
343 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
344 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
345 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
346 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
348 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
349 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
353 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
354 * The default -1 (auto, enabled)
356 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
357 module_param_named(bapm, amdgpu_bapm, int, 0444);
360 * DOC: deep_color (int)
361 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
363 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
364 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
368 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
370 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
371 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
374 * DOC: vm_fragment_size (int)
375 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
377 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
378 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
381 * DOC: vm_block_size (int)
382 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
384 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
385 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
388 * DOC: vm_fault_stop (int)
389 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
391 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
392 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
395 * DOC: vm_debug (int)
396 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
398 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
399 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
402 * DOC: vm_update_mode (int)
403 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
404 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
406 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
407 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
410 * DOC: exp_hw_support (int)
411 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
413 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
414 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
418 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
420 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
421 module_param_named(dc, amdgpu_dc, int, 0444);
424 * DOC: sched_jobs (int)
425 * Override the max number of jobs supported in the sw queue. The default is 32.
427 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
428 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
431 * DOC: sched_hw_submission (int)
432 * Override the max number of HW submissions. The default is 2.
434 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
435 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
438 * DOC: ppfeaturemask (hexint)
439 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
440 * The default is the current set of stable power features.
442 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
443 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
446 * DOC: forcelongtraining (uint)
447 * Force long memory training in resume.
448 * The default is zero, indicates short training in resume.
450 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
451 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
454 * DOC: pcie_gen_cap (uint)
455 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
456 * The default is 0 (automatic for each asic).
458 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
459 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
462 * DOC: pcie_lane_cap (uint)
463 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
464 * The default is 0 (automatic for each asic).
466 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
467 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
470 * DOC: cg_mask (uint)
471 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
472 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
474 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
475 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
478 * DOC: pg_mask (uint)
479 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
480 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
482 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
483 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
486 * DOC: sdma_phase_quantum (uint)
487 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
489 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
490 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
493 * DOC: disable_cu (charp)
494 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
496 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
497 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
500 * DOC: virtual_display (charp)
501 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
502 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
503 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
504 * device at 26:00.0. The default is NULL.
506 MODULE_PARM_DESC(virtual_display,
507 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
508 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
511 * DOC: job_hang_limit (int)
512 * Set how much time allow a job hang and not drop it. The default is 0.
514 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
515 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
519 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
521 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
522 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
524 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
525 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
528 * DOC: gpu_recovery (int)
529 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
531 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)");
532 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
535 * DOC: emu_mode (int)
536 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
538 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
539 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
542 * DOC: ras_enable (int)
543 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
545 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
546 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
549 * DOC: ras_mask (uint)
550 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
551 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
553 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
554 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
557 * DOC: timeout_fatal_disable (bool)
558 * Disable Watchdog timeout fatal error event
560 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
561 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
564 * DOC: timeout_period (uint)
565 * Modify the watchdog timeout max_cycles as (1 << period)
567 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
568 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
571 * DOC: si_support (int)
572 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
573 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
574 * otherwise using amdgpu driver.
576 #ifdef CONFIG_DRM_AMDGPU_SI
578 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
579 int amdgpu_si_support = 0;
580 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
582 int amdgpu_si_support = 1;
583 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
586 module_param_named(si_support, amdgpu_si_support, int, 0444);
590 * DOC: cik_support (int)
591 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
592 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
593 * otherwise using amdgpu driver.
595 #ifdef CONFIG_DRM_AMDGPU_CIK
597 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
598 int amdgpu_cik_support = 0;
599 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
601 int amdgpu_cik_support = 1;
602 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
605 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
609 * DOC: smu_memory_pool_size (uint)
610 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
611 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
613 MODULE_PARM_DESC(smu_memory_pool_size,
614 "reserve gtt for smu debug usage, 0 = disable,"
615 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
616 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
619 * DOC: async_gfx_ring (int)
620 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
622 MODULE_PARM_DESC(async_gfx_ring,
623 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
624 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
628 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
630 MODULE_PARM_DESC(mcbp,
631 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
632 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
635 * DOC: discovery (int)
636 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
637 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
639 MODULE_PARM_DESC(discovery,
640 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
641 module_param_named(discovery, amdgpu_discovery, int, 0444);
645 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
646 * (0 = disabled (default), 1 = enabled)
648 MODULE_PARM_DESC(mes,
649 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
650 module_param_named(mes, amdgpu_mes, int, 0444);
654 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
655 * do not support per-process XNACK this also disables retry page faults.
656 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
658 MODULE_PARM_DESC(noretry,
659 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
660 module_param_named(noretry, amdgpu_noretry, int, 0644);
663 * DOC: force_asic_type (int)
664 * A non negative value used to specify the asic type for all supported GPUs.
666 MODULE_PARM_DESC(force_asic_type,
667 "A non negative value used to specify the asic type for all supported GPUs");
668 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
672 #ifdef CONFIG_HSA_AMD
674 * DOC: sched_policy (int)
675 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
676 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
677 * assigns queues to HQDs.
679 int sched_policy = KFD_SCHED_POLICY_HWS;
680 module_param(sched_policy, int, 0444);
681 MODULE_PARM_DESC(sched_policy,
682 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
685 * DOC: hws_max_conc_proc (int)
686 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
687 * number of VMIDs assigned to the HWS, which is also the default.
689 int hws_max_conc_proc = 8;
690 module_param(hws_max_conc_proc, int, 0444);
691 MODULE_PARM_DESC(hws_max_conc_proc,
692 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
695 * DOC: cwsr_enable (int)
696 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
697 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
701 module_param(cwsr_enable, int, 0444);
702 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
705 * DOC: max_num_of_queues_per_device (int)
706 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
709 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
710 module_param(max_num_of_queues_per_device, int, 0444);
711 MODULE_PARM_DESC(max_num_of_queues_per_device,
712 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
715 * DOC: send_sigterm (int)
716 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
717 * but just print errors on dmesg. Setting 1 enables sending sigterm.
720 module_param(send_sigterm, int, 0444);
721 MODULE_PARM_DESC(send_sigterm,
722 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
725 * DOC: debug_largebar (int)
726 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
727 * system. This limits the VRAM size reported to ROCm applications to the visible
728 * size, usually 256MB.
729 * Default value is 0, diabled.
732 module_param(debug_largebar, int, 0444);
733 MODULE_PARM_DESC(debug_largebar,
734 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
737 * DOC: ignore_crat (int)
738 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
739 * table to get information about AMD APUs. This option can serve as a workaround on
740 * systems with a broken CRAT table.
742 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
746 module_param(ignore_crat, int, 0444);
747 MODULE_PARM_DESC(ignore_crat,
748 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
751 * DOC: halt_if_hws_hang (int)
752 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
753 * Setting 1 enables halt on hang.
755 int halt_if_hws_hang;
756 module_param(halt_if_hws_hang, int, 0644);
757 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
760 * DOC: hws_gws_support(bool)
761 * Assume that HWS supports GWS barriers regardless of what firmware version
762 * check says. Default value: false (rely on MEC2 firmware version check).
764 bool hws_gws_support;
765 module_param(hws_gws_support, bool, 0444);
766 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
769 * DOC: queue_preemption_timeout_ms (int)
770 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
772 int queue_preemption_timeout_ms = 9000;
773 module_param(queue_preemption_timeout_ms, int, 0644);
774 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
777 * DOC: debug_evictions(bool)
778 * Enable extra debug messages to help determine the cause of evictions
780 bool debug_evictions;
781 module_param(debug_evictions, bool, 0644);
782 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
785 * DOC: no_system_mem_limit(bool)
786 * Disable system memory limit, to support multiple process shared memory
788 bool no_system_mem_limit;
789 module_param(no_system_mem_limit, bool, 0644);
790 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
793 * DOC: no_queue_eviction_on_vm_fault (int)
794 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
796 int amdgpu_no_queue_eviction_on_vm_fault = 0;
797 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
798 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
802 * DOC: dcfeaturemask (uint)
803 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
804 * The default is the current set of stable display features.
806 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
807 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
810 * DOC: dcdebugmask (uint)
811 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
813 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
814 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
817 * DOC: abmlevel (uint)
818 * Override the default ABM (Adaptive Backlight Management) level used for DC
819 * enabled hardware. Requires DMCU to be supported and loaded.
820 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
821 * default. Values 1-4 control the maximum allowable brightness reduction via
822 * the ABM algorithm, with 1 being the least reduction and 4 being the most
825 * Defaults to 0, or disabled. Userspace can still override this level later
828 uint amdgpu_dm_abm_level;
829 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
830 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
832 int amdgpu_backlight = -1;
833 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
834 module_param_named(backlight, amdgpu_backlight, bint, 0444);
838 * Trusted Memory Zone (TMZ) is a method to protect data being written
839 * to or read from memory.
841 * The default value: 0 (off). TODO: change to auto till it is completed.
843 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
844 module_param_named(tmz, amdgpu_tmz, int, 0444);
847 * DOC: reset_method (int)
848 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci)
850 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)");
851 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
854 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
855 * threshold value of faulty pages detected by RAS ECC, which may
856 * result in the GPU entering bad status when the number of total
857 * faulty pages by ECC exceeds the threshold value.
859 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
860 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
862 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
863 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
866 * DOC: smu_pptable_id (int)
867 * Used to override pptable id. id = 0 use VBIOS pptable.
868 * id > 0 use the soft pptable with specicfied id.
870 MODULE_PARM_DESC(smu_pptable_id,
871 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
872 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
874 /* These devices are not supported by amdgpu.
875 * They are supported by the mach64, r128, radeon drivers
877 static const u16 amdgpu_unsupported_pciidlist[] = {
1502 /* radeon secondary ids */
1585 static const struct pci_device_id pciidlist[] = {
1586 #ifdef CONFIG_DRM_AMDGPU_SI
1587 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1588 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1589 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1590 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1591 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1592 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1593 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1594 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1595 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1596 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1597 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1598 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1599 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1600 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1601 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1602 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1603 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1604 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1605 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1606 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1607 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1608 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1609 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1610 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1611 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1612 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1613 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1614 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1615 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1616 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1617 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1618 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1619 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1620 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1621 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1622 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1623 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1624 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1625 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1626 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1627 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1628 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1629 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1630 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1631 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1632 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1633 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1634 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1635 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1636 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1637 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1638 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1639 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1640 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1641 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1642 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1643 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1644 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1645 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1646 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1647 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1648 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1649 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1650 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1651 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1652 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1653 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1654 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1655 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1656 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1657 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1658 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1660 #ifdef CONFIG_DRM_AMDGPU_CIK
1662 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1663 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1664 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1665 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1666 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1667 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1668 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1669 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1670 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1671 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1672 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1673 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1674 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1675 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1676 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1677 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1678 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1679 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1680 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1681 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1682 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1683 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1685 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1686 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1687 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1688 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1689 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1690 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1691 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1692 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1693 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1694 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1695 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1697 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1698 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1699 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1700 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1701 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1702 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1703 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1704 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1705 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1706 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1707 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1708 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1710 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1711 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1712 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1713 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1714 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1715 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1716 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1717 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1718 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1719 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1720 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1721 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1722 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1723 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1724 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1725 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1727 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1728 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1729 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1730 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1731 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1732 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1733 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1734 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1735 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1736 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1737 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1738 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1739 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1740 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1741 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1742 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1745 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1746 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1747 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1748 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1749 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1751 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1752 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1753 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1754 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1755 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1756 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1757 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1758 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1759 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1761 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1762 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1764 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1765 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1766 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1767 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1768 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1770 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1772 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1773 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1774 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1775 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1776 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1777 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1778 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1779 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1780 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1782 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1783 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1784 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1785 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1786 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1787 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1788 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1789 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1790 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1791 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1792 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1793 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1794 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1796 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1797 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1798 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1799 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1800 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1801 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1802 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1803 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1805 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1806 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1807 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1809 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1810 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1811 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1812 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1813 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1814 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1815 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1816 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1817 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1818 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1819 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1820 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1821 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1822 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1823 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1825 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1826 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1827 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1828 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1829 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1831 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1832 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1833 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1834 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1835 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1836 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1837 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1839 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1840 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1842 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1843 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1844 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1845 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1847 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1848 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1849 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1850 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1851 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1852 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1853 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1854 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1856 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1857 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1858 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1859 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1862 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1863 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1864 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1865 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1868 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1869 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1871 /* Sienna_Cichlid */
1872 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1873 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1874 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1875 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1876 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1877 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1878 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1879 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1880 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1881 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1882 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1883 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1884 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1887 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1890 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1891 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1894 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1895 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1896 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1897 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1898 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1899 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1900 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1901 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1902 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1904 /* DIMGREY_CAVEFISH */
1905 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1906 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1907 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1908 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1909 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1910 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1911 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1912 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1913 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1914 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1915 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1916 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1919 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1920 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1921 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1922 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1924 /* CYAN_SKILLFISH */
1925 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1926 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1929 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1930 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1931 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1932 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1933 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1935 { PCI_DEVICE(0x1002, PCI_ANY_ID),
1936 .class = PCI_CLASS_DISPLAY_VGA << 8,
1937 .class_mask = 0xffffff,
1938 .driver_data = CHIP_IP_DISCOVERY },
1940 { PCI_DEVICE(0x1002, PCI_ANY_ID),
1941 .class = PCI_CLASS_DISPLAY_OTHER << 8,
1942 .class_mask = 0xffffff,
1943 .driver_data = CHIP_IP_DISCOVERY },
1948 MODULE_DEVICE_TABLE(pci, pciidlist);
1950 static const struct drm_driver amdgpu_kms_driver;
1952 static bool amdgpu_is_fw_framebuffer(resource_size_t base,
1953 resource_size_t size)
1956 #if IS_REACHABLE(CONFIG_FB)
1957 struct apertures_struct *a;
1959 a = alloc_apertures(1);
1963 a->ranges[0].base = base;
1964 a->ranges[0].size = size;
1966 found = is_firmware_framebuffer(a);
1972 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
1974 struct pci_dev *p = NULL;
1982 for (i = 1; i < 4; i++) {
1983 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
1984 adev->pdev->bus->number, i);
1986 pm_runtime_get_sync(&p->dev);
1987 pm_runtime_mark_last_busy(&p->dev);
1988 pm_runtime_put_autosuspend(&p->dev);
1994 static int amdgpu_pci_probe(struct pci_dev *pdev,
1995 const struct pci_device_id *ent)
1997 struct drm_device *ddev;
1998 struct amdgpu_device *adev;
1999 unsigned long flags = ent->driver_data;
2000 int ret, retry = 0, i;
2001 bool supports_atomic = false;
2003 resource_size_t base, size;
2005 /* skip devices which are owned by radeon */
2006 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2007 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2011 if (amdgpu_virtual_display ||
2012 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2013 supports_atomic = true;
2015 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2016 DRM_INFO("This hardware requires experimental hardware support.\n"
2017 "See modparam exp_hw_support\n");
2021 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2022 * however, SME requires an indirect IOMMU mapping because the encryption
2023 * bit is beyond the DMA mask of the chip.
2025 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2026 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2027 dev_info(&pdev->dev,
2028 "SME is not compatible with RAVEN\n");
2032 #ifdef CONFIG_DRM_AMDGPU_SI
2033 if (!amdgpu_si_support) {
2034 switch (flags & AMD_ASIC_MASK) {
2040 dev_info(&pdev->dev,
2041 "SI support provided by radeon.\n");
2042 dev_info(&pdev->dev,
2043 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2049 #ifdef CONFIG_DRM_AMDGPU_CIK
2050 if (!amdgpu_cik_support) {
2051 switch (flags & AMD_ASIC_MASK) {
2057 dev_info(&pdev->dev,
2058 "CIK support provided by radeon.\n");
2059 dev_info(&pdev->dev,
2060 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2067 base = pci_resource_start(pdev, 0);
2068 size = pci_resource_len(pdev, 0);
2069 is_fw_fb = amdgpu_is_fw_framebuffer(base, size);
2071 /* Get rid of things like offb */
2072 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver);
2076 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2078 return PTR_ERR(adev);
2080 adev->dev = &pdev->dev;
2082 ddev = adev_to_drm(adev);
2083 adev->is_fw_fb = is_fw_fb;
2085 if (!supports_atomic)
2086 ddev->driver_features &= ~DRIVER_ATOMIC;
2088 ret = pci_enable_device(pdev);
2092 pci_set_drvdata(pdev, ddev);
2094 ret = amdgpu_driver_load_kms(adev, ent->driver_data);
2099 ret = drm_dev_register(ddev, ent->driver_data);
2100 if (ret == -EAGAIN && ++retry <= 3) {
2101 DRM_INFO("retry init %d\n", retry);
2102 /* Don't request EX mode too frequently which is attacking */
2110 * 1. don't init fbdev on hw without DCE
2111 * 2. don't init fbdev if there are no connectors
2113 if (adev->mode_info.mode_config_initialized &&
2114 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2115 /* select 8 bpp console on low vram cards */
2116 if (adev->gmc.real_vram_size <= (32*1024*1024))
2117 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2119 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2122 ret = amdgpu_debugfs_init(adev);
2124 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2127 /* only need to skip on ATPX */
2128 if (amdgpu_device_supports_px(ddev))
2129 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2130 /* we want direct complete for BOCO */
2131 if (amdgpu_device_supports_boco(ddev))
2132 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2133 DPM_FLAG_SMART_SUSPEND |
2134 DPM_FLAG_MAY_SKIP_RESUME);
2135 pm_runtime_use_autosuspend(ddev->dev);
2136 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2138 pm_runtime_allow(ddev->dev);
2140 pm_runtime_mark_last_busy(ddev->dev);
2141 pm_runtime_put_autosuspend(ddev->dev);
2144 * For runpm implemented via BACO, PMFW will handle the
2145 * timing for BACO in and out:
2146 * - put ASIC into BACO state only when both video and
2147 * audio functions are in D3 state.
2148 * - pull ASIC out of BACO state when either video or
2149 * audio function is in D0 state.
2150 * Also, at startup, PMFW assumes both functions are in
2153 * So if snd driver was loaded prior to amdgpu driver
2154 * and audio function was put into D3 state, there will
2155 * be no PMFW-aware D-state transition(D0->D3) on runpm
2156 * suspend. Thus the BACO will be not correctly kicked in.
2158 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2159 * into D0 state. Then there will be a PMFW-aware D-state
2160 * transition(D0->D3) on runpm suspend.
2162 if (amdgpu_device_supports_baco(ddev) &&
2163 !(adev->flags & AMD_IS_APU) &&
2164 (adev->asic_type >= CHIP_NAVI10))
2165 amdgpu_get_secondary_funcs(adev);
2171 pci_disable_device(pdev);
2176 amdgpu_pci_remove(struct pci_dev *pdev)
2178 struct drm_device *dev = pci_get_drvdata(pdev);
2179 struct amdgpu_device *adev = drm_to_adev(dev);
2181 drm_dev_unplug(dev);
2184 pm_runtime_get_sync(dev->dev);
2185 pm_runtime_forbid(dev->dev);
2188 amdgpu_driver_unload_kms(dev);
2191 * Flush any in flight DMA operations from device.
2192 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2193 * StatusTransactions Pending bit.
2195 pci_disable_device(pdev);
2196 pci_wait_for_pending_transaction(pdev);
2200 amdgpu_pci_shutdown(struct pci_dev *pdev)
2202 struct drm_device *dev = pci_get_drvdata(pdev);
2203 struct amdgpu_device *adev = drm_to_adev(dev);
2205 if (amdgpu_ras_intr_triggered())
2208 /* if we are running in a VM, make sure the device
2209 * torn down properly on reboot/shutdown.
2210 * unfortunately we can't detect certain
2211 * hypervisors so just do this all the time.
2213 if (!amdgpu_passthrough(adev))
2214 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2215 amdgpu_device_ip_suspend(adev);
2216 adev->mp1_state = PP_MP1_STATE_NONE;
2220 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2222 * @work: work_struct.
2224 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2226 struct list_head device_list;
2227 struct amdgpu_device *adev;
2229 struct amdgpu_reset_context reset_context;
2231 memset(&reset_context, 0, sizeof(reset_context));
2233 mutex_lock(&mgpu_info.mutex);
2234 if (mgpu_info.pending_reset == true) {
2235 mutex_unlock(&mgpu_info.mutex);
2238 mgpu_info.pending_reset = true;
2239 mutex_unlock(&mgpu_info.mutex);
2241 /* Use a common context, just need to make sure full reset is done */
2242 reset_context.method = AMD_RESET_METHOD_NONE;
2243 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2245 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2246 adev = mgpu_info.gpu_ins[i].adev;
2247 reset_context.reset_req_dev = adev;
2248 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2250 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2251 r, adev_to_drm(adev)->unique);
2253 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2256 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2257 adev = mgpu_info.gpu_ins[i].adev;
2258 flush_work(&adev->xgmi_reset_work);
2259 adev->gmc.xgmi.pending_reset = false;
2262 /* reset function will rebuild the xgmi hive info , clear it now */
2263 for (i = 0; i < mgpu_info.num_dgpu; i++)
2264 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2266 INIT_LIST_HEAD(&device_list);
2268 for (i = 0; i < mgpu_info.num_dgpu; i++)
2269 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2271 /* unregister the GPU first, reset function will add them back */
2272 list_for_each_entry(adev, &device_list, reset_list)
2273 amdgpu_unregister_gpu_instance(adev);
2275 /* Use a common context, just need to make sure full reset is done */
2276 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2277 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2280 DRM_ERROR("reinit gpus failure");
2283 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2284 adev = mgpu_info.gpu_ins[i].adev;
2285 if (!adev->kfd.init_complete)
2286 amdgpu_amdkfd_device_init(adev);
2287 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2292 static int amdgpu_pmops_prepare(struct device *dev)
2294 struct drm_device *drm_dev = dev_get_drvdata(dev);
2295 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2297 /* Return a positive number here so
2298 * DPM_FLAG_SMART_SUSPEND works properly
2300 if (amdgpu_device_supports_boco(drm_dev))
2301 return pm_runtime_suspended(dev);
2303 /* if we will not support s3 or s2i for the device
2306 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2307 !amdgpu_acpi_is_s3_active(adev))
2313 static void amdgpu_pmops_complete(struct device *dev)
2318 static int amdgpu_pmops_suspend(struct device *dev)
2320 struct drm_device *drm_dev = dev_get_drvdata(dev);
2321 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2324 if (amdgpu_acpi_is_s0ix_active(adev))
2325 adev->in_s0ix = true;
2328 r = amdgpu_device_suspend(drm_dev, true);
2332 r = amdgpu_asic_reset(adev);
2336 static int amdgpu_pmops_resume(struct device *dev)
2338 struct drm_device *drm_dev = dev_get_drvdata(dev);
2339 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2342 /* Avoids registers access if device is physically gone */
2343 if (!pci_device_is_present(adev->pdev))
2344 adev->no_hw_access = true;
2346 r = amdgpu_device_resume(drm_dev, true);
2347 if (amdgpu_acpi_is_s0ix_active(adev))
2348 adev->in_s0ix = false;
2350 adev->in_s3 = false;
2354 static int amdgpu_pmops_freeze(struct device *dev)
2356 struct drm_device *drm_dev = dev_get_drvdata(dev);
2357 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2361 r = amdgpu_device_suspend(drm_dev, true);
2362 adev->in_s4 = false;
2365 return amdgpu_asic_reset(adev);
2368 static int amdgpu_pmops_thaw(struct device *dev)
2370 struct drm_device *drm_dev = dev_get_drvdata(dev);
2372 return amdgpu_device_resume(drm_dev, true);
2375 static int amdgpu_pmops_poweroff(struct device *dev)
2377 struct drm_device *drm_dev = dev_get_drvdata(dev);
2379 return amdgpu_device_suspend(drm_dev, true);
2382 static int amdgpu_pmops_restore(struct device *dev)
2384 struct drm_device *drm_dev = dev_get_drvdata(dev);
2386 return amdgpu_device_resume(drm_dev, true);
2389 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2391 struct pci_dev *pdev = to_pci_dev(dev);
2392 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2393 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2397 pm_runtime_forbid(dev);
2401 /* wait for all rings to drain before suspending */
2402 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2403 struct amdgpu_ring *ring = adev->rings[i];
2404 if (ring && ring->sched.ready) {
2405 ret = amdgpu_fence_wait_empty(ring);
2411 adev->in_runpm = true;
2412 if (amdgpu_device_supports_px(drm_dev))
2413 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2416 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2417 * proper cleanups and put itself into a state ready for PNP. That
2418 * can address some random resuming failure observed on BOCO capable
2420 * TODO: this may be also needed for PX capable platform.
2422 if (amdgpu_device_supports_boco(drm_dev))
2423 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2425 ret = amdgpu_device_suspend(drm_dev, false);
2427 adev->in_runpm = false;
2428 if (amdgpu_device_supports_boco(drm_dev))
2429 adev->mp1_state = PP_MP1_STATE_NONE;
2433 if (amdgpu_device_supports_boco(drm_dev))
2434 adev->mp1_state = PP_MP1_STATE_NONE;
2436 if (amdgpu_device_supports_px(drm_dev)) {
2437 /* Only need to handle PCI state in the driver for ATPX
2438 * PCI core handles it for _PR3.
2440 amdgpu_device_cache_pci_state(pdev);
2441 pci_disable_device(pdev);
2442 pci_ignore_hotplug(pdev);
2443 pci_set_power_state(pdev, PCI_D3cold);
2444 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2445 } else if (amdgpu_device_supports_boco(drm_dev)) {
2447 } else if (amdgpu_device_supports_baco(drm_dev)) {
2448 amdgpu_device_baco_enter(drm_dev);
2454 static int amdgpu_pmops_runtime_resume(struct device *dev)
2456 struct pci_dev *pdev = to_pci_dev(dev);
2457 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2458 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2464 /* Avoids registers access if device is physically gone */
2465 if (!pci_device_is_present(adev->pdev))
2466 adev->no_hw_access = true;
2468 if (amdgpu_device_supports_px(drm_dev)) {
2469 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2471 /* Only need to handle PCI state in the driver for ATPX
2472 * PCI core handles it for _PR3.
2474 pci_set_power_state(pdev, PCI_D0);
2475 amdgpu_device_load_pci_state(pdev);
2476 ret = pci_enable_device(pdev);
2479 pci_set_master(pdev);
2480 } else if (amdgpu_device_supports_boco(drm_dev)) {
2481 /* Only need to handle PCI state in the driver for ATPX
2482 * PCI core handles it for _PR3.
2484 pci_set_master(pdev);
2485 } else if (amdgpu_device_supports_baco(drm_dev)) {
2486 amdgpu_device_baco_exit(drm_dev);
2488 ret = amdgpu_device_resume(drm_dev, false);
2492 if (amdgpu_device_supports_px(drm_dev))
2493 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2494 adev->in_runpm = false;
2498 static int amdgpu_pmops_runtime_idle(struct device *dev)
2500 struct drm_device *drm_dev = dev_get_drvdata(dev);
2501 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2502 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2506 pm_runtime_forbid(dev);
2510 if (amdgpu_device_has_dc_support(adev)) {
2511 struct drm_crtc *crtc;
2513 drm_for_each_crtc(crtc, drm_dev) {
2514 drm_modeset_lock(&crtc->mutex, NULL);
2515 if (crtc->state->active)
2517 drm_modeset_unlock(&crtc->mutex);
2523 struct drm_connector *list_connector;
2524 struct drm_connector_list_iter iter;
2526 mutex_lock(&drm_dev->mode_config.mutex);
2527 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2529 drm_connector_list_iter_begin(drm_dev, &iter);
2530 drm_for_each_connector_iter(list_connector, &iter) {
2531 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2537 drm_connector_list_iter_end(&iter);
2539 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2540 mutex_unlock(&drm_dev->mode_config.mutex);
2544 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
2546 pm_runtime_mark_last_busy(dev);
2547 pm_runtime_autosuspend(dev);
2551 long amdgpu_drm_ioctl(struct file *filp,
2552 unsigned int cmd, unsigned long arg)
2554 struct drm_file *file_priv = filp->private_data;
2555 struct drm_device *dev;
2557 dev = file_priv->minor->dev;
2558 ret = pm_runtime_get_sync(dev->dev);
2562 ret = drm_ioctl(filp, cmd, arg);
2564 pm_runtime_mark_last_busy(dev->dev);
2566 pm_runtime_put_autosuspend(dev->dev);
2570 static const struct dev_pm_ops amdgpu_pm_ops = {
2571 .prepare = amdgpu_pmops_prepare,
2572 .complete = amdgpu_pmops_complete,
2573 .suspend = amdgpu_pmops_suspend,
2574 .resume = amdgpu_pmops_resume,
2575 .freeze = amdgpu_pmops_freeze,
2576 .thaw = amdgpu_pmops_thaw,
2577 .poweroff = amdgpu_pmops_poweroff,
2578 .restore = amdgpu_pmops_restore,
2579 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2580 .runtime_resume = amdgpu_pmops_runtime_resume,
2581 .runtime_idle = amdgpu_pmops_runtime_idle,
2584 static int amdgpu_flush(struct file *f, fl_owner_t id)
2586 struct drm_file *file_priv = f->private_data;
2587 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2588 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2590 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2591 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2593 return timeout >= 0 ? 0 : timeout;
2596 static const struct file_operations amdgpu_driver_kms_fops = {
2597 .owner = THIS_MODULE,
2599 .flush = amdgpu_flush,
2600 .release = drm_release,
2601 .unlocked_ioctl = amdgpu_drm_ioctl,
2602 .mmap = drm_gem_mmap,
2605 #ifdef CONFIG_COMPAT
2606 .compat_ioctl = amdgpu_kms_compat_ioctl,
2608 #ifdef CONFIG_PROC_FS
2609 .show_fdinfo = amdgpu_show_fdinfo
2613 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2615 struct drm_file *file;
2620 if (filp->f_op != &amdgpu_driver_kms_fops) {
2624 file = filp->private_data;
2625 *fpriv = file->driver_priv;
2629 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2630 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2631 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2632 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2633 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2634 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2635 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2637 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2638 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2639 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2640 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2641 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2642 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2643 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2644 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2645 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2646 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2649 static const struct drm_driver amdgpu_kms_driver = {
2653 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2654 DRIVER_SYNCOBJ_TIMELINE,
2655 .open = amdgpu_driver_open_kms,
2656 .postclose = amdgpu_driver_postclose_kms,
2657 .lastclose = amdgpu_driver_lastclose_kms,
2658 .ioctls = amdgpu_ioctls_kms,
2659 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2660 .dumb_create = amdgpu_mode_dumb_create,
2661 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2662 .fops = &amdgpu_driver_kms_fops,
2663 .release = &amdgpu_driver_release_kms,
2665 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2666 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2667 .gem_prime_import = amdgpu_gem_prime_import,
2668 .gem_prime_mmap = drm_gem_prime_mmap,
2670 .name = DRIVER_NAME,
2671 .desc = DRIVER_DESC,
2672 .date = DRIVER_DATE,
2673 .major = KMS_DRIVER_MAJOR,
2674 .minor = KMS_DRIVER_MINOR,
2675 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2678 static struct pci_error_handlers amdgpu_pci_err_handler = {
2679 .error_detected = amdgpu_pci_error_detected,
2680 .mmio_enabled = amdgpu_pci_mmio_enabled,
2681 .slot_reset = amdgpu_pci_slot_reset,
2682 .resume = amdgpu_pci_resume,
2685 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2686 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2687 extern const struct attribute_group amdgpu_vbios_version_attr_group;
2689 static const struct attribute_group *amdgpu_sysfs_groups[] = {
2690 &amdgpu_vram_mgr_attr_group,
2691 &amdgpu_gtt_mgr_attr_group,
2692 &amdgpu_vbios_version_attr_group,
2697 static struct pci_driver amdgpu_kms_pci_driver = {
2698 .name = DRIVER_NAME,
2699 .id_table = pciidlist,
2700 .probe = amdgpu_pci_probe,
2701 .remove = amdgpu_pci_remove,
2702 .shutdown = amdgpu_pci_shutdown,
2703 .driver.pm = &amdgpu_pm_ops,
2704 .err_handler = &amdgpu_pci_err_handler,
2705 .dev_groups = amdgpu_sysfs_groups,
2708 static int __init amdgpu_init(void)
2712 if (drm_firmware_drivers_only())
2715 r = amdgpu_sync_init();
2719 r = amdgpu_fence_slab_init();
2723 DRM_INFO("amdgpu kernel modesetting enabled.\n");
2724 amdgpu_register_atpx_handler();
2725 amdgpu_acpi_detect();
2727 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2728 amdgpu_amdkfd_init();
2730 /* let modprobe override vga console setting */
2731 return pci_register_driver(&amdgpu_kms_pci_driver);
2740 static void __exit amdgpu_exit(void)
2742 amdgpu_amdkfd_fini();
2743 pci_unregister_driver(&amdgpu_kms_pci_driver);
2744 amdgpu_unregister_atpx_handler();
2746 amdgpu_fence_slab_fini();
2747 mmu_notifier_synchronize();
2750 module_init(amdgpu_init);
2751 module_exit(amdgpu_exit);
2753 MODULE_AUTHOR(DRIVER_AUTHOR);
2754 MODULE_DESCRIPTION(DRIVER_DESC);
2755 MODULE_LICENSE("GPL and additional rights");
projects / linux-2.6-microblaze.git / blob