drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 /*
  25  * GPU doorbell structures, functions & helpers
  26  */
  27 struct amdgpu_doorbell {
  28         /* doorbell mmio */
  29         resource_size_t         base;
  30         resource_size_t         size;
  31         u32 __iomem             *ptr;
  32         u32                     num_doorbells;  /* Number of doorbells actually reserved for amdgpu. */
  33 };
  34
  35 /* Reserved doorbells for amdgpu (including multimedia).
  36  * KFD can use all the rest in the 2M doorbell bar.
  37  * For asic before vega10, doorbell is 32-bit, so the
  38  * index/offset is in dword. For vega10 and after, doorbell
  39  * can be 64-bit, so the index defined is in qword.
  40  */
  41 struct amdgpu_doorbell_index {
  42         uint32_t kiq;
  43         uint32_t mec_ring0;
  44         uint32_t mec_ring1;
  45         uint32_t mec_ring2;
  46         uint32_t mec_ring3;
  47         uint32_t mec_ring4;
  48         uint32_t mec_ring5;
  49         uint32_t mec_ring6;
  50         uint32_t mec_ring7;
  51         uint32_t userqueue_start;
  52         uint32_t userqueue_end;
  53         uint32_t gfx_ring0;
  54         uint32_t gfx_ring1;
  55         uint32_t sdma_engine[8];
  56         uint32_t mes_ring;
  57         uint32_t ih;
  58         union {
  59                 struct {
  60                         uint32_t vcn_ring0_1;
  61                         uint32_t vcn_ring2_3;
  62                         uint32_t vcn_ring4_5;
  63                         uint32_t vcn_ring6_7;
  64                 } vcn;
  65                 struct {
  66                         uint32_t uvd_ring0_1;
  67                         uint32_t uvd_ring2_3;
  68                         uint32_t uvd_ring4_5;
  69                         uint32_t uvd_ring6_7;
  70                         uint32_t vce_ring0_1;
  71                         uint32_t vce_ring2_3;
  72                         uint32_t vce_ring4_5;
  73                         uint32_t vce_ring6_7;
  74                 } uvd_vce;
  75         };
  76         uint32_t first_non_cp;
  77         uint32_t last_non_cp;
  78         uint32_t max_assignment;
  79         /* Per engine SDMA doorbell size in dword */
  80         uint32_t sdma_doorbell_range;
  81 };
  82
  83 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
  84 {
  85         AMDGPU_DOORBELL_KIQ                     = 0x000,
  86         AMDGPU_DOORBELL_HIQ                     = 0x001,
  87         AMDGPU_DOORBELL_DIQ                     = 0x002,
  88         AMDGPU_DOORBELL_MEC_RING0               = 0x010,
  89         AMDGPU_DOORBELL_MEC_RING1               = 0x011,
  90         AMDGPU_DOORBELL_MEC_RING2               = 0x012,
  91         AMDGPU_DOORBELL_MEC_RING3               = 0x013,
  92         AMDGPU_DOORBELL_MEC_RING4               = 0x014,
  93         AMDGPU_DOORBELL_MEC_RING5               = 0x015,
  94         AMDGPU_DOORBELL_MEC_RING6               = 0x016,
  95         AMDGPU_DOORBELL_MEC_RING7               = 0x017,
  96         AMDGPU_DOORBELL_GFX_RING0               = 0x020,
  97         AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,
  98         AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,
  99         AMDGPU_DOORBELL_IH                      = 0x1E8,
 100         AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,
 101         AMDGPU_DOORBELL_INVALID                 = 0xFFFF
 102 } AMDGPU_DOORBELL_ASSIGNMENT;
 103
 104 typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
 105 {
 106         /* Compute + GFX: 0~255 */
 107         AMDGPU_VEGA20_DOORBELL_KIQ                     = 0x000,
 108         AMDGPU_VEGA20_DOORBELL_HIQ                     = 0x001,
 109         AMDGPU_VEGA20_DOORBELL_DIQ                     = 0x002,
 110         AMDGPU_VEGA20_DOORBELL_MEC_RING0               = 0x003,
 111         AMDGPU_VEGA20_DOORBELL_MEC_RING1               = 0x004,
 112         AMDGPU_VEGA20_DOORBELL_MEC_RING2               = 0x005,
 113         AMDGPU_VEGA20_DOORBELL_MEC_RING3               = 0x006,
 114         AMDGPU_VEGA20_DOORBELL_MEC_RING4               = 0x007,
 115         AMDGPU_VEGA20_DOORBELL_MEC_RING5               = 0x008,
 116         AMDGPU_VEGA20_DOORBELL_MEC_RING6               = 0x009,
 117         AMDGPU_VEGA20_DOORBELL_MEC_RING7               = 0x00A,
 118         AMDGPU_VEGA20_DOORBELL_USERQUEUE_START         = 0x00B,
 119         AMDGPU_VEGA20_DOORBELL_USERQUEUE_END           = 0x08A,
 120         AMDGPU_VEGA20_DOORBELL_GFX_RING0               = 0x08B,
 121         /* SDMA:256~335*/
 122         AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0            = 0x100,
 123         AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1            = 0x10A,
 124         AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2            = 0x114,
 125         AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3            = 0x11E,
 126         AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4            = 0x128,
 127         AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5            = 0x132,
 128         AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6            = 0x13C,
 129         AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7            = 0x146,
 130         /* IH: 376~391 */
 131         AMDGPU_VEGA20_DOORBELL_IH                      = 0x178,
 132         /* MMSCH: 392~407
 133          * overlap the doorbell assignment with VCN as they are  mutually exclusive
 134          * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
 135          */
 136         AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* VNC0 */
 137         AMDGPU_VEGA20_DOORBELL64_VCN2_3                  = 0x189,
 138         AMDGPU_VEGA20_DOORBELL64_VCN4_5                  = 0x18A,
 139         AMDGPU_VEGA20_DOORBELL64_VCN6_7                  = 0x18B,
 140
 141         AMDGPU_VEGA20_DOORBELL64_VCN8_9                  = 0x18C, /* VNC1 */
 142         AMDGPU_VEGA20_DOORBELL64_VCNa_b                  = 0x18D,
 143         AMDGPU_VEGA20_DOORBELL64_VCNc_d                  = 0x18E,
 144         AMDGPU_VEGA20_DOORBELL64_VCNe_f                  = 0x18F,
 145
 146         AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1             = 0x188,
 147         AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3             = 0x189,
 148         AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5             = 0x18A,
 149         AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7             = 0x18B,
 150
 151         AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1             = 0x18C,
 152         AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3             = 0x18D,
 153         AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5             = 0x18E,
 154         AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7             = 0x18F,
 155
 156         AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP            = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0,
 157         AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP             = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
 158
 159         AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT            = 0x18F,
 160         AMDGPU_VEGA20_DOORBELL_INVALID                   = 0xFFFF
 161 } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
 162
 163 typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
 164 {
 165         /* Compute + GFX: 0~255 */
 166         AMDGPU_NAVI10_DOORBELL_KIQ                      = 0x000,
 167         AMDGPU_NAVI10_DOORBELL_HIQ                      = 0x001,
 168         AMDGPU_NAVI10_DOORBELL_DIQ                      = 0x002,
 169         AMDGPU_NAVI10_DOORBELL_MEC_RING0                = 0x003,
 170         AMDGPU_NAVI10_DOORBELL_MEC_RING1                = 0x004,
 171         AMDGPU_NAVI10_DOORBELL_MEC_RING2                = 0x005,
 172         AMDGPU_NAVI10_DOORBELL_MEC_RING3                = 0x006,
 173         AMDGPU_NAVI10_DOORBELL_MEC_RING4                = 0x007,
 174         AMDGPU_NAVI10_DOORBELL_MEC_RING5                = 0x008,
 175         AMDGPU_NAVI10_DOORBELL_MEC_RING6                = 0x009,
 176         AMDGPU_NAVI10_DOORBELL_MEC_RING7                = 0x00A,
 177         AMDGPU_NAVI10_DOORBELL_USERQUEUE_START          = 0x00B,
 178         AMDGPU_NAVI10_DOORBELL_USERQUEUE_END            = 0x08A,
 179         AMDGPU_NAVI10_DOORBELL_GFX_RING0                = 0x08B,
 180         AMDGPU_NAVI10_DOORBELL_GFX_RING1                = 0x08C,
 181         AMDGPU_NAVI10_DOORBELL_MES_RING                 = 0x090,
 182         /* SDMA:256~335*/
 183         AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0             = 0x100,
 184         AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1             = 0x10A,
 185         AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2             = 0x114,
 186         AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3             = 0x11E,
 187         /* IH: 376~391 */
 188         AMDGPU_NAVI10_DOORBELL_IH                       = 0x178,
 189         /* MMSCH: 392~407
 190          * overlap the doorbell assignment with VCN as they are  mutually exclusive
 191          * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
 192          */
 193         AMDGPU_NAVI10_DOORBELL64_VCN0_1                 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
 194         AMDGPU_NAVI10_DOORBELL64_VCN2_3                 = 0x189,
 195         AMDGPU_NAVI10_DOORBELL64_VCN4_5                 = 0x18A,
 196         AMDGPU_NAVI10_DOORBELL64_VCN6_7                 = 0x18B,
 197
 198         AMDGPU_NAVI10_DOORBELL64_VCN8_9                 = 0x18C,
 199         AMDGPU_NAVI10_DOORBELL64_VCNa_b                 = 0x18D,
 200         AMDGPU_NAVI10_DOORBELL64_VCNc_d                 = 0x18E,
 201         AMDGPU_NAVI10_DOORBELL64_VCNe_f                 = 0x18F,
 202
 203         AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP           = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0,
 204         AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP            = AMDGPU_NAVI10_DOORBELL64_VCNe_f,
 205
 206         AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT           = 0x18F,
 207         AMDGPU_NAVI10_DOORBELL_INVALID                  = 0xFFFF
 208 } AMDGPU_NAVI10_DOORBELL_ASSIGNMENT;
 209
 210 /*
 211  * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
 212  */
 213 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
 214 {
 215         /*
 216          * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
 217          * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
 218          *  Compute related doorbells are allocated from 0x00 to 0x8a
 219          */
 220
 221
 222         /* kernel scheduling */
 223         AMDGPU_DOORBELL64_KIQ                     = 0x00,
 224
 225         /* HSA interface queue and debug queue */
 226         AMDGPU_DOORBELL64_HIQ                     = 0x01,
 227         AMDGPU_DOORBELL64_DIQ                     = 0x02,
 228
 229         /* Compute engines */
 230         AMDGPU_DOORBELL64_MEC_RING0               = 0x03,
 231         AMDGPU_DOORBELL64_MEC_RING1               = 0x04,
 232         AMDGPU_DOORBELL64_MEC_RING2               = 0x05,
 233         AMDGPU_DOORBELL64_MEC_RING3               = 0x06,
 234         AMDGPU_DOORBELL64_MEC_RING4               = 0x07,
 235         AMDGPU_DOORBELL64_MEC_RING5               = 0x08,
 236         AMDGPU_DOORBELL64_MEC_RING6               = 0x09,
 237         AMDGPU_DOORBELL64_MEC_RING7               = 0x0a,
 238
 239         /* User queue doorbell range (128 doorbells) */
 240         AMDGPU_DOORBELL64_USERQUEUE_START         = 0x0b,
 241         AMDGPU_DOORBELL64_USERQUEUE_END           = 0x8a,
 242
 243         /* Graphics engine */
 244         AMDGPU_DOORBELL64_GFX_RING0               = 0x8b,
 245
 246         /*
 247          * Other graphics doorbells can be allocated here: from 0x8c to 0xdf
 248          * Graphics voltage island aperture 1
 249          * default non-graphics QWORD index is 0xe0 - 0xFF inclusive
 250          */
 251
 252         /* For vega10 sriov, the sdma doorbell must be fixed as follow
 253          * to keep the same setting with host driver, or it will
 254          * happen conflicts
 255          */
 256         AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xF0,
 257         AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
 258         AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xF2,
 259         AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
 260
 261         /* Interrupt handler */
 262         AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
 263         AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */
 264         AMDGPU_DOORBELL64_IH_RING2                = 0xF6,  /* For page migration translation/invalidation log */
 265
 266         /* VCN engine use 32 bits doorbell  */
 267         AMDGPU_DOORBELL64_VCN0_1                  = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
 268         AMDGPU_DOORBELL64_VCN2_3                  = 0xF9,
 269         AMDGPU_DOORBELL64_VCN4_5                  = 0xFA,
 270         AMDGPU_DOORBELL64_VCN6_7                  = 0xFB,
 271
 272         /* overlap the doorbell assignment with VCN as they are  mutually exclusive
 273          * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
 274          */
 275         AMDGPU_DOORBELL64_UVD_RING0_1             = 0xF8,
 276         AMDGPU_DOORBELL64_UVD_RING2_3             = 0xF9,
 277         AMDGPU_DOORBELL64_UVD_RING4_5             = 0xFA,
 278         AMDGPU_DOORBELL64_UVD_RING6_7             = 0xFB,
 279
 280         AMDGPU_DOORBELL64_VCE_RING0_1             = 0xFC,
 281         AMDGPU_DOORBELL64_VCE_RING2_3             = 0xFD,
 282         AMDGPU_DOORBELL64_VCE_RING4_5             = 0xFE,
 283         AMDGPU_DOORBELL64_VCE_RING6_7             = 0xFF,
 284
 285         AMDGPU_DOORBELL64_FIRST_NON_CP            = AMDGPU_DOORBELL64_sDMA_ENGINE0,
 286         AMDGPU_DOORBELL64_LAST_NON_CP             = AMDGPU_DOORBELL64_VCE_RING6_7,
 287
 288         AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,
 289         AMDGPU_DOORBELL64_INVALID                 = 0xFFFF
 290 } AMDGPU_DOORBELL64_ASSIGNMENT;
 291
 292 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
 293 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
 294 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
 295 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
 296
 297 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
 298 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
 299 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
 300 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
 301