2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * based on nouveau_prime.c
24 * Authors: Alex Deucher
28 * DOC: PRIME Buffer Sharing
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
35 #include "amdgpu_display.h"
36 #include "amdgpu_gem.h"
37 #include "amdgpu_dma_buf.h"
38 #include "amdgpu_xgmi.h"
39 #include <drm/amdgpu_drm.h>
40 #include <linux/dma-buf.h>
41 #include <linux/dma-fence-array.h>
42 #include <linux/pci-p2pdma.h>
43 #include <linux/pm_runtime.h>
46 __dma_resv_make_exclusive(struct dma_resv *obj)
48 struct dma_fence **fences;
52 if (!dma_resv_shared_list(obj)) /* no shared fences to convert */
55 r = dma_resv_get_fences(obj, NULL, &count, &fences);
60 /* Now that was unexpected. */
61 } else if (count == 1) {
62 dma_resv_add_excl_fence(obj, fences[0]);
63 dma_fence_put(fences[0]);
66 struct dma_fence_array *array;
68 array = dma_fence_array_create(count, fences,
69 dma_fence_context_alloc(1), 0,
74 dma_resv_add_excl_fence(obj, &array->base);
75 dma_fence_put(&array->base);
82 dma_fence_put(fences[count]);
88 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
90 * @dmabuf: DMA-buf where we attach to
91 * @attach: attachment to add
93 * Add the attachment as user to the exported DMA-buf.
95 static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
96 struct dma_buf_attachment *attach)
98 struct drm_gem_object *obj = dmabuf->priv;
99 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
100 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
103 if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0)
104 attach->peer2peer = false;
106 if (attach->dev->driver == adev->dev->driver)
109 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
113 r = amdgpu_bo_reserve(bo, false);
114 if (unlikely(r != 0))
118 * We only create shared fences for internal use, but importers
119 * of the dmabuf rely on exclusive fences for implicitly
120 * tracking write hazards. As any of the current fences may
121 * correspond to a write, we need to convert all existing
122 * fences on the reservation object into a single exclusive
125 r = __dma_resv_make_exclusive(bo->tbo.base.resv);
129 bo->prime_shared_count++;
130 amdgpu_bo_unreserve(bo);
134 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
139 * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
141 * @dmabuf: DMA-buf where we remove the attachment from
142 * @attach: the attachment to remove
144 * Called when an attachment is removed from the DMA-buf.
146 static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
147 struct dma_buf_attachment *attach)
149 struct drm_gem_object *obj = dmabuf->priv;
150 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
151 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
153 if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
154 bo->prime_shared_count--;
156 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
157 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
161 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
163 * @attach: attachment to pin down
165 * Pin the BO which is backing the DMA-buf so that it can't move any more.
167 static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
169 struct drm_gem_object *obj = attach->dmabuf->priv;
170 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
173 /* pin buffer into GTT */
174 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
178 if (bo->tbo.moving) {
179 r = dma_fence_wait(bo->tbo.moving, true);
189 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
191 * @attach: attachment to unpin
193 * Unpin a previously pinned BO to make it movable again.
195 static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
197 struct drm_gem_object *obj = attach->dmabuf->priv;
198 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
204 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
205 * @attach: DMA-buf attachment
206 * @dir: DMA direction
208 * Makes sure that the shared DMA buffer can be accessed by the target device.
209 * For now, simply pins it to the GTT domain, where it should be accessible by
213 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
216 static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
217 enum dma_data_direction dir)
219 struct dma_buf *dma_buf = attach->dmabuf;
220 struct drm_gem_object *obj = dma_buf->priv;
221 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
222 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
223 struct sg_table *sgt;
226 if (!bo->tbo.pin_count) {
227 /* move buffer into GTT or VRAM */
228 struct ttm_operation_ctx ctx = { false, false };
229 unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
231 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
233 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
234 domains |= AMDGPU_GEM_DOMAIN_VRAM;
236 amdgpu_bo_placement_from_domain(bo, domains);
237 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
241 } else if (!(amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type) &
242 AMDGPU_GEM_DOMAIN_GTT)) {
243 return ERR_PTR(-EBUSY);
246 switch (bo->tbo.resource->mem_type) {
248 sgt = drm_prime_pages_to_sg(obj->dev,
250 bo->tbo.ttm->num_pages);
254 if (dma_map_sgtable(attach->dev, sgt, dir,
255 DMA_ATTR_SKIP_CPU_SYNC))
260 r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
261 bo->tbo.base.size, attach->dev,
267 return ERR_PTR(-EINVAL);
275 return ERR_PTR(-EBUSY);
279 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
280 * @attach: DMA-buf attachment
281 * @sgt: sg_table to unmap
282 * @dir: DMA direction
284 * This is called when a shared DMA buffer no longer needs to be accessible by
285 * another device. For now, simply unpins the buffer from GTT.
287 static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
288 struct sg_table *sgt,
289 enum dma_data_direction dir)
291 if (sgt->sgl->page_link) {
292 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
296 amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt);
301 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
302 * @dma_buf: Shared DMA buffer
303 * @direction: Direction of DMA transfer
305 * This is called before CPU access to the shared DMA buffer's memory. If it's
306 * a read access, the buffer is moved to the GTT domain if possible, for optimal
307 * CPU read performance.
310 * 0 on success or a negative error code on failure.
312 static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
313 enum dma_data_direction direction)
315 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
316 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
317 struct ttm_operation_ctx ctx = { true, false };
318 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
320 bool reads = (direction == DMA_BIDIRECTIONAL ||
321 direction == DMA_FROM_DEVICE);
323 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
327 ret = amdgpu_bo_reserve(bo, false);
328 if (unlikely(ret != 0))
331 if (!bo->tbo.pin_count &&
332 (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
333 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
334 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
337 amdgpu_bo_unreserve(bo);
341 const struct dma_buf_ops amdgpu_dmabuf_ops = {
342 .attach = amdgpu_dma_buf_attach,
343 .detach = amdgpu_dma_buf_detach,
344 .pin = amdgpu_dma_buf_pin,
345 .unpin = amdgpu_dma_buf_unpin,
346 .map_dma_buf = amdgpu_dma_buf_map,
347 .unmap_dma_buf = amdgpu_dma_buf_unmap,
348 .release = drm_gem_dmabuf_release,
349 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
350 .mmap = drm_gem_dmabuf_mmap,
351 .vmap = drm_gem_dmabuf_vmap,
352 .vunmap = drm_gem_dmabuf_vunmap,
356 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
358 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
360 * The main work is done by the &drm_gem_prime_export helper.
363 * Shared DMA buffer representing the GEM BO from the given device.
365 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
368 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
371 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
372 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
373 return ERR_PTR(-EPERM);
375 buf = drm_gem_prime_export(gobj, flags);
377 buf->ops = &amdgpu_dmabuf_ops;
383 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
388 * Creates an empty SG BO for DMA-buf import.
391 * A new GEM BO of the given DRM device, representing the memory
392 * described by the given DMA-buf attachment and scatter/gather table.
394 static struct drm_gem_object *
395 amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
397 struct dma_resv *resv = dma_buf->resv;
398 struct amdgpu_device *adev = drm_to_adev(dev);
399 struct drm_gem_object *gobj;
400 struct amdgpu_bo *bo;
404 dma_resv_lock(resv, NULL);
406 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
407 struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
409 flags |= other->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;
412 ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
413 AMDGPU_GEM_DOMAIN_CPU, flags,
414 ttm_bo_type_sg, resv, &gobj);
418 bo = gem_to_amdgpu_bo(gobj);
419 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
420 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
421 if (dma_buf->ops != &amdgpu_dmabuf_ops)
422 bo->prime_shared_count = 1;
424 dma_resv_unlock(resv);
428 dma_resv_unlock(resv);
433 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
435 * @attach: the DMA-buf attachment
437 * Invalidate the DMA-buf attachment, making sure that the we re-create the
438 * mapping before the next use.
441 amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
443 struct drm_gem_object *obj = attach->importer_priv;
444 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
445 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
446 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
447 struct ttm_operation_ctx ctx = { false, false };
448 struct ttm_placement placement = {};
449 struct amdgpu_vm_bo_base *bo_base;
452 if (bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
455 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
457 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
461 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
462 struct amdgpu_vm *vm = bo_base->vm;
463 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
466 /* When we get an error here it means that somebody
467 * else is holding the VM lock and updating page tables
468 * So we can just continue here.
470 r = dma_resv_lock(resv, ticket);
475 /* TODO: This is more problematic and we actually need
476 * to allow page tables updates without holding the
479 if (!dma_resv_trylock(resv))
483 r = amdgpu_vm_clear_freed(adev, vm, NULL);
485 r = amdgpu_vm_handle_moved(adev, vm);
487 if (r && r != -EBUSY)
488 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
491 dma_resv_unlock(resv);
495 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
496 .allow_peer2peer = true,
497 .move_notify = amdgpu_dma_buf_move_notify
501 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
503 * @dma_buf: Shared DMA buffer
505 * Import a dma_buf into a the driver and potentially create a new GEM object.
508 * GEM BO representing the shared DMA buffer for the given device.
510 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
511 struct dma_buf *dma_buf)
513 struct dma_buf_attachment *attach;
514 struct drm_gem_object *obj;
516 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
518 if (obj->dev == dev) {
520 * Importing dmabuf exported from out own gem increases
521 * refcount on gem itself instead of f_count of dmabuf.
523 drm_gem_object_get(obj);
528 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
532 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
533 &amdgpu_dma_buf_attach_ops, obj);
534 if (IS_ERR(attach)) {
535 drm_gem_object_put(obj);
536 return ERR_CAST(attach);
539 get_dma_buf(dma_buf);
540 obj->import_attach = attach;
545 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
547 * @adev: amdgpu_device pointer of the importer
548 * @bo: amdgpu buffer object
551 * True if dmabuf accessible over xgmi, false otherwise.
553 bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
554 struct amdgpu_bo *bo)
556 struct drm_gem_object *obj = &bo->tbo.base;
557 struct drm_gem_object *gobj;
559 if (obj->import_attach) {
560 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
562 if (dma_buf->ops != &amdgpu_dmabuf_ops)
563 /* No XGMI with non AMD GPUs */
566 gobj = dma_buf->priv;
567 bo = gem_to_amdgpu_bo(gobj);
570 if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
571 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))