drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30
  31 #include "soc15.h"
  32 #include "gfx_v9_0.h"
  33 #include "gmc_v9_0.h"
  34 #include "df_v1_7.h"
  35 #include "df_v3_6.h"
  36 #include "nbio_v6_1.h"
  37 #include "nbio_v7_0.h"
  38 #include "nbio_v7_4.h"
  39 #include "hdp_v4_0.h"
  40 #include "vega10_ih.h"
  41 #include "vega20_ih.h"
  42 #include "sdma_v4_0.h"
  43 #include "uvd_v7_0.h"
  44 #include "vce_v4_0.h"
  45 #include "vcn_v1_0.h"
  46 #include "vcn_v2_5.h"
  47 #include "jpeg_v2_5.h"
  48 #include "smuio_v9_0.h"
  49 #include "gmc_v10_0.h"
  50 #include "gfxhub_v2_0.h"
  51 #include "mmhub_v2_0.h"
  52 #include "nbio_v2_3.h"
  53 #include "nbio_v7_2.h"
  54 #include "hdp_v5_0.h"
  55 #include "nv.h"
  56 #include "navi10_ih.h"
  57 #include "gfx_v10_0.h"
  58 #include "sdma_v5_0.h"
  59 #include "sdma_v5_2.h"
  60 #include "vcn_v2_0.h"
  61 #include "jpeg_v2_0.h"
  62 #include "vcn_v3_0.h"
  63 #include "jpeg_v3_0.h"
  64 #include "amdgpu_vkms.h"
  65 #include "mes_v10_1.h"
  66 #include "smuio_v11_0.h"
  67 #include "smuio_v11_0_6.h"
  68 #include "smuio_v13_0.h"
  69
  70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
  71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
  72
  73 #define mmRCC_CONFIG_MEMSIZE    0xde3
  74 #define mmMM_INDEX              0x0
  75 #define mmMM_INDEX_HI           0x6
  76 #define mmMM_DATA               0x1
  77
  78 static const char *hw_id_names[HW_ID_MAX] = {
  79         [MP1_HWID]              = "MP1",
  80         [MP2_HWID]              = "MP2",
  81         [THM_HWID]              = "THM",
  82         [SMUIO_HWID]            = "SMUIO",
  83         [FUSE_HWID]             = "FUSE",
  84         [CLKA_HWID]             = "CLKA",
  85         [PWR_HWID]              = "PWR",
  86         [GC_HWID]               = "GC",
  87         [UVD_HWID]              = "UVD",
  88         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
  89         [ACP_HWID]              = "ACP",
  90         [DCI_HWID]              = "DCI",
  91         [DMU_HWID]              = "DMU",
  92         [DCO_HWID]              = "DCO",
  93         [DIO_HWID]              = "DIO",
  94         [XDMA_HWID]             = "XDMA",
  95         [DCEAZ_HWID]            = "DCEAZ",
  96         [DAZ_HWID]              = "DAZ",
  97         [SDPMUX_HWID]           = "SDPMUX",
  98         [NTB_HWID]              = "NTB",
  99         [IOHC_HWID]             = "IOHC",
 100         [L2IMU_HWID]            = "L2IMU",
 101         [VCE_HWID]              = "VCE",
 102         [MMHUB_HWID]            = "MMHUB",
 103         [ATHUB_HWID]            = "ATHUB",
 104         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 105         [DFX_HWID]              = "DFX",
 106         [DBGU0_HWID]            = "DBGU0",
 107         [DBGU1_HWID]            = "DBGU1",
 108         [OSSSYS_HWID]           = "OSSSYS",
 109         [HDP_HWID]              = "HDP",
 110         [SDMA0_HWID]            = "SDMA0",
 111         [SDMA1_HWID]            = "SDMA1",
 112         [SDMA2_HWID]            = "SDMA2",
 113         [SDMA3_HWID]            = "SDMA3",
 114         [ISP_HWID]              = "ISP",
 115         [DBGU_IO_HWID]          = "DBGU_IO",
 116         [DF_HWID]               = "DF",
 117         [CLKB_HWID]             = "CLKB",
 118         [FCH_HWID]              = "FCH",
 119         [DFX_DAP_HWID]          = "DFX_DAP",
 120         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 121         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 122         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 123         [L1IMU3_HWID]           = "L1IMU3",
 124         [L1IMU4_HWID]           = "L1IMU4",
 125         [L1IMU5_HWID]           = "L1IMU5",
 126         [L1IMU6_HWID]           = "L1IMU6",
 127         [L1IMU7_HWID]           = "L1IMU7",
 128         [L1IMU8_HWID]           = "L1IMU8",
 129         [L1IMU9_HWID]           = "L1IMU9",
 130         [L1IMU10_HWID]          = "L1IMU10",
 131         [L1IMU11_HWID]          = "L1IMU11",
 132         [L1IMU12_HWID]          = "L1IMU12",
 133         [L1IMU13_HWID]          = "L1IMU13",
 134         [L1IMU14_HWID]          = "L1IMU14",
 135         [L1IMU15_HWID]          = "L1IMU15",
 136         [WAFLC_HWID]            = "WAFLC",
 137         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 138         [PCIE_HWID]             = "PCIE",
 139         [PCS_HWID]              = "PCS",
 140         [DDCL_HWID]             = "DDCL",
 141         [SST_HWID]              = "SST",
 142         [IOAGR_HWID]            = "IOAGR",
 143         [NBIF_HWID]             = "NBIF",
 144         [IOAPIC_HWID]           = "IOAPIC",
 145         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 146         [NTBCCP_HWID]           = "NTBCCP",
 147         [UMC_HWID]              = "UMC",
 148         [SATA_HWID]             = "SATA",
 149         [USB_HWID]              = "USB",
 150         [CCXSEC_HWID]           = "CCXSEC",
 151         [XGMI_HWID]             = "XGMI",
 152         [XGBE_HWID]             = "XGBE",
 153         [MP0_HWID]              = "MP0",
 154 };
 155
 156 static int hw_id_map[MAX_HWIP] = {
 157         [GC_HWIP]       = GC_HWID,
 158         [HDP_HWIP]      = HDP_HWID,
 159         [SDMA0_HWIP]    = SDMA0_HWID,
 160         [SDMA1_HWIP]    = SDMA1_HWID,
 161         [SDMA2_HWIP]    = SDMA2_HWID,
 162         [SDMA3_HWIP]    = SDMA3_HWID,
 163         [MMHUB_HWIP]    = MMHUB_HWID,
 164         [ATHUB_HWIP]    = ATHUB_HWID,
 165         [NBIO_HWIP]     = NBIF_HWID,
 166         [MP0_HWIP]      = MP0_HWID,
 167         [MP1_HWIP]      = MP1_HWID,
 168         [UVD_HWIP]      = UVD_HWID,
 169         [VCE_HWIP]      = VCE_HWID,
 170         [DF_HWIP]       = DF_HWID,
 171         [DCE_HWIP]      = DMU_HWID,
 172         [OSSSYS_HWIP]   = OSSSYS_HWID,
 173         [SMUIO_HWIP]    = SMUIO_HWID,
 174         [PWR_HWIP]      = PWR_HWID,
 175         [NBIF_HWIP]     = NBIF_HWID,
 176         [THM_HWIP]      = THM_HWID,
 177         [CLK_HWIP]      = CLKA_HWID,
 178         [UMC_HWIP]      = UMC_HWID,
 179         [XGMI_HWIP]     = XGMI_HWID,
 180         [DCI_HWIP]      = DCI_HWID,
 181 };
 182
 183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
 184 {
 185         uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 186         uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 187
 188         amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 189                                   adev->mman.discovery_tmr_size, false);
 190         return 0;
 191 }
 192
 193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
 194 {
 195         const struct firmware *fw;
 196         const char *fw_name;
 197         int r;
 198
 199         switch (amdgpu_discovery) {
 200         case 2:
 201                 fw_name = FIRMWARE_IP_DISCOVERY;
 202                 break;
 203         default:
 204                 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
 205                 return -EINVAL;
 206         }
 207
 208         r = request_firmware(&fw, fw_name, adev->dev);
 209         if (r) {
 210                 dev_err(adev->dev, "can't load firmware \"%s\"\n",
 211                         fw_name);
 212                 return r;
 213         }
 214
 215         memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
 216         release_firmware(fw);
 217
 218         return 0;
 219 }
 220
 221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 222 {
 223         uint16_t checksum = 0;
 224         int i;
 225
 226         for (i = 0; i < size; i++)
 227                 checksum += data[i];
 228
 229         return checksum;
 230 }
 231
 232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 233                                                     uint16_t expected)
 234 {
 235         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 236 }
 237
 238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
 239 {
 240         struct binary_header *bhdr;
 241         bhdr = (struct binary_header *)binary;
 242
 243         return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
 244 }
 245
 246 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 247 {
 248         struct table_info *info;
 249         struct binary_header *bhdr;
 250         struct ip_discovery_header *ihdr;
 251         struct gpu_info_header *ghdr;
 252         uint16_t offset;
 253         uint16_t size;
 254         uint16_t checksum;
 255         int r;
 256
 257         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 258         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 259         if (!adev->mman.discovery_bin)
 260                 return -ENOMEM;
 261
 262         r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin);
 263         if (r) {
 264                 dev_err(adev->dev, "failed to read ip discovery binary from vram\n");
 265                 r = -EINVAL;
 266                 goto out;
 267         }
 268
 269         if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 270                 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n");
 271                 /* retry read ip discovery binary from file */
 272                 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
 273                 if (r) {
 274                         dev_err(adev->dev, "failed to read ip discovery binary from file\n");
 275                         r = -EINVAL;
 276                         goto out;
 277                 }
 278                 /* check the ip discovery binary signature */
 279                 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 280                         dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n");
 281                         r = -EINVAL;
 282                         goto out;
 283                 }
 284         }
 285
 286         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 287
 288         offset = offsetof(struct binary_header, binary_checksum) +
 289                 sizeof(bhdr->binary_checksum);
 290         size = le16_to_cpu(bhdr->binary_size) - offset;
 291         checksum = le16_to_cpu(bhdr->binary_checksum);
 292
 293         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 294                                               size, checksum)) {
 295                 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
 296                 r = -EINVAL;
 297                 goto out;
 298         }
 299
 300         info = &bhdr->table_list[IP_DISCOVERY];
 301         offset = le16_to_cpu(info->offset);
 302         checksum = le16_to_cpu(info->checksum);
 303         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 304
 305         if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 306                 dev_err(adev->dev, "invalid ip discovery data table signature\n");
 307                 r = -EINVAL;
 308                 goto out;
 309         }
 310
 311         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 312                                               le16_to_cpu(ihdr->size), checksum)) {
 313                 dev_err(adev->dev, "invalid ip discovery data table checksum\n");
 314                 r = -EINVAL;
 315                 goto out;
 316         }
 317
 318         info = &bhdr->table_list[GC];
 319         offset = le16_to_cpu(info->offset);
 320         checksum = le16_to_cpu(info->checksum);
 321         ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 322
 323         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 324                                               le32_to_cpu(ghdr->size), checksum)) {
 325                 dev_err(adev->dev, "invalid gc data table checksum\n");
 326                 r = -EINVAL;
 327                 goto out;
 328         }
 329
 330         return 0;
 331
 332 out:
 333         kfree(adev->mman.discovery_bin);
 334         adev->mman.discovery_bin = NULL;
 335
 336         return r;
 337 }
 338
 339 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 340 {
 341         kfree(adev->mman.discovery_bin);
 342         adev->mman.discovery_bin = NULL;
 343 }
 344
 345 static int amdgpu_discovery_validate_ip(const struct ip *ip)
 346 {
 347         if (ip->number_instance >= HWIP_MAX_INSTANCE) {
 348                 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
 349                           ip->number_instance);
 350                 return -EINVAL;
 351         }
 352         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 353                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 354                           le16_to_cpu(ip->hw_id));
 355                 return -EINVAL;
 356         }
 357
 358         return 0;
 359 }
 360
 361 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 362 {
 363         struct binary_header *bhdr;
 364         struct ip_discovery_header *ihdr;
 365         struct die_header *dhdr;
 366         struct ip *ip;
 367         uint16_t die_offset;
 368         uint16_t ip_offset;
 369         uint16_t num_dies;
 370         uint16_t num_ips;
 371         uint8_t num_base_address;
 372         int hw_ip;
 373         int i, j, k;
 374         int r;
 375
 376         r = amdgpu_discovery_init(adev);
 377         if (r) {
 378                 DRM_ERROR("amdgpu_discovery_init failed\n");
 379                 return r;
 380         }
 381
 382         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 383         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 384                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 385         num_dies = le16_to_cpu(ihdr->num_dies);
 386
 387         DRM_DEBUG("number of dies: %d\n", num_dies);
 388
 389         for (i = 0; i < num_dies; i++) {
 390                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 391                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 392                 num_ips = le16_to_cpu(dhdr->num_ips);
 393                 ip_offset = die_offset + sizeof(*dhdr);
 394
 395                 if (le16_to_cpu(dhdr->die_id) != i) {
 396                         DRM_ERROR("invalid die id %d, expected %d\n",
 397                                         le16_to_cpu(dhdr->die_id), i);
 398                         return -EINVAL;
 399                 }
 400
 401                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
 402                                 le16_to_cpu(dhdr->die_id), num_ips);
 403
 404                 for (j = 0; j < num_ips; j++) {
 405                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 406
 407                         if (amdgpu_discovery_validate_ip(ip))
 408                                 goto next_ip;
 409
 410                         num_base_address = ip->num_base_address;
 411
 412                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
 413                                   hw_id_names[le16_to_cpu(ip->hw_id)],
 414                                   le16_to_cpu(ip->hw_id),
 415                                   ip->number_instance,
 416                                   ip->major, ip->minor,
 417                                   ip->revision);
 418
 419                         if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
 420                                 /* Bit [5:0]: original revision value
 421                                  * Bit [7:6]: en/decode capability:
 422                                  *     0b00 : VCN function normally
 423                                  *     0b10 : encode is disabled
 424                                  *     0b01 : decode is disabled
 425                                  */
 426                                 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
 427                                         ip->revision & 0xc0;
 428                                 ip->revision &= ~0xc0;
 429                                 adev->vcn.num_vcn_inst++;
 430                         }
 431                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
 432                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
 433                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
 434                             le16_to_cpu(ip->hw_id) == SDMA3_HWID)
 435                                 adev->sdma.num_instances++;
 436
 437                         for (k = 0; k < num_base_address; k++) {
 438                                 /*
 439                                  * convert the endianness of base addresses in place,
 440                                  * so that we don't need to convert them when accessing adev->reg_offset.
 441                                  */
 442                                 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
 443                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
 444                         }
 445
 446                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
 447                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
 448                                         DRM_DEBUG("set register base offset for %s\n",
 449                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
 450                                         adev->reg_offset[hw_ip][ip->number_instance] =
 451                                                 ip->base_address;
 452                                         /* Instance support is somewhat inconsistent.
 453                                          * SDMA is a good example.  Sienna cichlid has 4 total
 454                                          * SDMA instances, each enumerated separately (HWIDs
 455                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
 456                                          * but they are enumerated as multiple instances of the
 457                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
 458                                          * example.  On most chips there are multiple instances
 459                                          * with the same HWID.
 460                                          */
 461                                         adev->ip_versions[hw_ip][ip->number_instance] =
 462                                                 IP_VERSION(ip->major, ip->minor, ip->revision);
 463                                 }
 464                         }
 465
 466 next_ip:
 467                         ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
 468                 }
 469         }
 470
 471         return 0;
 472 }
 473
 474 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
 475                                     int *major, int *minor, int *revision)
 476 {
 477         struct binary_header *bhdr;
 478         struct ip_discovery_header *ihdr;
 479         struct die_header *dhdr;
 480         struct ip *ip;
 481         uint16_t die_offset;
 482         uint16_t ip_offset;
 483         uint16_t num_dies;
 484         uint16_t num_ips;
 485         int i, j;
 486
 487         if (!adev->mman.discovery_bin) {
 488                 DRM_ERROR("ip discovery uninitialized\n");
 489                 return -EINVAL;
 490         }
 491
 492         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 493         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 494                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 495         num_dies = le16_to_cpu(ihdr->num_dies);
 496
 497         for (i = 0; i < num_dies; i++) {
 498                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 499                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 500                 num_ips = le16_to_cpu(dhdr->num_ips);
 501                 ip_offset = die_offset + sizeof(*dhdr);
 502
 503                 for (j = 0; j < num_ips; j++) {
 504                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 505
 506                         if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
 507                                 if (major)
 508                                         *major = ip->major;
 509                                 if (minor)
 510                                         *minor = ip->minor;
 511                                 if (revision)
 512                                         *revision = ip->revision;
 513                                 return 0;
 514                         }
 515                         ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
 516                 }
 517         }
 518
 519         return -EINVAL;
 520 }
 521
 522 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
 523 {
 524         struct binary_header *bhdr;
 525         struct harvest_table *harvest_info;
 526         int i, vcn_harvest_count = 0;
 527
 528         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 529         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
 530                         le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
 531
 532         for (i = 0; i < 32; i++) {
 533                 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
 534                         break;
 535
 536                 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
 537                 case VCN_HWID:
 538                         vcn_harvest_count++;
 539                         if (harvest_info->list[i].number_instance == 0)
 540                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 541                         else
 542                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 543                         break;
 544                 case DMU_HWID:
 545                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 546                         break;
 547                 default:
 548                         break;
 549                 }
 550         }
 551         /* some IP discovery tables on Navy Flounder don't have this set correctly */
 552         if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
 553             (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2)) &&
 554             (adev->pdev->revision != 0xFF))
 555                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 556         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
 557                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
 558                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
 559         }
 560         if ((adev->pdev->device == 0x731E &&
 561              (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) ||
 562             (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9)  ||
 563             (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) {
 564                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
 565                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
 566         }
 567 }
 568
 569 union gc_info {
 570         struct gc_info_v1_0 v1;
 571         struct gc_info_v2_0 v2;
 572 };
 573
 574 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
 575 {
 576         struct binary_header *bhdr;
 577         union gc_info *gc_info;
 578
 579         if (!adev->mman.discovery_bin) {
 580                 DRM_ERROR("ip discovery uninitialized\n");
 581                 return -EINVAL;
 582         }
 583
 584         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 585         gc_info = (union gc_info *)(adev->mman.discovery_bin +
 586                         le16_to_cpu(bhdr->table_list[GC].offset));
 587         switch (gc_info->v1.header.version_major) {
 588         case 1:
 589                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
 590                 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
 591                                                       le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
 592                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
 593                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
 594                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
 595                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
 596                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
 597                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
 598                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
 599                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
 600                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
 601                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
 602                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
 603                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
 604                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
 605                         le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
 606                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
 607                 break;
 608         case 2:
 609                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
 610                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
 611                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
 612                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
 613                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
 614                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
 615                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
 616                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
 617                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
 618                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
 619                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
 620                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
 621                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
 622                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
 623                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
 624                         le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
 625                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
 626                 break;
 627         default:
 628                 dev_err(adev->dev,
 629                         "Unhandled GC info table %d.%d\n",
 630                         gc_info->v1.header.version_major,
 631                         gc_info->v1.header.version_minor);
 632                 return -EINVAL;
 633         }
 634         return 0;
 635 }
 636
 637 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
 638 {
 639         /* what IP to use for this? */
 640         switch (adev->ip_versions[GC_HWIP][0]) {
 641         case IP_VERSION(9, 0, 1):
 642         case IP_VERSION(9, 1, 0):
 643         case IP_VERSION(9, 2, 1):
 644         case IP_VERSION(9, 2, 2):
 645         case IP_VERSION(9, 3, 0):
 646         case IP_VERSION(9, 4, 0):
 647         case IP_VERSION(9, 4, 1):
 648         case IP_VERSION(9, 4, 2):
 649                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 650                 break;
 651         case IP_VERSION(10, 1, 10):
 652         case IP_VERSION(10, 1, 1):
 653         case IP_VERSION(10, 1, 2):
 654         case IP_VERSION(10, 1, 3):
 655         case IP_VERSION(10, 3, 0):
 656         case IP_VERSION(10, 3, 1):
 657         case IP_VERSION(10, 3, 2):
 658         case IP_VERSION(10, 3, 3):
 659         case IP_VERSION(10, 3, 4):
 660         case IP_VERSION(10, 3, 5):
 661                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 662                 break;
 663         default:
 664                 dev_err(adev->dev,
 665                         "Failed to add common ip block(GC_HWIP:0x%x)\n",
 666                         adev->ip_versions[GC_HWIP][0]);
 667                 return -EINVAL;
 668         }
 669         return 0;
 670 }
 671
 672 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
 673 {
 674         /* use GC or MMHUB IP version */
 675         switch (adev->ip_versions[GC_HWIP][0]) {
 676         case IP_VERSION(9, 0, 1):
 677         case IP_VERSION(9, 1, 0):
 678         case IP_VERSION(9, 2, 1):
 679         case IP_VERSION(9, 2, 2):
 680         case IP_VERSION(9, 3, 0):
 681         case IP_VERSION(9, 4, 0):
 682         case IP_VERSION(9, 4, 1):
 683         case IP_VERSION(9, 4, 2):
 684                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 685                 break;
 686         case IP_VERSION(10, 1, 10):
 687         case IP_VERSION(10, 1, 1):
 688         case IP_VERSION(10, 1, 2):
 689         case IP_VERSION(10, 1, 3):
 690         case IP_VERSION(10, 3, 0):
 691         case IP_VERSION(10, 3, 1):
 692         case IP_VERSION(10, 3, 2):
 693         case IP_VERSION(10, 3, 3):
 694         case IP_VERSION(10, 3, 4):
 695         case IP_VERSION(10, 3, 5):
 696                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 697                 break;
 698         default:
 699                 dev_err(adev->dev,
 700                         "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
 701                         adev->ip_versions[GC_HWIP][0]);
 702                 return -EINVAL;
 703         }
 704         return 0;
 705 }
 706
 707 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
 708 {
 709         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
 710         case IP_VERSION(4, 0, 0):
 711         case IP_VERSION(4, 0, 1):
 712         case IP_VERSION(4, 1, 0):
 713         case IP_VERSION(4, 1, 1):
 714         case IP_VERSION(4, 3, 0):
 715                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 716                 break;
 717         case IP_VERSION(4, 2, 0):
 718         case IP_VERSION(4, 2, 1):
 719         case IP_VERSION(4, 4, 0):
 720                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
 721                 break;
 722         case IP_VERSION(5, 0, 0):
 723         case IP_VERSION(5, 0, 1):
 724         case IP_VERSION(5, 0, 2):
 725         case IP_VERSION(5, 0, 3):
 726         case IP_VERSION(5, 2, 0):
 727         case IP_VERSION(5, 2, 1):
 728                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 729                 break;
 730         default:
 731                 dev_err(adev->dev,
 732                         "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
 733                         adev->ip_versions[OSSSYS_HWIP][0]);
 734                 return -EINVAL;
 735         }
 736         return 0;
 737 }
 738
 739 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
 740 {
 741         switch (adev->ip_versions[MP0_HWIP][0]) {
 742         case IP_VERSION(9, 0, 0):
 743                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 744                 break;
 745         case IP_VERSION(10, 0, 0):
 746         case IP_VERSION(10, 0, 1):
 747                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 748                 break;
 749         case IP_VERSION(11, 0, 0):
 750         case IP_VERSION(11, 0, 2):
 751         case IP_VERSION(11, 0, 4):
 752         case IP_VERSION(11, 0, 5):
 753         case IP_VERSION(11, 0, 9):
 754         case IP_VERSION(11, 0, 7):
 755         case IP_VERSION(11, 0, 11):
 756         case IP_VERSION(11, 0, 12):
 757         case IP_VERSION(11, 0, 13):
 758         case IP_VERSION(11, 5, 0):
 759                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 760                 break;
 761         case IP_VERSION(11, 0, 8):
 762                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
 763                 break;
 764         case IP_VERSION(11, 0, 3):
 765         case IP_VERSION(12, 0, 1):
 766                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
 767                 break;
 768         case IP_VERSION(13, 0, 1):
 769         case IP_VERSION(13, 0, 2):
 770         case IP_VERSION(13, 0, 3):
 771                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
 772                 break;
 773         default:
 774                 dev_err(adev->dev,
 775                         "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
 776                         adev->ip_versions[MP0_HWIP][0]);
 777                 return -EINVAL;
 778         }
 779         return 0;
 780 }
 781
 782 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
 783 {
 784         switch (adev->ip_versions[MP1_HWIP][0]) {
 785         case IP_VERSION(9, 0, 0):
 786         case IP_VERSION(10, 0, 0):
 787         case IP_VERSION(10, 0, 1):
 788         case IP_VERSION(11, 0, 2):
 789                 if (adev->asic_type == CHIP_ARCTURUS)
 790                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 791                 else
 792                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 793                 break;
 794         case IP_VERSION(11, 0, 0):
 795         case IP_VERSION(11, 0, 5):
 796         case IP_VERSION(11, 0, 9):
 797         case IP_VERSION(11, 0, 7):
 798         case IP_VERSION(11, 0, 8):
 799         case IP_VERSION(11, 0, 11):
 800         case IP_VERSION(11, 0, 12):
 801         case IP_VERSION(11, 0, 13):
 802         case IP_VERSION(11, 5, 0):
 803                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 804                 break;
 805         case IP_VERSION(12, 0, 0):
 806         case IP_VERSION(12, 0, 1):
 807                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
 808                 break;
 809         case IP_VERSION(13, 0, 1):
 810         case IP_VERSION(13, 0, 2):
 811         case IP_VERSION(13, 0, 3):
 812                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
 813                 break;
 814         default:
 815                 dev_err(adev->dev,
 816                         "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
 817                         adev->ip_versions[MP1_HWIP][0]);
 818                 return -EINVAL;
 819         }
 820         return 0;
 821 }
 822
 823 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
 824 {
 825         if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
 826                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 827 #if defined(CONFIG_DRM_AMD_DC)
 828         } else if (adev->ip_versions[DCE_HWIP][0]) {
 829                 switch (adev->ip_versions[DCE_HWIP][0]) {
 830                 case IP_VERSION(1, 0, 0):
 831                 case IP_VERSION(1, 0, 1):
 832                 case IP_VERSION(2, 0, 2):
 833                 case IP_VERSION(2, 0, 0):
 834                 case IP_VERSION(2, 0, 3):
 835                 case IP_VERSION(2, 1, 0):
 836                 case IP_VERSION(3, 0, 0):
 837                 case IP_VERSION(3, 0, 2):
 838                 case IP_VERSION(3, 0, 3):
 839                 case IP_VERSION(3, 0, 1):
 840                 case IP_VERSION(3, 1, 2):
 841                 case IP_VERSION(3, 1, 3):
 842                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 843                         break;
 844                 default:
 845                         dev_err(adev->dev,
 846                                 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
 847                                 adev->ip_versions[DCE_HWIP][0]);
 848                         return -EINVAL;
 849                 }
 850         } else if (adev->ip_versions[DCI_HWIP][0]) {
 851                 switch (adev->ip_versions[DCI_HWIP][0]) {
 852                 case IP_VERSION(12, 0, 0):
 853                 case IP_VERSION(12, 0, 1):
 854                 case IP_VERSION(12, 1, 0):
 855                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 856                         break;
 857                 default:
 858                         dev_err(adev->dev,
 859                                 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
 860                                 adev->ip_versions[DCI_HWIP][0]);
 861                         return -EINVAL;
 862                 }
 863 #endif
 864         }
 865         return 0;
 866 }
 867
 868 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
 869 {
 870         switch (adev->ip_versions[GC_HWIP][0]) {
 871         case IP_VERSION(9, 0, 1):
 872         case IP_VERSION(9, 1, 0):
 873         case IP_VERSION(9, 2, 1):
 874         case IP_VERSION(9, 2, 2):
 875         case IP_VERSION(9, 3, 0):
 876         case IP_VERSION(9, 4, 0):
 877         case IP_VERSION(9, 4, 1):
 878         case IP_VERSION(9, 4, 2):
 879                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 880                 break;
 881         case IP_VERSION(10, 1, 10):
 882         case IP_VERSION(10, 1, 2):
 883         case IP_VERSION(10, 1, 1):
 884         case IP_VERSION(10, 1, 3):
 885         case IP_VERSION(10, 3, 0):
 886         case IP_VERSION(10, 3, 2):
 887         case IP_VERSION(10, 3, 1):
 888         case IP_VERSION(10, 3, 4):
 889         case IP_VERSION(10, 3, 5):
 890         case IP_VERSION(10, 3, 3):
 891                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 892                 break;
 893         default:
 894                 dev_err(adev->dev,
 895                         "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
 896                         adev->ip_versions[GC_HWIP][0]);
 897                 return -EINVAL;
 898         }
 899         return 0;
 900 }
 901
 902 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
 903 {
 904         switch (adev->ip_versions[SDMA0_HWIP][0]) {
 905         case IP_VERSION(4, 0, 0):
 906         case IP_VERSION(4, 0, 1):
 907         case IP_VERSION(4, 1, 0):
 908         case IP_VERSION(4, 1, 1):
 909         case IP_VERSION(4, 1, 2):
 910         case IP_VERSION(4, 2, 0):
 911         case IP_VERSION(4, 2, 2):
 912         case IP_VERSION(4, 4, 0):
 913                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 914                 break;
 915         case IP_VERSION(5, 0, 0):
 916         case IP_VERSION(5, 0, 1):
 917         case IP_VERSION(5, 0, 2):
 918         case IP_VERSION(5, 0, 5):
 919                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 920                 break;
 921         case IP_VERSION(5, 2, 0):
 922         case IP_VERSION(5, 2, 2):
 923         case IP_VERSION(5, 2, 4):
 924         case IP_VERSION(5, 2, 5):
 925         case IP_VERSION(5, 2, 3):
 926         case IP_VERSION(5, 2, 1):
 927                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 928                 break;
 929         default:
 930                 dev_err(adev->dev,
 931                         "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
 932                         adev->ip_versions[SDMA0_HWIP][0]);
 933                 return -EINVAL;
 934         }
 935         return 0;
 936 }
 937
 938 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
 939 {
 940         if (adev->ip_versions[VCE_HWIP][0]) {
 941                 switch (adev->ip_versions[UVD_HWIP][0]) {
 942                 case IP_VERSION(7, 0, 0):
 943                 case IP_VERSION(7, 2, 0):
 944                         /* UVD is not supported on vega20 SR-IOV */
 945                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
 946                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 947                         break;
 948                 default:
 949                         dev_err(adev->dev,
 950                                 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
 951                                 adev->ip_versions[UVD_HWIP][0]);
 952                         return -EINVAL;
 953                 }
 954                 switch (adev->ip_versions[VCE_HWIP][0]) {
 955                 case IP_VERSION(4, 0, 0):
 956                 case IP_VERSION(4, 1, 0):
 957                         /* VCE is not supported on vega20 SR-IOV */
 958                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
 959                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 960                         break;
 961                 default:
 962                         dev_err(adev->dev,
 963                                 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
 964                                 adev->ip_versions[VCE_HWIP][0]);
 965                         return -EINVAL;
 966                 }
 967         } else {
 968                 switch (adev->ip_versions[UVD_HWIP][0]) {
 969                 case IP_VERSION(1, 0, 0):
 970                 case IP_VERSION(1, 0, 1):
 971                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 972                         break;
 973                 case IP_VERSION(2, 0, 0):
 974                 case IP_VERSION(2, 0, 2):
 975                 case IP_VERSION(2, 2, 0):
 976                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 977                         if (!amdgpu_sriov_vf(adev))
 978                                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 979                         break;
 980                 case IP_VERSION(2, 0, 3):
 981                         break;
 982                 case IP_VERSION(2, 5, 0):
 983                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 984                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
 985                         break;
 986                 case IP_VERSION(2, 6, 0):
 987                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
 988                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
 989                         break;
 990                 case IP_VERSION(3, 0, 0):
 991                 case IP_VERSION(3, 0, 16):
 992                 case IP_VERSION(3, 1, 1):
 993                 case IP_VERSION(3, 0, 2):
 994                 case IP_VERSION(3, 0, 192):
 995                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 996                         if (!amdgpu_sriov_vf(adev))
 997                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 998                         break;
 999                 case IP_VERSION(3, 0, 33):
1000                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1001                         break;
1002                 default:
1003                         dev_err(adev->dev,
1004                                 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
1005                                 adev->ip_versions[UVD_HWIP][0]);
1006                         return -EINVAL;
1007                 }
1008         }
1009         return 0;
1010 }
1011
1012 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
1013 {
1014         switch (adev->ip_versions[GC_HWIP][0]) {
1015         case IP_VERSION(10, 1, 10):
1016         case IP_VERSION(10, 1, 1):
1017         case IP_VERSION(10, 1, 2):
1018         case IP_VERSION(10, 1, 3):
1019         case IP_VERSION(10, 3, 0):
1020         case IP_VERSION(10, 3, 1):
1021         case IP_VERSION(10, 3, 2):
1022         case IP_VERSION(10, 3, 3):
1023         case IP_VERSION(10, 3, 4):
1024         case IP_VERSION(10, 3, 5):
1025                 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
1026                 break;
1027         default:
1028                 break;
1029         }
1030         return 0;
1031 }
1032
1033 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
1034 {
1035         int r;
1036
1037         switch (adev->asic_type) {
1038         case CHIP_VEGA10:
1039                 vega10_reg_base_init(adev);
1040                 adev->sdma.num_instances = 2;
1041                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1042                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1043                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
1044                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
1045                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
1046                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
1047                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1048                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
1049                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
1050                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1051                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1052                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1053                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
1054                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
1055                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1056                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1057                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
1058                 break;
1059         case CHIP_VEGA12:
1060                 vega10_reg_base_init(adev);
1061                 adev->sdma.num_instances = 2;
1062                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1063                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1064                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
1065                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
1066                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
1067                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
1068                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
1069                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
1070                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
1071                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1072                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1073                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1074                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
1075                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
1076                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1077                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1078                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
1079                 break;
1080         case CHIP_RAVEN:
1081                 vega10_reg_base_init(adev);
1082                 adev->sdma.num_instances = 1;
1083                 adev->vcn.num_vcn_inst = 1;
1084                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1085                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1086                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1087                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
1088                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
1089                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
1090                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
1091                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
1092                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
1093                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
1094                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
1095                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
1096                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
1097                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
1098                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
1099                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
1100                 } else {
1101                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1102                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1103                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
1104                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
1105                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
1106                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1107                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
1108                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
1109                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
1110                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
1111                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
1112                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
1113                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
1114                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
1115                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
1116                 }
1117                 break;
1118         case CHIP_VEGA20:
1119                 vega20_reg_base_init(adev);
1120                 adev->sdma.num_instances = 2;
1121                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1122                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1123                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
1124                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
1125                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
1126                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
1127                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
1128                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
1129                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
1130                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
1131                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1132                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
1133                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
1134                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
1135                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
1136                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
1137                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
1138                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
1139                 break;
1140         case CHIP_ARCTURUS:
1141                 arct_reg_base_init(adev);
1142                 adev->sdma.num_instances = 8;
1143                 adev->vcn.num_vcn_inst = 2;
1144                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1145                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1146                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
1147                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
1148                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
1149                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
1150                 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
1151                 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
1152                 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
1153                 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
1154                 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
1155                 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
1156                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
1157                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
1158                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
1159                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
1160                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1161                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
1162                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
1163                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
1164                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
1165                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
1166                 break;
1167         case CHIP_ALDEBARAN:
1168                 aldebaran_reg_base_init(adev);
1169                 adev->sdma.num_instances = 5;
1170                 adev->vcn.num_vcn_inst = 2;
1171                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1172                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1173                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
1174                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
1175                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
1176                 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
1177                 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
1178                 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
1179                 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
1180                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
1181                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
1182                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
1183                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
1184                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
1185                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
1186                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
1187                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
1188                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
1189                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
1190                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
1191                 break;
1192         default:
1193                 r = amdgpu_discovery_reg_base_init(adev);
1194                 if (r)
1195                         return -EINVAL;
1196
1197                 amdgpu_discovery_harvest_ip(adev);
1198
1199                 if (!adev->mman.discovery_bin) {
1200                         DRM_ERROR("ip discovery uninitialized\n");
1201                         return -EINVAL;
1202                 }
1203                 break;
1204         }
1205
1206         switch (adev->ip_versions[GC_HWIP][0]) {
1207         case IP_VERSION(9, 0, 1):
1208         case IP_VERSION(9, 2, 1):
1209         case IP_VERSION(9, 4, 0):
1210         case IP_VERSION(9, 4, 1):
1211         case IP_VERSION(9, 4, 2):
1212                 adev->family = AMDGPU_FAMILY_AI;
1213                 break;
1214         case IP_VERSION(9, 1, 0):
1215         case IP_VERSION(9, 2, 2):
1216         case IP_VERSION(9, 3, 0):
1217                 adev->family = AMDGPU_FAMILY_RV;
1218                 break;
1219         case IP_VERSION(10, 1, 10):
1220         case IP_VERSION(10, 1, 1):
1221         case IP_VERSION(10, 1, 2):
1222         case IP_VERSION(10, 1, 3):
1223         case IP_VERSION(10, 3, 0):
1224         case IP_VERSION(10, 3, 2):
1225         case IP_VERSION(10, 3, 4):
1226         case IP_VERSION(10, 3, 5):
1227                 adev->family = AMDGPU_FAMILY_NV;
1228                 break;
1229         case IP_VERSION(10, 3, 1):
1230                 adev->family = AMDGPU_FAMILY_VGH;
1231                 break;
1232         case IP_VERSION(10, 3, 3):
1233                 adev->family = AMDGPU_FAMILY_YC;
1234                 break;
1235         default:
1236                 return -EINVAL;
1237         }
1238
1239         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
1240                 adev->gmc.xgmi.supported = true;
1241
1242         /* set NBIO version */
1243         switch (adev->ip_versions[NBIO_HWIP][0]) {
1244         case IP_VERSION(6, 1, 0):
1245         case IP_VERSION(6, 2, 0):
1246                 adev->nbio.funcs = &nbio_v6_1_funcs;
1247                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
1248                 break;
1249         case IP_VERSION(7, 0, 0):
1250         case IP_VERSION(7, 0, 1):
1251         case IP_VERSION(2, 5, 0):
1252                 adev->nbio.funcs = &nbio_v7_0_funcs;
1253                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
1254                 break;
1255         case IP_VERSION(7, 4, 0):
1256         case IP_VERSION(7, 4, 1):
1257                 adev->nbio.funcs = &nbio_v7_4_funcs;
1258                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
1259                 break;
1260         case IP_VERSION(7, 4, 4):
1261                 adev->nbio.funcs = &nbio_v7_4_funcs;
1262                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
1263                 break;
1264         case IP_VERSION(7, 2, 0):
1265         case IP_VERSION(7, 2, 1):
1266         case IP_VERSION(7, 5, 0):
1267                 adev->nbio.funcs = &nbio_v7_2_funcs;
1268                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
1269                 break;
1270         case IP_VERSION(2, 1, 1):
1271         case IP_VERSION(2, 3, 0):
1272         case IP_VERSION(2, 3, 1):
1273         case IP_VERSION(2, 3, 2):
1274                 adev->nbio.funcs = &nbio_v2_3_funcs;
1275                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
1276                 break;
1277         case IP_VERSION(3, 3, 0):
1278         case IP_VERSION(3, 3, 1):
1279         case IP_VERSION(3, 3, 2):
1280         case IP_VERSION(3, 3, 3):
1281                 adev->nbio.funcs = &nbio_v2_3_funcs;
1282                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
1283                 break;
1284         default:
1285                 break;
1286         }
1287
1288         switch (adev->ip_versions[HDP_HWIP][0]) {
1289         case IP_VERSION(4, 0, 0):
1290         case IP_VERSION(4, 0, 1):
1291         case IP_VERSION(4, 1, 0):
1292         case IP_VERSION(4, 1, 1):
1293         case IP_VERSION(4, 1, 2):
1294         case IP_VERSION(4, 2, 0):
1295         case IP_VERSION(4, 2, 1):
1296         case IP_VERSION(4, 4, 0):
1297                 adev->hdp.funcs = &hdp_v4_0_funcs;
1298                 break;
1299         case IP_VERSION(5, 0, 0):
1300         case IP_VERSION(5, 0, 1):
1301         case IP_VERSION(5, 0, 2):
1302         case IP_VERSION(5, 0, 3):
1303         case IP_VERSION(5, 0, 4):
1304         case IP_VERSION(5, 2, 0):
1305                 adev->hdp.funcs = &hdp_v5_0_funcs;
1306                 break;
1307         default:
1308                 break;
1309         }
1310
1311         switch (adev->ip_versions[DF_HWIP][0]) {
1312         case IP_VERSION(3, 6, 0):
1313         case IP_VERSION(3, 6, 1):
1314         case IP_VERSION(3, 6, 2):
1315                 adev->df.funcs = &df_v3_6_funcs;
1316                 break;
1317         case IP_VERSION(2, 1, 0):
1318         case IP_VERSION(2, 1, 1):
1319         case IP_VERSION(2, 5, 0):
1320         case IP_VERSION(3, 5, 1):
1321         case IP_VERSION(3, 5, 2):
1322                 adev->df.funcs = &df_v1_7_funcs;
1323                 break;
1324         default:
1325                 break;
1326         }
1327
1328         switch (adev->ip_versions[SMUIO_HWIP][0]) {
1329         case IP_VERSION(9, 0, 0):
1330         case IP_VERSION(9, 0, 1):
1331         case IP_VERSION(10, 0, 0):
1332         case IP_VERSION(10, 0, 1):
1333         case IP_VERSION(10, 0, 2):
1334                 adev->smuio.funcs = &smuio_v9_0_funcs;
1335                 break;
1336         case IP_VERSION(11, 0, 0):
1337         case IP_VERSION(11, 0, 2):
1338         case IP_VERSION(11, 0, 3):
1339         case IP_VERSION(11, 0, 4):
1340         case IP_VERSION(11, 0, 7):
1341         case IP_VERSION(11, 0, 8):
1342                 adev->smuio.funcs = &smuio_v11_0_funcs;
1343                 break;
1344         case IP_VERSION(11, 0, 6):
1345         case IP_VERSION(11, 0, 10):
1346         case IP_VERSION(11, 0, 11):
1347         case IP_VERSION(11, 5, 0):
1348         case IP_VERSION(13, 0, 1):
1349                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
1350                 break;
1351         case IP_VERSION(13, 0, 2):
1352                 adev->smuio.funcs = &smuio_v13_0_funcs;
1353                 break;
1354         default:
1355                 break;
1356         }
1357
1358         r = amdgpu_discovery_set_common_ip_blocks(adev);
1359         if (r)
1360                 return r;
1361
1362         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
1363         if (r)
1364                 return r;
1365
1366         /* For SR-IOV, PSP needs to be initialized before IH */
1367         if (amdgpu_sriov_vf(adev)) {
1368                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
1369                 if (r)
1370                         return r;
1371                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1372                 if (r)
1373                         return r;
1374         } else {
1375                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1376                 if (r)
1377                         return r;
1378
1379                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1380                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
1381                         if (r)
1382                                 return r;
1383                 }
1384         }
1385
1386         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1387                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1388                 if (r)
1389                         return r;
1390         }
1391
1392         r = amdgpu_discovery_set_display_ip_blocks(adev);
1393         if (r)
1394                 return r;
1395
1396         r = amdgpu_discovery_set_gc_ip_blocks(adev);
1397         if (r)
1398                 return r;
1399
1400         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
1401         if (r)
1402                 return r;
1403
1404         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
1405             !amdgpu_sriov_vf(adev)) {
1406                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1407                 if (r)
1408                         return r;
1409         }
1410
1411         r = amdgpu_discovery_set_mm_ip_blocks(adev);
1412         if (r)
1413                 return r;
1414
1415         if (adev->enable_mes) {
1416                 r = amdgpu_discovery_set_mes_ip_blocks(adev);
1417                 if (r)
1418                         return r;
1419         }
1420
1421         return 0;
1422 }
1423