drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30
  31 #include "soc15.h"
  32 #include "gfx_v9_0.h"
  33 #include "gmc_v9_0.h"
  34 #include "df_v1_7.h"
  35 #include "df_v3_6.h"
  36 #include "nbio_v6_1.h"
  37 #include "nbio_v7_0.h"
  38 #include "nbio_v7_4.h"
  39 #include "hdp_v4_0.h"
  40 #include "vega10_ih.h"
  41 #include "vega20_ih.h"
  42 #include "sdma_v4_0.h"
  43 #include "uvd_v7_0.h"
  44 #include "vce_v4_0.h"
  45 #include "vcn_v1_0.h"
  46 #include "vcn_v2_5.h"
  47 #include "jpeg_v2_5.h"
  48 #include "smuio_v9_0.h"
  49 #include "gmc_v10_0.h"
  50 #include "gfxhub_v2_0.h"
  51 #include "mmhub_v2_0.h"
  52 #include "nbio_v2_3.h"
  53 #include "nbio_v7_2.h"
  54 #include "hdp_v5_0.h"
  55 #include "nv.h"
  56 #include "navi10_ih.h"
  57 #include "gfx_v10_0.h"
  58 #include "sdma_v5_0.h"
  59 #include "sdma_v5_2.h"
  60 #include "vcn_v2_0.h"
  61 #include "jpeg_v2_0.h"
  62 #include "vcn_v3_0.h"
  63 #include "jpeg_v3_0.h"
  64 #include "amdgpu_vkms.h"
  65 #include "mes_v10_1.h"
  66 #include "smuio_v11_0.h"
  67 #include "smuio_v11_0_6.h"
  68 #include "smuio_v13_0.h"
  69
  70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
  71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
  72
  73 #define mmRCC_CONFIG_MEMSIZE    0xde3
  74 #define mmMM_INDEX              0x0
  75 #define mmMM_INDEX_HI           0x6
  76 #define mmMM_DATA               0x1
  77
  78 static const char *hw_id_names[HW_ID_MAX] = {
  79         [MP1_HWID]              = "MP1",
  80         [MP2_HWID]              = "MP2",
  81         [THM_HWID]              = "THM",
  82         [SMUIO_HWID]            = "SMUIO",
  83         [FUSE_HWID]             = "FUSE",
  84         [CLKA_HWID]             = "CLKA",
  85         [PWR_HWID]              = "PWR",
  86         [GC_HWID]               = "GC",
  87         [UVD_HWID]              = "UVD",
  88         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
  89         [ACP_HWID]              = "ACP",
  90         [DCI_HWID]              = "DCI",
  91         [DMU_HWID]              = "DMU",
  92         [DCO_HWID]              = "DCO",
  93         [DIO_HWID]              = "DIO",
  94         [XDMA_HWID]             = "XDMA",
  95         [DCEAZ_HWID]            = "DCEAZ",
  96         [DAZ_HWID]              = "DAZ",
  97         [SDPMUX_HWID]           = "SDPMUX",
  98         [NTB_HWID]              = "NTB",
  99         [IOHC_HWID]             = "IOHC",
 100         [L2IMU_HWID]            = "L2IMU",
 101         [VCE_HWID]              = "VCE",
 102         [MMHUB_HWID]            = "MMHUB",
 103         [ATHUB_HWID]            = "ATHUB",
 104         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 105         [DFX_HWID]              = "DFX",
 106         [DBGU0_HWID]            = "DBGU0",
 107         [DBGU1_HWID]            = "DBGU1",
 108         [OSSSYS_HWID]           = "OSSSYS",
 109         [HDP_HWID]              = "HDP",
 110         [SDMA0_HWID]            = "SDMA0",
 111         [SDMA1_HWID]            = "SDMA1",
 112         [SDMA2_HWID]            = "SDMA2",
 113         [SDMA3_HWID]            = "SDMA3",
 114         [ISP_HWID]              = "ISP",
 115         [DBGU_IO_HWID]          = "DBGU_IO",
 116         [DF_HWID]               = "DF",
 117         [CLKB_HWID]             = "CLKB",
 118         [FCH_HWID]              = "FCH",
 119         [DFX_DAP_HWID]          = "DFX_DAP",
 120         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 121         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 122         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 123         [L1IMU3_HWID]           = "L1IMU3",
 124         [L1IMU4_HWID]           = "L1IMU4",
 125         [L1IMU5_HWID]           = "L1IMU5",
 126         [L1IMU6_HWID]           = "L1IMU6",
 127         [L1IMU7_HWID]           = "L1IMU7",
 128         [L1IMU8_HWID]           = "L1IMU8",
 129         [L1IMU9_HWID]           = "L1IMU9",
 130         [L1IMU10_HWID]          = "L1IMU10",
 131         [L1IMU11_HWID]          = "L1IMU11",
 132         [L1IMU12_HWID]          = "L1IMU12",
 133         [L1IMU13_HWID]          = "L1IMU13",
 134         [L1IMU14_HWID]          = "L1IMU14",
 135         [L1IMU15_HWID]          = "L1IMU15",
 136         [WAFLC_HWID]            = "WAFLC",
 137         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 138         [PCIE_HWID]             = "PCIE",
 139         [PCS_HWID]              = "PCS",
 140         [DDCL_HWID]             = "DDCL",
 141         [SST_HWID]              = "SST",
 142         [IOAGR_HWID]            = "IOAGR",
 143         [NBIF_HWID]             = "NBIF",
 144         [IOAPIC_HWID]           = "IOAPIC",
 145         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 146         [NTBCCP_HWID]           = "NTBCCP",
 147         [UMC_HWID]              = "UMC",
 148         [SATA_HWID]             = "SATA",
 149         [USB_HWID]              = "USB",
 150         [CCXSEC_HWID]           = "CCXSEC",
 151         [XGMI_HWID]             = "XGMI",
 152         [XGBE_HWID]             = "XGBE",
 153         [MP0_HWID]              = "MP0",
 154 };
 155
 156 static int hw_id_map[MAX_HWIP] = {
 157         [GC_HWIP]       = GC_HWID,
 158         [HDP_HWIP]      = HDP_HWID,
 159         [SDMA0_HWIP]    = SDMA0_HWID,
 160         [SDMA1_HWIP]    = SDMA1_HWID,
 161         [SDMA2_HWIP]    = SDMA2_HWID,
 162         [SDMA3_HWIP]    = SDMA3_HWID,
 163         [MMHUB_HWIP]    = MMHUB_HWID,
 164         [ATHUB_HWIP]    = ATHUB_HWID,
 165         [NBIO_HWIP]     = NBIF_HWID,
 166         [MP0_HWIP]      = MP0_HWID,
 167         [MP1_HWIP]      = MP1_HWID,
 168         [UVD_HWIP]      = UVD_HWID,
 169         [VCE_HWIP]      = VCE_HWID,
 170         [DF_HWIP]       = DF_HWID,
 171         [DCE_HWIP]      = DMU_HWID,
 172         [OSSSYS_HWIP]   = OSSSYS_HWID,
 173         [SMUIO_HWIP]    = SMUIO_HWID,
 174         [PWR_HWIP]      = PWR_HWID,
 175         [NBIF_HWIP]     = NBIF_HWID,
 176         [THM_HWIP]      = THM_HWID,
 177         [CLK_HWIP]      = CLKA_HWID,
 178         [UMC_HWIP]      = UMC_HWID,
 179         [XGMI_HWIP]     = XGMI_HWID,
 180         [DCI_HWIP]      = DCI_HWID,
 181 };
 182
 183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
 184 {
 185         uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 186         uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 187
 188         amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 189                                   adev->mman.discovery_tmr_size, false);
 190         return 0;
 191 }
 192
 193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
 194 {
 195         const struct firmware *fw;
 196         const char *fw_name;
 197         int r;
 198
 199         switch (amdgpu_discovery) {
 200         case 2:
 201                 fw_name = FIRMWARE_IP_DISCOVERY;
 202                 break;
 203         default:
 204                 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
 205                 return -EINVAL;
 206         }
 207
 208         r = request_firmware(&fw, fw_name, adev->dev);
 209         if (r) {
 210                 dev_err(adev->dev, "can't load firmware \"%s\"\n",
 211                         fw_name);
 212                 return r;
 213         }
 214
 215         memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
 216         release_firmware(fw);
 217
 218         return 0;
 219 }
 220
 221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 222 {
 223         uint16_t checksum = 0;
 224         int i;
 225
 226         for (i = 0; i < size; i++)
 227                 checksum += data[i];
 228
 229         return checksum;
 230 }
 231
 232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 233                                                     uint16_t expected)
 234 {
 235         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 236 }
 237
 238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
 239 {
 240         struct binary_header *bhdr;
 241         bhdr = (struct binary_header *)binary;
 242
 243         return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
 244 }
 245
 246 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
 247 {
 248         /*
 249          * So far, apply this quirk only on those Navy Flounder boards which
 250          * have a bad harvest table of VCN config.
 251          */
 252         if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
 253                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
 254                 switch (adev->pdev->revision) {
 255                 case 0xC1:
 256                 case 0xC2:
 257                 case 0xC3:
 258                 case 0xC5:
 259                 case 0xC7:
 260                 case 0xCF:
 261                 case 0xDF:
 262                         adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 263                         break;
 264                 default:
 265                         break;
 266                 }
 267         }
 268 }
 269
 270 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 271 {
 272         struct table_info *info;
 273         struct binary_header *bhdr;
 274         struct ip_discovery_header *ihdr;
 275         struct gpu_info_header *ghdr;
 276         uint16_t offset;
 277         uint16_t size;
 278         uint16_t checksum;
 279         int r;
 280
 281         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 282         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 283         if (!adev->mman.discovery_bin)
 284                 return -ENOMEM;
 285
 286         r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin);
 287         if (r) {
 288                 dev_err(adev->dev, "failed to read ip discovery binary from vram\n");
 289                 r = -EINVAL;
 290                 goto out;
 291         }
 292
 293         if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 294                 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n");
 295                 /* retry read ip discovery binary from file */
 296                 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
 297                 if (r) {
 298                         dev_err(adev->dev, "failed to read ip discovery binary from file\n");
 299                         r = -EINVAL;
 300                         goto out;
 301                 }
 302                 /* check the ip discovery binary signature */
 303                 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 304                         dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n");
 305                         r = -EINVAL;
 306                         goto out;
 307                 }
 308         }
 309
 310         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 311
 312         offset = offsetof(struct binary_header, binary_checksum) +
 313                 sizeof(bhdr->binary_checksum);
 314         size = le16_to_cpu(bhdr->binary_size) - offset;
 315         checksum = le16_to_cpu(bhdr->binary_checksum);
 316
 317         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 318                                               size, checksum)) {
 319                 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
 320                 r = -EINVAL;
 321                 goto out;
 322         }
 323
 324         info = &bhdr->table_list[IP_DISCOVERY];
 325         offset = le16_to_cpu(info->offset);
 326         checksum = le16_to_cpu(info->checksum);
 327         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 328
 329         if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 330                 dev_err(adev->dev, "invalid ip discovery data table signature\n");
 331                 r = -EINVAL;
 332                 goto out;
 333         }
 334
 335         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 336                                               le16_to_cpu(ihdr->size), checksum)) {
 337                 dev_err(adev->dev, "invalid ip discovery data table checksum\n");
 338                 r = -EINVAL;
 339                 goto out;
 340         }
 341
 342         info = &bhdr->table_list[GC];
 343         offset = le16_to_cpu(info->offset);
 344         checksum = le16_to_cpu(info->checksum);
 345         ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 346
 347         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 348                                               le32_to_cpu(ghdr->size), checksum)) {
 349                 dev_err(adev->dev, "invalid gc data table checksum\n");
 350                 r = -EINVAL;
 351                 goto out;
 352         }
 353
 354         return 0;
 355
 356 out:
 357         kfree(adev->mman.discovery_bin);
 358         adev->mman.discovery_bin = NULL;
 359
 360         return r;
 361 }
 362
 363 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
 364
 365 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 366 {
 367         amdgpu_discovery_sysfs_fini(adev);
 368         kfree(adev->mman.discovery_bin);
 369         adev->mman.discovery_bin = NULL;
 370 }
 371
 372 static int amdgpu_discovery_validate_ip(const struct ip *ip)
 373 {
 374         if (ip->number_instance >= HWIP_MAX_INSTANCE) {
 375                 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
 376                           ip->number_instance);
 377                 return -EINVAL;
 378         }
 379         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 380                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 381                           le16_to_cpu(ip->hw_id));
 382                 return -EINVAL;
 383         }
 384
 385         return 0;
 386 }
 387
 388 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
 389                                                 uint32_t *vcn_harvest_count)
 390 {
 391         struct binary_header *bhdr;
 392         struct ip_discovery_header *ihdr;
 393         struct die_header *dhdr;
 394         struct ip *ip;
 395         uint16_t die_offset, ip_offset, num_dies, num_ips;
 396         int i, j;
 397
 398         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 399         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 400                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 401         num_dies = le16_to_cpu(ihdr->num_dies);
 402
 403         /* scan harvest bit of all IP data structures */
 404         for (i = 0; i < num_dies; i++) {
 405                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 406                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 407                 num_ips = le16_to_cpu(dhdr->num_ips);
 408                 ip_offset = die_offset + sizeof(*dhdr);
 409
 410                 for (j = 0; j < num_ips; j++) {
 411                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 412
 413                         if (amdgpu_discovery_validate_ip(ip))
 414                                 goto next_ip;
 415
 416                         if (le16_to_cpu(ip->harvest) == 1) {
 417                                 switch (le16_to_cpu(ip->hw_id)) {
 418                                 case VCN_HWID:
 419                                         (*vcn_harvest_count)++;
 420                                         if (ip->number_instance == 0)
 421                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 422                                         else
 423                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 424                                         break;
 425                                 case DMU_HWID:
 426                                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 427                                         break;
 428                                 default:
 429                                         break;
 430                                 }
 431                         }
 432 next_ip:
 433                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
 434                 }
 435         }
 436 }
 437
 438 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
 439                                                      uint32_t *vcn_harvest_count)
 440 {
 441         struct binary_header *bhdr;
 442         struct harvest_table *harvest_info;
 443         int i;
 444
 445         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 446         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
 447                         le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
 448         for (i = 0; i < 32; i++) {
 449                 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
 450                         break;
 451
 452                 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
 453                 case VCN_HWID:
 454                         (*vcn_harvest_count)++;
 455                         if (harvest_info->list[i].number_instance == 0)
 456                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 457                         else
 458                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 459                         break;
 460                 case DMU_HWID:
 461                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 462                         break;
 463                 default:
 464                         break;
 465                 }
 466         }
 467 }
 468
 469 /* ================================================== */
 470
 471 struct ip_hw_instance {
 472         struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
 473
 474         int hw_id;
 475         u8  num_instance;
 476         u8  major, minor, revision;
 477         u8  harvest;
 478
 479         int num_base_addresses;
 480         u32 base_addr[];
 481 };
 482
 483 struct ip_hw_id {
 484         struct kset hw_id_kset;  /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
 485         int hw_id;
 486 };
 487
 488 struct ip_die_entry {
 489         struct kset ip_kset;     /* ip_discovery/die/#die/, contains ip_hw_id  */
 490         u16 num_ips;
 491 };
 492
 493 /* -------------------------------------------------- */
 494
 495 struct ip_hw_instance_attr {
 496         struct attribute attr;
 497         ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
 498 };
 499
 500 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 501 {
 502         return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
 503 }
 504
 505 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 506 {
 507         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
 508 }
 509
 510 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 511 {
 512         return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
 513 }
 514
 515 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 516 {
 517         return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
 518 }
 519
 520 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 521 {
 522         return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
 523 }
 524
 525 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 526 {
 527         return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
 528 }
 529
 530 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 531 {
 532         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
 533 }
 534
 535 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 536 {
 537         ssize_t res, at;
 538         int ii;
 539
 540         for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
 541                 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
 542                  */
 543                 if (at + 12 > PAGE_SIZE)
 544                         break;
 545                 res = sysfs_emit_at(buf, at, "0x%08X\n",
 546                                     ip_hw_instance->base_addr[ii]);
 547                 if (res <= 0)
 548                         break;
 549                 at += res;
 550         }
 551
 552         return res < 0 ? res : at;
 553 }
 554
 555 static struct ip_hw_instance_attr ip_hw_attr[] = {
 556         __ATTR_RO(hw_id),
 557         __ATTR_RO(num_instance),
 558         __ATTR_RO(major),
 559         __ATTR_RO(minor),
 560         __ATTR_RO(revision),
 561         __ATTR_RO(harvest),
 562         __ATTR_RO(num_base_addresses),
 563         __ATTR_RO(base_addr),
 564 };
 565
 566 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
 567 ATTRIBUTE_GROUPS(ip_hw_instance);
 568
 569 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
 570 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
 571
 572 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
 573                                         struct attribute *attr,
 574                                         char *buf)
 575 {
 576         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 577         struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
 578
 579         if (!ip_hw_attr->show)
 580                 return -EIO;
 581
 582         return ip_hw_attr->show(ip_hw_instance, buf);
 583 }
 584
 585 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
 586         .show = ip_hw_instance_attr_show,
 587 };
 588
 589 static void ip_hw_instance_release(struct kobject *kobj)
 590 {
 591         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 592
 593         kfree(ip_hw_instance);
 594 }
 595
 596 static struct kobj_type ip_hw_instance_ktype = {
 597         .release = ip_hw_instance_release,
 598         .sysfs_ops = &ip_hw_instance_sysfs_ops,
 599         .default_groups = ip_hw_instance_groups,
 600 };
 601
 602 /* -------------------------------------------------- */
 603
 604 #define to_ip_hw_id(x)  container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
 605
 606 static void ip_hw_id_release(struct kobject *kobj)
 607 {
 608         struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
 609
 610         if (!list_empty(&ip_hw_id->hw_id_kset.list))
 611                 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
 612         kfree(ip_hw_id);
 613 }
 614
 615 static struct kobj_type ip_hw_id_ktype = {
 616         .release = ip_hw_id_release,
 617         .sysfs_ops = &kobj_sysfs_ops,
 618 };
 619
 620 /* -------------------------------------------------- */
 621
 622 static void die_kobj_release(struct kobject *kobj);
 623 static void ip_disc_release(struct kobject *kobj);
 624
 625 struct ip_die_entry_attribute {
 626         struct attribute attr;
 627         ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
 628 };
 629
 630 #define to_ip_die_entry_attr(x)  container_of(x, struct ip_die_entry_attribute, attr)
 631
 632 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
 633 {
 634         return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
 635 }
 636
 637 /* If there are more ip_die_entry attrs, other than the number of IPs,
 638  * we can make this intro an array of attrs, and then initialize
 639  * ip_die_entry_attrs in a loop.
 640  */
 641 static struct ip_die_entry_attribute num_ips_attr =
 642         __ATTR_RO(num_ips);
 643
 644 static struct attribute *ip_die_entry_attrs[] = {
 645         &num_ips_attr.attr,
 646         NULL,
 647 };
 648 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
 649
 650 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
 651
 652 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
 653                                       struct attribute *attr,
 654                                       char *buf)
 655 {
 656         struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
 657         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 658
 659         if (!ip_die_entry_attr->show)
 660                 return -EIO;
 661
 662         return ip_die_entry_attr->show(ip_die_entry, buf);
 663 }
 664
 665 static void ip_die_entry_release(struct kobject *kobj)
 666 {
 667         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 668
 669         if (!list_empty(&ip_die_entry->ip_kset.list))
 670                 DRM_ERROR("ip_die_entry->ip_kset is not empty");
 671         kfree(ip_die_entry);
 672 }
 673
 674 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
 675         .show = ip_die_entry_attr_show,
 676 };
 677
 678 static struct kobj_type ip_die_entry_ktype = {
 679         .release = ip_die_entry_release,
 680         .sysfs_ops = &ip_die_entry_sysfs_ops,
 681         .default_groups = ip_die_entry_groups,
 682 };
 683
 684 static struct kobj_type die_kobj_ktype = {
 685         .release = die_kobj_release,
 686         .sysfs_ops = &kobj_sysfs_ops,
 687 };
 688
 689 static struct kobj_type ip_discovery_ktype = {
 690         .release = ip_disc_release,
 691         .sysfs_ops = &kobj_sysfs_ops,
 692 };
 693
 694 struct ip_discovery_top {
 695         struct kobject kobj;    /* ip_discovery/ */
 696         struct kset die_kset;   /* ip_discovery/die/, contains ip_die_entry */
 697         struct amdgpu_device *adev;
 698 };
 699
 700 static void die_kobj_release(struct kobject *kobj)
 701 {
 702         struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
 703                                                        struct ip_discovery_top,
 704                                                        die_kset);
 705         if (!list_empty(&ip_top->die_kset.list))
 706                 DRM_ERROR("ip_top->die_kset is not empty");
 707 }
 708
 709 static void ip_disc_release(struct kobject *kobj)
 710 {
 711         struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
 712                                                        kobj);
 713         struct amdgpu_device *adev = ip_top->adev;
 714
 715         adev->ip_top = NULL;
 716         kfree(ip_top);
 717 }
 718
 719 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
 720                                       struct ip_die_entry *ip_die_entry,
 721                                       const size_t _ip_offset, const int num_ips)
 722 {
 723         int ii, jj, kk, res;
 724
 725         DRM_DEBUG("num_ips:%d", num_ips);
 726
 727         /* Find all IPs of a given HW ID, and add their instance to
 728          * #die/#hw_id/#instance/<attributes>
 729          */
 730         for (ii = 0; ii < HW_ID_MAX; ii++) {
 731                 struct ip_hw_id *ip_hw_id = NULL;
 732                 size_t ip_offset = _ip_offset;
 733
 734                 for (jj = 0; jj < num_ips; jj++) {
 735                         struct ip *ip;
 736                         struct ip_hw_instance *ip_hw_instance;
 737
 738                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 739                         if (amdgpu_discovery_validate_ip(ip) ||
 740                             le16_to_cpu(ip->hw_id) != ii)
 741                                 goto next_ip;
 742
 743                         DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
 744
 745                         /* We have a hw_id match; register the hw
 746                          * block if not yet registered.
 747                          */
 748                         if (!ip_hw_id) {
 749                                 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
 750                                 if (!ip_hw_id)
 751                                         return -ENOMEM;
 752                                 ip_hw_id->hw_id = ii;
 753
 754                                 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
 755                                 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
 756                                 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
 757                                 res = kset_register(&ip_hw_id->hw_id_kset);
 758                                 if (res) {
 759                                         DRM_ERROR("Couldn't register ip_hw_id kset");
 760                                         kfree(ip_hw_id);
 761                                         return res;
 762                                 }
 763                                 if (hw_id_names[ii]) {
 764                                         res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
 765                                                                 &ip_hw_id->hw_id_kset.kobj,
 766                                                                 hw_id_names[ii]);
 767                                         if (res) {
 768                                                 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
 769                                                           hw_id_names[ii],
 770                                                           kobject_name(&ip_die_entry->ip_kset.kobj));
 771                                         }
 772                                 }
 773                         }
 774
 775                         /* Now register its instance.
 776                          */
 777                         ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
 778                                                              base_addr,
 779                                                              ip->num_base_address),
 780                                                  GFP_KERNEL);
 781                         if (!ip_hw_instance) {
 782                                 DRM_ERROR("no memory for ip_hw_instance");
 783                                 return -ENOMEM;
 784                         }
 785                         ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
 786                         ip_hw_instance->num_instance = ip->number_instance;
 787                         ip_hw_instance->major = ip->major;
 788                         ip_hw_instance->minor = ip->minor;
 789                         ip_hw_instance->revision = ip->revision;
 790                         ip_hw_instance->harvest = ip->harvest;
 791                         ip_hw_instance->num_base_addresses = ip->num_base_address;
 792
 793                         for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++)
 794                                 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
 795
 796                         kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
 797                         ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
 798                         res = kobject_add(&ip_hw_instance->kobj, NULL,
 799                                           "%d", ip_hw_instance->num_instance);
 800 next_ip:
 801                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
 802                 }
 803         }
 804
 805         return 0;
 806 }
 807
 808 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
 809 {
 810         struct binary_header *bhdr;
 811         struct ip_discovery_header *ihdr;
 812         struct die_header *dhdr;
 813         struct kset *die_kset = &adev->ip_top->die_kset;
 814         u16 num_dies, die_offset, num_ips;
 815         size_t ip_offset;
 816         int ii, res;
 817
 818         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 819         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 820                                               le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 821         num_dies = le16_to_cpu(ihdr->num_dies);
 822
 823         DRM_DEBUG("number of dies: %d\n", num_dies);
 824
 825         for (ii = 0; ii < num_dies; ii++) {
 826                 struct ip_die_entry *ip_die_entry;
 827
 828                 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
 829                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 830                 num_ips = le16_to_cpu(dhdr->num_ips);
 831                 ip_offset = die_offset + sizeof(*dhdr);
 832
 833                 /* Add the die to the kset.
 834                  *
 835                  * dhdr->die_id == ii, which was checked in
 836                  * amdgpu_discovery_reg_base_init().
 837                  */
 838
 839                 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
 840                 if (!ip_die_entry)
 841                         return -ENOMEM;
 842
 843                 ip_die_entry->num_ips = num_ips;
 844
 845                 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
 846                 ip_die_entry->ip_kset.kobj.kset = die_kset;
 847                 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
 848                 res = kset_register(&ip_die_entry->ip_kset);
 849                 if (res) {
 850                         DRM_ERROR("Couldn't register ip_die_entry kset");
 851                         kfree(ip_die_entry);
 852                         return res;
 853                 }
 854
 855                 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips);
 856         }
 857
 858         return 0;
 859 }
 860
 861 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
 862 {
 863         struct kset *die_kset;
 864         int res, ii;
 865
 866         adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
 867         if (!adev->ip_top)
 868                 return -ENOMEM;
 869
 870         adev->ip_top->adev = adev;
 871
 872         res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
 873                                    &adev->dev->kobj, "ip_discovery");
 874         if (res) {
 875                 DRM_ERROR("Couldn't init and add ip_discovery/");
 876                 goto Err;
 877         }
 878
 879         die_kset = &adev->ip_top->die_kset;
 880         kobject_set_name(&die_kset->kobj, "%s", "die");
 881         die_kset->kobj.parent = &adev->ip_top->kobj;
 882         die_kset->kobj.ktype = &die_kobj_ktype;
 883         res = kset_register(&adev->ip_top->die_kset);
 884         if (res) {
 885                 DRM_ERROR("Couldn't register die_kset");
 886                 goto Err;
 887         }
 888
 889         for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
 890                 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
 891         ip_hw_instance_attrs[ii] = NULL;
 892
 893         res = amdgpu_discovery_sysfs_recurse(adev);
 894
 895         return res;
 896 Err:
 897         kobject_put(&adev->ip_top->kobj);
 898         return res;
 899 }
 900
 901 /* -------------------------------------------------- */
 902
 903 #define list_to_kobj(el) container_of(el, struct kobject, entry)
 904
 905 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
 906 {
 907         struct list_head *el, *tmp;
 908         struct kset *hw_id_kset;
 909
 910         hw_id_kset = &ip_hw_id->hw_id_kset;
 911         spin_lock(&hw_id_kset->list_lock);
 912         list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
 913                 list_del_init(el);
 914                 spin_unlock(&hw_id_kset->list_lock);
 915                 /* kobject is embedded in ip_hw_instance */
 916                 kobject_put(list_to_kobj(el));
 917                 spin_lock(&hw_id_kset->list_lock);
 918         }
 919         spin_unlock(&hw_id_kset->list_lock);
 920         kobject_put(&ip_hw_id->hw_id_kset.kobj);
 921 }
 922
 923 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
 924 {
 925         struct list_head *el, *tmp;
 926         struct kset *ip_kset;
 927
 928         ip_kset = &ip_die_entry->ip_kset;
 929         spin_lock(&ip_kset->list_lock);
 930         list_for_each_prev_safe(el, tmp, &ip_kset->list) {
 931                 list_del_init(el);
 932                 spin_unlock(&ip_kset->list_lock);
 933                 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
 934                 spin_lock(&ip_kset->list_lock);
 935         }
 936         spin_unlock(&ip_kset->list_lock);
 937         kobject_put(&ip_die_entry->ip_kset.kobj);
 938 }
 939
 940 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
 941 {
 942         struct list_head *el, *tmp;
 943         struct kset *die_kset;
 944
 945         die_kset = &adev->ip_top->die_kset;
 946         spin_lock(&die_kset->list_lock);
 947         list_for_each_prev_safe(el, tmp, &die_kset->list) {
 948                 list_del_init(el);
 949                 spin_unlock(&die_kset->list_lock);
 950                 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
 951                 spin_lock(&die_kset->list_lock);
 952         }
 953         spin_unlock(&die_kset->list_lock);
 954         kobject_put(&adev->ip_top->die_kset.kobj);
 955         kobject_put(&adev->ip_top->kobj);
 956 }
 957
 958 /* ================================================== */
 959
 960 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 961 {
 962         struct binary_header *bhdr;
 963         struct ip_discovery_header *ihdr;
 964         struct die_header *dhdr;
 965         struct ip *ip;
 966         uint16_t die_offset;
 967         uint16_t ip_offset;
 968         uint16_t num_dies;
 969         uint16_t num_ips;
 970         uint8_t num_base_address;
 971         int hw_ip;
 972         int i, j, k;
 973         int r;
 974
 975         r = amdgpu_discovery_init(adev);
 976         if (r) {
 977                 DRM_ERROR("amdgpu_discovery_init failed\n");
 978                 return r;
 979         }
 980
 981         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 982         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 983                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 984         num_dies = le16_to_cpu(ihdr->num_dies);
 985
 986         DRM_DEBUG("number of dies: %d\n", num_dies);
 987
 988         for (i = 0; i < num_dies; i++) {
 989                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 990                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 991                 num_ips = le16_to_cpu(dhdr->num_ips);
 992                 ip_offset = die_offset + sizeof(*dhdr);
 993
 994                 if (le16_to_cpu(dhdr->die_id) != i) {
 995                         DRM_ERROR("invalid die id %d, expected %d\n",
 996                                         le16_to_cpu(dhdr->die_id), i);
 997                         return -EINVAL;
 998                 }
 999
1000                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1001                                 le16_to_cpu(dhdr->die_id), num_ips);
1002
1003                 for (j = 0; j < num_ips; j++) {
1004                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1005
1006                         if (amdgpu_discovery_validate_ip(ip))
1007                                 goto next_ip;
1008
1009                         num_base_address = ip->num_base_address;
1010
1011                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1012                                   hw_id_names[le16_to_cpu(ip->hw_id)],
1013                                   le16_to_cpu(ip->hw_id),
1014                                   ip->number_instance,
1015                                   ip->major, ip->minor,
1016                                   ip->revision);
1017
1018                         if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1019                                 /* Bit [5:0]: original revision value
1020                                  * Bit [7:6]: en/decode capability:
1021                                  *     0b00 : VCN function normally
1022                                  *     0b10 : encode is disabled
1023                                  *     0b01 : decode is disabled
1024                                  */
1025                                 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
1026                                         ip->revision & 0xc0;
1027                                 ip->revision &= ~0xc0;
1028                                 adev->vcn.num_vcn_inst++;
1029                         }
1030                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1031                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1032                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1033                             le16_to_cpu(ip->hw_id) == SDMA3_HWID)
1034                                 adev->sdma.num_instances++;
1035
1036                         for (k = 0; k < num_base_address; k++) {
1037                                 /*
1038                                  * convert the endianness of base addresses in place,
1039                                  * so that we don't need to convert them when accessing adev->reg_offset.
1040                                  */
1041                                 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1042                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1043                         }
1044
1045                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1046                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
1047                                         DRM_DEBUG("set register base offset for %s\n",
1048                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
1049                                         adev->reg_offset[hw_ip][ip->number_instance] =
1050                                                 ip->base_address;
1051                                         /* Instance support is somewhat inconsistent.
1052                                          * SDMA is a good example.  Sienna cichlid has 4 total
1053                                          * SDMA instances, each enumerated separately (HWIDs
1054                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
1055                                          * but they are enumerated as multiple instances of the
1056                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
1057                                          * example.  On most chips there are multiple instances
1058                                          * with the same HWID.
1059                                          */
1060                                         adev->ip_versions[hw_ip][ip->number_instance] =
1061                                                 IP_VERSION(ip->major, ip->minor, ip->revision);
1062                                 }
1063                         }
1064
1065 next_ip:
1066                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
1067                 }
1068         }
1069
1070         amdgpu_discovery_sysfs_init(adev);
1071
1072         return 0;
1073 }
1074
1075 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
1076                                     int *major, int *minor, int *revision)
1077 {
1078         struct binary_header *bhdr;
1079         struct ip_discovery_header *ihdr;
1080         struct die_header *dhdr;
1081         struct ip *ip;
1082         uint16_t die_offset;
1083         uint16_t ip_offset;
1084         uint16_t num_dies;
1085         uint16_t num_ips;
1086         int i, j;
1087
1088         if (!adev->mman.discovery_bin) {
1089                 DRM_ERROR("ip discovery uninitialized\n");
1090                 return -EINVAL;
1091         }
1092
1093         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1094         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1095                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1096         num_dies = le16_to_cpu(ihdr->num_dies);
1097
1098         for (i = 0; i < num_dies; i++) {
1099                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1100                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1101                 num_ips = le16_to_cpu(dhdr->num_ips);
1102                 ip_offset = die_offset + sizeof(*dhdr);
1103
1104                 for (j = 0; j < num_ips; j++) {
1105                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1106
1107                         if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
1108                                 if (major)
1109                                         *major = ip->major;
1110                                 if (minor)
1111                                         *minor = ip->minor;
1112                                 if (revision)
1113                                         *revision = ip->revision;
1114                                 return 0;
1115                         }
1116                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
1117                 }
1118         }
1119
1120         return -EINVAL;
1121 }
1122
1123 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1124 {
1125         int vcn_harvest_count = 0;
1126
1127         /*
1128          * Harvest table does not fit Navi1x and legacy GPUs,
1129          * so read harvest bit per IP data structure to set
1130          * harvest configuration.
1131          */
1132         if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
1133                 if ((adev->pdev->device == 0x731E &&
1134                         (adev->pdev->revision == 0xC6 ||
1135                          adev->pdev->revision == 0xC7)) ||
1136                         (adev->pdev->device == 0x7340 &&
1137                          adev->pdev->revision == 0xC9) ||
1138                         (adev->pdev->device == 0x7360 &&
1139                          adev->pdev->revision == 0xC7))
1140                         amdgpu_discovery_read_harvest_bit_per_ip(adev,
1141                                 &vcn_harvest_count);
1142         } else {
1143                 amdgpu_discovery_read_from_harvest_table(adev,
1144                         &vcn_harvest_count);
1145         }
1146
1147         amdgpu_discovery_harvest_config_quirk(adev);
1148
1149         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1150                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1151                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1152         }
1153 }
1154
1155 union gc_info {
1156         struct gc_info_v1_0 v1;
1157         struct gc_info_v1_1 v1_1;
1158         struct gc_info_v1_2 v1_2;
1159         struct gc_info_v2_0 v2;
1160 };
1161
1162 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1163 {
1164         struct binary_header *bhdr;
1165         union gc_info *gc_info;
1166
1167         if (!adev->mman.discovery_bin) {
1168                 DRM_ERROR("ip discovery uninitialized\n");
1169                 return -EINVAL;
1170         }
1171
1172         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1173         gc_info = (union gc_info *)(adev->mman.discovery_bin +
1174                         le16_to_cpu(bhdr->table_list[GC].offset));
1175         switch (le16_to_cpu(gc_info->v1.header.version_major)) {
1176         case 1:
1177                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1178                 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1179                                                       le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1180                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1181                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1182                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1183                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1184                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1185                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1186                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1187                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1188                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1189                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1190                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1191                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1192                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1193                         le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1194                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1195                 if (gc_info->v1.header.version_minor >= 1) {
1196                         adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
1197                         adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
1198                         adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
1199                 }
1200                 if (gc_info->v1.header.version_minor >= 2) {
1201                         adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
1202                         adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
1203                         adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
1204                         adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
1205                         adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
1206                         adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1207                         adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1208                         adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1209                 }
1210                 break;
1211         case 2:
1212                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1213                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1214                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1215                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1216                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1217                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1218                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1219                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1220                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1221                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1222                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1223                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1224                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1225                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1226                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1227                         le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1228                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1229                 break;
1230         default:
1231                 dev_err(adev->dev,
1232                         "Unhandled GC info table %d.%d\n",
1233                         le16_to_cpu(gc_info->v1.header.version_major),
1234                         le16_to_cpu(gc_info->v1.header.version_minor));
1235                 return -EINVAL;
1236         }
1237         return 0;
1238 }
1239
1240 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1241 {
1242         /* what IP to use for this? */
1243         switch (adev->ip_versions[GC_HWIP][0]) {
1244         case IP_VERSION(9, 0, 1):
1245         case IP_VERSION(9, 1, 0):
1246         case IP_VERSION(9, 2, 1):
1247         case IP_VERSION(9, 2, 2):
1248         case IP_VERSION(9, 3, 0):
1249         case IP_VERSION(9, 4, 0):
1250         case IP_VERSION(9, 4, 1):
1251         case IP_VERSION(9, 4, 2):
1252                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1253                 break;
1254         case IP_VERSION(10, 1, 10):
1255         case IP_VERSION(10, 1, 1):
1256         case IP_VERSION(10, 1, 2):
1257         case IP_VERSION(10, 1, 3):
1258         case IP_VERSION(10, 1, 4):
1259         case IP_VERSION(10, 3, 0):
1260         case IP_VERSION(10, 3, 1):
1261         case IP_VERSION(10, 3, 2):
1262         case IP_VERSION(10, 3, 3):
1263         case IP_VERSION(10, 3, 4):
1264         case IP_VERSION(10, 3, 5):
1265         case IP_VERSION(10, 3, 6):
1266         case IP_VERSION(10, 3, 7):
1267                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1268                 break;
1269         default:
1270                 dev_err(adev->dev,
1271                         "Failed to add common ip block(GC_HWIP:0x%x)\n",
1272                         adev->ip_versions[GC_HWIP][0]);
1273                 return -EINVAL;
1274         }
1275         return 0;
1276 }
1277
1278 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1279 {
1280         /* use GC or MMHUB IP version */
1281         switch (adev->ip_versions[GC_HWIP][0]) {
1282         case IP_VERSION(9, 0, 1):
1283         case IP_VERSION(9, 1, 0):
1284         case IP_VERSION(9, 2, 1):
1285         case IP_VERSION(9, 2, 2):
1286         case IP_VERSION(9, 3, 0):
1287         case IP_VERSION(9, 4, 0):
1288         case IP_VERSION(9, 4, 1):
1289         case IP_VERSION(9, 4, 2):
1290                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1291                 break;
1292         case IP_VERSION(10, 1, 10):
1293         case IP_VERSION(10, 1, 1):
1294         case IP_VERSION(10, 1, 2):
1295         case IP_VERSION(10, 1, 3):
1296         case IP_VERSION(10, 1, 4):
1297         case IP_VERSION(10, 3, 0):
1298         case IP_VERSION(10, 3, 1):
1299         case IP_VERSION(10, 3, 2):
1300         case IP_VERSION(10, 3, 3):
1301         case IP_VERSION(10, 3, 4):
1302         case IP_VERSION(10, 3, 5):
1303         case IP_VERSION(10, 3, 6):
1304         case IP_VERSION(10, 3, 7):
1305                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1306                 break;
1307         default:
1308                 dev_err(adev->dev,
1309                         "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1310                         adev->ip_versions[GC_HWIP][0]);
1311                 return -EINVAL;
1312         }
1313         return 0;
1314 }
1315
1316 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1317 {
1318         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
1319         case IP_VERSION(4, 0, 0):
1320         case IP_VERSION(4, 0, 1):
1321         case IP_VERSION(4, 1, 0):
1322         case IP_VERSION(4, 1, 1):
1323         case IP_VERSION(4, 3, 0):
1324                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1325                 break;
1326         case IP_VERSION(4, 2, 0):
1327         case IP_VERSION(4, 2, 1):
1328         case IP_VERSION(4, 4, 0):
1329                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1330                 break;
1331         case IP_VERSION(5, 0, 0):
1332         case IP_VERSION(5, 0, 1):
1333         case IP_VERSION(5, 0, 2):
1334         case IP_VERSION(5, 0, 3):
1335         case IP_VERSION(5, 2, 0):
1336         case IP_VERSION(5, 2, 1):
1337                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1338                 break;
1339         default:
1340                 dev_err(adev->dev,
1341                         "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1342                         adev->ip_versions[OSSSYS_HWIP][0]);
1343                 return -EINVAL;
1344         }
1345         return 0;
1346 }
1347
1348 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1349 {
1350         switch (adev->ip_versions[MP0_HWIP][0]) {
1351         case IP_VERSION(9, 0, 0):
1352                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1353                 break;
1354         case IP_VERSION(10, 0, 0):
1355         case IP_VERSION(10, 0, 1):
1356                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1357                 break;
1358         case IP_VERSION(11, 0, 0):
1359         case IP_VERSION(11, 0, 2):
1360         case IP_VERSION(11, 0, 4):
1361         case IP_VERSION(11, 0, 5):
1362         case IP_VERSION(11, 0, 9):
1363         case IP_VERSION(11, 0, 7):
1364         case IP_VERSION(11, 0, 11):
1365         case IP_VERSION(11, 0, 12):
1366         case IP_VERSION(11, 0, 13):
1367         case IP_VERSION(11, 5, 0):
1368                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1369                 break;
1370         case IP_VERSION(11, 0, 8):
1371                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1372                 break;
1373         case IP_VERSION(11, 0, 3):
1374         case IP_VERSION(12, 0, 1):
1375                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1376                 break;
1377         case IP_VERSION(13, 0, 1):
1378         case IP_VERSION(13, 0, 2):
1379         case IP_VERSION(13, 0, 3):
1380         case IP_VERSION(13, 0, 5):
1381         case IP_VERSION(13, 0, 8):
1382                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1383                 break;
1384         default:
1385                 dev_err(adev->dev,
1386                         "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1387                         adev->ip_versions[MP0_HWIP][0]);
1388                 return -EINVAL;
1389         }
1390         return 0;
1391 }
1392
1393 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1394 {
1395         switch (adev->ip_versions[MP1_HWIP][0]) {
1396         case IP_VERSION(9, 0, 0):
1397         case IP_VERSION(10, 0, 0):
1398         case IP_VERSION(10, 0, 1):
1399         case IP_VERSION(11, 0, 2):
1400                 if (adev->asic_type == CHIP_ARCTURUS)
1401                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1402                 else
1403                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1404                 break;
1405         case IP_VERSION(11, 0, 0):
1406         case IP_VERSION(11, 0, 5):
1407         case IP_VERSION(11, 0, 9):
1408         case IP_VERSION(11, 0, 7):
1409         case IP_VERSION(11, 0, 8):
1410         case IP_VERSION(11, 0, 11):
1411         case IP_VERSION(11, 0, 12):
1412         case IP_VERSION(11, 0, 13):
1413         case IP_VERSION(11, 5, 0):
1414                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1415                 break;
1416         case IP_VERSION(12, 0, 0):
1417         case IP_VERSION(12, 0, 1):
1418                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1419                 break;
1420         case IP_VERSION(13, 0, 1):
1421         case IP_VERSION(13, 0, 2):
1422         case IP_VERSION(13, 0, 3):
1423         case IP_VERSION(13, 0, 5):
1424         case IP_VERSION(13, 0, 8):
1425                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1426                 break;
1427         default:
1428                 dev_err(adev->dev,
1429                         "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
1430                         adev->ip_versions[MP1_HWIP][0]);
1431                 return -EINVAL;
1432         }
1433         return 0;
1434 }
1435
1436 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
1437 {
1438         if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
1439                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1440                 return 0;
1441         }
1442
1443         if (!amdgpu_device_has_dc_support(adev))
1444                 return 0;
1445
1446 #if defined(CONFIG_DRM_AMD_DC)
1447         if (adev->ip_versions[DCE_HWIP][0]) {
1448                 switch (adev->ip_versions[DCE_HWIP][0]) {
1449                 case IP_VERSION(1, 0, 0):
1450                 case IP_VERSION(1, 0, 1):
1451                 case IP_VERSION(2, 0, 2):
1452                 case IP_VERSION(2, 0, 0):
1453                 case IP_VERSION(2, 0, 3):
1454                 case IP_VERSION(2, 1, 0):
1455                 case IP_VERSION(3, 0, 0):
1456                 case IP_VERSION(3, 0, 2):
1457                 case IP_VERSION(3, 0, 3):
1458                 case IP_VERSION(3, 0, 1):
1459                 case IP_VERSION(3, 1, 2):
1460                 case IP_VERSION(3, 1, 3):
1461                 case IP_VERSION(3, 1, 5):
1462                 case IP_VERSION(3, 1, 6):
1463                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1464                         break;
1465                 default:
1466                         dev_err(adev->dev,
1467                                 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
1468                                 adev->ip_versions[DCE_HWIP][0]);
1469                         return -EINVAL;
1470                 }
1471         } else if (adev->ip_versions[DCI_HWIP][0]) {
1472                 switch (adev->ip_versions[DCI_HWIP][0]) {
1473                 case IP_VERSION(12, 0, 0):
1474                 case IP_VERSION(12, 0, 1):
1475                 case IP_VERSION(12, 1, 0):
1476                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1477                         break;
1478                 default:
1479                         dev_err(adev->dev,
1480                                 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
1481                                 adev->ip_versions[DCI_HWIP][0]);
1482                         return -EINVAL;
1483                 }
1484         }
1485 #endif
1486         return 0;
1487 }
1488
1489 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
1490 {
1491         switch (adev->ip_versions[GC_HWIP][0]) {
1492         case IP_VERSION(9, 0, 1):
1493         case IP_VERSION(9, 1, 0):
1494         case IP_VERSION(9, 2, 1):
1495         case IP_VERSION(9, 2, 2):
1496         case IP_VERSION(9, 3, 0):
1497         case IP_VERSION(9, 4, 0):
1498         case IP_VERSION(9, 4, 1):
1499         case IP_VERSION(9, 4, 2):
1500                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1501                 break;
1502         case IP_VERSION(10, 1, 10):
1503         case IP_VERSION(10, 1, 2):
1504         case IP_VERSION(10, 1, 1):
1505         case IP_VERSION(10, 1, 3):
1506         case IP_VERSION(10, 1, 4):
1507         case IP_VERSION(10, 3, 0):
1508         case IP_VERSION(10, 3, 2):
1509         case IP_VERSION(10, 3, 1):
1510         case IP_VERSION(10, 3, 4):
1511         case IP_VERSION(10, 3, 5):
1512         case IP_VERSION(10, 3, 6):
1513         case IP_VERSION(10, 3, 3):
1514         case IP_VERSION(10, 3, 7):
1515                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1516                 break;
1517         default:
1518                 dev_err(adev->dev,
1519                         "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
1520                         adev->ip_versions[GC_HWIP][0]);
1521                 return -EINVAL;
1522         }
1523         return 0;
1524 }
1525
1526 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
1527 {
1528         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1529         case IP_VERSION(4, 0, 0):
1530         case IP_VERSION(4, 0, 1):
1531         case IP_VERSION(4, 1, 0):
1532         case IP_VERSION(4, 1, 1):
1533         case IP_VERSION(4, 1, 2):
1534         case IP_VERSION(4, 2, 0):
1535         case IP_VERSION(4, 2, 2):
1536         case IP_VERSION(4, 4, 0):
1537                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1538                 break;
1539         case IP_VERSION(5, 0, 0):
1540         case IP_VERSION(5, 0, 1):
1541         case IP_VERSION(5, 0, 2):
1542         case IP_VERSION(5, 0, 5):
1543                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
1544                 break;
1545         case IP_VERSION(5, 2, 0):
1546         case IP_VERSION(5, 2, 2):
1547         case IP_VERSION(5, 2, 4):
1548         case IP_VERSION(5, 2, 5):
1549         case IP_VERSION(5, 2, 6):
1550         case IP_VERSION(5, 2, 3):
1551         case IP_VERSION(5, 2, 1):
1552         case IP_VERSION(5, 2, 7):
1553                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1554                 break;
1555         default:
1556                 dev_err(adev->dev,
1557                         "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
1558                         adev->ip_versions[SDMA0_HWIP][0]);
1559                 return -EINVAL;
1560         }
1561         return 0;
1562 }
1563
1564 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
1565 {
1566         if (adev->ip_versions[VCE_HWIP][0]) {
1567                 switch (adev->ip_versions[UVD_HWIP][0]) {
1568                 case IP_VERSION(7, 0, 0):
1569                 case IP_VERSION(7, 2, 0):
1570                         /* UVD is not supported on vega20 SR-IOV */
1571                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1572                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
1573                         break;
1574                 default:
1575                         dev_err(adev->dev,
1576                                 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
1577                                 adev->ip_versions[UVD_HWIP][0]);
1578                         return -EINVAL;
1579                 }
1580                 switch (adev->ip_versions[VCE_HWIP][0]) {
1581                 case IP_VERSION(4, 0, 0):
1582                 case IP_VERSION(4, 1, 0):
1583                         /* VCE is not supported on vega20 SR-IOV */
1584                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1585                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
1586                         break;
1587                 default:
1588                         dev_err(adev->dev,
1589                                 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
1590                                 adev->ip_versions[VCE_HWIP][0]);
1591                         return -EINVAL;
1592                 }
1593         } else {
1594                 switch (adev->ip_versions[UVD_HWIP][0]) {
1595                 case IP_VERSION(1, 0, 0):
1596                 case IP_VERSION(1, 0, 1):
1597                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1598                         break;
1599                 case IP_VERSION(2, 0, 0):
1600                 case IP_VERSION(2, 0, 2):
1601                 case IP_VERSION(2, 2, 0):
1602                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
1603                         if (!amdgpu_sriov_vf(adev))
1604                                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1605                         break;
1606                 case IP_VERSION(2, 0, 3):
1607                         break;
1608                 case IP_VERSION(2, 5, 0):
1609                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1610                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1611                         break;
1612                 case IP_VERSION(2, 6, 0):
1613                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1614                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1615                         break;
1616                 case IP_VERSION(3, 0, 0):
1617                 case IP_VERSION(3, 0, 16):
1618                 case IP_VERSION(3, 1, 1):
1619                 case IP_VERSION(3, 1, 2):
1620                 case IP_VERSION(3, 0, 2):
1621                 case IP_VERSION(3, 0, 192):
1622                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1623                         if (!amdgpu_sriov_vf(adev))
1624                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
1625                         break;
1626                 case IP_VERSION(3, 0, 33):
1627                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1628                         break;
1629                 default:
1630                         dev_err(adev->dev,
1631                                 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
1632                                 adev->ip_versions[UVD_HWIP][0]);
1633                         return -EINVAL;
1634                 }
1635         }
1636         return 0;
1637 }
1638
1639 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
1640 {
1641         switch (adev->ip_versions[GC_HWIP][0]) {
1642         case IP_VERSION(10, 1, 10):
1643         case IP_VERSION(10, 1, 1):
1644         case IP_VERSION(10, 1, 2):
1645         case IP_VERSION(10, 1, 3):
1646         case IP_VERSION(10, 1, 4):
1647         case IP_VERSION(10, 3, 0):
1648         case IP_VERSION(10, 3, 1):
1649         case IP_VERSION(10, 3, 2):
1650         case IP_VERSION(10, 3, 3):
1651         case IP_VERSION(10, 3, 4):
1652         case IP_VERSION(10, 3, 5):
1653         case IP_VERSION(10, 3, 6):
1654                 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
1655                 break;
1656         default:
1657                 break;
1658         }
1659         return 0;
1660 }
1661
1662 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
1663 {
1664         int r;
1665
1666         switch (adev->asic_type) {
1667         case CHIP_VEGA10:
1668                 vega10_reg_base_init(adev);
1669                 adev->sdma.num_instances = 2;
1670                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1671                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1672                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
1673                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
1674                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
1675                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
1676                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1677                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
1678                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
1679                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1680                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1681                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1682                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
1683                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
1684                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1685                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1686                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
1687                 break;
1688         case CHIP_VEGA12:
1689                 vega10_reg_base_init(adev);
1690                 adev->sdma.num_instances = 2;
1691                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1692                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1693                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
1694                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
1695                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
1696                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
1697                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
1698                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
1699                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
1700                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1701                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1702                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1703                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
1704                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
1705                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1706                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1707                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
1708                 break;
1709         case CHIP_RAVEN:
1710                 vega10_reg_base_init(adev);
1711                 adev->sdma.num_instances = 1;
1712                 adev->vcn.num_vcn_inst = 1;
1713                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1714                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1715                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1716                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
1717                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
1718                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
1719                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
1720                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
1721                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
1722                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
1723                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
1724                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
1725                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
1726                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
1727                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
1728                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
1729                 } else {
1730                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1731                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1732                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
1733                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
1734                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
1735                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1736                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
1737                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
1738                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
1739                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
1740                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
1741                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
1742                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
1743                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
1744                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
1745                 }
1746                 break;
1747         case CHIP_VEGA20:
1748                 vega20_reg_base_init(adev);
1749                 adev->sdma.num_instances = 2;
1750                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1751                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1752                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
1753                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
1754                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
1755                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
1756                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
1757                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
1758                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
1759                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
1760                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1761                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
1762                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
1763                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
1764                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
1765                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
1766                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
1767                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
1768                 break;
1769         case CHIP_ARCTURUS:
1770                 arct_reg_base_init(adev);
1771                 adev->sdma.num_instances = 8;
1772                 adev->vcn.num_vcn_inst = 2;
1773                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1774                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1775                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
1776                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
1777                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
1778                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
1779                 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
1780                 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
1781                 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
1782                 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
1783                 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
1784                 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
1785                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
1786                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
1787                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
1788                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
1789                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1790                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
1791                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
1792                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
1793                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
1794                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
1795                 break;
1796         case CHIP_ALDEBARAN:
1797                 aldebaran_reg_base_init(adev);
1798                 adev->sdma.num_instances = 5;
1799                 adev->vcn.num_vcn_inst = 2;
1800                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1801                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1802                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
1803                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
1804                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
1805                 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
1806                 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
1807                 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
1808                 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
1809                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
1810                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
1811                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
1812                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
1813                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
1814                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
1815                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
1816                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
1817                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
1818                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
1819                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
1820                 break;
1821         default:
1822                 r = amdgpu_discovery_reg_base_init(adev);
1823                 if (r)
1824                         return -EINVAL;
1825
1826                 amdgpu_discovery_harvest_ip(adev);
1827                 break;
1828         }
1829
1830         switch (adev->ip_versions[GC_HWIP][0]) {
1831         case IP_VERSION(9, 0, 1):
1832         case IP_VERSION(9, 2, 1):
1833         case IP_VERSION(9, 4, 0):
1834         case IP_VERSION(9, 4, 1):
1835         case IP_VERSION(9, 4, 2):
1836                 adev->family = AMDGPU_FAMILY_AI;
1837                 break;
1838         case IP_VERSION(9, 1, 0):
1839         case IP_VERSION(9, 2, 2):
1840         case IP_VERSION(9, 3, 0):
1841                 adev->family = AMDGPU_FAMILY_RV;
1842                 break;
1843         case IP_VERSION(10, 1, 10):
1844         case IP_VERSION(10, 1, 1):
1845         case IP_VERSION(10, 1, 2):
1846         case IP_VERSION(10, 1, 3):
1847         case IP_VERSION(10, 1, 4):
1848         case IP_VERSION(10, 3, 0):
1849         case IP_VERSION(10, 3, 2):
1850         case IP_VERSION(10, 3, 4):
1851         case IP_VERSION(10, 3, 5):
1852                 adev->family = AMDGPU_FAMILY_NV;
1853                 break;
1854         case IP_VERSION(10, 3, 1):
1855                 adev->family = AMDGPU_FAMILY_VGH;
1856                 break;
1857         case IP_VERSION(10, 3, 3):
1858                 adev->family = AMDGPU_FAMILY_YC;
1859                 break;
1860         case IP_VERSION(10, 3, 6):
1861                 adev->family = AMDGPU_FAMILY_GC_10_3_6;
1862                 break;
1863         case IP_VERSION(10, 3, 7):
1864                 adev->family = AMDGPU_FAMILY_GC_10_3_7;
1865                 break;
1866         default:
1867                 return -EINVAL;
1868         }
1869
1870         switch (adev->ip_versions[GC_HWIP][0]) {
1871         case IP_VERSION(9, 1, 0):
1872         case IP_VERSION(9, 2, 2):
1873         case IP_VERSION(9, 3, 0):
1874         case IP_VERSION(10, 1, 3):
1875         case IP_VERSION(10, 1, 4):
1876         case IP_VERSION(10, 3, 1):
1877         case IP_VERSION(10, 3, 3):
1878         case IP_VERSION(10, 3, 6):
1879         case IP_VERSION(10, 3, 7):
1880                 adev->flags |= AMD_IS_APU;
1881                 break;
1882         default:
1883                 break;
1884         }
1885
1886         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
1887                 adev->gmc.xgmi.supported = true;
1888
1889         /* set NBIO version */
1890         switch (adev->ip_versions[NBIO_HWIP][0]) {
1891         case IP_VERSION(6, 1, 0):
1892         case IP_VERSION(6, 2, 0):
1893                 adev->nbio.funcs = &nbio_v6_1_funcs;
1894                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
1895                 break;
1896         case IP_VERSION(7, 0, 0):
1897         case IP_VERSION(7, 0, 1):
1898         case IP_VERSION(2, 5, 0):
1899                 adev->nbio.funcs = &nbio_v7_0_funcs;
1900                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
1901                 break;
1902         case IP_VERSION(7, 4, 0):
1903         case IP_VERSION(7, 4, 1):
1904                 adev->nbio.funcs = &nbio_v7_4_funcs;
1905                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
1906                 break;
1907         case IP_VERSION(7, 4, 4):
1908                 adev->nbio.funcs = &nbio_v7_4_funcs;
1909                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
1910                 break;
1911         case IP_VERSION(7, 2, 0):
1912         case IP_VERSION(7, 2, 1):
1913         case IP_VERSION(7, 3, 0):
1914         case IP_VERSION(7, 5, 0):
1915         case IP_VERSION(7, 5, 1):
1916                 adev->nbio.funcs = &nbio_v7_2_funcs;
1917                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
1918                 break;
1919         case IP_VERSION(2, 1, 1):
1920         case IP_VERSION(2, 3, 0):
1921         case IP_VERSION(2, 3, 1):
1922         case IP_VERSION(2, 3, 2):
1923                 adev->nbio.funcs = &nbio_v2_3_funcs;
1924                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
1925                 break;
1926         case IP_VERSION(3, 3, 0):
1927         case IP_VERSION(3, 3, 1):
1928         case IP_VERSION(3, 3, 2):
1929         case IP_VERSION(3, 3, 3):
1930                 adev->nbio.funcs = &nbio_v2_3_funcs;
1931                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
1932                 break;
1933         default:
1934                 break;
1935         }
1936
1937         switch (adev->ip_versions[HDP_HWIP][0]) {
1938         case IP_VERSION(4, 0, 0):
1939         case IP_VERSION(4, 0, 1):
1940         case IP_VERSION(4, 1, 0):
1941         case IP_VERSION(4, 1, 1):
1942         case IP_VERSION(4, 1, 2):
1943         case IP_VERSION(4, 2, 0):
1944         case IP_VERSION(4, 2, 1):
1945         case IP_VERSION(4, 4, 0):
1946                 adev->hdp.funcs = &hdp_v4_0_funcs;
1947                 break;
1948         case IP_VERSION(5, 0, 0):
1949         case IP_VERSION(5, 0, 1):
1950         case IP_VERSION(5, 0, 2):
1951         case IP_VERSION(5, 0, 3):
1952         case IP_VERSION(5, 0, 4):
1953         case IP_VERSION(5, 2, 0):
1954                 adev->hdp.funcs = &hdp_v5_0_funcs;
1955                 break;
1956         default:
1957                 break;
1958         }
1959
1960         switch (adev->ip_versions[DF_HWIP][0]) {
1961         case IP_VERSION(3, 6, 0):
1962         case IP_VERSION(3, 6, 1):
1963         case IP_VERSION(3, 6, 2):
1964                 adev->df.funcs = &df_v3_6_funcs;
1965                 break;
1966         case IP_VERSION(2, 1, 0):
1967         case IP_VERSION(2, 1, 1):
1968         case IP_VERSION(2, 5, 0):
1969         case IP_VERSION(3, 5, 1):
1970         case IP_VERSION(3, 5, 2):
1971                 adev->df.funcs = &df_v1_7_funcs;
1972                 break;
1973         default:
1974                 break;
1975         }
1976
1977         switch (adev->ip_versions[SMUIO_HWIP][0]) {
1978         case IP_VERSION(9, 0, 0):
1979         case IP_VERSION(9, 0, 1):
1980         case IP_VERSION(10, 0, 0):
1981         case IP_VERSION(10, 0, 1):
1982         case IP_VERSION(10, 0, 2):
1983                 adev->smuio.funcs = &smuio_v9_0_funcs;
1984                 break;
1985         case IP_VERSION(11, 0, 0):
1986         case IP_VERSION(11, 0, 2):
1987         case IP_VERSION(11, 0, 3):
1988         case IP_VERSION(11, 0, 4):
1989         case IP_VERSION(11, 0, 7):
1990         case IP_VERSION(11, 0, 8):
1991                 adev->smuio.funcs = &smuio_v11_0_funcs;
1992                 break;
1993         case IP_VERSION(11, 0, 6):
1994         case IP_VERSION(11, 0, 10):
1995         case IP_VERSION(11, 0, 11):
1996         case IP_VERSION(11, 5, 0):
1997         case IP_VERSION(13, 0, 1):
1998         case IP_VERSION(13, 0, 9):
1999         case IP_VERSION(13, 0, 10):
2000                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
2001                 break;
2002         case IP_VERSION(13, 0, 2):
2003                 adev->smuio.funcs = &smuio_v13_0_funcs;
2004                 break;
2005         default:
2006                 break;
2007         }
2008
2009         r = amdgpu_discovery_set_common_ip_blocks(adev);
2010         if (r)
2011                 return r;
2012
2013         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
2014         if (r)
2015                 return r;
2016
2017         /* For SR-IOV, PSP needs to be initialized before IH */
2018         if (amdgpu_sriov_vf(adev)) {
2019                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2020                 if (r)
2021                         return r;
2022                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2023                 if (r)
2024                         return r;
2025         } else {
2026                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2027                 if (r)
2028                         return r;
2029
2030                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2031                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
2032                         if (r)
2033                                 return r;
2034                 }
2035         }
2036
2037         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2038                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2039                 if (r)
2040                         return r;
2041         }
2042
2043         r = amdgpu_discovery_set_display_ip_blocks(adev);
2044         if (r)
2045                 return r;
2046
2047         r = amdgpu_discovery_set_gc_ip_blocks(adev);
2048         if (r)
2049                 return r;
2050
2051         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
2052         if (r)
2053                 return r;
2054
2055         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
2056             !amdgpu_sriov_vf(adev)) {
2057                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2058                 if (r)
2059                         return r;
2060         }
2061
2062         r = amdgpu_discovery_set_mm_ip_blocks(adev);
2063         if (r)
2064                 return r;
2065
2066         if (adev->enable_mes) {
2067                 r = amdgpu_discovery_set_mes_ip_blocks(adev);
2068                 if (r)
2069                         return r;
2070         }
2071
2072         return 0;
2073 }
2074