drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30
  31 #include "soc15.h"
  32 #include "gfx_v9_0.h"
  33 #include "gmc_v9_0.h"
  34 #include "df_v1_7.h"
  35 #include "df_v3_6.h"
  36 #include "nbio_v6_1.h"
  37 #include "nbio_v7_0.h"
  38 #include "nbio_v7_4.h"
  39 #include "hdp_v4_0.h"
  40 #include "vega10_ih.h"
  41 #include "vega20_ih.h"
  42 #include "sdma_v4_0.h"
  43 #include "uvd_v7_0.h"
  44 #include "vce_v4_0.h"
  45 #include "vcn_v1_0.h"
  46 #include "vcn_v2_5.h"
  47 #include "jpeg_v2_5.h"
  48 #include "smuio_v9_0.h"
  49 #include "gmc_v10_0.h"
  50 #include "gfxhub_v2_0.h"
  51 #include "mmhub_v2_0.h"
  52 #include "nbio_v2_3.h"
  53 #include "nbio_v7_2.h"
  54 #include "hdp_v5_0.h"
  55 #include "nv.h"
  56 #include "navi10_ih.h"
  57 #include "gfx_v10_0.h"
  58 #include "sdma_v5_0.h"
  59 #include "sdma_v5_2.h"
  60 #include "vcn_v2_0.h"
  61 #include "jpeg_v2_0.h"
  62 #include "vcn_v3_0.h"
  63 #include "jpeg_v3_0.h"
  64 #include "amdgpu_vkms.h"
  65 #include "mes_v10_1.h"
  66 #include "smuio_v11_0.h"
  67 #include "smuio_v11_0_6.h"
  68 #include "smuio_v13_0.h"
  69
  70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
  71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
  72
  73 #define mmRCC_CONFIG_MEMSIZE    0xde3
  74 #define mmMM_INDEX              0x0
  75 #define mmMM_INDEX_HI           0x6
  76 #define mmMM_DATA               0x1
  77
  78 static const char *hw_id_names[HW_ID_MAX] = {
  79         [MP1_HWID]              = "MP1",
  80         [MP2_HWID]              = "MP2",
  81         [THM_HWID]              = "THM",
  82         [SMUIO_HWID]            = "SMUIO",
  83         [FUSE_HWID]             = "FUSE",
  84         [CLKA_HWID]             = "CLKA",
  85         [PWR_HWID]              = "PWR",
  86         [GC_HWID]               = "GC",
  87         [UVD_HWID]              = "UVD",
  88         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
  89         [ACP_HWID]              = "ACP",
  90         [DCI_HWID]              = "DCI",
  91         [DMU_HWID]              = "DMU",
  92         [DCO_HWID]              = "DCO",
  93         [DIO_HWID]              = "DIO",
  94         [XDMA_HWID]             = "XDMA",
  95         [DCEAZ_HWID]            = "DCEAZ",
  96         [DAZ_HWID]              = "DAZ",
  97         [SDPMUX_HWID]           = "SDPMUX",
  98         [NTB_HWID]              = "NTB",
  99         [IOHC_HWID]             = "IOHC",
 100         [L2IMU_HWID]            = "L2IMU",
 101         [VCE_HWID]              = "VCE",
 102         [MMHUB_HWID]            = "MMHUB",
 103         [ATHUB_HWID]            = "ATHUB",
 104         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 105         [DFX_HWID]              = "DFX",
 106         [DBGU0_HWID]            = "DBGU0",
 107         [DBGU1_HWID]            = "DBGU1",
 108         [OSSSYS_HWID]           = "OSSSYS",
 109         [HDP_HWID]              = "HDP",
 110         [SDMA0_HWID]            = "SDMA0",
 111         [SDMA1_HWID]            = "SDMA1",
 112         [SDMA2_HWID]            = "SDMA2",
 113         [SDMA3_HWID]            = "SDMA3",
 114         [ISP_HWID]              = "ISP",
 115         [DBGU_IO_HWID]          = "DBGU_IO",
 116         [DF_HWID]               = "DF",
 117         [CLKB_HWID]             = "CLKB",
 118         [FCH_HWID]              = "FCH",
 119         [DFX_DAP_HWID]          = "DFX_DAP",
 120         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 121         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 122         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 123         [L1IMU3_HWID]           = "L1IMU3",
 124         [L1IMU4_HWID]           = "L1IMU4",
 125         [L1IMU5_HWID]           = "L1IMU5",
 126         [L1IMU6_HWID]           = "L1IMU6",
 127         [L1IMU7_HWID]           = "L1IMU7",
 128         [L1IMU8_HWID]           = "L1IMU8",
 129         [L1IMU9_HWID]           = "L1IMU9",
 130         [L1IMU10_HWID]          = "L1IMU10",
 131         [L1IMU11_HWID]          = "L1IMU11",
 132         [L1IMU12_HWID]          = "L1IMU12",
 133         [L1IMU13_HWID]          = "L1IMU13",
 134         [L1IMU14_HWID]          = "L1IMU14",
 135         [L1IMU15_HWID]          = "L1IMU15",
 136         [WAFLC_HWID]            = "WAFLC",
 137         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 138         [PCIE_HWID]             = "PCIE",
 139         [PCS_HWID]              = "PCS",
 140         [DDCL_HWID]             = "DDCL",
 141         [SST_HWID]              = "SST",
 142         [IOAGR_HWID]            = "IOAGR",
 143         [NBIF_HWID]             = "NBIF",
 144         [IOAPIC_HWID]           = "IOAPIC",
 145         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 146         [NTBCCP_HWID]           = "NTBCCP",
 147         [UMC_HWID]              = "UMC",
 148         [SATA_HWID]             = "SATA",
 149         [USB_HWID]              = "USB",
 150         [CCXSEC_HWID]           = "CCXSEC",
 151         [XGMI_HWID]             = "XGMI",
 152         [XGBE_HWID]             = "XGBE",
 153         [MP0_HWID]              = "MP0",
 154 };
 155
 156 static int hw_id_map[MAX_HWIP] = {
 157         [GC_HWIP]       = GC_HWID,
 158         [HDP_HWIP]      = HDP_HWID,
 159         [SDMA0_HWIP]    = SDMA0_HWID,
 160         [SDMA1_HWIP]    = SDMA1_HWID,
 161         [SDMA2_HWIP]    = SDMA2_HWID,
 162         [SDMA3_HWIP]    = SDMA3_HWID,
 163         [MMHUB_HWIP]    = MMHUB_HWID,
 164         [ATHUB_HWIP]    = ATHUB_HWID,
 165         [NBIO_HWIP]     = NBIF_HWID,
 166         [MP0_HWIP]      = MP0_HWID,
 167         [MP1_HWIP]      = MP1_HWID,
 168         [UVD_HWIP]      = UVD_HWID,
 169         [VCE_HWIP]      = VCE_HWID,
 170         [DF_HWIP]       = DF_HWID,
 171         [DCE_HWIP]      = DMU_HWID,
 172         [OSSSYS_HWIP]   = OSSSYS_HWID,
 173         [SMUIO_HWIP]    = SMUIO_HWID,
 174         [PWR_HWIP]      = PWR_HWID,
 175         [NBIF_HWIP]     = NBIF_HWID,
 176         [THM_HWIP]      = THM_HWID,
 177         [CLK_HWIP]      = CLKA_HWID,
 178         [UMC_HWIP]      = UMC_HWID,
 179         [XGMI_HWIP]     = XGMI_HWID,
 180         [DCI_HWIP]      = DCI_HWID,
 181 };
 182
 183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
 184 {
 185         uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 186         uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 187
 188         amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 189                                   adev->mman.discovery_tmr_size, false);
 190         return 0;
 191 }
 192
 193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
 194 {
 195         const struct firmware *fw;
 196         const char *fw_name;
 197         int r;
 198
 199         switch (amdgpu_discovery) {
 200         case 2:
 201                 fw_name = FIRMWARE_IP_DISCOVERY;
 202                 break;
 203         default:
 204                 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
 205                 return -EINVAL;
 206         }
 207
 208         r = request_firmware(&fw, fw_name, adev->dev);
 209         if (r) {
 210                 dev_err(adev->dev, "can't load firmware \"%s\"\n",
 211                         fw_name);
 212                 return r;
 213         }
 214
 215         memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
 216         release_firmware(fw);
 217
 218         return 0;
 219 }
 220
 221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 222 {
 223         uint16_t checksum = 0;
 224         int i;
 225
 226         for (i = 0; i < size; i++)
 227                 checksum += data[i];
 228
 229         return checksum;
 230 }
 231
 232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 233                                                     uint16_t expected)
 234 {
 235         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 236 }
 237
 238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
 239 {
 240         struct binary_header *bhdr;
 241         bhdr = (struct binary_header *)binary;
 242
 243         return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
 244 }
 245
 246 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
 247 {
 248         /*
 249          * So far, apply this quirk only on those Navy Flounder boards which
 250          * have a bad harvest table of VCN config.
 251          */
 252         if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
 253                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
 254                 switch (adev->pdev->revision) {
 255                 case 0xC1:
 256                 case 0xC2:
 257                 case 0xC3:
 258                 case 0xC5:
 259                 case 0xC7:
 260                 case 0xCF:
 261                 case 0xDF:
 262                         adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 263                         break;
 264                 default:
 265                         break;
 266                 }
 267         }
 268 }
 269
 270 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 271 {
 272         struct table_info *info;
 273         struct binary_header *bhdr;
 274         struct ip_discovery_header *ihdr;
 275         struct gpu_info_header *ghdr;
 276         uint16_t offset;
 277         uint16_t size;
 278         uint16_t checksum;
 279         int r;
 280
 281         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 282         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 283         if (!adev->mman.discovery_bin)
 284                 return -ENOMEM;
 285
 286         r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin);
 287         if (r) {
 288                 dev_err(adev->dev, "failed to read ip discovery binary from vram\n");
 289                 r = -EINVAL;
 290                 goto out;
 291         }
 292
 293         if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 294                 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n");
 295                 /* retry read ip discovery binary from file */
 296                 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
 297                 if (r) {
 298                         dev_err(adev->dev, "failed to read ip discovery binary from file\n");
 299                         r = -EINVAL;
 300                         goto out;
 301                 }
 302                 /* check the ip discovery binary signature */
 303                 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 304                         dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n");
 305                         r = -EINVAL;
 306                         goto out;
 307                 }
 308         }
 309
 310         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 311
 312         offset = offsetof(struct binary_header, binary_checksum) +
 313                 sizeof(bhdr->binary_checksum);
 314         size = le16_to_cpu(bhdr->binary_size) - offset;
 315         checksum = le16_to_cpu(bhdr->binary_checksum);
 316
 317         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 318                                               size, checksum)) {
 319                 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
 320                 r = -EINVAL;
 321                 goto out;
 322         }
 323
 324         info = &bhdr->table_list[IP_DISCOVERY];
 325         offset = le16_to_cpu(info->offset);
 326         checksum = le16_to_cpu(info->checksum);
 327         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 328
 329         if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 330                 dev_err(adev->dev, "invalid ip discovery data table signature\n");
 331                 r = -EINVAL;
 332                 goto out;
 333         }
 334
 335         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 336                                               le16_to_cpu(ihdr->size), checksum)) {
 337                 dev_err(adev->dev, "invalid ip discovery data table checksum\n");
 338                 r = -EINVAL;
 339                 goto out;
 340         }
 341
 342         info = &bhdr->table_list[GC];
 343         offset = le16_to_cpu(info->offset);
 344         checksum = le16_to_cpu(info->checksum);
 345         ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 346
 347         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 348                                               le32_to_cpu(ghdr->size), checksum)) {
 349                 dev_err(adev->dev, "invalid gc data table checksum\n");
 350                 r = -EINVAL;
 351                 goto out;
 352         }
 353
 354         return 0;
 355
 356 out:
 357         kfree(adev->mman.discovery_bin);
 358         adev->mman.discovery_bin = NULL;
 359
 360         return r;
 361 }
 362
 363 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
 364
 365 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 366 {
 367         amdgpu_discovery_sysfs_fini(adev);
 368         kfree(adev->mman.discovery_bin);
 369         adev->mman.discovery_bin = NULL;
 370 }
 371
 372 static int amdgpu_discovery_validate_ip(const struct ip *ip)
 373 {
 374         if (ip->number_instance >= HWIP_MAX_INSTANCE) {
 375                 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
 376                           ip->number_instance);
 377                 return -EINVAL;
 378         }
 379         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 380                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 381                           le16_to_cpu(ip->hw_id));
 382                 return -EINVAL;
 383         }
 384
 385         return 0;
 386 }
 387
 388 /* ================================================== */
 389
 390 struct ip_hw_instance {
 391         struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
 392
 393         int hw_id;
 394         u8  num_instance;
 395         u8  major, minor, revision;
 396         u8  harvest;
 397
 398         int num_base_addresses;
 399         u32 base_addr[];
 400 };
 401
 402 struct ip_hw_id {
 403         struct kset hw_id_kset;  /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
 404         int hw_id;
 405 };
 406
 407 struct ip_die_entry {
 408         struct kset ip_kset;     /* ip_discovery/die/#die/, contains ip_hw_id  */
 409         u16 num_ips;
 410 };
 411
 412 /* -------------------------------------------------- */
 413
 414 struct ip_hw_instance_attr {
 415         struct attribute attr;
 416         ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
 417 };
 418
 419 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 420 {
 421         return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
 422 }
 423
 424 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 425 {
 426         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
 427 }
 428
 429 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 430 {
 431         return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
 432 }
 433
 434 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 435 {
 436         return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
 437 }
 438
 439 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 440 {
 441         return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
 442 }
 443
 444 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 445 {
 446         return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
 447 }
 448
 449 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 450 {
 451         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
 452 }
 453
 454 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 455 {
 456         ssize_t res, at;
 457         int ii;
 458
 459         for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
 460                 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
 461                  */
 462                 if (at + 12 > PAGE_SIZE)
 463                         break;
 464                 res = sysfs_emit_at(buf, at, "0x%08X\n",
 465                                     ip_hw_instance->base_addr[ii]);
 466                 if (res <= 0)
 467                         break;
 468                 at += res;
 469         }
 470
 471         return res < 0 ? res : at;
 472 }
 473
 474 static struct ip_hw_instance_attr ip_hw_attr[] = {
 475         __ATTR_RO(hw_id),
 476         __ATTR_RO(num_instance),
 477         __ATTR_RO(major),
 478         __ATTR_RO(minor),
 479         __ATTR_RO(revision),
 480         __ATTR_RO(harvest),
 481         __ATTR_RO(num_base_addresses),
 482         __ATTR_RO(base_addr),
 483 };
 484
 485 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
 486 ATTRIBUTE_GROUPS(ip_hw_instance);
 487
 488 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
 489 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
 490
 491 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
 492                                         struct attribute *attr,
 493                                         char *buf)
 494 {
 495         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 496         struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
 497
 498         if (!ip_hw_attr->show)
 499                 return -EIO;
 500
 501         return ip_hw_attr->show(ip_hw_instance, buf);
 502 }
 503
 504 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
 505         .show = ip_hw_instance_attr_show,
 506 };
 507
 508 static void ip_hw_instance_release(struct kobject *kobj)
 509 {
 510         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 511
 512         kfree(ip_hw_instance);
 513 }
 514
 515 static struct kobj_type ip_hw_instance_ktype = {
 516         .release = ip_hw_instance_release,
 517         .sysfs_ops = &ip_hw_instance_sysfs_ops,
 518         .default_groups = ip_hw_instance_groups,
 519 };
 520
 521 /* -------------------------------------------------- */
 522
 523 #define to_ip_hw_id(x)  container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
 524
 525 static void ip_hw_id_release(struct kobject *kobj)
 526 {
 527         struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
 528
 529         if (!list_empty(&ip_hw_id->hw_id_kset.list))
 530                 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
 531         kfree(ip_hw_id);
 532 }
 533
 534 static struct kobj_type ip_hw_id_ktype = {
 535         .release = ip_hw_id_release,
 536         .sysfs_ops = &kobj_sysfs_ops,
 537 };
 538
 539 /* -------------------------------------------------- */
 540
 541 static void die_kobj_release(struct kobject *kobj);
 542 static void ip_disc_release(struct kobject *kobj);
 543
 544 struct ip_die_entry_attribute {
 545         struct attribute attr;
 546         ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
 547 };
 548
 549 #define to_ip_die_entry_attr(x)  container_of(x, struct ip_die_entry_attribute, attr)
 550
 551 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
 552 {
 553         return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
 554 }
 555
 556 /* If there are more ip_die_entry attrs, other than the number of IPs,
 557  * we can make this intro an array of attrs, and then initialize
 558  * ip_die_entry_attrs in a loop.
 559  */
 560 static struct ip_die_entry_attribute num_ips_attr =
 561         __ATTR_RO(num_ips);
 562
 563 static struct attribute *ip_die_entry_attrs[] = {
 564         &num_ips_attr.attr,
 565         NULL,
 566 };
 567 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
 568
 569 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
 570
 571 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
 572                                       struct attribute *attr,
 573                                       char *buf)
 574 {
 575         struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
 576         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 577
 578         if (!ip_die_entry_attr->show)
 579                 return -EIO;
 580
 581         return ip_die_entry_attr->show(ip_die_entry, buf);
 582 }
 583
 584 static void ip_die_entry_release(struct kobject *kobj)
 585 {
 586         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 587
 588         if (!list_empty(&ip_die_entry->ip_kset.list))
 589                 DRM_ERROR("ip_die_entry->ip_kset is not empty");
 590         kfree(ip_die_entry);
 591 }
 592
 593 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
 594         .show = ip_die_entry_attr_show,
 595 };
 596
 597 static struct kobj_type ip_die_entry_ktype = {
 598         .release = ip_die_entry_release,
 599         .sysfs_ops = &ip_die_entry_sysfs_ops,
 600         .default_groups = ip_die_entry_groups,
 601 };
 602
 603 static struct kobj_type die_kobj_ktype = {
 604         .release = die_kobj_release,
 605         .sysfs_ops = &kobj_sysfs_ops,
 606 };
 607
 608 static struct kobj_type ip_discovery_ktype = {
 609         .release = ip_disc_release,
 610         .sysfs_ops = &kobj_sysfs_ops,
 611 };
 612
 613 struct ip_discovery_top {
 614         struct kobject kobj;    /* ip_discovery/ */
 615         struct kset die_kset;   /* ip_discovery/die/, contains ip_die_entry */
 616         struct amdgpu_device *adev;
 617 };
 618
 619 static void die_kobj_release(struct kobject *kobj)
 620 {
 621         struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
 622                                                        struct ip_discovery_top,
 623                                                        die_kset);
 624         if (!list_empty(&ip_top->die_kset.list))
 625                 DRM_ERROR("ip_top->die_kset is not empty");
 626 }
 627
 628 static void ip_disc_release(struct kobject *kobj)
 629 {
 630         struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
 631                                                        kobj);
 632         struct amdgpu_device *adev = ip_top->adev;
 633
 634         adev->ip_top = NULL;
 635         kfree(ip_top);
 636 }
 637
 638 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
 639                                       struct ip_die_entry *ip_die_entry,
 640                                       const size_t _ip_offset, const int num_ips)
 641 {
 642         int ii, jj, kk, res;
 643
 644         DRM_DEBUG("num_ips:%d", num_ips);
 645
 646         /* Find all IPs of a given HW ID, and add their instance to
 647          * #die/#hw_id/#instance/<attributes>
 648          */
 649         for (ii = 0; ii < HW_ID_MAX; ii++) {
 650                 struct ip_hw_id *ip_hw_id = NULL;
 651                 size_t ip_offset = _ip_offset;
 652
 653                 for (jj = 0; jj < num_ips; jj++) {
 654                         struct ip *ip;
 655                         struct ip_hw_instance *ip_hw_instance;
 656
 657                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 658                         if (amdgpu_discovery_validate_ip(ip) ||
 659                             le16_to_cpu(ip->hw_id) != ii)
 660                                 goto next_ip;
 661
 662                         DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
 663
 664                         /* We have a hw_id match; register the hw
 665                          * block if not yet registered.
 666                          */
 667                         if (!ip_hw_id) {
 668                                 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
 669                                 if (!ip_hw_id)
 670                                         return -ENOMEM;
 671                                 ip_hw_id->hw_id = ii;
 672
 673                                 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
 674                                 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
 675                                 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
 676                                 res = kset_register(&ip_hw_id->hw_id_kset);
 677                                 if (res) {
 678                                         DRM_ERROR("Couldn't register ip_hw_id kset");
 679                                         kfree(ip_hw_id);
 680                                         return res;
 681                                 }
 682                                 if (hw_id_names[ii]) {
 683                                         res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
 684                                                                 &ip_hw_id->hw_id_kset.kobj,
 685                                                                 hw_id_names[ii]);
 686                                         if (res) {
 687                                                 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
 688                                                           hw_id_names[ii],
 689                                                           kobject_name(&ip_die_entry->ip_kset.kobj));
 690                                         }
 691                                 }
 692                         }
 693
 694                         /* Now register its instance.
 695                          */
 696                         ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
 697                                                              base_addr,
 698                                                              ip->num_base_address),
 699                                                  GFP_KERNEL);
 700                         if (!ip_hw_instance) {
 701                                 DRM_ERROR("no memory for ip_hw_instance");
 702                                 return -ENOMEM;
 703                         }
 704                         ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
 705                         ip_hw_instance->num_instance = ip->number_instance;
 706                         ip_hw_instance->major = ip->major;
 707                         ip_hw_instance->minor = ip->minor;
 708                         ip_hw_instance->revision = ip->revision;
 709                         ip_hw_instance->harvest = ip->harvest;
 710                         ip_hw_instance->num_base_addresses = ip->num_base_address;
 711
 712                         for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++)
 713                                 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
 714
 715                         kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
 716                         ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
 717                         res = kobject_add(&ip_hw_instance->kobj, NULL,
 718                                           "%d", ip_hw_instance->num_instance);
 719 next_ip:
 720                         ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
 721                 }
 722         }
 723
 724         return 0;
 725 }
 726
 727 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
 728 {
 729         struct binary_header *bhdr;
 730         struct ip_discovery_header *ihdr;
 731         struct die_header *dhdr;
 732         struct kset *die_kset = &adev->ip_top->die_kset;
 733         u16 num_dies, die_offset, num_ips;
 734         size_t ip_offset;
 735         int ii, res;
 736
 737         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 738         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 739                                               le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 740         num_dies = le16_to_cpu(ihdr->num_dies);
 741
 742         DRM_DEBUG("number of dies: %d\n", num_dies);
 743
 744         for (ii = 0; ii < num_dies; ii++) {
 745                 struct ip_die_entry *ip_die_entry;
 746
 747                 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
 748                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 749                 num_ips = le16_to_cpu(dhdr->num_ips);
 750                 ip_offset = die_offset + sizeof(*dhdr);
 751
 752                 /* Add the die to the kset.
 753                  *
 754                  * dhdr->die_id == ii, which was checked in
 755                  * amdgpu_discovery_reg_base_init().
 756                  */
 757
 758                 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
 759                 if (!ip_die_entry)
 760                         return -ENOMEM;
 761
 762                 ip_die_entry->num_ips = num_ips;
 763
 764                 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
 765                 ip_die_entry->ip_kset.kobj.kset = die_kset;
 766                 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
 767                 res = kset_register(&ip_die_entry->ip_kset);
 768                 if (res) {
 769                         DRM_ERROR("Couldn't register ip_die_entry kset");
 770                         kfree(ip_die_entry);
 771                         return res;
 772                 }
 773
 774                 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips);
 775         }
 776
 777         return 0;
 778 }
 779
 780 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
 781 {
 782         struct kset *die_kset;
 783         int res, ii;
 784
 785         adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
 786         if (!adev->ip_top)
 787                 return -ENOMEM;
 788
 789         adev->ip_top->adev = adev;
 790
 791         res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
 792                                    &adev->dev->kobj, "ip_discovery");
 793         if (res) {
 794                 DRM_ERROR("Couldn't init and add ip_discovery/");
 795                 goto Err;
 796         }
 797
 798         die_kset = &adev->ip_top->die_kset;
 799         kobject_set_name(&die_kset->kobj, "%s", "die");
 800         die_kset->kobj.parent = &adev->ip_top->kobj;
 801         die_kset->kobj.ktype = &die_kobj_ktype;
 802         res = kset_register(&adev->ip_top->die_kset);
 803         if (res) {
 804                 DRM_ERROR("Couldn't register die_kset");
 805                 goto Err;
 806         }
 807
 808         for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
 809                 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
 810         ip_hw_instance_attrs[ii] = NULL;
 811
 812         res = amdgpu_discovery_sysfs_recurse(adev);
 813
 814         return res;
 815 Err:
 816         kobject_put(&adev->ip_top->kobj);
 817         return res;
 818 }
 819
 820 /* -------------------------------------------------- */
 821
 822 #define list_to_kobj(el) container_of(el, struct kobject, entry)
 823
 824 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
 825 {
 826         struct list_head *el, *tmp;
 827         struct kset *hw_id_kset;
 828
 829         hw_id_kset = &ip_hw_id->hw_id_kset;
 830         spin_lock(&hw_id_kset->list_lock);
 831         list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
 832                 list_del_init(el);
 833                 spin_unlock(&hw_id_kset->list_lock);
 834                 /* kobject is embedded in ip_hw_instance */
 835                 kobject_put(list_to_kobj(el));
 836                 spin_lock(&hw_id_kset->list_lock);
 837         }
 838         spin_unlock(&hw_id_kset->list_lock);
 839         kobject_put(&ip_hw_id->hw_id_kset.kobj);
 840 }
 841
 842 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
 843 {
 844         struct list_head *el, *tmp;
 845         struct kset *ip_kset;
 846
 847         ip_kset = &ip_die_entry->ip_kset;
 848         spin_lock(&ip_kset->list_lock);
 849         list_for_each_prev_safe(el, tmp, &ip_kset->list) {
 850                 list_del_init(el);
 851                 spin_unlock(&ip_kset->list_lock);
 852                 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
 853                 spin_lock(&ip_kset->list_lock);
 854         }
 855         spin_unlock(&ip_kset->list_lock);
 856         kobject_put(&ip_die_entry->ip_kset.kobj);
 857 }
 858
 859 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
 860 {
 861         struct list_head *el, *tmp;
 862         struct kset *die_kset;
 863
 864         die_kset = &adev->ip_top->die_kset;
 865         spin_lock(&die_kset->list_lock);
 866         list_for_each_prev_safe(el, tmp, &die_kset->list) {
 867                 list_del_init(el);
 868                 spin_unlock(&die_kset->list_lock);
 869                 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
 870                 spin_lock(&die_kset->list_lock);
 871         }
 872         spin_unlock(&die_kset->list_lock);
 873         kobject_put(&adev->ip_top->die_kset.kobj);
 874         kobject_put(&adev->ip_top->kobj);
 875 }
 876
 877 /* ================================================== */
 878
 879 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 880 {
 881         struct binary_header *bhdr;
 882         struct ip_discovery_header *ihdr;
 883         struct die_header *dhdr;
 884         struct ip *ip;
 885         uint16_t die_offset;
 886         uint16_t ip_offset;
 887         uint16_t num_dies;
 888         uint16_t num_ips;
 889         uint8_t num_base_address;
 890         int hw_ip;
 891         int i, j, k;
 892         int r;
 893
 894         r = amdgpu_discovery_init(adev);
 895         if (r) {
 896                 DRM_ERROR("amdgpu_discovery_init failed\n");
 897                 return r;
 898         }
 899
 900         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 901         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 902                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 903         num_dies = le16_to_cpu(ihdr->num_dies);
 904
 905         DRM_DEBUG("number of dies: %d\n", num_dies);
 906
 907         for (i = 0; i < num_dies; i++) {
 908                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 909                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 910                 num_ips = le16_to_cpu(dhdr->num_ips);
 911                 ip_offset = die_offset + sizeof(*dhdr);
 912
 913                 if (le16_to_cpu(dhdr->die_id) != i) {
 914                         DRM_ERROR("invalid die id %d, expected %d\n",
 915                                         le16_to_cpu(dhdr->die_id), i);
 916                         return -EINVAL;
 917                 }
 918
 919                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
 920                                 le16_to_cpu(dhdr->die_id), num_ips);
 921
 922                 for (j = 0; j < num_ips; j++) {
 923                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 924
 925                         if (amdgpu_discovery_validate_ip(ip))
 926                                 goto next_ip;
 927
 928                         num_base_address = ip->num_base_address;
 929
 930                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
 931                                   hw_id_names[le16_to_cpu(ip->hw_id)],
 932                                   le16_to_cpu(ip->hw_id),
 933                                   ip->number_instance,
 934                                   ip->major, ip->minor,
 935                                   ip->revision);
 936
 937                         if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
 938                                 /* Bit [5:0]: original revision value
 939                                  * Bit [7:6]: en/decode capability:
 940                                  *     0b00 : VCN function normally
 941                                  *     0b10 : encode is disabled
 942                                  *     0b01 : decode is disabled
 943                                  */
 944                                 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
 945                                         ip->revision & 0xc0;
 946                                 ip->revision &= ~0xc0;
 947                                 adev->vcn.num_vcn_inst++;
 948                         }
 949                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
 950                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
 951                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
 952                             le16_to_cpu(ip->hw_id) == SDMA3_HWID)
 953                                 adev->sdma.num_instances++;
 954
 955                         for (k = 0; k < num_base_address; k++) {
 956                                 /*
 957                                  * convert the endianness of base addresses in place,
 958                                  * so that we don't need to convert them when accessing adev->reg_offset.
 959                                  */
 960                                 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
 961                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
 962                         }
 963
 964                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
 965                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
 966                                         DRM_DEBUG("set register base offset for %s\n",
 967                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
 968                                         adev->reg_offset[hw_ip][ip->number_instance] =
 969                                                 ip->base_address;
 970                                         /* Instance support is somewhat inconsistent.
 971                                          * SDMA is a good example.  Sienna cichlid has 4 total
 972                                          * SDMA instances, each enumerated separately (HWIDs
 973                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
 974                                          * but they are enumerated as multiple instances of the
 975                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
 976                                          * example.  On most chips there are multiple instances
 977                                          * with the same HWID.
 978                                          */
 979                                         adev->ip_versions[hw_ip][ip->number_instance] =
 980                                                 IP_VERSION(ip->major, ip->minor, ip->revision);
 981                                 }
 982                         }
 983
 984 next_ip:
 985                         ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
 986                 }
 987         }
 988
 989         amdgpu_discovery_sysfs_init(adev);
 990
 991         return 0;
 992 }
 993
 994 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
 995                                     int *major, int *minor, int *revision)
 996 {
 997         struct binary_header *bhdr;
 998         struct ip_discovery_header *ihdr;
 999         struct die_header *dhdr;
1000         struct ip *ip;
1001         uint16_t die_offset;
1002         uint16_t ip_offset;
1003         uint16_t num_dies;
1004         uint16_t num_ips;
1005         int i, j;
1006
1007         if (!adev->mman.discovery_bin) {
1008                 DRM_ERROR("ip discovery uninitialized\n");
1009                 return -EINVAL;
1010         }
1011
1012         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1013         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1014                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1015         num_dies = le16_to_cpu(ihdr->num_dies);
1016
1017         for (i = 0; i < num_dies; i++) {
1018                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1019                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1020                 num_ips = le16_to_cpu(dhdr->num_ips);
1021                 ip_offset = die_offset + sizeof(*dhdr);
1022
1023                 for (j = 0; j < num_ips; j++) {
1024                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1025
1026                         if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
1027                                 if (major)
1028                                         *major = ip->major;
1029                                 if (minor)
1030                                         *minor = ip->minor;
1031                                 if (revision)
1032                                         *revision = ip->revision;
1033                                 return 0;
1034                         }
1035                         ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
1036                 }
1037         }
1038
1039         return -EINVAL;
1040 }
1041
1042 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1043 {
1044         struct binary_header *bhdr;
1045         struct harvest_table *harvest_info;
1046         int i, vcn_harvest_count = 0;
1047
1048         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1049         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
1050                         le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
1051
1052         for (i = 0; i < 32; i++) {
1053                 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
1054                         break;
1055
1056                 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
1057                 case VCN_HWID:
1058                         vcn_harvest_count++;
1059                         if (harvest_info->list[i].number_instance == 0)
1060                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
1061                         else
1062                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
1063                         break;
1064                 case DMU_HWID:
1065                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
1066                         break;
1067                 default:
1068                         break;
1069                 }
1070         }
1071
1072         amdgpu_discovery_harvest_config_quirk(adev);
1073
1074         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1075                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1076                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1077         }
1078         if ((adev->pdev->device == 0x731E &&
1079              (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) ||
1080             (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9)  ||
1081             (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) {
1082                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1083                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1084         }
1085 }
1086
1087 union gc_info {
1088         struct gc_info_v1_0 v1;
1089         struct gc_info_v2_0 v2;
1090 };
1091
1092 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1093 {
1094         struct binary_header *bhdr;
1095         union gc_info *gc_info;
1096
1097         if (!adev->mman.discovery_bin) {
1098                 DRM_ERROR("ip discovery uninitialized\n");
1099                 return -EINVAL;
1100         }
1101
1102         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1103         gc_info = (union gc_info *)(adev->mman.discovery_bin +
1104                         le16_to_cpu(bhdr->table_list[GC].offset));
1105         switch (gc_info->v1.header.version_major) {
1106         case 1:
1107                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1108                 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1109                                                       le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1110                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1111                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1112                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1113                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1114                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1115                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1116                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1117                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1118                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1119                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1120                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1121                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1122                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1123                         le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1124                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1125                 break;
1126         case 2:
1127                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1128                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1129                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1130                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1131                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1132                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1133                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1134                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1135                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1136                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1137                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1138                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1139                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1140                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1141                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1142                         le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1143                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1144                 break;
1145         default:
1146                 dev_err(adev->dev,
1147                         "Unhandled GC info table %d.%d\n",
1148                         gc_info->v1.header.version_major,
1149                         gc_info->v1.header.version_minor);
1150                 return -EINVAL;
1151         }
1152         return 0;
1153 }
1154
1155 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1156 {
1157         /* what IP to use for this? */
1158         switch (adev->ip_versions[GC_HWIP][0]) {
1159         case IP_VERSION(9, 0, 1):
1160         case IP_VERSION(9, 1, 0):
1161         case IP_VERSION(9, 2, 1):
1162         case IP_VERSION(9, 2, 2):
1163         case IP_VERSION(9, 3, 0):
1164         case IP_VERSION(9, 4, 0):
1165         case IP_VERSION(9, 4, 1):
1166         case IP_VERSION(9, 4, 2):
1167                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1168                 break;
1169         case IP_VERSION(10, 1, 10):
1170         case IP_VERSION(10, 1, 1):
1171         case IP_VERSION(10, 1, 2):
1172         case IP_VERSION(10, 1, 3):
1173         case IP_VERSION(10, 1, 4):
1174         case IP_VERSION(10, 3, 0):
1175         case IP_VERSION(10, 3, 1):
1176         case IP_VERSION(10, 3, 2):
1177         case IP_VERSION(10, 3, 3):
1178         case IP_VERSION(10, 3, 4):
1179         case IP_VERSION(10, 3, 5):
1180         case IP_VERSION(10, 3, 6):
1181         case IP_VERSION(10, 3, 7):
1182                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1183                 break;
1184         default:
1185                 dev_err(adev->dev,
1186                         "Failed to add common ip block(GC_HWIP:0x%x)\n",
1187                         adev->ip_versions[GC_HWIP][0]);
1188                 return -EINVAL;
1189         }
1190         return 0;
1191 }
1192
1193 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1194 {
1195         /* use GC or MMHUB IP version */
1196         switch (adev->ip_versions[GC_HWIP][0]) {
1197         case IP_VERSION(9, 0, 1):
1198         case IP_VERSION(9, 1, 0):
1199         case IP_VERSION(9, 2, 1):
1200         case IP_VERSION(9, 2, 2):
1201         case IP_VERSION(9, 3, 0):
1202         case IP_VERSION(9, 4, 0):
1203         case IP_VERSION(9, 4, 1):
1204         case IP_VERSION(9, 4, 2):
1205                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1206                 break;
1207         case IP_VERSION(10, 1, 10):
1208         case IP_VERSION(10, 1, 1):
1209         case IP_VERSION(10, 1, 2):
1210         case IP_VERSION(10, 1, 3):
1211         case IP_VERSION(10, 1, 4):
1212         case IP_VERSION(10, 3, 0):
1213         case IP_VERSION(10, 3, 1):
1214         case IP_VERSION(10, 3, 2):
1215         case IP_VERSION(10, 3, 3):
1216         case IP_VERSION(10, 3, 4):
1217         case IP_VERSION(10, 3, 5):
1218         case IP_VERSION(10, 3, 6):
1219         case IP_VERSION(10, 3, 7):
1220                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1221                 break;
1222         default:
1223                 dev_err(adev->dev,
1224                         "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1225                         adev->ip_versions[GC_HWIP][0]);
1226                 return -EINVAL;
1227         }
1228         return 0;
1229 }
1230
1231 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1232 {
1233         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
1234         case IP_VERSION(4, 0, 0):
1235         case IP_VERSION(4, 0, 1):
1236         case IP_VERSION(4, 1, 0):
1237         case IP_VERSION(4, 1, 1):
1238         case IP_VERSION(4, 3, 0):
1239                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1240                 break;
1241         case IP_VERSION(4, 2, 0):
1242         case IP_VERSION(4, 2, 1):
1243         case IP_VERSION(4, 4, 0):
1244                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1245                 break;
1246         case IP_VERSION(5, 0, 0):
1247         case IP_VERSION(5, 0, 1):
1248         case IP_VERSION(5, 0, 2):
1249         case IP_VERSION(5, 0, 3):
1250         case IP_VERSION(5, 2, 0):
1251         case IP_VERSION(5, 2, 1):
1252                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1253                 break;
1254         default:
1255                 dev_err(adev->dev,
1256                         "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1257                         adev->ip_versions[OSSSYS_HWIP][0]);
1258                 return -EINVAL;
1259         }
1260         return 0;
1261 }
1262
1263 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1264 {
1265         switch (adev->ip_versions[MP0_HWIP][0]) {
1266         case IP_VERSION(9, 0, 0):
1267                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1268                 break;
1269         case IP_VERSION(10, 0, 0):
1270         case IP_VERSION(10, 0, 1):
1271                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1272                 break;
1273         case IP_VERSION(11, 0, 0):
1274         case IP_VERSION(11, 0, 2):
1275         case IP_VERSION(11, 0, 4):
1276         case IP_VERSION(11, 0, 5):
1277         case IP_VERSION(11, 0, 9):
1278         case IP_VERSION(11, 0, 7):
1279         case IP_VERSION(11, 0, 11):
1280         case IP_VERSION(11, 0, 12):
1281         case IP_VERSION(11, 0, 13):
1282         case IP_VERSION(11, 5, 0):
1283                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1284                 break;
1285         case IP_VERSION(11, 0, 8):
1286                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1287                 break;
1288         case IP_VERSION(11, 0, 3):
1289         case IP_VERSION(12, 0, 1):
1290                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1291                 break;
1292         case IP_VERSION(13, 0, 1):
1293         case IP_VERSION(13, 0, 2):
1294         case IP_VERSION(13, 0, 3):
1295         case IP_VERSION(13, 0, 8):
1296                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1297                 break;
1298         default:
1299                 dev_err(adev->dev,
1300                         "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1301                         adev->ip_versions[MP0_HWIP][0]);
1302                 return -EINVAL;
1303         }
1304         return 0;
1305 }
1306
1307 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1308 {
1309         switch (adev->ip_versions[MP1_HWIP][0]) {
1310         case IP_VERSION(9, 0, 0):
1311         case IP_VERSION(10, 0, 0):
1312         case IP_VERSION(10, 0, 1):
1313         case IP_VERSION(11, 0, 2):
1314                 if (adev->asic_type == CHIP_ARCTURUS)
1315                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1316                 else
1317                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1318                 break;
1319         case IP_VERSION(11, 0, 0):
1320         case IP_VERSION(11, 0, 5):
1321         case IP_VERSION(11, 0, 9):
1322         case IP_VERSION(11, 0, 7):
1323         case IP_VERSION(11, 0, 8):
1324         case IP_VERSION(11, 0, 11):
1325         case IP_VERSION(11, 0, 12):
1326         case IP_VERSION(11, 0, 13):
1327         case IP_VERSION(11, 5, 0):
1328                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1329                 break;
1330         case IP_VERSION(12, 0, 0):
1331         case IP_VERSION(12, 0, 1):
1332                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1333                 break;
1334         case IP_VERSION(13, 0, 1):
1335         case IP_VERSION(13, 0, 2):
1336         case IP_VERSION(13, 0, 3):
1337         case IP_VERSION(13, 0, 8):
1338                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1339                 break;
1340         default:
1341                 dev_err(adev->dev,
1342                         "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
1343                         adev->ip_versions[MP1_HWIP][0]);
1344                 return -EINVAL;
1345         }
1346         return 0;
1347 }
1348
1349 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
1350 {
1351         if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
1352                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1353                 return 0;
1354         }
1355
1356         if (!amdgpu_device_has_dc_support(adev))
1357                 return 0;
1358
1359 #if defined(CONFIG_DRM_AMD_DC)
1360         if (adev->ip_versions[DCE_HWIP][0]) {
1361                 switch (adev->ip_versions[DCE_HWIP][0]) {
1362                 case IP_VERSION(1, 0, 0):
1363                 case IP_VERSION(1, 0, 1):
1364                 case IP_VERSION(2, 0, 2):
1365                 case IP_VERSION(2, 0, 0):
1366                 case IP_VERSION(2, 0, 3):
1367                 case IP_VERSION(2, 1, 0):
1368                 case IP_VERSION(3, 0, 0):
1369                 case IP_VERSION(3, 0, 2):
1370                 case IP_VERSION(3, 0, 3):
1371                 case IP_VERSION(3, 0, 1):
1372                 case IP_VERSION(3, 1, 2):
1373                 case IP_VERSION(3, 1, 3):
1374                 case IP_VERSION(3, 1, 6):
1375                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1376                         break;
1377                 default:
1378                         dev_err(adev->dev,
1379                                 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
1380                                 adev->ip_versions[DCE_HWIP][0]);
1381                         return -EINVAL;
1382                 }
1383         } else if (adev->ip_versions[DCI_HWIP][0]) {
1384                 switch (adev->ip_versions[DCI_HWIP][0]) {
1385                 case IP_VERSION(12, 0, 0):
1386                 case IP_VERSION(12, 0, 1):
1387                 case IP_VERSION(12, 1, 0):
1388                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1389                         break;
1390                 default:
1391                         dev_err(adev->dev,
1392                                 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
1393                                 adev->ip_versions[DCI_HWIP][0]);
1394                         return -EINVAL;
1395                 }
1396         }
1397 #endif
1398         return 0;
1399 }
1400
1401 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
1402 {
1403         switch (adev->ip_versions[GC_HWIP][0]) {
1404         case IP_VERSION(9, 0, 1):
1405         case IP_VERSION(9, 1, 0):
1406         case IP_VERSION(9, 2, 1):
1407         case IP_VERSION(9, 2, 2):
1408         case IP_VERSION(9, 3, 0):
1409         case IP_VERSION(9, 4, 0):
1410         case IP_VERSION(9, 4, 1):
1411         case IP_VERSION(9, 4, 2):
1412                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1413                 break;
1414         case IP_VERSION(10, 1, 10):
1415         case IP_VERSION(10, 1, 2):
1416         case IP_VERSION(10, 1, 1):
1417         case IP_VERSION(10, 1, 3):
1418         case IP_VERSION(10, 1, 4):
1419         case IP_VERSION(10, 3, 0):
1420         case IP_VERSION(10, 3, 2):
1421         case IP_VERSION(10, 3, 1):
1422         case IP_VERSION(10, 3, 4):
1423         case IP_VERSION(10, 3, 5):
1424         case IP_VERSION(10, 3, 6):
1425         case IP_VERSION(10, 3, 3):
1426         case IP_VERSION(10, 3, 7):
1427                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1428                 break;
1429         default:
1430                 dev_err(adev->dev,
1431                         "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
1432                         adev->ip_versions[GC_HWIP][0]);
1433                 return -EINVAL;
1434         }
1435         return 0;
1436 }
1437
1438 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
1439 {
1440         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1441         case IP_VERSION(4, 0, 0):
1442         case IP_VERSION(4, 0, 1):
1443         case IP_VERSION(4, 1, 0):
1444         case IP_VERSION(4, 1, 1):
1445         case IP_VERSION(4, 1, 2):
1446         case IP_VERSION(4, 2, 0):
1447         case IP_VERSION(4, 2, 2):
1448         case IP_VERSION(4, 4, 0):
1449                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1450                 break;
1451         case IP_VERSION(5, 0, 0):
1452         case IP_VERSION(5, 0, 1):
1453         case IP_VERSION(5, 0, 2):
1454         case IP_VERSION(5, 0, 5):
1455                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
1456                 break;
1457         case IP_VERSION(5, 2, 0):
1458         case IP_VERSION(5, 2, 2):
1459         case IP_VERSION(5, 2, 4):
1460         case IP_VERSION(5, 2, 5):
1461         case IP_VERSION(5, 2, 3):
1462         case IP_VERSION(5, 2, 1):
1463         case IP_VERSION(5, 2, 7):
1464                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1465                 break;
1466         default:
1467                 dev_err(adev->dev,
1468                         "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
1469                         adev->ip_versions[SDMA0_HWIP][0]);
1470                 return -EINVAL;
1471         }
1472         return 0;
1473 }
1474
1475 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
1476 {
1477         if (adev->ip_versions[VCE_HWIP][0]) {
1478                 switch (adev->ip_versions[UVD_HWIP][0]) {
1479                 case IP_VERSION(7, 0, 0):
1480                 case IP_VERSION(7, 2, 0):
1481                         /* UVD is not supported on vega20 SR-IOV */
1482                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1483                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
1484                         break;
1485                 default:
1486                         dev_err(adev->dev,
1487                                 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
1488                                 adev->ip_versions[UVD_HWIP][0]);
1489                         return -EINVAL;
1490                 }
1491                 switch (adev->ip_versions[VCE_HWIP][0]) {
1492                 case IP_VERSION(4, 0, 0):
1493                 case IP_VERSION(4, 1, 0):
1494                         /* VCE is not supported on vega20 SR-IOV */
1495                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1496                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
1497                         break;
1498                 default:
1499                         dev_err(adev->dev,
1500                                 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
1501                                 adev->ip_versions[VCE_HWIP][0]);
1502                         return -EINVAL;
1503                 }
1504         } else {
1505                 switch (adev->ip_versions[UVD_HWIP][0]) {
1506                 case IP_VERSION(1, 0, 0):
1507                 case IP_VERSION(1, 0, 1):
1508                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1509                         break;
1510                 case IP_VERSION(2, 0, 0):
1511                 case IP_VERSION(2, 0, 2):
1512                 case IP_VERSION(2, 2, 0):
1513                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
1514                         if (!amdgpu_sriov_vf(adev))
1515                                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1516                         break;
1517                 case IP_VERSION(2, 0, 3):
1518                         break;
1519                 case IP_VERSION(2, 5, 0):
1520                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1521                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1522                         break;
1523                 case IP_VERSION(2, 6, 0):
1524                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1525                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1526                         break;
1527                 case IP_VERSION(3, 0, 0):
1528                 case IP_VERSION(3, 0, 16):
1529                 case IP_VERSION(3, 1, 1):
1530                 case IP_VERSION(3, 0, 2):
1531                 case IP_VERSION(3, 0, 192):
1532                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1533                         if (!amdgpu_sriov_vf(adev))
1534                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
1535                         break;
1536                 case IP_VERSION(3, 0, 33):
1537                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1538                         break;
1539                 default:
1540                         dev_err(adev->dev,
1541                                 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
1542                                 adev->ip_versions[UVD_HWIP][0]);
1543                         return -EINVAL;
1544                 }
1545         }
1546         return 0;
1547 }
1548
1549 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
1550 {
1551         switch (adev->ip_versions[GC_HWIP][0]) {
1552         case IP_VERSION(10, 1, 10):
1553         case IP_VERSION(10, 1, 1):
1554         case IP_VERSION(10, 1, 2):
1555         case IP_VERSION(10, 1, 3):
1556         case IP_VERSION(10, 1, 4):
1557         case IP_VERSION(10, 3, 0):
1558         case IP_VERSION(10, 3, 1):
1559         case IP_VERSION(10, 3, 2):
1560         case IP_VERSION(10, 3, 3):
1561         case IP_VERSION(10, 3, 4):
1562         case IP_VERSION(10, 3, 5):
1563         case IP_VERSION(10, 3, 6):
1564                 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
1565                 break;
1566         default:
1567                 break;
1568         }
1569         return 0;
1570 }
1571
1572 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
1573 {
1574         int r;
1575
1576         switch (adev->asic_type) {
1577         case CHIP_VEGA10:
1578                 vega10_reg_base_init(adev);
1579                 adev->sdma.num_instances = 2;
1580                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1581                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1582                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
1583                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
1584                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
1585                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
1586                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1587                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
1588                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
1589                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1590                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1591                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1592                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
1593                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
1594                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1595                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1596                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
1597                 break;
1598         case CHIP_VEGA12:
1599                 vega10_reg_base_init(adev);
1600                 adev->sdma.num_instances = 2;
1601                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1602                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1603                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
1604                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
1605                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
1606                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
1607                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
1608                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
1609                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
1610                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1611                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1612                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1613                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
1614                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
1615                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1616                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1617                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
1618                 break;
1619         case CHIP_RAVEN:
1620                 vega10_reg_base_init(adev);
1621                 adev->sdma.num_instances = 1;
1622                 adev->vcn.num_vcn_inst = 1;
1623                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1624                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1625                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1626                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
1627                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
1628                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
1629                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
1630                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
1631                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
1632                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
1633                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
1634                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
1635                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
1636                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
1637                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
1638                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
1639                 } else {
1640                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1641                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1642                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
1643                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
1644                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
1645                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1646                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
1647                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
1648                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
1649                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
1650                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
1651                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
1652                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
1653                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
1654                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
1655                 }
1656                 break;
1657         case CHIP_VEGA20:
1658                 vega20_reg_base_init(adev);
1659                 adev->sdma.num_instances = 2;
1660                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1661                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1662                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
1663                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
1664                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
1665                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
1666                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
1667                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
1668                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
1669                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
1670                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1671                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
1672                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
1673                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
1674                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
1675                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
1676                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
1677                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
1678                 break;
1679         case CHIP_ARCTURUS:
1680                 arct_reg_base_init(adev);
1681                 adev->sdma.num_instances = 8;
1682                 adev->vcn.num_vcn_inst = 2;
1683                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1684                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1685                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
1686                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
1687                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
1688                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
1689                 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
1690                 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
1691                 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
1692                 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
1693                 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
1694                 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
1695                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
1696                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
1697                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
1698                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
1699                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1700                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
1701                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
1702                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
1703                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
1704                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
1705                 break;
1706         case CHIP_ALDEBARAN:
1707                 aldebaran_reg_base_init(adev);
1708                 adev->sdma.num_instances = 5;
1709                 adev->vcn.num_vcn_inst = 2;
1710                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1711                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1712                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
1713                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
1714                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
1715                 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
1716                 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
1717                 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
1718                 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
1719                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
1720                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
1721                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
1722                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
1723                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
1724                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
1725                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
1726                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
1727                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
1728                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
1729                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
1730                 break;
1731         default:
1732                 r = amdgpu_discovery_reg_base_init(adev);
1733                 if (r)
1734                         return -EINVAL;
1735
1736                 amdgpu_discovery_harvest_ip(adev);
1737                 break;
1738         }
1739
1740         switch (adev->ip_versions[GC_HWIP][0]) {
1741         case IP_VERSION(9, 0, 1):
1742         case IP_VERSION(9, 2, 1):
1743         case IP_VERSION(9, 4, 0):
1744         case IP_VERSION(9, 4, 1):
1745         case IP_VERSION(9, 4, 2):
1746                 adev->family = AMDGPU_FAMILY_AI;
1747                 break;
1748         case IP_VERSION(9, 1, 0):
1749         case IP_VERSION(9, 2, 2):
1750         case IP_VERSION(9, 3, 0):
1751                 adev->family = AMDGPU_FAMILY_RV;
1752                 break;
1753         case IP_VERSION(10, 1, 10):
1754         case IP_VERSION(10, 1, 1):
1755         case IP_VERSION(10, 1, 2):
1756         case IP_VERSION(10, 1, 3):
1757         case IP_VERSION(10, 1, 4):
1758         case IP_VERSION(10, 3, 0):
1759         case IP_VERSION(10, 3, 2):
1760         case IP_VERSION(10, 3, 4):
1761         case IP_VERSION(10, 3, 5):
1762                 adev->family = AMDGPU_FAMILY_NV;
1763                 break;
1764         case IP_VERSION(10, 3, 1):
1765                 adev->family = AMDGPU_FAMILY_VGH;
1766                 break;
1767         case IP_VERSION(10, 3, 3):
1768                 adev->family = AMDGPU_FAMILY_YC;
1769                 break;
1770         case IP_VERSION(10, 3, 6):
1771                 adev->family = AMDGPU_FAMILY_GC_10_3_6;
1772                 break;
1773         case IP_VERSION(10, 3, 7):
1774                 adev->family = AMDGPU_FAMILY_GC_10_3_7;
1775                 break;
1776         default:
1777                 return -EINVAL;
1778         }
1779
1780         switch (adev->ip_versions[GC_HWIP][0]) {
1781         case IP_VERSION(9, 1, 0):
1782         case IP_VERSION(9, 2, 2):
1783         case IP_VERSION(9, 3, 0):
1784         case IP_VERSION(10, 1, 3):
1785         case IP_VERSION(10, 1, 4):
1786         case IP_VERSION(10, 3, 1):
1787         case IP_VERSION(10, 3, 3):
1788         case IP_VERSION(10, 3, 6):
1789         case IP_VERSION(10, 3, 7):
1790                 adev->flags |= AMD_IS_APU;
1791                 break;
1792         default:
1793                 break;
1794         }
1795
1796         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
1797                 adev->gmc.xgmi.supported = true;
1798
1799         /* set NBIO version */
1800         switch (adev->ip_versions[NBIO_HWIP][0]) {
1801         case IP_VERSION(6, 1, 0):
1802         case IP_VERSION(6, 2, 0):
1803                 adev->nbio.funcs = &nbio_v6_1_funcs;
1804                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
1805                 break;
1806         case IP_VERSION(7, 0, 0):
1807         case IP_VERSION(7, 0, 1):
1808         case IP_VERSION(2, 5, 0):
1809                 adev->nbio.funcs = &nbio_v7_0_funcs;
1810                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
1811                 break;
1812         case IP_VERSION(7, 4, 0):
1813         case IP_VERSION(7, 4, 1):
1814                 adev->nbio.funcs = &nbio_v7_4_funcs;
1815                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
1816                 break;
1817         case IP_VERSION(7, 4, 4):
1818                 adev->nbio.funcs = &nbio_v7_4_funcs;
1819                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
1820                 break;
1821         case IP_VERSION(7, 2, 0):
1822         case IP_VERSION(7, 2, 1):
1823         case IP_VERSION(7, 5, 0):
1824         case IP_VERSION(7, 5, 1):
1825                 adev->nbio.funcs = &nbio_v7_2_funcs;
1826                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
1827                 break;
1828         case IP_VERSION(2, 1, 1):
1829         case IP_VERSION(2, 3, 0):
1830         case IP_VERSION(2, 3, 1):
1831         case IP_VERSION(2, 3, 2):
1832                 adev->nbio.funcs = &nbio_v2_3_funcs;
1833                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
1834                 break;
1835         case IP_VERSION(3, 3, 0):
1836         case IP_VERSION(3, 3, 1):
1837         case IP_VERSION(3, 3, 2):
1838         case IP_VERSION(3, 3, 3):
1839                 adev->nbio.funcs = &nbio_v2_3_funcs;
1840                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
1841                 break;
1842         default:
1843                 break;
1844         }
1845
1846         switch (adev->ip_versions[HDP_HWIP][0]) {
1847         case IP_VERSION(4, 0, 0):
1848         case IP_VERSION(4, 0, 1):
1849         case IP_VERSION(4, 1, 0):
1850         case IP_VERSION(4, 1, 1):
1851         case IP_VERSION(4, 1, 2):
1852         case IP_VERSION(4, 2, 0):
1853         case IP_VERSION(4, 2, 1):
1854         case IP_VERSION(4, 4, 0):
1855                 adev->hdp.funcs = &hdp_v4_0_funcs;
1856                 break;
1857         case IP_VERSION(5, 0, 0):
1858         case IP_VERSION(5, 0, 1):
1859         case IP_VERSION(5, 0, 2):
1860         case IP_VERSION(5, 0, 3):
1861         case IP_VERSION(5, 0, 4):
1862         case IP_VERSION(5, 2, 0):
1863                 adev->hdp.funcs = &hdp_v5_0_funcs;
1864                 break;
1865         default:
1866                 break;
1867         }
1868
1869         switch (adev->ip_versions[DF_HWIP][0]) {
1870         case IP_VERSION(3, 6, 0):
1871         case IP_VERSION(3, 6, 1):
1872         case IP_VERSION(3, 6, 2):
1873                 adev->df.funcs = &df_v3_6_funcs;
1874                 break;
1875         case IP_VERSION(2, 1, 0):
1876         case IP_VERSION(2, 1, 1):
1877         case IP_VERSION(2, 5, 0):
1878         case IP_VERSION(3, 5, 1):
1879         case IP_VERSION(3, 5, 2):
1880                 adev->df.funcs = &df_v1_7_funcs;
1881                 break;
1882         default:
1883                 break;
1884         }
1885
1886         switch (adev->ip_versions[SMUIO_HWIP][0]) {
1887         case IP_VERSION(9, 0, 0):
1888         case IP_VERSION(9, 0, 1):
1889         case IP_VERSION(10, 0, 0):
1890         case IP_VERSION(10, 0, 1):
1891         case IP_VERSION(10, 0, 2):
1892                 adev->smuio.funcs = &smuio_v9_0_funcs;
1893                 break;
1894         case IP_VERSION(11, 0, 0):
1895         case IP_VERSION(11, 0, 2):
1896         case IP_VERSION(11, 0, 3):
1897         case IP_VERSION(11, 0, 4):
1898         case IP_VERSION(11, 0, 7):
1899         case IP_VERSION(11, 0, 8):
1900                 adev->smuio.funcs = &smuio_v11_0_funcs;
1901                 break;
1902         case IP_VERSION(11, 0, 6):
1903         case IP_VERSION(11, 0, 10):
1904         case IP_VERSION(11, 0, 11):
1905         case IP_VERSION(11, 5, 0):
1906         case IP_VERSION(13, 0, 1):
1907         case IP_VERSION(13, 0, 9):
1908                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
1909                 break;
1910         case IP_VERSION(13, 0, 2):
1911                 adev->smuio.funcs = &smuio_v13_0_funcs;
1912                 break;
1913         default:
1914                 break;
1915         }
1916
1917         r = amdgpu_discovery_set_common_ip_blocks(adev);
1918         if (r)
1919                 return r;
1920
1921         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
1922         if (r)
1923                 return r;
1924
1925         /* For SR-IOV, PSP needs to be initialized before IH */
1926         if (amdgpu_sriov_vf(adev)) {
1927                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
1928                 if (r)
1929                         return r;
1930                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1931                 if (r)
1932                         return r;
1933         } else {
1934                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1935                 if (r)
1936                         return r;
1937
1938                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1939                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
1940                         if (r)
1941                                 return r;
1942                 }
1943         }
1944
1945         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1946                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1947                 if (r)
1948                         return r;
1949         }
1950
1951         r = amdgpu_discovery_set_display_ip_blocks(adev);
1952         if (r)
1953                 return r;
1954
1955         r = amdgpu_discovery_set_gc_ip_blocks(adev);
1956         if (r)
1957                 return r;
1958
1959         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
1960         if (r)
1961                 return r;
1962
1963         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
1964             !amdgpu_sriov_vf(adev)) {
1965                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1966                 if (r)
1967                         return r;
1968         }
1969
1970         r = amdgpu_discovery_set_mm_ip_blocks(adev);
1971         if (r)
1972                 return r;
1973
1974         if (adev->enable_mes) {
1975                 r = amdgpu_discovery_set_mes_ip_blocks(adev);
1976                 if (r)
1977                         return r;
1978         }
1979
1980         return 0;
1981 }
1982