2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_discovery.h"
28 #include "soc15_hw_ip.h"
29 #include "discovery.h"
36 #include "nbio_v6_1.h"
37 #include "nbio_v7_0.h"
38 #include "nbio_v7_4.h"
40 #include "vega10_ih.h"
41 #include "vega20_ih.h"
42 #include "sdma_v4_0.h"
47 #include "jpeg_v2_5.h"
48 #include "smuio_v9_0.h"
49 #include "gmc_v10_0.h"
50 #include "gfxhub_v2_0.h"
51 #include "mmhub_v2_0.h"
52 #include "nbio_v2_3.h"
53 #include "nbio_v7_2.h"
56 #include "navi10_ih.h"
57 #include "gfx_v10_0.h"
58 #include "sdma_v5_0.h"
59 #include "sdma_v5_2.h"
61 #include "jpeg_v2_0.h"
63 #include "jpeg_v3_0.h"
64 #include "amdgpu_vkms.h"
65 #include "mes_v10_1.h"
66 #include "smuio_v11_0.h"
67 #include "smuio_v11_0_6.h"
68 #include "smuio_v13_0.h"
70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
73 #define mmRCC_CONFIG_MEMSIZE 0xde3
74 #define mmMM_INDEX 0x0
75 #define mmMM_INDEX_HI 0x6
78 static const char *hw_id_names[HW_ID_MAX] = {
82 [SMUIO_HWID] = "SMUIO",
88 [AUDIO_AZ_HWID] = "AUDIO_AZ",
95 [DCEAZ_HWID] = "DCEAZ",
97 [SDPMUX_HWID] = "SDPMUX",
100 [L2IMU_HWID] = "L2IMU",
102 [MMHUB_HWID] = "MMHUB",
103 [ATHUB_HWID] = "ATHUB",
104 [DBGU_NBIO_HWID] = "DBGU_NBIO",
106 [DBGU0_HWID] = "DBGU0",
107 [DBGU1_HWID] = "DBGU1",
108 [OSSSYS_HWID] = "OSSSYS",
110 [SDMA0_HWID] = "SDMA0",
111 [SDMA1_HWID] = "SDMA1",
112 [SDMA2_HWID] = "SDMA2",
113 [SDMA3_HWID] = "SDMA3",
115 [DBGU_IO_HWID] = "DBGU_IO",
117 [CLKB_HWID] = "CLKB",
119 [DFX_DAP_HWID] = "DFX_DAP",
120 [L1IMU_PCIE_HWID] = "L1IMU_PCIE",
121 [L1IMU_NBIF_HWID] = "L1IMU_NBIF",
122 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
123 [L1IMU3_HWID] = "L1IMU3",
124 [L1IMU4_HWID] = "L1IMU4",
125 [L1IMU5_HWID] = "L1IMU5",
126 [L1IMU6_HWID] = "L1IMU6",
127 [L1IMU7_HWID] = "L1IMU7",
128 [L1IMU8_HWID] = "L1IMU8",
129 [L1IMU9_HWID] = "L1IMU9",
130 [L1IMU10_HWID] = "L1IMU10",
131 [L1IMU11_HWID] = "L1IMU11",
132 [L1IMU12_HWID] = "L1IMU12",
133 [L1IMU13_HWID] = "L1IMU13",
134 [L1IMU14_HWID] = "L1IMU14",
135 [L1IMU15_HWID] = "L1IMU15",
136 [WAFLC_HWID] = "WAFLC",
137 [FCH_USB_PD_HWID] = "FCH_USB_PD",
138 [PCIE_HWID] = "PCIE",
140 [DDCL_HWID] = "DDCL",
142 [IOAGR_HWID] = "IOAGR",
143 [NBIF_HWID] = "NBIF",
144 [IOAPIC_HWID] = "IOAPIC",
145 [SYSTEMHUB_HWID] = "SYSTEMHUB",
146 [NTBCCP_HWID] = "NTBCCP",
148 [SATA_HWID] = "SATA",
150 [CCXSEC_HWID] = "CCXSEC",
151 [XGMI_HWID] = "XGMI",
152 [XGBE_HWID] = "XGBE",
156 static int hw_id_map[MAX_HWIP] = {
158 [HDP_HWIP] = HDP_HWID,
159 [SDMA0_HWIP] = SDMA0_HWID,
160 [SDMA1_HWIP] = SDMA1_HWID,
161 [SDMA2_HWIP] = SDMA2_HWID,
162 [SDMA3_HWIP] = SDMA3_HWID,
163 [MMHUB_HWIP] = MMHUB_HWID,
164 [ATHUB_HWIP] = ATHUB_HWID,
165 [NBIO_HWIP] = NBIF_HWID,
166 [MP0_HWIP] = MP0_HWID,
167 [MP1_HWIP] = MP1_HWID,
168 [UVD_HWIP] = UVD_HWID,
169 [VCE_HWIP] = VCE_HWID,
171 [DCE_HWIP] = DMU_HWID,
172 [OSSSYS_HWIP] = OSSSYS_HWID,
173 [SMUIO_HWIP] = SMUIO_HWID,
174 [PWR_HWIP] = PWR_HWID,
175 [NBIF_HWIP] = NBIF_HWID,
176 [THM_HWIP] = THM_HWID,
177 [CLK_HWIP] = CLKA_HWID,
178 [UMC_HWIP] = UMC_HWID,
179 [XGMI_HWIP] = XGMI_HWID,
180 [DCI_HWIP] = DCI_HWID,
183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
185 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
186 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
188 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
189 adev->mman.discovery_tmr_size, false);
193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
195 const struct firmware *fw;
199 switch (amdgpu_discovery) {
201 fw_name = FIRMWARE_IP_DISCOVERY;
204 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
208 r = request_firmware(&fw, fw_name, adev->dev);
210 dev_err(adev->dev, "can't load firmware \"%s\"\n",
215 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
216 release_firmware(fw);
221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
223 uint16_t checksum = 0;
226 for (i = 0; i < size; i++)
232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
235 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
240 struct binary_header *bhdr;
241 bhdr = (struct binary_header *)binary;
243 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
246 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
249 * So far, apply this quirk only on those Navy Flounder boards which
250 * have a bad harvest table of VCN config.
252 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
253 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
254 switch (adev->pdev->revision) {
262 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
270 static int amdgpu_discovery_init(struct amdgpu_device *adev)
272 struct table_info *info;
273 struct binary_header *bhdr;
274 struct ip_discovery_header *ihdr;
275 struct gpu_info_header *ghdr;
281 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
282 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
283 if (!adev->mman.discovery_bin)
286 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin);
288 dev_err(adev->dev, "failed to read ip discovery binary from vram\n");
293 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
294 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n");
295 /* retry read ip discovery binary from file */
296 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
298 dev_err(adev->dev, "failed to read ip discovery binary from file\n");
302 /* check the ip discovery binary signature */
303 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
304 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n");
310 bhdr = (struct binary_header *)adev->mman.discovery_bin;
312 offset = offsetof(struct binary_header, binary_checksum) +
313 sizeof(bhdr->binary_checksum);
314 size = le16_to_cpu(bhdr->binary_size) - offset;
315 checksum = le16_to_cpu(bhdr->binary_checksum);
317 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
319 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
324 info = &bhdr->table_list[IP_DISCOVERY];
325 offset = le16_to_cpu(info->offset);
326 checksum = le16_to_cpu(info->checksum);
327 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
329 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
330 dev_err(adev->dev, "invalid ip discovery data table signature\n");
335 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
336 le16_to_cpu(ihdr->size), checksum)) {
337 dev_err(adev->dev, "invalid ip discovery data table checksum\n");
342 info = &bhdr->table_list[GC];
343 offset = le16_to_cpu(info->offset);
344 checksum = le16_to_cpu(info->checksum);
345 ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
347 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
348 le32_to_cpu(ghdr->size), checksum)) {
349 dev_err(adev->dev, "invalid gc data table checksum\n");
357 kfree(adev->mman.discovery_bin);
358 adev->mman.discovery_bin = NULL;
363 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
365 void amdgpu_discovery_fini(struct amdgpu_device *adev)
367 amdgpu_discovery_sysfs_fini(adev);
368 kfree(adev->mman.discovery_bin);
369 adev->mman.discovery_bin = NULL;
372 static int amdgpu_discovery_validate_ip(const struct ip *ip)
374 if (ip->number_instance >= HWIP_MAX_INSTANCE) {
375 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
376 ip->number_instance);
379 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
380 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
381 le16_to_cpu(ip->hw_id));
388 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
389 uint32_t *vcn_harvest_count)
391 struct binary_header *bhdr;
392 struct ip_discovery_header *ihdr;
393 struct die_header *dhdr;
395 uint16_t die_offset, ip_offset, num_dies, num_ips;
398 bhdr = (struct binary_header *)adev->mman.discovery_bin;
399 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
400 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
401 num_dies = le16_to_cpu(ihdr->num_dies);
403 /* scan harvest bit of all IP data structures */
404 for (i = 0; i < num_dies; i++) {
405 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
406 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
407 num_ips = le16_to_cpu(dhdr->num_ips);
408 ip_offset = die_offset + sizeof(*dhdr);
410 for (j = 0; j < num_ips; j++) {
411 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
413 if (amdgpu_discovery_validate_ip(ip))
416 if (le16_to_cpu(ip->harvest) == 1) {
417 switch (le16_to_cpu(ip->hw_id)) {
419 (*vcn_harvest_count)++;
420 if (ip->number_instance == 0)
421 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
423 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
426 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
433 ip_offset += struct_size(ip, base_address, ip->num_base_address);
438 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
439 uint32_t *vcn_harvest_count,
440 uint32_t *umc_harvest_count)
442 struct binary_header *bhdr;
443 struct harvest_table *harvest_info;
446 bhdr = (struct binary_header *)adev->mman.discovery_bin;
447 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
448 le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
449 for (i = 0; i < 32; i++) {
450 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
453 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
455 (*vcn_harvest_count)++;
456 if (harvest_info->list[i].number_instance == 0)
457 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
459 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
462 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
465 (*umc_harvest_count)++;
473 /* ================================================== */
475 struct ip_hw_instance {
476 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
480 u8 major, minor, revision;
483 int num_base_addresses;
488 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
492 struct ip_die_entry {
493 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */
497 /* -------------------------------------------------- */
499 struct ip_hw_instance_attr {
500 struct attribute attr;
501 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
504 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
506 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
509 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
511 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
514 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
516 return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
519 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
521 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
524 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
526 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
529 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
531 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
534 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
536 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
539 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
544 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
545 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
547 if (at + 12 > PAGE_SIZE)
549 res = sysfs_emit_at(buf, at, "0x%08X\n",
550 ip_hw_instance->base_addr[ii]);
556 return res < 0 ? res : at;
559 static struct ip_hw_instance_attr ip_hw_attr[] = {
561 __ATTR_RO(num_instance),
566 __ATTR_RO(num_base_addresses),
567 __ATTR_RO(base_addr),
570 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
571 ATTRIBUTE_GROUPS(ip_hw_instance);
573 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
574 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
576 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
577 struct attribute *attr,
580 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
581 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
583 if (!ip_hw_attr->show)
586 return ip_hw_attr->show(ip_hw_instance, buf);
589 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
590 .show = ip_hw_instance_attr_show,
593 static void ip_hw_instance_release(struct kobject *kobj)
595 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
597 kfree(ip_hw_instance);
600 static struct kobj_type ip_hw_instance_ktype = {
601 .release = ip_hw_instance_release,
602 .sysfs_ops = &ip_hw_instance_sysfs_ops,
603 .default_groups = ip_hw_instance_groups,
606 /* -------------------------------------------------- */
608 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
610 static void ip_hw_id_release(struct kobject *kobj)
612 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
614 if (!list_empty(&ip_hw_id->hw_id_kset.list))
615 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
619 static struct kobj_type ip_hw_id_ktype = {
620 .release = ip_hw_id_release,
621 .sysfs_ops = &kobj_sysfs_ops,
624 /* -------------------------------------------------- */
626 static void die_kobj_release(struct kobject *kobj);
627 static void ip_disc_release(struct kobject *kobj);
629 struct ip_die_entry_attribute {
630 struct attribute attr;
631 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
634 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr)
636 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
638 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
641 /* If there are more ip_die_entry attrs, other than the number of IPs,
642 * we can make this intro an array of attrs, and then initialize
643 * ip_die_entry_attrs in a loop.
645 static struct ip_die_entry_attribute num_ips_attr =
648 static struct attribute *ip_die_entry_attrs[] = {
652 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
654 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
656 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
657 struct attribute *attr,
660 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
661 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
663 if (!ip_die_entry_attr->show)
666 return ip_die_entry_attr->show(ip_die_entry, buf);
669 static void ip_die_entry_release(struct kobject *kobj)
671 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
673 if (!list_empty(&ip_die_entry->ip_kset.list))
674 DRM_ERROR("ip_die_entry->ip_kset is not empty");
678 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
679 .show = ip_die_entry_attr_show,
682 static struct kobj_type ip_die_entry_ktype = {
683 .release = ip_die_entry_release,
684 .sysfs_ops = &ip_die_entry_sysfs_ops,
685 .default_groups = ip_die_entry_groups,
688 static struct kobj_type die_kobj_ktype = {
689 .release = die_kobj_release,
690 .sysfs_ops = &kobj_sysfs_ops,
693 static struct kobj_type ip_discovery_ktype = {
694 .release = ip_disc_release,
695 .sysfs_ops = &kobj_sysfs_ops,
698 struct ip_discovery_top {
699 struct kobject kobj; /* ip_discovery/ */
700 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */
701 struct amdgpu_device *adev;
704 static void die_kobj_release(struct kobject *kobj)
706 struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
707 struct ip_discovery_top,
709 if (!list_empty(&ip_top->die_kset.list))
710 DRM_ERROR("ip_top->die_kset is not empty");
713 static void ip_disc_release(struct kobject *kobj)
715 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
717 struct amdgpu_device *adev = ip_top->adev;
723 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
724 struct ip_die_entry *ip_die_entry,
725 const size_t _ip_offset, const int num_ips)
729 DRM_DEBUG("num_ips:%d", num_ips);
731 /* Find all IPs of a given HW ID, and add their instance to
732 * #die/#hw_id/#instance/<attributes>
734 for (ii = 0; ii < HW_ID_MAX; ii++) {
735 struct ip_hw_id *ip_hw_id = NULL;
736 size_t ip_offset = _ip_offset;
738 for (jj = 0; jj < num_ips; jj++) {
740 struct ip_hw_instance *ip_hw_instance;
742 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
743 if (amdgpu_discovery_validate_ip(ip) ||
744 le16_to_cpu(ip->hw_id) != ii)
747 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
749 /* We have a hw_id match; register the hw
750 * block if not yet registered.
753 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
756 ip_hw_id->hw_id = ii;
758 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
759 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
760 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
761 res = kset_register(&ip_hw_id->hw_id_kset);
763 DRM_ERROR("Couldn't register ip_hw_id kset");
767 if (hw_id_names[ii]) {
768 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
769 &ip_hw_id->hw_id_kset.kobj,
772 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
774 kobject_name(&ip_die_entry->ip_kset.kobj));
779 /* Now register its instance.
781 ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
783 ip->num_base_address),
785 if (!ip_hw_instance) {
786 DRM_ERROR("no memory for ip_hw_instance");
789 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
790 ip_hw_instance->num_instance = ip->number_instance;
791 ip_hw_instance->major = ip->major;
792 ip_hw_instance->minor = ip->minor;
793 ip_hw_instance->revision = ip->revision;
794 ip_hw_instance->harvest = ip->harvest;
795 ip_hw_instance->num_base_addresses = ip->num_base_address;
797 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++)
798 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
800 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
801 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
802 res = kobject_add(&ip_hw_instance->kobj, NULL,
803 "%d", ip_hw_instance->num_instance);
805 ip_offset += struct_size(ip, base_address, ip->num_base_address);
812 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
814 struct binary_header *bhdr;
815 struct ip_discovery_header *ihdr;
816 struct die_header *dhdr;
817 struct kset *die_kset = &adev->ip_top->die_kset;
818 u16 num_dies, die_offset, num_ips;
822 bhdr = (struct binary_header *)adev->mman.discovery_bin;
823 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
824 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
825 num_dies = le16_to_cpu(ihdr->num_dies);
827 DRM_DEBUG("number of dies: %d\n", num_dies);
829 for (ii = 0; ii < num_dies; ii++) {
830 struct ip_die_entry *ip_die_entry;
832 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
833 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
834 num_ips = le16_to_cpu(dhdr->num_ips);
835 ip_offset = die_offset + sizeof(*dhdr);
837 /* Add the die to the kset.
839 * dhdr->die_id == ii, which was checked in
840 * amdgpu_discovery_reg_base_init().
843 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
847 ip_die_entry->num_ips = num_ips;
849 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
850 ip_die_entry->ip_kset.kobj.kset = die_kset;
851 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
852 res = kset_register(&ip_die_entry->ip_kset);
854 DRM_ERROR("Couldn't register ip_die_entry kset");
859 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips);
865 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
867 struct kset *die_kset;
870 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
874 adev->ip_top->adev = adev;
876 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
877 &adev->dev->kobj, "ip_discovery");
879 DRM_ERROR("Couldn't init and add ip_discovery/");
883 die_kset = &adev->ip_top->die_kset;
884 kobject_set_name(&die_kset->kobj, "%s", "die");
885 die_kset->kobj.parent = &adev->ip_top->kobj;
886 die_kset->kobj.ktype = &die_kobj_ktype;
887 res = kset_register(&adev->ip_top->die_kset);
889 DRM_ERROR("Couldn't register die_kset");
893 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
894 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
895 ip_hw_instance_attrs[ii] = NULL;
897 res = amdgpu_discovery_sysfs_recurse(adev);
901 kobject_put(&adev->ip_top->kobj);
905 /* -------------------------------------------------- */
907 #define list_to_kobj(el) container_of(el, struct kobject, entry)
909 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
911 struct list_head *el, *tmp;
912 struct kset *hw_id_kset;
914 hw_id_kset = &ip_hw_id->hw_id_kset;
915 spin_lock(&hw_id_kset->list_lock);
916 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
918 spin_unlock(&hw_id_kset->list_lock);
919 /* kobject is embedded in ip_hw_instance */
920 kobject_put(list_to_kobj(el));
921 spin_lock(&hw_id_kset->list_lock);
923 spin_unlock(&hw_id_kset->list_lock);
924 kobject_put(&ip_hw_id->hw_id_kset.kobj);
927 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
929 struct list_head *el, *tmp;
930 struct kset *ip_kset;
932 ip_kset = &ip_die_entry->ip_kset;
933 spin_lock(&ip_kset->list_lock);
934 list_for_each_prev_safe(el, tmp, &ip_kset->list) {
936 spin_unlock(&ip_kset->list_lock);
937 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
938 spin_lock(&ip_kset->list_lock);
940 spin_unlock(&ip_kset->list_lock);
941 kobject_put(&ip_die_entry->ip_kset.kobj);
944 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
946 struct list_head *el, *tmp;
947 struct kset *die_kset;
949 die_kset = &adev->ip_top->die_kset;
950 spin_lock(&die_kset->list_lock);
951 list_for_each_prev_safe(el, tmp, &die_kset->list) {
953 spin_unlock(&die_kset->list_lock);
954 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
955 spin_lock(&die_kset->list_lock);
957 spin_unlock(&die_kset->list_lock);
958 kobject_put(&adev->ip_top->die_kset.kobj);
959 kobject_put(&adev->ip_top->kobj);
962 /* ================================================== */
964 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
966 struct binary_header *bhdr;
967 struct ip_discovery_header *ihdr;
968 struct die_header *dhdr;
974 uint8_t num_base_address;
979 r = amdgpu_discovery_init(adev);
981 DRM_ERROR("amdgpu_discovery_init failed\n");
985 bhdr = (struct binary_header *)adev->mman.discovery_bin;
986 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
987 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
988 num_dies = le16_to_cpu(ihdr->num_dies);
990 DRM_DEBUG("number of dies: %d\n", num_dies);
992 for (i = 0; i < num_dies; i++) {
993 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
994 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
995 num_ips = le16_to_cpu(dhdr->num_ips);
996 ip_offset = die_offset + sizeof(*dhdr);
998 if (le16_to_cpu(dhdr->die_id) != i) {
999 DRM_ERROR("invalid die id %d, expected %d\n",
1000 le16_to_cpu(dhdr->die_id), i);
1004 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1005 le16_to_cpu(dhdr->die_id), num_ips);
1007 for (j = 0; j < num_ips; j++) {
1008 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1010 if (amdgpu_discovery_validate_ip(ip))
1013 num_base_address = ip->num_base_address;
1015 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1016 hw_id_names[le16_to_cpu(ip->hw_id)],
1017 le16_to_cpu(ip->hw_id),
1018 ip->number_instance,
1019 ip->major, ip->minor,
1022 if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1023 /* Bit [5:0]: original revision value
1024 * Bit [7:6]: en/decode capability:
1025 * 0b00 : VCN function normally
1026 * 0b10 : encode is disabled
1027 * 0b01 : decode is disabled
1029 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
1030 ip->revision & 0xc0;
1031 ip->revision &= ~0xc0;
1032 adev->vcn.num_vcn_inst++;
1034 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1035 le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1036 le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1037 le16_to_cpu(ip->hw_id) == SDMA3_HWID)
1038 adev->sdma.num_instances++;
1040 if (le16_to_cpu(ip->hw_id) == UMC_HWID)
1041 adev->gmc.num_umc++;
1043 for (k = 0; k < num_base_address; k++) {
1045 * convert the endianness of base addresses in place,
1046 * so that we don't need to convert them when accessing adev->reg_offset.
1048 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1049 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1052 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1053 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
1054 DRM_DEBUG("set register base offset for %s\n",
1055 hw_id_names[le16_to_cpu(ip->hw_id)]);
1056 adev->reg_offset[hw_ip][ip->number_instance] =
1058 /* Instance support is somewhat inconsistent.
1059 * SDMA is a good example. Sienna cichlid has 4 total
1060 * SDMA instances, each enumerated separately (HWIDs
1061 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances,
1062 * but they are enumerated as multiple instances of the
1063 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another
1064 * example. On most chips there are multiple instances
1065 * with the same HWID.
1067 adev->ip_versions[hw_ip][ip->number_instance] =
1068 IP_VERSION(ip->major, ip->minor, ip->revision);
1073 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1077 amdgpu_discovery_sysfs_init(adev);
1082 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
1083 int *major, int *minor, int *revision)
1085 struct binary_header *bhdr;
1086 struct ip_discovery_header *ihdr;
1087 struct die_header *dhdr;
1089 uint16_t die_offset;
1095 if (!adev->mman.discovery_bin) {
1096 DRM_ERROR("ip discovery uninitialized\n");
1100 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1101 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1102 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1103 num_dies = le16_to_cpu(ihdr->num_dies);
1105 for (i = 0; i < num_dies; i++) {
1106 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1107 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1108 num_ips = le16_to_cpu(dhdr->num_ips);
1109 ip_offset = die_offset + sizeof(*dhdr);
1111 for (j = 0; j < num_ips; j++) {
1112 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1114 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
1120 *revision = ip->revision;
1123 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1130 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1132 int vcn_harvest_count = 0;
1133 int umc_harvest_count = 0;
1136 * Harvest table does not fit Navi1x and legacy GPUs,
1137 * so read harvest bit per IP data structure to set
1138 * harvest configuration.
1140 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
1141 if ((adev->pdev->device == 0x731E &&
1142 (adev->pdev->revision == 0xC6 ||
1143 adev->pdev->revision == 0xC7)) ||
1144 (adev->pdev->device == 0x7340 &&
1145 adev->pdev->revision == 0xC9) ||
1146 (adev->pdev->device == 0x7360 &&
1147 adev->pdev->revision == 0xC7))
1148 amdgpu_discovery_read_harvest_bit_per_ip(adev,
1149 &vcn_harvest_count);
1151 amdgpu_discovery_read_from_harvest_table(adev,
1153 &umc_harvest_count);
1156 amdgpu_discovery_harvest_config_quirk(adev);
1158 if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1159 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1160 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1163 if (umc_harvest_count < adev->gmc.num_umc) {
1164 adev->gmc.num_umc -= umc_harvest_count;
1169 struct gc_info_v1_0 v1;
1170 struct gc_info_v1_1 v1_1;
1171 struct gc_info_v1_2 v1_2;
1172 struct gc_info_v2_0 v2;
1175 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1177 struct binary_header *bhdr;
1178 union gc_info *gc_info;
1180 if (!adev->mman.discovery_bin) {
1181 DRM_ERROR("ip discovery uninitialized\n");
1185 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1186 gc_info = (union gc_info *)(adev->mman.discovery_bin +
1187 le16_to_cpu(bhdr->table_list[GC].offset));
1188 switch (le16_to_cpu(gc_info->v1.header.version_major)) {
1190 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1191 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1192 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1193 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1194 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1195 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1196 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1197 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1198 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1199 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1200 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1201 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1202 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1203 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1204 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1205 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1206 le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1207 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1208 if (gc_info->v1.header.version_minor >= 1) {
1209 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
1210 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
1211 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
1213 if (gc_info->v1.header.version_minor >= 2) {
1214 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
1215 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
1216 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
1217 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
1218 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
1219 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1220 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1221 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1225 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1226 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1227 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1228 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1229 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1230 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1231 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1232 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1233 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1234 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1235 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1236 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1237 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1238 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1239 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1240 le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1241 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1245 "Unhandled GC info table %d.%d\n",
1246 le16_to_cpu(gc_info->v1.header.version_major),
1247 le16_to_cpu(gc_info->v1.header.version_minor));
1253 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1255 /* what IP to use for this? */
1256 switch (adev->ip_versions[GC_HWIP][0]) {
1257 case IP_VERSION(9, 0, 1):
1258 case IP_VERSION(9, 1, 0):
1259 case IP_VERSION(9, 2, 1):
1260 case IP_VERSION(9, 2, 2):
1261 case IP_VERSION(9, 3, 0):
1262 case IP_VERSION(9, 4, 0):
1263 case IP_VERSION(9, 4, 1):
1264 case IP_VERSION(9, 4, 2):
1265 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1267 case IP_VERSION(10, 1, 10):
1268 case IP_VERSION(10, 1, 1):
1269 case IP_VERSION(10, 1, 2):
1270 case IP_VERSION(10, 1, 3):
1271 case IP_VERSION(10, 1, 4):
1272 case IP_VERSION(10, 3, 0):
1273 case IP_VERSION(10, 3, 1):
1274 case IP_VERSION(10, 3, 2):
1275 case IP_VERSION(10, 3, 3):
1276 case IP_VERSION(10, 3, 4):
1277 case IP_VERSION(10, 3, 5):
1278 case IP_VERSION(10, 3, 6):
1279 case IP_VERSION(10, 3, 7):
1280 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1284 "Failed to add common ip block(GC_HWIP:0x%x)\n",
1285 adev->ip_versions[GC_HWIP][0]);
1291 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1293 /* use GC or MMHUB IP version */
1294 switch (adev->ip_versions[GC_HWIP][0]) {
1295 case IP_VERSION(9, 0, 1):
1296 case IP_VERSION(9, 1, 0):
1297 case IP_VERSION(9, 2, 1):
1298 case IP_VERSION(9, 2, 2):
1299 case IP_VERSION(9, 3, 0):
1300 case IP_VERSION(9, 4, 0):
1301 case IP_VERSION(9, 4, 1):
1302 case IP_VERSION(9, 4, 2):
1303 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1305 case IP_VERSION(10, 1, 10):
1306 case IP_VERSION(10, 1, 1):
1307 case IP_VERSION(10, 1, 2):
1308 case IP_VERSION(10, 1, 3):
1309 case IP_VERSION(10, 1, 4):
1310 case IP_VERSION(10, 3, 0):
1311 case IP_VERSION(10, 3, 1):
1312 case IP_VERSION(10, 3, 2):
1313 case IP_VERSION(10, 3, 3):
1314 case IP_VERSION(10, 3, 4):
1315 case IP_VERSION(10, 3, 5):
1316 case IP_VERSION(10, 3, 6):
1317 case IP_VERSION(10, 3, 7):
1318 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1322 "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1323 adev->ip_versions[GC_HWIP][0]);
1329 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1331 switch (adev->ip_versions[OSSSYS_HWIP][0]) {
1332 case IP_VERSION(4, 0, 0):
1333 case IP_VERSION(4, 0, 1):
1334 case IP_VERSION(4, 1, 0):
1335 case IP_VERSION(4, 1, 1):
1336 case IP_VERSION(4, 3, 0):
1337 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1339 case IP_VERSION(4, 2, 0):
1340 case IP_VERSION(4, 2, 1):
1341 case IP_VERSION(4, 4, 0):
1342 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1344 case IP_VERSION(5, 0, 0):
1345 case IP_VERSION(5, 0, 1):
1346 case IP_VERSION(5, 0, 2):
1347 case IP_VERSION(5, 0, 3):
1348 case IP_VERSION(5, 2, 0):
1349 case IP_VERSION(5, 2, 1):
1350 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1354 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1355 adev->ip_versions[OSSSYS_HWIP][0]);
1361 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1363 switch (adev->ip_versions[MP0_HWIP][0]) {
1364 case IP_VERSION(9, 0, 0):
1365 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1367 case IP_VERSION(10, 0, 0):
1368 case IP_VERSION(10, 0, 1):
1369 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1371 case IP_VERSION(11, 0, 0):
1372 case IP_VERSION(11, 0, 2):
1373 case IP_VERSION(11, 0, 4):
1374 case IP_VERSION(11, 0, 5):
1375 case IP_VERSION(11, 0, 9):
1376 case IP_VERSION(11, 0, 7):
1377 case IP_VERSION(11, 0, 11):
1378 case IP_VERSION(11, 0, 12):
1379 case IP_VERSION(11, 0, 13):
1380 case IP_VERSION(11, 5, 0):
1381 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1383 case IP_VERSION(11, 0, 8):
1384 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1386 case IP_VERSION(11, 0, 3):
1387 case IP_VERSION(12, 0, 1):
1388 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1390 case IP_VERSION(13, 0, 1):
1391 case IP_VERSION(13, 0, 2):
1392 case IP_VERSION(13, 0, 3):
1393 case IP_VERSION(13, 0, 5):
1394 case IP_VERSION(13, 0, 8):
1395 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1399 "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1400 adev->ip_versions[MP0_HWIP][0]);
1406 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1408 switch (adev->ip_versions[MP1_HWIP][0]) {
1409 case IP_VERSION(9, 0, 0):
1410 case IP_VERSION(10, 0, 0):
1411 case IP_VERSION(10, 0, 1):
1412 case IP_VERSION(11, 0, 2):
1413 if (adev->asic_type == CHIP_ARCTURUS)
1414 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1416 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1418 case IP_VERSION(11, 0, 0):
1419 case IP_VERSION(11, 0, 5):
1420 case IP_VERSION(11, 0, 9):
1421 case IP_VERSION(11, 0, 7):
1422 case IP_VERSION(11, 0, 8):
1423 case IP_VERSION(11, 0, 11):
1424 case IP_VERSION(11, 0, 12):
1425 case IP_VERSION(11, 0, 13):
1426 case IP_VERSION(11, 5, 0):
1427 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1429 case IP_VERSION(12, 0, 0):
1430 case IP_VERSION(12, 0, 1):
1431 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1433 case IP_VERSION(13, 0, 1):
1434 case IP_VERSION(13, 0, 2):
1435 case IP_VERSION(13, 0, 3):
1436 case IP_VERSION(13, 0, 5):
1437 case IP_VERSION(13, 0, 8):
1438 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1442 "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
1443 adev->ip_versions[MP1_HWIP][0]);
1449 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
1451 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
1452 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1456 if (!amdgpu_device_has_dc_support(adev))
1459 #if defined(CONFIG_DRM_AMD_DC)
1460 if (adev->ip_versions[DCE_HWIP][0]) {
1461 switch (adev->ip_versions[DCE_HWIP][0]) {
1462 case IP_VERSION(1, 0, 0):
1463 case IP_VERSION(1, 0, 1):
1464 case IP_VERSION(2, 0, 2):
1465 case IP_VERSION(2, 0, 0):
1466 case IP_VERSION(2, 0, 3):
1467 case IP_VERSION(2, 1, 0):
1468 case IP_VERSION(3, 0, 0):
1469 case IP_VERSION(3, 0, 2):
1470 case IP_VERSION(3, 0, 3):
1471 case IP_VERSION(3, 0, 1):
1472 case IP_VERSION(3, 1, 2):
1473 case IP_VERSION(3, 1, 3):
1474 case IP_VERSION(3, 1, 5):
1475 case IP_VERSION(3, 1, 6):
1476 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1480 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
1481 adev->ip_versions[DCE_HWIP][0]);
1484 } else if (adev->ip_versions[DCI_HWIP][0]) {
1485 switch (adev->ip_versions[DCI_HWIP][0]) {
1486 case IP_VERSION(12, 0, 0):
1487 case IP_VERSION(12, 0, 1):
1488 case IP_VERSION(12, 1, 0):
1489 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1493 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
1494 adev->ip_versions[DCI_HWIP][0]);
1502 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
1504 switch (adev->ip_versions[GC_HWIP][0]) {
1505 case IP_VERSION(9, 0, 1):
1506 case IP_VERSION(9, 1, 0):
1507 case IP_VERSION(9, 2, 1):
1508 case IP_VERSION(9, 2, 2):
1509 case IP_VERSION(9, 3, 0):
1510 case IP_VERSION(9, 4, 0):
1511 case IP_VERSION(9, 4, 1):
1512 case IP_VERSION(9, 4, 2):
1513 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1515 case IP_VERSION(10, 1, 10):
1516 case IP_VERSION(10, 1, 2):
1517 case IP_VERSION(10, 1, 1):
1518 case IP_VERSION(10, 1, 3):
1519 case IP_VERSION(10, 1, 4):
1520 case IP_VERSION(10, 3, 0):
1521 case IP_VERSION(10, 3, 2):
1522 case IP_VERSION(10, 3, 1):
1523 case IP_VERSION(10, 3, 4):
1524 case IP_VERSION(10, 3, 5):
1525 case IP_VERSION(10, 3, 6):
1526 case IP_VERSION(10, 3, 3):
1527 case IP_VERSION(10, 3, 7):
1528 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1532 "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
1533 adev->ip_versions[GC_HWIP][0]);
1539 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
1541 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1542 case IP_VERSION(4, 0, 0):
1543 case IP_VERSION(4, 0, 1):
1544 case IP_VERSION(4, 1, 0):
1545 case IP_VERSION(4, 1, 1):
1546 case IP_VERSION(4, 1, 2):
1547 case IP_VERSION(4, 2, 0):
1548 case IP_VERSION(4, 2, 2):
1549 case IP_VERSION(4, 4, 0):
1550 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1552 case IP_VERSION(5, 0, 0):
1553 case IP_VERSION(5, 0, 1):
1554 case IP_VERSION(5, 0, 2):
1555 case IP_VERSION(5, 0, 5):
1556 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
1558 case IP_VERSION(5, 2, 0):
1559 case IP_VERSION(5, 2, 2):
1560 case IP_VERSION(5, 2, 4):
1561 case IP_VERSION(5, 2, 5):
1562 case IP_VERSION(5, 2, 6):
1563 case IP_VERSION(5, 2, 3):
1564 case IP_VERSION(5, 2, 1):
1565 case IP_VERSION(5, 2, 7):
1566 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1570 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
1571 adev->ip_versions[SDMA0_HWIP][0]);
1577 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
1579 if (adev->ip_versions[VCE_HWIP][0]) {
1580 switch (adev->ip_versions[UVD_HWIP][0]) {
1581 case IP_VERSION(7, 0, 0):
1582 case IP_VERSION(7, 2, 0):
1583 /* UVD is not supported on vega20 SR-IOV */
1584 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1585 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
1589 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
1590 adev->ip_versions[UVD_HWIP][0]);
1593 switch (adev->ip_versions[VCE_HWIP][0]) {
1594 case IP_VERSION(4, 0, 0):
1595 case IP_VERSION(4, 1, 0):
1596 /* VCE is not supported on vega20 SR-IOV */
1597 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1598 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
1602 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
1603 adev->ip_versions[VCE_HWIP][0]);
1607 switch (adev->ip_versions[UVD_HWIP][0]) {
1608 case IP_VERSION(1, 0, 0):
1609 case IP_VERSION(1, 0, 1):
1610 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1612 case IP_VERSION(2, 0, 0):
1613 case IP_VERSION(2, 0, 2):
1614 case IP_VERSION(2, 2, 0):
1615 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
1616 if (!amdgpu_sriov_vf(adev))
1617 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1619 case IP_VERSION(2, 0, 3):
1621 case IP_VERSION(2, 5, 0):
1622 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1623 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1625 case IP_VERSION(2, 6, 0):
1626 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1627 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1629 case IP_VERSION(3, 0, 0):
1630 case IP_VERSION(3, 0, 16):
1631 case IP_VERSION(3, 1, 1):
1632 case IP_VERSION(3, 1, 2):
1633 case IP_VERSION(3, 0, 2):
1634 case IP_VERSION(3, 0, 192):
1635 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1636 if (!amdgpu_sriov_vf(adev))
1637 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
1639 case IP_VERSION(3, 0, 33):
1640 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1644 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
1645 adev->ip_versions[UVD_HWIP][0]);
1652 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
1654 switch (adev->ip_versions[GC_HWIP][0]) {
1655 case IP_VERSION(10, 1, 10):
1656 case IP_VERSION(10, 1, 1):
1657 case IP_VERSION(10, 1, 2):
1658 case IP_VERSION(10, 1, 3):
1659 case IP_VERSION(10, 1, 4):
1660 case IP_VERSION(10, 3, 0):
1661 case IP_VERSION(10, 3, 1):
1662 case IP_VERSION(10, 3, 2):
1663 case IP_VERSION(10, 3, 3):
1664 case IP_VERSION(10, 3, 4):
1665 case IP_VERSION(10, 3, 5):
1666 case IP_VERSION(10, 3, 6):
1667 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
1675 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
1679 switch (adev->asic_type) {
1681 vega10_reg_base_init(adev);
1682 adev->sdma.num_instances = 2;
1683 adev->gmc.num_umc = 4;
1684 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1685 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1686 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
1687 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
1688 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
1689 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
1690 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1691 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
1692 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
1693 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1694 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1695 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1696 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
1697 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
1698 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1699 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1700 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
1703 vega10_reg_base_init(adev);
1704 adev->sdma.num_instances = 2;
1705 adev->gmc.num_umc = 4;
1706 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1707 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1708 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
1709 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
1710 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
1711 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
1712 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
1713 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
1714 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
1715 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1716 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1717 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1718 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
1719 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
1720 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1721 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1722 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
1725 vega10_reg_base_init(adev);
1726 adev->sdma.num_instances = 1;
1727 adev->vcn.num_vcn_inst = 1;
1728 adev->gmc.num_umc = 2;
1729 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1730 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1731 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1732 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
1733 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
1734 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
1735 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
1736 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
1737 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
1738 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
1739 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
1740 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
1741 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
1742 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
1743 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
1744 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
1746 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1747 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1748 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
1749 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
1750 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
1751 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1752 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
1753 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
1754 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
1755 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
1756 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
1757 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
1758 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
1759 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
1760 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
1764 vega20_reg_base_init(adev);
1765 adev->sdma.num_instances = 2;
1766 adev->gmc.num_umc = 8;
1767 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1768 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1769 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
1770 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
1771 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
1772 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
1773 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
1774 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
1775 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
1776 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
1777 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1778 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
1779 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
1780 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
1781 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
1782 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
1783 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
1784 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
1787 arct_reg_base_init(adev);
1788 adev->sdma.num_instances = 8;
1789 adev->vcn.num_vcn_inst = 2;
1790 adev->gmc.num_umc = 8;
1791 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1792 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1793 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
1794 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
1795 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
1796 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
1797 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
1798 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
1799 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
1800 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
1801 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
1802 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
1803 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
1804 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
1805 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
1806 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
1807 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1808 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
1809 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
1810 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
1811 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
1812 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
1814 case CHIP_ALDEBARAN:
1815 aldebaran_reg_base_init(adev);
1816 adev->sdma.num_instances = 5;
1817 adev->vcn.num_vcn_inst = 2;
1818 adev->gmc.num_umc = 4;
1819 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1820 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1821 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
1822 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
1823 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
1824 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
1825 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
1826 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
1827 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
1828 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
1829 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
1830 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
1831 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
1832 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
1833 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
1834 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
1835 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
1836 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
1837 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
1838 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
1841 r = amdgpu_discovery_reg_base_init(adev);
1845 amdgpu_discovery_harvest_ip(adev);
1849 switch (adev->ip_versions[GC_HWIP][0]) {
1850 case IP_VERSION(9, 0, 1):
1851 case IP_VERSION(9, 2, 1):
1852 case IP_VERSION(9, 4, 0):
1853 case IP_VERSION(9, 4, 1):
1854 case IP_VERSION(9, 4, 2):
1855 adev->family = AMDGPU_FAMILY_AI;
1857 case IP_VERSION(9, 1, 0):
1858 case IP_VERSION(9, 2, 2):
1859 case IP_VERSION(9, 3, 0):
1860 adev->family = AMDGPU_FAMILY_RV;
1862 case IP_VERSION(10, 1, 10):
1863 case IP_VERSION(10, 1, 1):
1864 case IP_VERSION(10, 1, 2):
1865 case IP_VERSION(10, 1, 3):
1866 case IP_VERSION(10, 1, 4):
1867 case IP_VERSION(10, 3, 0):
1868 case IP_VERSION(10, 3, 2):
1869 case IP_VERSION(10, 3, 4):
1870 case IP_VERSION(10, 3, 5):
1871 adev->family = AMDGPU_FAMILY_NV;
1873 case IP_VERSION(10, 3, 1):
1874 adev->family = AMDGPU_FAMILY_VGH;
1876 case IP_VERSION(10, 3, 3):
1877 adev->family = AMDGPU_FAMILY_YC;
1879 case IP_VERSION(10, 3, 6):
1880 adev->family = AMDGPU_FAMILY_GC_10_3_6;
1882 case IP_VERSION(10, 3, 7):
1883 adev->family = AMDGPU_FAMILY_GC_10_3_7;
1889 switch (adev->ip_versions[GC_HWIP][0]) {
1890 case IP_VERSION(9, 1, 0):
1891 case IP_VERSION(9, 2, 2):
1892 case IP_VERSION(9, 3, 0):
1893 case IP_VERSION(10, 1, 3):
1894 case IP_VERSION(10, 1, 4):
1895 case IP_VERSION(10, 3, 1):
1896 case IP_VERSION(10, 3, 3):
1897 case IP_VERSION(10, 3, 6):
1898 case IP_VERSION(10, 3, 7):
1899 adev->flags |= AMD_IS_APU;
1905 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
1906 adev->gmc.xgmi.supported = true;
1908 /* set NBIO version */
1909 switch (adev->ip_versions[NBIO_HWIP][0]) {
1910 case IP_VERSION(6, 1, 0):
1911 case IP_VERSION(6, 2, 0):
1912 adev->nbio.funcs = &nbio_v6_1_funcs;
1913 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
1915 case IP_VERSION(7, 0, 0):
1916 case IP_VERSION(7, 0, 1):
1917 case IP_VERSION(2, 5, 0):
1918 adev->nbio.funcs = &nbio_v7_0_funcs;
1919 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
1921 case IP_VERSION(7, 4, 0):
1922 case IP_VERSION(7, 4, 1):
1923 adev->nbio.funcs = &nbio_v7_4_funcs;
1924 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
1926 case IP_VERSION(7, 4, 4):
1927 adev->nbio.funcs = &nbio_v7_4_funcs;
1928 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
1930 case IP_VERSION(7, 2, 0):
1931 case IP_VERSION(7, 2, 1):
1932 case IP_VERSION(7, 3, 0):
1933 case IP_VERSION(7, 5, 0):
1934 case IP_VERSION(7, 5, 1):
1935 adev->nbio.funcs = &nbio_v7_2_funcs;
1936 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
1938 case IP_VERSION(2, 1, 1):
1939 case IP_VERSION(2, 3, 0):
1940 case IP_VERSION(2, 3, 1):
1941 case IP_VERSION(2, 3, 2):
1942 adev->nbio.funcs = &nbio_v2_3_funcs;
1943 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
1945 case IP_VERSION(3, 3, 0):
1946 case IP_VERSION(3, 3, 1):
1947 case IP_VERSION(3, 3, 2):
1948 case IP_VERSION(3, 3, 3):
1949 adev->nbio.funcs = &nbio_v2_3_funcs;
1950 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
1956 switch (adev->ip_versions[HDP_HWIP][0]) {
1957 case IP_VERSION(4, 0, 0):
1958 case IP_VERSION(4, 0, 1):
1959 case IP_VERSION(4, 1, 0):
1960 case IP_VERSION(4, 1, 1):
1961 case IP_VERSION(4, 1, 2):
1962 case IP_VERSION(4, 2, 0):
1963 case IP_VERSION(4, 2, 1):
1964 case IP_VERSION(4, 4, 0):
1965 adev->hdp.funcs = &hdp_v4_0_funcs;
1967 case IP_VERSION(5, 0, 0):
1968 case IP_VERSION(5, 0, 1):
1969 case IP_VERSION(5, 0, 2):
1970 case IP_VERSION(5, 0, 3):
1971 case IP_VERSION(5, 0, 4):
1972 case IP_VERSION(5, 2, 0):
1973 adev->hdp.funcs = &hdp_v5_0_funcs;
1979 switch (adev->ip_versions[DF_HWIP][0]) {
1980 case IP_VERSION(3, 6, 0):
1981 case IP_VERSION(3, 6, 1):
1982 case IP_VERSION(3, 6, 2):
1983 adev->df.funcs = &df_v3_6_funcs;
1985 case IP_VERSION(2, 1, 0):
1986 case IP_VERSION(2, 1, 1):
1987 case IP_VERSION(2, 5, 0):
1988 case IP_VERSION(3, 5, 1):
1989 case IP_VERSION(3, 5, 2):
1990 adev->df.funcs = &df_v1_7_funcs;
1996 switch (adev->ip_versions[SMUIO_HWIP][0]) {
1997 case IP_VERSION(9, 0, 0):
1998 case IP_VERSION(9, 0, 1):
1999 case IP_VERSION(10, 0, 0):
2000 case IP_VERSION(10, 0, 1):
2001 case IP_VERSION(10, 0, 2):
2002 adev->smuio.funcs = &smuio_v9_0_funcs;
2004 case IP_VERSION(11, 0, 0):
2005 case IP_VERSION(11, 0, 2):
2006 case IP_VERSION(11, 0, 3):
2007 case IP_VERSION(11, 0, 4):
2008 case IP_VERSION(11, 0, 7):
2009 case IP_VERSION(11, 0, 8):
2010 adev->smuio.funcs = &smuio_v11_0_funcs;
2012 case IP_VERSION(11, 0, 6):
2013 case IP_VERSION(11, 0, 10):
2014 case IP_VERSION(11, 0, 11):
2015 case IP_VERSION(11, 5, 0):
2016 case IP_VERSION(13, 0, 1):
2017 case IP_VERSION(13, 0, 9):
2018 case IP_VERSION(13, 0, 10):
2019 adev->smuio.funcs = &smuio_v11_0_6_funcs;
2021 case IP_VERSION(13, 0, 2):
2022 adev->smuio.funcs = &smuio_v13_0_funcs;
2028 r = amdgpu_discovery_set_common_ip_blocks(adev);
2032 r = amdgpu_discovery_set_gmc_ip_blocks(adev);
2036 /* For SR-IOV, PSP needs to be initialized before IH */
2037 if (amdgpu_sriov_vf(adev)) {
2038 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2041 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2045 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2049 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2050 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2056 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2057 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2062 r = amdgpu_discovery_set_display_ip_blocks(adev);
2066 r = amdgpu_discovery_set_gc_ip_blocks(adev);
2070 r = amdgpu_discovery_set_sdma_ip_blocks(adev);
2074 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
2075 !amdgpu_sriov_vf(adev)) {
2076 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2081 r = amdgpu_discovery_set_mm_ip_blocks(adev);
2085 if (adev->enable_mes) {
2086 r = amdgpu_discovery_set_mes_ip_blocks(adev);