2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_discovery.h"
28 #include "soc15_hw_ip.h"
29 #include "discovery.h"
33 #include "gfx_v9_4_3.h"
38 #include "nbio_v6_1.h"
39 #include "nbio_v7_0.h"
40 #include "nbio_v7_4.h"
41 #include "nbio_v7_9.h"
42 #include "nbio_v7_11.h"
44 #include "vega10_ih.h"
45 #include "vega20_ih.h"
46 #include "sdma_v4_0.h"
47 #include "sdma_v4_4_2.h"
52 #include "jpeg_v2_5.h"
53 #include "smuio_v9_0.h"
54 #include "gmc_v10_0.h"
55 #include "gmc_v11_0.h"
56 #include "gfxhub_v2_0.h"
57 #include "mmhub_v2_0.h"
58 #include "nbio_v2_3.h"
59 #include "nbio_v4_3.h"
60 #include "nbio_v7_2.h"
61 #include "nbio_v7_7.h"
67 #include "navi10_ih.h"
70 #include "gfx_v10_0.h"
71 #include "gfx_v11_0.h"
72 #include "sdma_v5_0.h"
73 #include "sdma_v5_2.h"
74 #include "sdma_v6_0.h"
75 #include "lsdma_v6_0.h"
77 #include "jpeg_v2_0.h"
79 #include "jpeg_v3_0.h"
81 #include "jpeg_v4_0.h"
82 #include "vcn_v4_0_3.h"
83 #include "jpeg_v4_0_3.h"
84 #include "vcn_v4_0_5.h"
85 #include "jpeg_v4_0_5.h"
86 #include "amdgpu_vkms.h"
87 #include "mes_v10_1.h"
88 #include "mes_v11_0.h"
89 #include "smuio_v11_0.h"
90 #include "smuio_v11_0_6.h"
91 #include "smuio_v13_0.h"
92 #include "smuio_v13_0_3.h"
93 #include "smuio_v13_0_6.h"
95 #include "amdgpu_vpe.h"
97 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
98 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
100 #define mmRCC_CONFIG_MEMSIZE 0xde3
101 #define mmMM_INDEX 0x0
102 #define mmMM_INDEX_HI 0x6
103 #define mmMM_DATA 0x1
105 static const char *hw_id_names[HW_ID_MAX] = {
109 [SMUIO_HWID] = "SMUIO",
110 [FUSE_HWID] = "FUSE",
111 [CLKA_HWID] = "CLKA",
115 [AUDIO_AZ_HWID] = "AUDIO_AZ",
121 [XDMA_HWID] = "XDMA",
122 [DCEAZ_HWID] = "DCEAZ",
124 [SDPMUX_HWID] = "SDPMUX",
126 [IOHC_HWID] = "IOHC",
127 [L2IMU_HWID] = "L2IMU",
129 [MMHUB_HWID] = "MMHUB",
130 [ATHUB_HWID] = "ATHUB",
131 [DBGU_NBIO_HWID] = "DBGU_NBIO",
133 [DBGU0_HWID] = "DBGU0",
134 [DBGU1_HWID] = "DBGU1",
135 [OSSSYS_HWID] = "OSSSYS",
137 [SDMA0_HWID] = "SDMA0",
138 [SDMA1_HWID] = "SDMA1",
139 [SDMA2_HWID] = "SDMA2",
140 [SDMA3_HWID] = "SDMA3",
141 [LSDMA_HWID] = "LSDMA",
143 [DBGU_IO_HWID] = "DBGU_IO",
145 [CLKB_HWID] = "CLKB",
147 [DFX_DAP_HWID] = "DFX_DAP",
148 [L1IMU_PCIE_HWID] = "L1IMU_PCIE",
149 [L1IMU_NBIF_HWID] = "L1IMU_NBIF",
150 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
151 [L1IMU3_HWID] = "L1IMU3",
152 [L1IMU4_HWID] = "L1IMU4",
153 [L1IMU5_HWID] = "L1IMU5",
154 [L1IMU6_HWID] = "L1IMU6",
155 [L1IMU7_HWID] = "L1IMU7",
156 [L1IMU8_HWID] = "L1IMU8",
157 [L1IMU9_HWID] = "L1IMU9",
158 [L1IMU10_HWID] = "L1IMU10",
159 [L1IMU11_HWID] = "L1IMU11",
160 [L1IMU12_HWID] = "L1IMU12",
161 [L1IMU13_HWID] = "L1IMU13",
162 [L1IMU14_HWID] = "L1IMU14",
163 [L1IMU15_HWID] = "L1IMU15",
164 [WAFLC_HWID] = "WAFLC",
165 [FCH_USB_PD_HWID] = "FCH_USB_PD",
166 [PCIE_HWID] = "PCIE",
168 [DDCL_HWID] = "DDCL",
170 [IOAGR_HWID] = "IOAGR",
171 [NBIF_HWID] = "NBIF",
172 [IOAPIC_HWID] = "IOAPIC",
173 [SYSTEMHUB_HWID] = "SYSTEMHUB",
174 [NTBCCP_HWID] = "NTBCCP",
176 [SATA_HWID] = "SATA",
178 [CCXSEC_HWID] = "CCXSEC",
179 [XGMI_HWID] = "XGMI",
180 [XGBE_HWID] = "XGBE",
185 static int hw_id_map[MAX_HWIP] = {
187 [HDP_HWIP] = HDP_HWID,
188 [SDMA0_HWIP] = SDMA0_HWID,
189 [SDMA1_HWIP] = SDMA1_HWID,
190 [SDMA2_HWIP] = SDMA2_HWID,
191 [SDMA3_HWIP] = SDMA3_HWID,
192 [LSDMA_HWIP] = LSDMA_HWID,
193 [MMHUB_HWIP] = MMHUB_HWID,
194 [ATHUB_HWIP] = ATHUB_HWID,
195 [NBIO_HWIP] = NBIF_HWID,
196 [MP0_HWIP] = MP0_HWID,
197 [MP1_HWIP] = MP1_HWID,
198 [UVD_HWIP] = UVD_HWID,
199 [VCE_HWIP] = VCE_HWID,
201 [DCE_HWIP] = DMU_HWID,
202 [OSSSYS_HWIP] = OSSSYS_HWID,
203 [SMUIO_HWIP] = SMUIO_HWID,
204 [PWR_HWIP] = PWR_HWID,
205 [NBIF_HWIP] = NBIF_HWID,
206 [THM_HWIP] = THM_HWID,
207 [CLK_HWIP] = CLKA_HWID,
208 [UMC_HWIP] = UMC_HWID,
209 [XGMI_HWIP] = XGMI_HWID,
210 [DCI_HWIP] = DCI_HWID,
211 [PCIE_HWIP] = PCIE_HWID,
212 [VPE_HWIP] = VPE_HWID,
215 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)
217 u64 tmr_offset, tmr_size, pos;
221 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size);
225 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET;
227 /* This region is read-only and reserved from system use */
228 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC);
230 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size);
231 memunmap(discv_regn);
238 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
241 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
245 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
246 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
247 adev->mman.discovery_tmr_size, false);
249 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
255 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
257 const struct firmware *fw;
261 switch (amdgpu_discovery) {
263 fw_name = FIRMWARE_IP_DISCOVERY;
266 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
270 r = request_firmware(&fw, fw_name, adev->dev);
272 dev_err(adev->dev, "can't load firmware \"%s\"\n",
277 memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
278 release_firmware(fw);
283 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
285 uint16_t checksum = 0;
288 for (i = 0; i < size; i++)
294 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
297 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
300 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
302 struct binary_header *bhdr;
303 bhdr = (struct binary_header *)binary;
305 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
308 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
311 * So far, apply this quirk only on those Navy Flounder boards which
312 * have a bad harvest table of VCN config.
314 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) &&
315 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) {
316 switch (adev->pdev->revision) {
324 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
325 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;
333 static int amdgpu_discovery_init(struct amdgpu_device *adev)
335 struct table_info *info;
336 struct binary_header *bhdr;
342 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
343 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
344 if (!adev->mman.discovery_bin)
347 /* Read from file if it is the preferred option */
348 if (amdgpu_discovery == 2) {
349 dev_info(adev->dev, "use ip discovery information from file");
350 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
353 dev_err(adev->dev, "failed to read ip discovery binary from file\n");
359 r = amdgpu_discovery_read_binary_from_mem(
360 adev, adev->mman.discovery_bin);
365 /* check the ip discovery binary signature */
366 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
368 "get invalid ip discovery binary signature\n");
373 bhdr = (struct binary_header *)adev->mman.discovery_bin;
375 offset = offsetof(struct binary_header, binary_checksum) +
376 sizeof(bhdr->binary_checksum);
377 size = le16_to_cpu(bhdr->binary_size) - offset;
378 checksum = le16_to_cpu(bhdr->binary_checksum);
380 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
382 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
387 info = &bhdr->table_list[IP_DISCOVERY];
388 offset = le16_to_cpu(info->offset);
389 checksum = le16_to_cpu(info->checksum);
392 struct ip_discovery_header *ihdr =
393 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
394 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
395 dev_err(adev->dev, "invalid ip discovery data table signature\n");
400 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
401 le16_to_cpu(ihdr->size), checksum)) {
402 dev_err(adev->dev, "invalid ip discovery data table checksum\n");
408 info = &bhdr->table_list[GC];
409 offset = le16_to_cpu(info->offset);
410 checksum = le16_to_cpu(info->checksum);
413 struct gpu_info_header *ghdr =
414 (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
416 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) {
417 dev_err(adev->dev, "invalid ip discovery gc table id\n");
422 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
423 le32_to_cpu(ghdr->size), checksum)) {
424 dev_err(adev->dev, "invalid gc data table checksum\n");
430 info = &bhdr->table_list[HARVEST_INFO];
431 offset = le16_to_cpu(info->offset);
432 checksum = le16_to_cpu(info->checksum);
435 struct harvest_info_header *hhdr =
436 (struct harvest_info_header *)(adev->mman.discovery_bin + offset);
438 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) {
439 dev_err(adev->dev, "invalid ip discovery harvest table signature\n");
444 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
445 sizeof(struct harvest_table), checksum)) {
446 dev_err(adev->dev, "invalid harvest data table checksum\n");
452 info = &bhdr->table_list[VCN_INFO];
453 offset = le16_to_cpu(info->offset);
454 checksum = le16_to_cpu(info->checksum);
457 struct vcn_info_header *vhdr =
458 (struct vcn_info_header *)(adev->mman.discovery_bin + offset);
460 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) {
461 dev_err(adev->dev, "invalid ip discovery vcn table id\n");
466 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
467 le32_to_cpu(vhdr->size_bytes), checksum)) {
468 dev_err(adev->dev, "invalid vcn data table checksum\n");
474 info = &bhdr->table_list[MALL_INFO];
475 offset = le16_to_cpu(info->offset);
476 checksum = le16_to_cpu(info->checksum);
479 struct mall_info_header *mhdr =
480 (struct mall_info_header *)(adev->mman.discovery_bin + offset);
482 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) {
483 dev_err(adev->dev, "invalid ip discovery mall table id\n");
488 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
489 le32_to_cpu(mhdr->size_bytes), checksum)) {
490 dev_err(adev->dev, "invalid mall data table checksum\n");
499 kfree(adev->mman.discovery_bin);
500 adev->mman.discovery_bin = NULL;
505 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
507 void amdgpu_discovery_fini(struct amdgpu_device *adev)
509 amdgpu_discovery_sysfs_fini(adev);
510 kfree(adev->mman.discovery_bin);
511 adev->mman.discovery_bin = NULL;
514 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip)
516 if (ip->instance_number >= HWIP_MAX_INSTANCE) {
517 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n",
518 ip->instance_number);
521 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
522 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
523 le16_to_cpu(ip->hw_id));
530 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
531 uint32_t *vcn_harvest_count)
533 struct binary_header *bhdr;
534 struct ip_discovery_header *ihdr;
535 struct die_header *dhdr;
537 uint16_t die_offset, ip_offset, num_dies, num_ips;
540 bhdr = (struct binary_header *)adev->mman.discovery_bin;
541 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
542 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
543 num_dies = le16_to_cpu(ihdr->num_dies);
545 /* scan harvest bit of all IP data structures */
546 for (i = 0; i < num_dies; i++) {
547 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
548 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
549 num_ips = le16_to_cpu(dhdr->num_ips);
550 ip_offset = die_offset + sizeof(*dhdr);
552 for (j = 0; j < num_ips; j++) {
553 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
555 if (amdgpu_discovery_validate_ip(ip))
558 if (le16_to_cpu(ip->variant) == 1) {
559 switch (le16_to_cpu(ip->hw_id)) {
561 (*vcn_harvest_count)++;
562 if (ip->instance_number == 0) {
563 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
564 adev->vcn.inst_mask &=
565 ~AMDGPU_VCN_HARVEST_VCN0;
566 adev->jpeg.inst_mask &=
567 ~AMDGPU_VCN_HARVEST_VCN0;
569 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
570 adev->vcn.inst_mask &=
571 ~AMDGPU_VCN_HARVEST_VCN1;
572 adev->jpeg.inst_mask &=
573 ~AMDGPU_VCN_HARVEST_VCN1;
577 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
584 if (ihdr->base_addr_64_bit)
585 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
587 ip_offset += struct_size(ip, base_address, ip->num_base_address);
592 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
593 uint32_t *vcn_harvest_count,
594 uint32_t *umc_harvest_count)
596 struct binary_header *bhdr;
597 struct harvest_table *harvest_info;
600 uint32_t umc_harvest_config = 0;
602 bhdr = (struct binary_header *)adev->mman.discovery_bin;
603 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset);
606 dev_err(adev->dev, "invalid harvest table offset\n");
610 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset);
612 for (i = 0; i < 32; i++) {
613 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
616 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
618 (*vcn_harvest_count)++;
619 adev->vcn.harvest_config |=
620 (1 << harvest_info->list[i].number_instance);
621 adev->jpeg.harvest_config |=
622 (1 << harvest_info->list[i].number_instance);
624 adev->vcn.inst_mask &=
625 ~(1U << harvest_info->list[i].number_instance);
626 adev->jpeg.inst_mask &=
627 ~(1U << harvest_info->list[i].number_instance);
630 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
633 umc_harvest_config |=
634 1 << (le16_to_cpu(harvest_info->list[i].number_instance));
635 (*umc_harvest_count)++;
638 adev->gfx.xcc_mask &=
639 ~(1U << harvest_info->list[i].number_instance);
642 adev->sdma.sdma_mask &=
643 ~(1U << harvest_info->list[i].number_instance);
650 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) &
654 /* ================================================== */
656 struct ip_hw_instance {
657 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
661 u8 major, minor, revision;
664 int num_base_addresses;
665 u32 base_addr[] __counted_by(num_base_addresses);
669 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
673 struct ip_die_entry {
674 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */
678 /* -------------------------------------------------- */
680 struct ip_hw_instance_attr {
681 struct attribute attr;
682 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
685 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
687 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
690 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
692 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
695 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
697 return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
700 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
702 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
705 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
707 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
710 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
712 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
715 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
717 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
720 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
725 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
726 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
728 if (at + 12 > PAGE_SIZE)
730 res = sysfs_emit_at(buf, at, "0x%08X\n",
731 ip_hw_instance->base_addr[ii]);
737 return res < 0 ? res : at;
740 static struct ip_hw_instance_attr ip_hw_attr[] = {
742 __ATTR_RO(num_instance),
747 __ATTR_RO(num_base_addresses),
748 __ATTR_RO(base_addr),
751 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
752 ATTRIBUTE_GROUPS(ip_hw_instance);
754 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
755 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
757 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
758 struct attribute *attr,
761 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
762 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
764 if (!ip_hw_attr->show)
767 return ip_hw_attr->show(ip_hw_instance, buf);
770 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
771 .show = ip_hw_instance_attr_show,
774 static void ip_hw_instance_release(struct kobject *kobj)
776 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
778 kfree(ip_hw_instance);
781 static const struct kobj_type ip_hw_instance_ktype = {
782 .release = ip_hw_instance_release,
783 .sysfs_ops = &ip_hw_instance_sysfs_ops,
784 .default_groups = ip_hw_instance_groups,
787 /* -------------------------------------------------- */
789 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
791 static void ip_hw_id_release(struct kobject *kobj)
793 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
795 if (!list_empty(&ip_hw_id->hw_id_kset.list))
796 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
800 static const struct kobj_type ip_hw_id_ktype = {
801 .release = ip_hw_id_release,
802 .sysfs_ops = &kobj_sysfs_ops,
805 /* -------------------------------------------------- */
807 static void die_kobj_release(struct kobject *kobj);
808 static void ip_disc_release(struct kobject *kobj);
810 struct ip_die_entry_attribute {
811 struct attribute attr;
812 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
815 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr)
817 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
819 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
822 /* If there are more ip_die_entry attrs, other than the number of IPs,
823 * we can make this intro an array of attrs, and then initialize
824 * ip_die_entry_attrs in a loop.
826 static struct ip_die_entry_attribute num_ips_attr =
829 static struct attribute *ip_die_entry_attrs[] = {
833 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
835 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
837 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
838 struct attribute *attr,
841 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
842 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
844 if (!ip_die_entry_attr->show)
847 return ip_die_entry_attr->show(ip_die_entry, buf);
850 static void ip_die_entry_release(struct kobject *kobj)
852 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
854 if (!list_empty(&ip_die_entry->ip_kset.list))
855 DRM_ERROR("ip_die_entry->ip_kset is not empty");
859 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
860 .show = ip_die_entry_attr_show,
863 static const struct kobj_type ip_die_entry_ktype = {
864 .release = ip_die_entry_release,
865 .sysfs_ops = &ip_die_entry_sysfs_ops,
866 .default_groups = ip_die_entry_groups,
869 static const struct kobj_type die_kobj_ktype = {
870 .release = die_kobj_release,
871 .sysfs_ops = &kobj_sysfs_ops,
874 static const struct kobj_type ip_discovery_ktype = {
875 .release = ip_disc_release,
876 .sysfs_ops = &kobj_sysfs_ops,
879 struct ip_discovery_top {
880 struct kobject kobj; /* ip_discovery/ */
881 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */
882 struct amdgpu_device *adev;
885 static void die_kobj_release(struct kobject *kobj)
887 struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
888 struct ip_discovery_top,
890 if (!list_empty(&ip_top->die_kset.list))
891 DRM_ERROR("ip_top->die_kset is not empty");
894 static void ip_disc_release(struct kobject *kobj)
896 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
898 struct amdgpu_device *adev = ip_top->adev;
904 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,
905 uint16_t hw_id, uint8_t inst)
909 /* Until a uniform way is figured, get mask based on hwid */
912 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;
915 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
919 /* TODO: It needs another parsing; for now, ignore.*/
922 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
925 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;
934 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
935 struct ip_die_entry *ip_die_entry,
936 const size_t _ip_offset, const int num_ips,
941 DRM_DEBUG("num_ips:%d", num_ips);
943 /* Find all IPs of a given HW ID, and add their instance to
944 * #die/#hw_id/#instance/<attributes>
946 for (ii = 0; ii < HW_ID_MAX; ii++) {
947 struct ip_hw_id *ip_hw_id = NULL;
948 size_t ip_offset = _ip_offset;
950 for (jj = 0; jj < num_ips; jj++) {
952 struct ip_hw_instance *ip_hw_instance;
954 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
955 if (amdgpu_discovery_validate_ip(ip) ||
956 le16_to_cpu(ip->hw_id) != ii)
959 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
961 /* We have a hw_id match; register the hw
962 * block if not yet registered.
965 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
968 ip_hw_id->hw_id = ii;
970 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
971 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
972 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
973 res = kset_register(&ip_hw_id->hw_id_kset);
975 DRM_ERROR("Couldn't register ip_hw_id kset");
979 if (hw_id_names[ii]) {
980 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
981 &ip_hw_id->hw_id_kset.kobj,
984 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
986 kobject_name(&ip_die_entry->ip_kset.kobj));
991 /* Now register its instance.
993 ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
995 ip->num_base_address),
997 if (!ip_hw_instance) {
998 DRM_ERROR("no memory for ip_hw_instance");
1001 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
1002 ip_hw_instance->num_instance = ip->instance_number;
1003 ip_hw_instance->major = ip->major;
1004 ip_hw_instance->minor = ip->minor;
1005 ip_hw_instance->revision = ip->revision;
1006 ip_hw_instance->harvest =
1007 amdgpu_discovery_get_harvest_info(
1008 adev, ip_hw_instance->hw_id,
1009 ip_hw_instance->num_instance);
1010 ip_hw_instance->num_base_addresses = ip->num_base_address;
1012 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) {
1014 ip_hw_instance->base_addr[kk] =
1015 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF;
1017 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
1020 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
1021 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
1022 res = kobject_add(&ip_hw_instance->kobj, NULL,
1023 "%d", ip_hw_instance->num_instance);
1026 ip_offset += struct_size(ip, base_address_64,
1027 ip->num_base_address);
1029 ip_offset += struct_size(ip, base_address,
1030 ip->num_base_address);
1037 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
1039 struct binary_header *bhdr;
1040 struct ip_discovery_header *ihdr;
1041 struct die_header *dhdr;
1042 struct kset *die_kset = &adev->ip_top->die_kset;
1043 u16 num_dies, die_offset, num_ips;
1047 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1048 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1049 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1050 num_dies = le16_to_cpu(ihdr->num_dies);
1052 DRM_DEBUG("number of dies: %d\n", num_dies);
1054 for (ii = 0; ii < num_dies; ii++) {
1055 struct ip_die_entry *ip_die_entry;
1057 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
1058 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1059 num_ips = le16_to_cpu(dhdr->num_ips);
1060 ip_offset = die_offset + sizeof(*dhdr);
1062 /* Add the die to the kset.
1064 * dhdr->die_id == ii, which was checked in
1065 * amdgpu_discovery_reg_base_init().
1068 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
1072 ip_die_entry->num_ips = num_ips;
1074 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
1075 ip_die_entry->ip_kset.kobj.kset = die_kset;
1076 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
1077 res = kset_register(&ip_die_entry->ip_kset);
1079 DRM_ERROR("Couldn't register ip_die_entry kset");
1080 kfree(ip_die_entry);
1084 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit);
1090 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
1092 struct kset *die_kset;
1095 if (!adev->mman.discovery_bin)
1098 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
1102 adev->ip_top->adev = adev;
1104 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
1105 &adev->dev->kobj, "ip_discovery");
1107 DRM_ERROR("Couldn't init and add ip_discovery/");
1111 die_kset = &adev->ip_top->die_kset;
1112 kobject_set_name(&die_kset->kobj, "%s", "die");
1113 die_kset->kobj.parent = &adev->ip_top->kobj;
1114 die_kset->kobj.ktype = &die_kobj_ktype;
1115 res = kset_register(&adev->ip_top->die_kset);
1117 DRM_ERROR("Couldn't register die_kset");
1121 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1122 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1123 ip_hw_instance_attrs[ii] = NULL;
1125 res = amdgpu_discovery_sysfs_recurse(adev);
1129 kobject_put(&adev->ip_top->kobj);
1133 /* -------------------------------------------------- */
1135 #define list_to_kobj(el) container_of(el, struct kobject, entry)
1137 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
1139 struct list_head *el, *tmp;
1140 struct kset *hw_id_kset;
1142 hw_id_kset = &ip_hw_id->hw_id_kset;
1143 spin_lock(&hw_id_kset->list_lock);
1144 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
1146 spin_unlock(&hw_id_kset->list_lock);
1147 /* kobject is embedded in ip_hw_instance */
1148 kobject_put(list_to_kobj(el));
1149 spin_lock(&hw_id_kset->list_lock);
1151 spin_unlock(&hw_id_kset->list_lock);
1152 kobject_put(&ip_hw_id->hw_id_kset.kobj);
1155 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
1157 struct list_head *el, *tmp;
1158 struct kset *ip_kset;
1160 ip_kset = &ip_die_entry->ip_kset;
1161 spin_lock(&ip_kset->list_lock);
1162 list_for_each_prev_safe(el, tmp, &ip_kset->list) {
1164 spin_unlock(&ip_kset->list_lock);
1165 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
1166 spin_lock(&ip_kset->list_lock);
1168 spin_unlock(&ip_kset->list_lock);
1169 kobject_put(&ip_die_entry->ip_kset.kobj);
1172 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
1174 struct list_head *el, *tmp;
1175 struct kset *die_kset;
1177 die_kset = &adev->ip_top->die_kset;
1178 spin_lock(&die_kset->list_lock);
1179 list_for_each_prev_safe(el, tmp, &die_kset->list) {
1181 spin_unlock(&die_kset->list_lock);
1182 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1183 spin_lock(&die_kset->list_lock);
1185 spin_unlock(&die_kset->list_lock);
1186 kobject_put(&adev->ip_top->die_kset.kobj);
1187 kobject_put(&adev->ip_top->kobj);
1190 /* ================================================== */
1192 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
1194 uint8_t num_base_address, subrev, variant;
1195 struct binary_header *bhdr;
1196 struct ip_discovery_header *ihdr;
1197 struct die_header *dhdr;
1199 uint16_t die_offset;
1207 r = amdgpu_discovery_init(adev);
1209 DRM_ERROR("amdgpu_discovery_init failed\n");
1213 adev->gfx.xcc_mask = 0;
1214 adev->sdma.sdma_mask = 0;
1215 adev->vcn.inst_mask = 0;
1216 adev->jpeg.inst_mask = 0;
1217 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1218 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1219 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1220 num_dies = le16_to_cpu(ihdr->num_dies);
1222 DRM_DEBUG("number of dies: %d\n", num_dies);
1224 for (i = 0; i < num_dies; i++) {
1225 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1226 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1227 num_ips = le16_to_cpu(dhdr->num_ips);
1228 ip_offset = die_offset + sizeof(*dhdr);
1230 if (le16_to_cpu(dhdr->die_id) != i) {
1231 DRM_ERROR("invalid die id %d, expected %d\n",
1232 le16_to_cpu(dhdr->die_id), i);
1236 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1237 le16_to_cpu(dhdr->die_id), num_ips);
1239 for (j = 0; j < num_ips; j++) {
1240 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
1242 if (amdgpu_discovery_validate_ip(ip))
1245 num_base_address = ip->num_base_address;
1247 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1248 hw_id_names[le16_to_cpu(ip->hw_id)],
1249 le16_to_cpu(ip->hw_id),
1250 ip->instance_number,
1251 ip->major, ip->minor,
1254 if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1255 /* Bit [5:0]: original revision value
1256 * Bit [7:6]: en/decode capability:
1257 * 0b00 : VCN function normally
1258 * 0b10 : encode is disabled
1259 * 0b01 : decode is disabled
1261 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
1262 ip->revision & 0xc0;
1263 ip->revision &= ~0xc0;
1264 if (adev->vcn.num_vcn_inst <
1265 AMDGPU_MAX_VCN_INSTANCES) {
1266 adev->vcn.num_vcn_inst++;
1267 adev->vcn.inst_mask |=
1268 (1U << ip->instance_number);
1269 adev->jpeg.inst_mask |=
1270 (1U << ip->instance_number);
1272 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n",
1273 adev->vcn.num_vcn_inst + 1,
1274 AMDGPU_MAX_VCN_INSTANCES);
1277 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1278 le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1279 le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1280 le16_to_cpu(ip->hw_id) == SDMA3_HWID) {
1281 if (adev->sdma.num_instances <
1282 AMDGPU_MAX_SDMA_INSTANCES) {
1283 adev->sdma.num_instances++;
1284 adev->sdma.sdma_mask |=
1285 (1U << ip->instance_number);
1287 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n",
1288 adev->sdma.num_instances + 1,
1289 AMDGPU_MAX_SDMA_INSTANCES);
1293 if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
1294 adev->gmc.num_umc++;
1295 adev->umc.node_inst_num++;
1298 if (le16_to_cpu(ip->hw_id) == GC_HWID)
1299 adev->gfx.xcc_mask |=
1300 (1U << ip->instance_number);
1302 for (k = 0; k < num_base_address; k++) {
1304 * convert the endianness of base addresses in place,
1305 * so that we don't need to convert them when accessing adev->reg_offset.
1307 if (ihdr->base_addr_64_bit)
1308 /* Truncate the 64bit base address from ip discovery
1309 * and only store lower 32bit ip base in reg_offset[].
1310 * Bits > 32 follows ASIC specific format, thus just
1311 * discard them and handle it within specific ASIC.
1312 * By this way reg_offset[] and related helpers can
1314 * The base address is in dwords, thus clear the
1315 * highest 2 bits to store.
1317 ip->base_address[k] =
1318 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
1320 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1321 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1324 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1325 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) &&
1326 hw_id_map[hw_ip] != 0) {
1327 DRM_DEBUG("set register base offset for %s\n",
1328 hw_id_names[le16_to_cpu(ip->hw_id)]);
1329 adev->reg_offset[hw_ip][ip->instance_number] =
1331 /* Instance support is somewhat inconsistent.
1332 * SDMA is a good example. Sienna cichlid has 4 total
1333 * SDMA instances, each enumerated separately (HWIDs
1334 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances,
1335 * but they are enumerated as multiple instances of the
1336 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another
1337 * example. On most chips there are multiple instances
1338 * with the same HWID.
1341 if (ihdr->version < 3) {
1345 subrev = ip->sub_revision;
1346 variant = ip->variant;
1349 adev->ip_versions[hw_ip]
1350 [ip->instance_number] =
1351 IP_VERSION_FULL(ip->major,
1360 if (ihdr->base_addr_64_bit)
1361 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
1363 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1370 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1372 int vcn_harvest_count = 0;
1373 int umc_harvest_count = 0;
1376 * Harvest table does not fit Navi1x and legacy GPUs,
1377 * so read harvest bit per IP data structure to set
1378 * harvest configuration.
1380 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) &&
1381 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) {
1382 if ((adev->pdev->device == 0x731E &&
1383 (adev->pdev->revision == 0xC6 ||
1384 adev->pdev->revision == 0xC7)) ||
1385 (adev->pdev->device == 0x7340 &&
1386 adev->pdev->revision == 0xC9) ||
1387 (adev->pdev->device == 0x7360 &&
1388 adev->pdev->revision == 0xC7))
1389 amdgpu_discovery_read_harvest_bit_per_ip(adev,
1390 &vcn_harvest_count);
1392 amdgpu_discovery_read_from_harvest_table(adev,
1394 &umc_harvest_count);
1397 amdgpu_discovery_harvest_config_quirk(adev);
1399 if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1400 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1401 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1404 if (umc_harvest_count < adev->gmc.num_umc) {
1405 adev->gmc.num_umc -= umc_harvest_count;
1410 struct gc_info_v1_0 v1;
1411 struct gc_info_v1_1 v1_1;
1412 struct gc_info_v1_2 v1_2;
1413 struct gc_info_v2_0 v2;
1414 struct gc_info_v2_1 v2_1;
1417 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1419 struct binary_header *bhdr;
1420 union gc_info *gc_info;
1423 if (!adev->mman.discovery_bin) {
1424 DRM_ERROR("ip discovery uninitialized\n");
1428 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1429 offset = le16_to_cpu(bhdr->table_list[GC].offset);
1434 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset);
1436 switch (le16_to_cpu(gc_info->v1.header.version_major)) {
1438 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1439 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1440 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1441 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1442 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1443 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1444 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1445 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1446 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1447 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1448 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1449 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1450 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1451 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1452 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1453 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1454 le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1455 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1456 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) {
1457 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
1458 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
1459 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
1461 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) {
1462 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
1463 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
1464 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
1465 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
1466 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
1467 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1468 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1469 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1473 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1474 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1475 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1476 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1477 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1478 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1479 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1480 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1481 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1482 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1483 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1484 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1485 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1486 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1487 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1488 le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1489 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1490 if (le16_to_cpu(gc_info->v2.header.version_minor == 1)) {
1491 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh);
1492 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu);
1493 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */
1494 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc);
1495 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc);
1496 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc);
1497 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */
1502 "Unhandled GC info table %d.%d\n",
1503 le16_to_cpu(gc_info->v1.header.version_major),
1504 le16_to_cpu(gc_info->v1.header.version_minor));
1511 struct mall_info_v1_0 v1;
1512 struct mall_info_v2_0 v2;
1515 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
1517 struct binary_header *bhdr;
1518 union mall_info *mall_info;
1519 u32 u, mall_size_per_umc, m_s_present, half_use;
1523 if (!adev->mman.discovery_bin) {
1524 DRM_ERROR("ip discovery uninitialized\n");
1528 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1529 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset);
1534 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset);
1536 switch (le16_to_cpu(mall_info->v1.header.version_major)) {
1539 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
1540 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
1541 half_use = le32_to_cpu(mall_info->v1.m_half_use);
1542 for (u = 0; u < adev->gmc.num_umc; u++) {
1543 if (m_s_present & (1 << u))
1544 mall_size += mall_size_per_umc * 2;
1545 else if (half_use & (1 << u))
1546 mall_size += mall_size_per_umc / 2;
1548 mall_size += mall_size_per_umc;
1550 adev->gmc.mall_size = mall_size;
1551 adev->gmc.m_half_use = half_use;
1554 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc);
1555 adev->gmc.mall_size = mall_size_per_umc * adev->gmc.num_umc;
1559 "Unhandled MALL info table %d.%d\n",
1560 le16_to_cpu(mall_info->v1.header.version_major),
1561 le16_to_cpu(mall_info->v1.header.version_minor));
1568 struct vcn_info_v1_0 v1;
1571 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
1573 struct binary_header *bhdr;
1574 union vcn_info *vcn_info;
1578 if (!adev->mman.discovery_bin) {
1579 DRM_ERROR("ip discovery uninitialized\n");
1583 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1584 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
1585 * but that may change in the future with new GPUs so keep this
1586 * check for defensive purposes.
1588 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
1589 dev_err(adev->dev, "invalid vcn instances\n");
1593 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1594 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset);
1599 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset);
1601 switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
1603 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1604 * so this won't overflow.
1606 for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
1607 adev->vcn.vcn_codec_disable_mask[v] =
1608 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
1613 "Unhandled VCN info table %d.%d\n",
1614 le16_to_cpu(vcn_info->v1.header.version_major),
1615 le16_to_cpu(vcn_info->v1.header.version_minor));
1621 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1623 /* what IP to use for this? */
1624 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1625 case IP_VERSION(9, 0, 1):
1626 case IP_VERSION(9, 1, 0):
1627 case IP_VERSION(9, 2, 1):
1628 case IP_VERSION(9, 2, 2):
1629 case IP_VERSION(9, 3, 0):
1630 case IP_VERSION(9, 4, 0):
1631 case IP_VERSION(9, 4, 1):
1632 case IP_VERSION(9, 4, 2):
1633 case IP_VERSION(9, 4, 3):
1634 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1636 case IP_VERSION(10, 1, 10):
1637 case IP_VERSION(10, 1, 1):
1638 case IP_VERSION(10, 1, 2):
1639 case IP_VERSION(10, 1, 3):
1640 case IP_VERSION(10, 1, 4):
1641 case IP_VERSION(10, 3, 0):
1642 case IP_VERSION(10, 3, 1):
1643 case IP_VERSION(10, 3, 2):
1644 case IP_VERSION(10, 3, 3):
1645 case IP_VERSION(10, 3, 4):
1646 case IP_VERSION(10, 3, 5):
1647 case IP_VERSION(10, 3, 6):
1648 case IP_VERSION(10, 3, 7):
1649 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1651 case IP_VERSION(11, 0, 0):
1652 case IP_VERSION(11, 0, 1):
1653 case IP_VERSION(11, 0, 2):
1654 case IP_VERSION(11, 0, 3):
1655 case IP_VERSION(11, 0, 4):
1656 case IP_VERSION(11, 5, 0):
1657 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
1661 "Failed to add common ip block(GC_HWIP:0x%x)\n",
1662 amdgpu_ip_version(adev, GC_HWIP, 0));
1668 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1670 /* use GC or MMHUB IP version */
1671 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1672 case IP_VERSION(9, 0, 1):
1673 case IP_VERSION(9, 1, 0):
1674 case IP_VERSION(9, 2, 1):
1675 case IP_VERSION(9, 2, 2):
1676 case IP_VERSION(9, 3, 0):
1677 case IP_VERSION(9, 4, 0):
1678 case IP_VERSION(9, 4, 1):
1679 case IP_VERSION(9, 4, 2):
1680 case IP_VERSION(9, 4, 3):
1681 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1683 case IP_VERSION(10, 1, 10):
1684 case IP_VERSION(10, 1, 1):
1685 case IP_VERSION(10, 1, 2):
1686 case IP_VERSION(10, 1, 3):
1687 case IP_VERSION(10, 1, 4):
1688 case IP_VERSION(10, 3, 0):
1689 case IP_VERSION(10, 3, 1):
1690 case IP_VERSION(10, 3, 2):
1691 case IP_VERSION(10, 3, 3):
1692 case IP_VERSION(10, 3, 4):
1693 case IP_VERSION(10, 3, 5):
1694 case IP_VERSION(10, 3, 6):
1695 case IP_VERSION(10, 3, 7):
1696 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1698 case IP_VERSION(11, 0, 0):
1699 case IP_VERSION(11, 0, 1):
1700 case IP_VERSION(11, 0, 2):
1701 case IP_VERSION(11, 0, 3):
1702 case IP_VERSION(11, 0, 4):
1703 case IP_VERSION(11, 5, 0):
1704 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
1707 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1708 amdgpu_ip_version(adev, GC_HWIP, 0));
1714 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1716 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) {
1717 case IP_VERSION(4, 0, 0):
1718 case IP_VERSION(4, 0, 1):
1719 case IP_VERSION(4, 1, 0):
1720 case IP_VERSION(4, 1, 1):
1721 case IP_VERSION(4, 3, 0):
1722 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1724 case IP_VERSION(4, 2, 0):
1725 case IP_VERSION(4, 2, 1):
1726 case IP_VERSION(4, 4, 0):
1727 case IP_VERSION(4, 4, 2):
1728 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1730 case IP_VERSION(5, 0, 0):
1731 case IP_VERSION(5, 0, 1):
1732 case IP_VERSION(5, 0, 2):
1733 case IP_VERSION(5, 0, 3):
1734 case IP_VERSION(5, 2, 0):
1735 case IP_VERSION(5, 2, 1):
1736 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1738 case IP_VERSION(6, 0, 0):
1739 case IP_VERSION(6, 0, 1):
1740 case IP_VERSION(6, 0, 2):
1741 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
1743 case IP_VERSION(6, 1, 0):
1744 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block);
1748 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1749 amdgpu_ip_version(adev, OSSSYS_HWIP, 0));
1755 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1757 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
1758 case IP_VERSION(9, 0, 0):
1759 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1761 case IP_VERSION(10, 0, 0):
1762 case IP_VERSION(10, 0, 1):
1763 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1765 case IP_VERSION(11, 0, 0):
1766 case IP_VERSION(11, 0, 2):
1767 case IP_VERSION(11, 0, 4):
1768 case IP_VERSION(11, 0, 5):
1769 case IP_VERSION(11, 0, 9):
1770 case IP_VERSION(11, 0, 7):
1771 case IP_VERSION(11, 0, 11):
1772 case IP_VERSION(11, 0, 12):
1773 case IP_VERSION(11, 0, 13):
1774 case IP_VERSION(11, 5, 0):
1775 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1777 case IP_VERSION(11, 0, 8):
1778 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1780 case IP_VERSION(11, 0, 3):
1781 case IP_VERSION(12, 0, 1):
1782 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1784 case IP_VERSION(13, 0, 0):
1785 case IP_VERSION(13, 0, 1):
1786 case IP_VERSION(13, 0, 2):
1787 case IP_VERSION(13, 0, 3):
1788 case IP_VERSION(13, 0, 5):
1789 case IP_VERSION(13, 0, 6):
1790 case IP_VERSION(13, 0, 7):
1791 case IP_VERSION(13, 0, 8):
1792 case IP_VERSION(13, 0, 10):
1793 case IP_VERSION(13, 0, 11):
1794 case IP_VERSION(14, 0, 0):
1795 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1797 case IP_VERSION(13, 0, 4):
1798 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block);
1802 "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1803 amdgpu_ip_version(adev, MP0_HWIP, 0));
1809 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1811 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1812 case IP_VERSION(9, 0, 0):
1813 case IP_VERSION(10, 0, 0):
1814 case IP_VERSION(10, 0, 1):
1815 case IP_VERSION(11, 0, 2):
1816 if (adev->asic_type == CHIP_ARCTURUS)
1817 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1819 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1821 case IP_VERSION(11, 0, 0):
1822 case IP_VERSION(11, 0, 5):
1823 case IP_VERSION(11, 0, 9):
1824 case IP_VERSION(11, 0, 7):
1825 case IP_VERSION(11, 0, 8):
1826 case IP_VERSION(11, 0, 11):
1827 case IP_VERSION(11, 0, 12):
1828 case IP_VERSION(11, 0, 13):
1829 case IP_VERSION(11, 5, 0):
1830 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1832 case IP_VERSION(12, 0, 0):
1833 case IP_VERSION(12, 0, 1):
1834 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1836 case IP_VERSION(13, 0, 0):
1837 case IP_VERSION(13, 0, 1):
1838 case IP_VERSION(13, 0, 2):
1839 case IP_VERSION(13, 0, 3):
1840 case IP_VERSION(13, 0, 4):
1841 case IP_VERSION(13, 0, 5):
1842 case IP_VERSION(13, 0, 6):
1843 case IP_VERSION(13, 0, 7):
1844 case IP_VERSION(13, 0, 8):
1845 case IP_VERSION(13, 0, 10):
1846 case IP_VERSION(13, 0, 11):
1847 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1849 case IP_VERSION(14, 0, 0):
1850 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);
1854 "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
1855 amdgpu_ip_version(adev, MP1_HWIP, 0));
1861 #if defined(CONFIG_DRM_AMD_DC)
1862 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
1864 amdgpu_device_set_sriov_virtual_display(adev);
1865 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1869 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
1871 if (adev->enable_virtual_display) {
1872 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1876 if (!amdgpu_device_has_dc_support(adev))
1879 #if defined(CONFIG_DRM_AMD_DC)
1880 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1881 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1882 case IP_VERSION(1, 0, 0):
1883 case IP_VERSION(1, 0, 1):
1884 case IP_VERSION(2, 0, 2):
1885 case IP_VERSION(2, 0, 0):
1886 case IP_VERSION(2, 0, 3):
1887 case IP_VERSION(2, 1, 0):
1888 case IP_VERSION(3, 0, 0):
1889 case IP_VERSION(3, 0, 2):
1890 case IP_VERSION(3, 0, 3):
1891 case IP_VERSION(3, 0, 1):
1892 case IP_VERSION(3, 1, 2):
1893 case IP_VERSION(3, 1, 3):
1894 case IP_VERSION(3, 1, 4):
1895 case IP_VERSION(3, 1, 5):
1896 case IP_VERSION(3, 1, 6):
1897 case IP_VERSION(3, 2, 0):
1898 case IP_VERSION(3, 2, 1):
1899 case IP_VERSION(3, 5, 0):
1900 if (amdgpu_sriov_vf(adev))
1901 amdgpu_discovery_set_sriov_display(adev);
1903 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1907 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
1908 amdgpu_ip_version(adev, DCE_HWIP, 0));
1911 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
1912 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
1913 case IP_VERSION(12, 0, 0):
1914 case IP_VERSION(12, 0, 1):
1915 case IP_VERSION(12, 1, 0):
1916 if (amdgpu_sriov_vf(adev))
1917 amdgpu_discovery_set_sriov_display(adev);
1919 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1923 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
1924 amdgpu_ip_version(adev, DCI_HWIP, 0));
1932 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
1934 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1935 case IP_VERSION(9, 0, 1):
1936 case IP_VERSION(9, 1, 0):
1937 case IP_VERSION(9, 2, 1):
1938 case IP_VERSION(9, 2, 2):
1939 case IP_VERSION(9, 3, 0):
1940 case IP_VERSION(9, 4, 0):
1941 case IP_VERSION(9, 4, 1):
1942 case IP_VERSION(9, 4, 2):
1943 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1945 case IP_VERSION(9, 4, 3):
1946 if (!amdgpu_exp_hw_support)
1948 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);
1950 case IP_VERSION(10, 1, 10):
1951 case IP_VERSION(10, 1, 2):
1952 case IP_VERSION(10, 1, 1):
1953 case IP_VERSION(10, 1, 3):
1954 case IP_VERSION(10, 1, 4):
1955 case IP_VERSION(10, 3, 0):
1956 case IP_VERSION(10, 3, 2):
1957 case IP_VERSION(10, 3, 1):
1958 case IP_VERSION(10, 3, 4):
1959 case IP_VERSION(10, 3, 5):
1960 case IP_VERSION(10, 3, 6):
1961 case IP_VERSION(10, 3, 3):
1962 case IP_VERSION(10, 3, 7):
1963 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1965 case IP_VERSION(11, 0, 0):
1966 case IP_VERSION(11, 0, 1):
1967 case IP_VERSION(11, 0, 2):
1968 case IP_VERSION(11, 0, 3):
1969 case IP_VERSION(11, 0, 4):
1970 case IP_VERSION(11, 5, 0):
1971 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
1974 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
1975 amdgpu_ip_version(adev, GC_HWIP, 0));
1981 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
1983 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1984 case IP_VERSION(4, 0, 0):
1985 case IP_VERSION(4, 0, 1):
1986 case IP_VERSION(4, 1, 0):
1987 case IP_VERSION(4, 1, 1):
1988 case IP_VERSION(4, 1, 2):
1989 case IP_VERSION(4, 2, 0):
1990 case IP_VERSION(4, 2, 2):
1991 case IP_VERSION(4, 4, 0):
1992 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1994 case IP_VERSION(4, 4, 2):
1995 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block);
1997 case IP_VERSION(5, 0, 0):
1998 case IP_VERSION(5, 0, 1):
1999 case IP_VERSION(5, 0, 2):
2000 case IP_VERSION(5, 0, 5):
2001 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
2003 case IP_VERSION(5, 2, 0):
2004 case IP_VERSION(5, 2, 2):
2005 case IP_VERSION(5, 2, 4):
2006 case IP_VERSION(5, 2, 5):
2007 case IP_VERSION(5, 2, 6):
2008 case IP_VERSION(5, 2, 3):
2009 case IP_VERSION(5, 2, 1):
2010 case IP_VERSION(5, 2, 7):
2011 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
2013 case IP_VERSION(6, 0, 0):
2014 case IP_VERSION(6, 0, 1):
2015 case IP_VERSION(6, 0, 2):
2016 case IP_VERSION(6, 0, 3):
2017 case IP_VERSION(6, 1, 0):
2018 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
2022 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
2023 amdgpu_ip_version(adev, SDMA0_HWIP, 0));
2029 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
2031 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2032 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2033 case IP_VERSION(7, 0, 0):
2034 case IP_VERSION(7, 2, 0):
2035 /* UVD is not supported on vega20 SR-IOV */
2036 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2037 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
2041 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
2042 amdgpu_ip_version(adev, UVD_HWIP, 0));
2045 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2046 case IP_VERSION(4, 0, 0):
2047 case IP_VERSION(4, 1, 0):
2048 /* VCE is not supported on vega20 SR-IOV */
2049 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2050 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
2054 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
2055 amdgpu_ip_version(adev, VCE_HWIP, 0));
2059 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2060 case IP_VERSION(1, 0, 0):
2061 case IP_VERSION(1, 0, 1):
2062 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
2064 case IP_VERSION(2, 0, 0):
2065 case IP_VERSION(2, 0, 2):
2066 case IP_VERSION(2, 2, 0):
2067 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
2068 if (!amdgpu_sriov_vf(adev))
2069 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
2071 case IP_VERSION(2, 0, 3):
2073 case IP_VERSION(2, 5, 0):
2074 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
2075 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
2077 case IP_VERSION(2, 6, 0):
2078 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
2079 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
2081 case IP_VERSION(3, 0, 0):
2082 case IP_VERSION(3, 0, 16):
2083 case IP_VERSION(3, 1, 1):
2084 case IP_VERSION(3, 1, 2):
2085 case IP_VERSION(3, 0, 2):
2086 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2087 if (!amdgpu_sriov_vf(adev))
2088 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
2090 case IP_VERSION(3, 0, 33):
2091 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2093 case IP_VERSION(4, 0, 0):
2094 case IP_VERSION(4, 0, 2):
2095 case IP_VERSION(4, 0, 4):
2096 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
2097 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
2099 case IP_VERSION(4, 0, 3):
2100 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
2101 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
2103 case IP_VERSION(4, 0, 5):
2104 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
2105 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
2109 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
2110 amdgpu_ip_version(adev, UVD_HWIP, 0));
2117 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
2119 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2120 case IP_VERSION(10, 1, 10):
2121 case IP_VERSION(10, 1, 1):
2122 case IP_VERSION(10, 1, 2):
2123 case IP_VERSION(10, 1, 3):
2124 case IP_VERSION(10, 1, 4):
2125 case IP_VERSION(10, 3, 0):
2126 case IP_VERSION(10, 3, 1):
2127 case IP_VERSION(10, 3, 2):
2128 case IP_VERSION(10, 3, 3):
2129 case IP_VERSION(10, 3, 4):
2130 case IP_VERSION(10, 3, 5):
2131 case IP_VERSION(10, 3, 6):
2133 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
2134 adev->enable_mes = true;
2136 adev->enable_mes_kiq = true;
2139 case IP_VERSION(11, 0, 0):
2140 case IP_VERSION(11, 0, 1):
2141 case IP_VERSION(11, 0, 2):
2142 case IP_VERSION(11, 0, 3):
2143 case IP_VERSION(11, 0, 4):
2144 case IP_VERSION(11, 5, 0):
2145 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
2146 adev->enable_mes = true;
2147 adev->enable_mes_kiq = true;
2155 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)
2157 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2158 case IP_VERSION(9, 4, 3):
2159 aqua_vanjaram_init_soc_config(adev);
2166 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev)
2168 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
2169 case IP_VERSION(6, 1, 0):
2170 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block);
2179 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)
2181 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
2182 case IP_VERSION(4, 0, 5):
2183 if (amdgpu_umsch_mm & 0x1) {
2184 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block);
2185 adev->enable_umsch_mm = true;
2195 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
2199 switch (adev->asic_type) {
2201 vega10_reg_base_init(adev);
2202 adev->sdma.num_instances = 2;
2203 adev->gmc.num_umc = 4;
2204 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2205 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2206 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
2207 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
2208 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
2209 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
2210 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2211 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
2212 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
2213 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2214 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2215 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2216 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
2217 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
2218 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2219 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2220 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
2223 vega10_reg_base_init(adev);
2224 adev->sdma.num_instances = 2;
2225 adev->gmc.num_umc = 4;
2226 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2227 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2228 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
2229 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
2230 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
2231 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
2232 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
2233 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
2234 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
2235 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2236 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2237 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2238 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
2239 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
2240 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2241 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2242 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
2245 vega10_reg_base_init(adev);
2246 adev->sdma.num_instances = 1;
2247 adev->vcn.num_vcn_inst = 1;
2248 adev->gmc.num_umc = 2;
2249 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
2250 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2251 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2252 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
2253 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
2254 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
2255 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
2256 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
2257 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
2258 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
2259 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
2260 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
2261 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
2262 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
2263 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
2264 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
2266 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2267 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2268 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
2269 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
2270 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
2271 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2272 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
2273 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
2274 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
2275 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
2276 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
2277 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
2278 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
2279 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
2280 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
2284 vega20_reg_base_init(adev);
2285 adev->sdma.num_instances = 2;
2286 adev->gmc.num_umc = 8;
2287 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2288 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2289 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
2290 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
2291 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
2292 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
2293 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
2294 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
2295 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
2296 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
2297 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2298 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
2299 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
2300 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
2301 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
2302 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
2303 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
2304 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
2307 arct_reg_base_init(adev);
2308 adev->sdma.num_instances = 8;
2309 adev->vcn.num_vcn_inst = 2;
2310 adev->gmc.num_umc = 8;
2311 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2312 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2313 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
2314 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
2315 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
2316 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
2317 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
2318 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
2319 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
2320 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
2321 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
2322 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
2323 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
2324 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
2325 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
2326 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
2327 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2328 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
2329 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
2330 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
2331 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
2332 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
2334 case CHIP_ALDEBARAN:
2335 aldebaran_reg_base_init(adev);
2336 adev->sdma.num_instances = 5;
2337 adev->vcn.num_vcn_inst = 2;
2338 adev->gmc.num_umc = 4;
2339 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2340 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2341 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
2342 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
2343 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
2344 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
2345 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
2346 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
2347 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
2348 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
2349 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
2350 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
2351 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
2352 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
2353 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
2354 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
2355 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
2356 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
2357 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
2358 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
2361 r = amdgpu_discovery_reg_base_init(adev);
2365 amdgpu_discovery_harvest_ip(adev);
2366 amdgpu_discovery_get_gfx_info(adev);
2367 amdgpu_discovery_get_mall_info(adev);
2368 amdgpu_discovery_get_vcn_info(adev);
2372 amdgpu_discovery_init_soc_config(adev);
2373 amdgpu_discovery_sysfs_init(adev);
2375 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2376 case IP_VERSION(9, 0, 1):
2377 case IP_VERSION(9, 2, 1):
2378 case IP_VERSION(9, 4, 0):
2379 case IP_VERSION(9, 4, 1):
2380 case IP_VERSION(9, 4, 2):
2381 case IP_VERSION(9, 4, 3):
2382 adev->family = AMDGPU_FAMILY_AI;
2384 case IP_VERSION(9, 1, 0):
2385 case IP_VERSION(9, 2, 2):
2386 case IP_VERSION(9, 3, 0):
2387 adev->family = AMDGPU_FAMILY_RV;
2389 case IP_VERSION(10, 1, 10):
2390 case IP_VERSION(10, 1, 1):
2391 case IP_VERSION(10, 1, 2):
2392 case IP_VERSION(10, 1, 3):
2393 case IP_VERSION(10, 1, 4):
2394 case IP_VERSION(10, 3, 0):
2395 case IP_VERSION(10, 3, 2):
2396 case IP_VERSION(10, 3, 4):
2397 case IP_VERSION(10, 3, 5):
2398 adev->family = AMDGPU_FAMILY_NV;
2400 case IP_VERSION(10, 3, 1):
2401 adev->family = AMDGPU_FAMILY_VGH;
2402 adev->apu_flags |= AMD_APU_IS_VANGOGH;
2404 case IP_VERSION(10, 3, 3):
2405 adev->family = AMDGPU_FAMILY_YC;
2407 case IP_VERSION(10, 3, 6):
2408 adev->family = AMDGPU_FAMILY_GC_10_3_6;
2410 case IP_VERSION(10, 3, 7):
2411 adev->family = AMDGPU_FAMILY_GC_10_3_7;
2413 case IP_VERSION(11, 0, 0):
2414 case IP_VERSION(11, 0, 2):
2415 case IP_VERSION(11, 0, 3):
2416 adev->family = AMDGPU_FAMILY_GC_11_0_0;
2418 case IP_VERSION(11, 0, 1):
2419 case IP_VERSION(11, 0, 4):
2420 adev->family = AMDGPU_FAMILY_GC_11_0_1;
2422 case IP_VERSION(11, 5, 0):
2423 adev->family = AMDGPU_FAMILY_GC_11_5_0;
2429 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2430 case IP_VERSION(9, 1, 0):
2431 case IP_VERSION(9, 2, 2):
2432 case IP_VERSION(9, 3, 0):
2433 case IP_VERSION(10, 1, 3):
2434 case IP_VERSION(10, 1, 4):
2435 case IP_VERSION(10, 3, 1):
2436 case IP_VERSION(10, 3, 3):
2437 case IP_VERSION(10, 3, 6):
2438 case IP_VERSION(10, 3, 7):
2439 case IP_VERSION(11, 0, 1):
2440 case IP_VERSION(11, 0, 4):
2441 case IP_VERSION(11, 5, 0):
2442 adev->flags |= AMD_IS_APU;
2448 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0))
2449 adev->gmc.xgmi.supported = true;
2451 /* set NBIO version */
2452 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
2453 case IP_VERSION(6, 1, 0):
2454 case IP_VERSION(6, 2, 0):
2455 adev->nbio.funcs = &nbio_v6_1_funcs;
2456 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
2458 case IP_VERSION(7, 0, 0):
2459 case IP_VERSION(7, 0, 1):
2460 case IP_VERSION(2, 5, 0):
2461 adev->nbio.funcs = &nbio_v7_0_funcs;
2462 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
2464 case IP_VERSION(7, 4, 0):
2465 case IP_VERSION(7, 4, 1):
2466 case IP_VERSION(7, 4, 4):
2467 adev->nbio.funcs = &nbio_v7_4_funcs;
2468 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
2470 case IP_VERSION(7, 9, 0):
2471 adev->nbio.funcs = &nbio_v7_9_funcs;
2472 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg;
2474 case IP_VERSION(7, 11, 0):
2475 adev->nbio.funcs = &nbio_v7_11_funcs;
2476 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg;
2478 case IP_VERSION(7, 2, 0):
2479 case IP_VERSION(7, 2, 1):
2480 case IP_VERSION(7, 3, 0):
2481 case IP_VERSION(7, 5, 0):
2482 case IP_VERSION(7, 5, 1):
2483 adev->nbio.funcs = &nbio_v7_2_funcs;
2484 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
2486 case IP_VERSION(2, 1, 1):
2487 case IP_VERSION(2, 3, 0):
2488 case IP_VERSION(2, 3, 1):
2489 case IP_VERSION(2, 3, 2):
2490 case IP_VERSION(3, 3, 0):
2491 case IP_VERSION(3, 3, 1):
2492 case IP_VERSION(3, 3, 2):
2493 case IP_VERSION(3, 3, 3):
2494 adev->nbio.funcs = &nbio_v2_3_funcs;
2495 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
2497 case IP_VERSION(4, 3, 0):
2498 case IP_VERSION(4, 3, 1):
2499 if (amdgpu_sriov_vf(adev))
2500 adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
2502 adev->nbio.funcs = &nbio_v4_3_funcs;
2503 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
2505 case IP_VERSION(7, 7, 0):
2506 case IP_VERSION(7, 7, 1):
2507 adev->nbio.funcs = &nbio_v7_7_funcs;
2508 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
2514 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
2515 case IP_VERSION(4, 0, 0):
2516 case IP_VERSION(4, 0, 1):
2517 case IP_VERSION(4, 1, 0):
2518 case IP_VERSION(4, 1, 1):
2519 case IP_VERSION(4, 1, 2):
2520 case IP_VERSION(4, 2, 0):
2521 case IP_VERSION(4, 2, 1):
2522 case IP_VERSION(4, 4, 0):
2523 case IP_VERSION(4, 4, 2):
2524 adev->hdp.funcs = &hdp_v4_0_funcs;
2526 case IP_VERSION(5, 0, 0):
2527 case IP_VERSION(5, 0, 1):
2528 case IP_VERSION(5, 0, 2):
2529 case IP_VERSION(5, 0, 3):
2530 case IP_VERSION(5, 0, 4):
2531 case IP_VERSION(5, 2, 0):
2532 adev->hdp.funcs = &hdp_v5_0_funcs;
2534 case IP_VERSION(5, 2, 1):
2535 adev->hdp.funcs = &hdp_v5_2_funcs;
2537 case IP_VERSION(6, 0, 0):
2538 case IP_VERSION(6, 0, 1):
2539 case IP_VERSION(6, 1, 0):
2540 adev->hdp.funcs = &hdp_v6_0_funcs;
2546 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) {
2547 case IP_VERSION(3, 6, 0):
2548 case IP_VERSION(3, 6, 1):
2549 case IP_VERSION(3, 6, 2):
2550 adev->df.funcs = &df_v3_6_funcs;
2552 case IP_VERSION(2, 1, 0):
2553 case IP_VERSION(2, 1, 1):
2554 case IP_VERSION(2, 5, 0):
2555 case IP_VERSION(3, 5, 1):
2556 case IP_VERSION(3, 5, 2):
2557 adev->df.funcs = &df_v1_7_funcs;
2559 case IP_VERSION(4, 3, 0):
2560 adev->df.funcs = &df_v4_3_funcs;
2566 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) {
2567 case IP_VERSION(9, 0, 0):
2568 case IP_VERSION(9, 0, 1):
2569 case IP_VERSION(10, 0, 0):
2570 case IP_VERSION(10, 0, 1):
2571 case IP_VERSION(10, 0, 2):
2572 adev->smuio.funcs = &smuio_v9_0_funcs;
2574 case IP_VERSION(11, 0, 0):
2575 case IP_VERSION(11, 0, 2):
2576 case IP_VERSION(11, 0, 3):
2577 case IP_VERSION(11, 0, 4):
2578 case IP_VERSION(11, 0, 7):
2579 case IP_VERSION(11, 0, 8):
2580 adev->smuio.funcs = &smuio_v11_0_funcs;
2582 case IP_VERSION(11, 0, 6):
2583 case IP_VERSION(11, 0, 10):
2584 case IP_VERSION(11, 0, 11):
2585 case IP_VERSION(11, 5, 0):
2586 case IP_VERSION(13, 0, 1):
2587 case IP_VERSION(13, 0, 9):
2588 case IP_VERSION(13, 0, 10):
2589 adev->smuio.funcs = &smuio_v11_0_6_funcs;
2591 case IP_VERSION(13, 0, 2):
2592 adev->smuio.funcs = &smuio_v13_0_funcs;
2594 case IP_VERSION(13, 0, 3):
2595 adev->smuio.funcs = &smuio_v13_0_3_funcs;
2596 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) {
2597 adev->flags |= AMD_IS_APU;
2600 case IP_VERSION(13, 0, 6):
2601 case IP_VERSION(13, 0, 8):
2602 case IP_VERSION(14, 0, 0):
2603 adev->smuio.funcs = &smuio_v13_0_6_funcs;
2609 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
2610 case IP_VERSION(6, 0, 0):
2611 case IP_VERSION(6, 0, 1):
2612 case IP_VERSION(6, 0, 2):
2613 case IP_VERSION(6, 0, 3):
2614 adev->lsdma.funcs = &lsdma_v6_0_funcs;
2620 r = amdgpu_discovery_set_common_ip_blocks(adev);
2624 r = amdgpu_discovery_set_gmc_ip_blocks(adev);
2628 /* For SR-IOV, PSP needs to be initialized before IH */
2629 if (amdgpu_sriov_vf(adev)) {
2630 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2633 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2637 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2641 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2642 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2648 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2649 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2654 r = amdgpu_discovery_set_display_ip_blocks(adev);
2658 r = amdgpu_discovery_set_gc_ip_blocks(adev);
2662 r = amdgpu_discovery_set_sdma_ip_blocks(adev);
2666 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
2667 !amdgpu_sriov_vf(adev)) ||
2668 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
2669 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2674 r = amdgpu_discovery_set_mm_ip_blocks(adev);
2678 r = amdgpu_discovery_set_mes_ip_blocks(adev);
2682 r = amdgpu_discovery_set_vpe_ip_blocks(adev);
2686 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev);