2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_discovery.h"
28 #include "soc15_hw_ip.h"
29 #include "discovery.h"
36 #include "nbio_v6_1.h"
37 #include "nbio_v7_0.h"
38 #include "nbio_v7_4.h"
40 #include "vega10_ih.h"
41 #include "vega20_ih.h"
42 #include "sdma_v4_0.h"
47 #include "jpeg_v2_5.h"
48 #include "smuio_v9_0.h"
49 #include "gmc_v10_0.h"
50 #include "gfxhub_v2_0.h"
51 #include "mmhub_v2_0.h"
52 #include "nbio_v2_3.h"
53 #include "nbio_v7_2.h"
56 #include "navi10_ih.h"
57 #include "gfx_v10_0.h"
58 #include "sdma_v5_0.h"
59 #include "sdma_v5_2.h"
61 #include "jpeg_v2_0.h"
63 #include "jpeg_v3_0.h"
64 #include "amdgpu_vkms.h"
65 #include "mes_v10_1.h"
66 #include "smuio_v11_0.h"
67 #include "smuio_v11_0_6.h"
68 #include "smuio_v13_0.h"
70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
73 #define mmRCC_CONFIG_MEMSIZE 0xde3
74 #define mmMM_INDEX 0x0
75 #define mmMM_INDEX_HI 0x6
78 static const char *hw_id_names[HW_ID_MAX] = {
82 [SMUIO_HWID] = "SMUIO",
88 [AUDIO_AZ_HWID] = "AUDIO_AZ",
95 [DCEAZ_HWID] = "DCEAZ",
97 [SDPMUX_HWID] = "SDPMUX",
100 [L2IMU_HWID] = "L2IMU",
102 [MMHUB_HWID] = "MMHUB",
103 [ATHUB_HWID] = "ATHUB",
104 [DBGU_NBIO_HWID] = "DBGU_NBIO",
106 [DBGU0_HWID] = "DBGU0",
107 [DBGU1_HWID] = "DBGU1",
108 [OSSSYS_HWID] = "OSSSYS",
110 [SDMA0_HWID] = "SDMA0",
111 [SDMA1_HWID] = "SDMA1",
112 [SDMA2_HWID] = "SDMA2",
113 [SDMA3_HWID] = "SDMA3",
115 [DBGU_IO_HWID] = "DBGU_IO",
117 [CLKB_HWID] = "CLKB",
119 [DFX_DAP_HWID] = "DFX_DAP",
120 [L1IMU_PCIE_HWID] = "L1IMU_PCIE",
121 [L1IMU_NBIF_HWID] = "L1IMU_NBIF",
122 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
123 [L1IMU3_HWID] = "L1IMU3",
124 [L1IMU4_HWID] = "L1IMU4",
125 [L1IMU5_HWID] = "L1IMU5",
126 [L1IMU6_HWID] = "L1IMU6",
127 [L1IMU7_HWID] = "L1IMU7",
128 [L1IMU8_HWID] = "L1IMU8",
129 [L1IMU9_HWID] = "L1IMU9",
130 [L1IMU10_HWID] = "L1IMU10",
131 [L1IMU11_HWID] = "L1IMU11",
132 [L1IMU12_HWID] = "L1IMU12",
133 [L1IMU13_HWID] = "L1IMU13",
134 [L1IMU14_HWID] = "L1IMU14",
135 [L1IMU15_HWID] = "L1IMU15",
136 [WAFLC_HWID] = "WAFLC",
137 [FCH_USB_PD_HWID] = "FCH_USB_PD",
138 [PCIE_HWID] = "PCIE",
140 [DDCL_HWID] = "DDCL",
142 [IOAGR_HWID] = "IOAGR",
143 [NBIF_HWID] = "NBIF",
144 [IOAPIC_HWID] = "IOAPIC",
145 [SYSTEMHUB_HWID] = "SYSTEMHUB",
146 [NTBCCP_HWID] = "NTBCCP",
148 [SATA_HWID] = "SATA",
150 [CCXSEC_HWID] = "CCXSEC",
151 [XGMI_HWID] = "XGMI",
152 [XGBE_HWID] = "XGBE",
156 static int hw_id_map[MAX_HWIP] = {
158 [HDP_HWIP] = HDP_HWID,
159 [SDMA0_HWIP] = SDMA0_HWID,
160 [SDMA1_HWIP] = SDMA1_HWID,
161 [SDMA2_HWIP] = SDMA2_HWID,
162 [SDMA3_HWIP] = SDMA3_HWID,
163 [MMHUB_HWIP] = MMHUB_HWID,
164 [ATHUB_HWIP] = ATHUB_HWID,
165 [NBIO_HWIP] = NBIF_HWID,
166 [MP0_HWIP] = MP0_HWID,
167 [MP1_HWIP] = MP1_HWID,
168 [UVD_HWIP] = UVD_HWID,
169 [VCE_HWIP] = VCE_HWID,
171 [DCE_HWIP] = DMU_HWID,
172 [OSSSYS_HWIP] = OSSSYS_HWID,
173 [SMUIO_HWIP] = SMUIO_HWID,
174 [PWR_HWIP] = PWR_HWID,
175 [NBIF_HWIP] = NBIF_HWID,
176 [THM_HWIP] = THM_HWID,
177 [CLK_HWIP] = CLKA_HWID,
178 [UMC_HWIP] = UMC_HWID,
179 [XGMI_HWIP] = XGMI_HWID,
180 [DCI_HWIP] = DCI_HWID,
183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
185 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
186 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
188 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
189 adev->mman.discovery_tmr_size, false);
193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
195 const struct firmware *fw;
199 switch (amdgpu_discovery) {
201 fw_name = FIRMWARE_IP_DISCOVERY;
204 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
208 r = request_firmware(&fw, fw_name, adev->dev);
210 dev_err(adev->dev, "can't load firmware \"%s\"\n",
215 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
216 release_firmware(fw);
221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
223 uint16_t checksum = 0;
226 for (i = 0; i < size; i++)
232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
235 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
240 struct binary_header *bhdr;
241 bhdr = (struct binary_header *)binary;
243 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
246 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
249 * So far, apply this quirk only on those Navy Flounder boards which
250 * have a bad harvest table of VCN config.
252 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
253 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
254 switch (adev->pdev->revision) {
262 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
270 static int amdgpu_discovery_init(struct amdgpu_device *adev)
272 struct table_info *info;
273 struct binary_header *bhdr;
274 struct ip_discovery_header *ihdr;
275 struct gpu_info_header *ghdr;
281 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
282 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
283 if (!adev->mman.discovery_bin)
286 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin);
288 dev_err(adev->dev, "failed to read ip discovery binary from vram\n");
293 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
294 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n");
295 /* retry read ip discovery binary from file */
296 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
298 dev_err(adev->dev, "failed to read ip discovery binary from file\n");
302 /* check the ip discovery binary signature */
303 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
304 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n");
310 bhdr = (struct binary_header *)adev->mman.discovery_bin;
312 offset = offsetof(struct binary_header, binary_checksum) +
313 sizeof(bhdr->binary_checksum);
314 size = le16_to_cpu(bhdr->binary_size) - offset;
315 checksum = le16_to_cpu(bhdr->binary_checksum);
317 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
319 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
324 info = &bhdr->table_list[IP_DISCOVERY];
325 offset = le16_to_cpu(info->offset);
326 checksum = le16_to_cpu(info->checksum);
327 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
329 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
330 dev_err(adev->dev, "invalid ip discovery data table signature\n");
335 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
336 le16_to_cpu(ihdr->size), checksum)) {
337 dev_err(adev->dev, "invalid ip discovery data table checksum\n");
342 info = &bhdr->table_list[GC];
343 offset = le16_to_cpu(info->offset);
344 checksum = le16_to_cpu(info->checksum);
345 ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
347 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
348 le32_to_cpu(ghdr->size), checksum)) {
349 dev_err(adev->dev, "invalid gc data table checksum\n");
357 kfree(adev->mman.discovery_bin);
358 adev->mman.discovery_bin = NULL;
363 void amdgpu_discovery_fini(struct amdgpu_device *adev)
365 kfree(adev->mman.discovery_bin);
366 adev->mman.discovery_bin = NULL;
369 static int amdgpu_discovery_validate_ip(const struct ip *ip)
371 if (ip->number_instance >= HWIP_MAX_INSTANCE) {
372 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
373 ip->number_instance);
376 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
377 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
378 le16_to_cpu(ip->hw_id));
385 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
387 struct binary_header *bhdr;
388 struct ip_discovery_header *ihdr;
389 struct die_header *dhdr;
395 uint8_t num_base_address;
400 r = amdgpu_discovery_init(adev);
402 DRM_ERROR("amdgpu_discovery_init failed\n");
406 bhdr = (struct binary_header *)adev->mman.discovery_bin;
407 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
408 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
409 num_dies = le16_to_cpu(ihdr->num_dies);
411 DRM_DEBUG("number of dies: %d\n", num_dies);
413 for (i = 0; i < num_dies; i++) {
414 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
415 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
416 num_ips = le16_to_cpu(dhdr->num_ips);
417 ip_offset = die_offset + sizeof(*dhdr);
419 if (le16_to_cpu(dhdr->die_id) != i) {
420 DRM_ERROR("invalid die id %d, expected %d\n",
421 le16_to_cpu(dhdr->die_id), i);
425 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
426 le16_to_cpu(dhdr->die_id), num_ips);
428 for (j = 0; j < num_ips; j++) {
429 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
431 if (amdgpu_discovery_validate_ip(ip))
434 num_base_address = ip->num_base_address;
436 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
437 hw_id_names[le16_to_cpu(ip->hw_id)],
438 le16_to_cpu(ip->hw_id),
440 ip->major, ip->minor,
443 if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
444 /* Bit [5:0]: original revision value
445 * Bit [7:6]: en/decode capability:
446 * 0b00 : VCN function normally
447 * 0b10 : encode is disabled
448 * 0b01 : decode is disabled
450 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
452 ip->revision &= ~0xc0;
453 adev->vcn.num_vcn_inst++;
455 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
456 le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
457 le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
458 le16_to_cpu(ip->hw_id) == SDMA3_HWID)
459 adev->sdma.num_instances++;
461 for (k = 0; k < num_base_address; k++) {
463 * convert the endianness of base addresses in place,
464 * so that we don't need to convert them when accessing adev->reg_offset.
466 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
467 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
470 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
471 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
472 DRM_DEBUG("set register base offset for %s\n",
473 hw_id_names[le16_to_cpu(ip->hw_id)]);
474 adev->reg_offset[hw_ip][ip->number_instance] =
476 /* Instance support is somewhat inconsistent.
477 * SDMA is a good example. Sienna cichlid has 4 total
478 * SDMA instances, each enumerated separately (HWIDs
479 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances,
480 * but they are enumerated as multiple instances of the
481 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another
482 * example. On most chips there are multiple instances
483 * with the same HWID.
485 adev->ip_versions[hw_ip][ip->number_instance] =
486 IP_VERSION(ip->major, ip->minor, ip->revision);
491 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
498 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
499 int *major, int *minor, int *revision)
501 struct binary_header *bhdr;
502 struct ip_discovery_header *ihdr;
503 struct die_header *dhdr;
511 if (!adev->mman.discovery_bin) {
512 DRM_ERROR("ip discovery uninitialized\n");
516 bhdr = (struct binary_header *)adev->mman.discovery_bin;
517 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
518 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
519 num_dies = le16_to_cpu(ihdr->num_dies);
521 for (i = 0; i < num_dies; i++) {
522 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
523 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
524 num_ips = le16_to_cpu(dhdr->num_ips);
525 ip_offset = die_offset + sizeof(*dhdr);
527 for (j = 0; j < num_ips; j++) {
528 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
530 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
536 *revision = ip->revision;
539 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
546 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
548 struct binary_header *bhdr;
549 struct harvest_table *harvest_info;
550 int i, vcn_harvest_count = 0;
552 bhdr = (struct binary_header *)adev->mman.discovery_bin;
553 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
554 le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
556 for (i = 0; i < 32; i++) {
557 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
560 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
563 if (harvest_info->list[i].number_instance == 0)
564 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
566 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
569 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
576 amdgpu_discovery_harvest_config_quirk(adev);
578 if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
579 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
580 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
582 if ((adev->pdev->device == 0x731E &&
583 (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) ||
584 (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9) ||
585 (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) {
586 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
587 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
592 struct gc_info_v1_0 v1;
593 struct gc_info_v2_0 v2;
596 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
598 struct binary_header *bhdr;
599 union gc_info *gc_info;
601 if (!adev->mman.discovery_bin) {
602 DRM_ERROR("ip discovery uninitialized\n");
606 bhdr = (struct binary_header *)adev->mman.discovery_bin;
607 gc_info = (union gc_info *)(adev->mman.discovery_bin +
608 le16_to_cpu(bhdr->table_list[GC].offset));
609 switch (gc_info->v1.header.version_major) {
611 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
612 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
613 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
614 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
615 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
616 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
617 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
618 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
619 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
620 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
621 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
622 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
623 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
624 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
625 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
626 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
627 le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
628 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
631 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
632 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
633 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
634 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
635 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
636 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
637 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
638 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
639 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
640 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
641 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
642 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
643 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
644 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
645 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
646 le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
647 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
651 "Unhandled GC info table %d.%d\n",
652 gc_info->v1.header.version_major,
653 gc_info->v1.header.version_minor);
659 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
661 /* what IP to use for this? */
662 switch (adev->ip_versions[GC_HWIP][0]) {
663 case IP_VERSION(9, 0, 1):
664 case IP_VERSION(9, 1, 0):
665 case IP_VERSION(9, 2, 1):
666 case IP_VERSION(9, 2, 2):
667 case IP_VERSION(9, 3, 0):
668 case IP_VERSION(9, 4, 0):
669 case IP_VERSION(9, 4, 1):
670 case IP_VERSION(9, 4, 2):
671 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
673 case IP_VERSION(10, 1, 10):
674 case IP_VERSION(10, 1, 1):
675 case IP_VERSION(10, 1, 2):
676 case IP_VERSION(10, 1, 3):
677 case IP_VERSION(10, 3, 0):
678 case IP_VERSION(10, 3, 1):
679 case IP_VERSION(10, 3, 2):
680 case IP_VERSION(10, 3, 3):
681 case IP_VERSION(10, 3, 4):
682 case IP_VERSION(10, 3, 5):
683 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
687 "Failed to add common ip block(GC_HWIP:0x%x)\n",
688 adev->ip_versions[GC_HWIP][0]);
694 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
696 /* use GC or MMHUB IP version */
697 switch (adev->ip_versions[GC_HWIP][0]) {
698 case IP_VERSION(9, 0, 1):
699 case IP_VERSION(9, 1, 0):
700 case IP_VERSION(9, 2, 1):
701 case IP_VERSION(9, 2, 2):
702 case IP_VERSION(9, 3, 0):
703 case IP_VERSION(9, 4, 0):
704 case IP_VERSION(9, 4, 1):
705 case IP_VERSION(9, 4, 2):
706 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
708 case IP_VERSION(10, 1, 10):
709 case IP_VERSION(10, 1, 1):
710 case IP_VERSION(10, 1, 2):
711 case IP_VERSION(10, 1, 3):
712 case IP_VERSION(10, 3, 0):
713 case IP_VERSION(10, 3, 1):
714 case IP_VERSION(10, 3, 2):
715 case IP_VERSION(10, 3, 3):
716 case IP_VERSION(10, 3, 4):
717 case IP_VERSION(10, 3, 5):
718 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
722 "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
723 adev->ip_versions[GC_HWIP][0]);
729 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
731 switch (adev->ip_versions[OSSSYS_HWIP][0]) {
732 case IP_VERSION(4, 0, 0):
733 case IP_VERSION(4, 0, 1):
734 case IP_VERSION(4, 1, 0):
735 case IP_VERSION(4, 1, 1):
736 case IP_VERSION(4, 3, 0):
737 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
739 case IP_VERSION(4, 2, 0):
740 case IP_VERSION(4, 2, 1):
741 case IP_VERSION(4, 4, 0):
742 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
744 case IP_VERSION(5, 0, 0):
745 case IP_VERSION(5, 0, 1):
746 case IP_VERSION(5, 0, 2):
747 case IP_VERSION(5, 0, 3):
748 case IP_VERSION(5, 2, 0):
749 case IP_VERSION(5, 2, 1):
750 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
754 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
755 adev->ip_versions[OSSSYS_HWIP][0]);
761 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
763 switch (adev->ip_versions[MP0_HWIP][0]) {
764 case IP_VERSION(9, 0, 0):
765 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
767 case IP_VERSION(10, 0, 0):
768 case IP_VERSION(10, 0, 1):
769 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
771 case IP_VERSION(11, 0, 0):
772 case IP_VERSION(11, 0, 2):
773 case IP_VERSION(11, 0, 4):
774 case IP_VERSION(11, 0, 5):
775 case IP_VERSION(11, 0, 9):
776 case IP_VERSION(11, 0, 7):
777 case IP_VERSION(11, 0, 11):
778 case IP_VERSION(11, 0, 12):
779 case IP_VERSION(11, 0, 13):
780 case IP_VERSION(11, 5, 0):
781 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
783 case IP_VERSION(11, 0, 8):
784 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
786 case IP_VERSION(11, 0, 3):
787 case IP_VERSION(12, 0, 1):
788 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
790 case IP_VERSION(13, 0, 1):
791 case IP_VERSION(13, 0, 2):
792 case IP_VERSION(13, 0, 3):
793 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
797 "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
798 adev->ip_versions[MP0_HWIP][0]);
804 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
806 switch (adev->ip_versions[MP1_HWIP][0]) {
807 case IP_VERSION(9, 0, 0):
808 case IP_VERSION(10, 0, 0):
809 case IP_VERSION(10, 0, 1):
810 case IP_VERSION(11, 0, 2):
811 if (adev->asic_type == CHIP_ARCTURUS)
812 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
814 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
816 case IP_VERSION(11, 0, 0):
817 case IP_VERSION(11, 0, 5):
818 case IP_VERSION(11, 0, 9):
819 case IP_VERSION(11, 0, 7):
820 case IP_VERSION(11, 0, 8):
821 case IP_VERSION(11, 0, 11):
822 case IP_VERSION(11, 0, 12):
823 case IP_VERSION(11, 0, 13):
824 case IP_VERSION(11, 5, 0):
825 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
827 case IP_VERSION(12, 0, 0):
828 case IP_VERSION(12, 0, 1):
829 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
831 case IP_VERSION(13, 0, 1):
832 case IP_VERSION(13, 0, 2):
833 case IP_VERSION(13, 0, 3):
834 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
838 "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
839 adev->ip_versions[MP1_HWIP][0]);
845 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
847 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
848 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
849 #if defined(CONFIG_DRM_AMD_DC)
850 } else if (adev->ip_versions[DCE_HWIP][0]) {
851 switch (adev->ip_versions[DCE_HWIP][0]) {
852 case IP_VERSION(1, 0, 0):
853 case IP_VERSION(1, 0, 1):
854 case IP_VERSION(2, 0, 2):
855 case IP_VERSION(2, 0, 0):
856 case IP_VERSION(2, 0, 3):
857 case IP_VERSION(2, 1, 0):
858 case IP_VERSION(3, 0, 0):
859 case IP_VERSION(3, 0, 2):
860 case IP_VERSION(3, 0, 3):
861 case IP_VERSION(3, 0, 1):
862 case IP_VERSION(3, 1, 2):
863 case IP_VERSION(3, 1, 3):
864 amdgpu_device_ip_block_add(adev, &dm_ip_block);
868 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
869 adev->ip_versions[DCE_HWIP][0]);
872 } else if (adev->ip_versions[DCI_HWIP][0]) {
873 switch (adev->ip_versions[DCI_HWIP][0]) {
874 case IP_VERSION(12, 0, 0):
875 case IP_VERSION(12, 0, 1):
876 case IP_VERSION(12, 1, 0):
877 amdgpu_device_ip_block_add(adev, &dm_ip_block);
881 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
882 adev->ip_versions[DCI_HWIP][0]);
890 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
892 switch (adev->ip_versions[GC_HWIP][0]) {
893 case IP_VERSION(9, 0, 1):
894 case IP_VERSION(9, 1, 0):
895 case IP_VERSION(9, 2, 1):
896 case IP_VERSION(9, 2, 2):
897 case IP_VERSION(9, 3, 0):
898 case IP_VERSION(9, 4, 0):
899 case IP_VERSION(9, 4, 1):
900 case IP_VERSION(9, 4, 2):
901 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
903 case IP_VERSION(10, 1, 10):
904 case IP_VERSION(10, 1, 2):
905 case IP_VERSION(10, 1, 1):
906 case IP_VERSION(10, 1, 3):
907 case IP_VERSION(10, 3, 0):
908 case IP_VERSION(10, 3, 2):
909 case IP_VERSION(10, 3, 1):
910 case IP_VERSION(10, 3, 4):
911 case IP_VERSION(10, 3, 5):
912 case IP_VERSION(10, 3, 3):
913 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
917 "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
918 adev->ip_versions[GC_HWIP][0]);
924 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
926 switch (adev->ip_versions[SDMA0_HWIP][0]) {
927 case IP_VERSION(4, 0, 0):
928 case IP_VERSION(4, 0, 1):
929 case IP_VERSION(4, 1, 0):
930 case IP_VERSION(4, 1, 1):
931 case IP_VERSION(4, 1, 2):
932 case IP_VERSION(4, 2, 0):
933 case IP_VERSION(4, 2, 2):
934 case IP_VERSION(4, 4, 0):
935 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
937 case IP_VERSION(5, 0, 0):
938 case IP_VERSION(5, 0, 1):
939 case IP_VERSION(5, 0, 2):
940 case IP_VERSION(5, 0, 5):
941 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
943 case IP_VERSION(5, 2, 0):
944 case IP_VERSION(5, 2, 2):
945 case IP_VERSION(5, 2, 4):
946 case IP_VERSION(5, 2, 5):
947 case IP_VERSION(5, 2, 3):
948 case IP_VERSION(5, 2, 1):
949 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
953 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
954 adev->ip_versions[SDMA0_HWIP][0]);
960 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
962 if (adev->ip_versions[VCE_HWIP][0]) {
963 switch (adev->ip_versions[UVD_HWIP][0]) {
964 case IP_VERSION(7, 0, 0):
965 case IP_VERSION(7, 2, 0):
966 /* UVD is not supported on vega20 SR-IOV */
967 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
968 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
972 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
973 adev->ip_versions[UVD_HWIP][0]);
976 switch (adev->ip_versions[VCE_HWIP][0]) {
977 case IP_VERSION(4, 0, 0):
978 case IP_VERSION(4, 1, 0):
979 /* VCE is not supported on vega20 SR-IOV */
980 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
981 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
985 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
986 adev->ip_versions[VCE_HWIP][0]);
990 switch (adev->ip_versions[UVD_HWIP][0]) {
991 case IP_VERSION(1, 0, 0):
992 case IP_VERSION(1, 0, 1):
993 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
995 case IP_VERSION(2, 0, 0):
996 case IP_VERSION(2, 0, 2):
997 case IP_VERSION(2, 2, 0):
998 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
999 if (!amdgpu_sriov_vf(adev))
1000 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1002 case IP_VERSION(2, 0, 3):
1004 case IP_VERSION(2, 5, 0):
1005 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1006 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1008 case IP_VERSION(2, 6, 0):
1009 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1010 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1012 case IP_VERSION(3, 0, 0):
1013 case IP_VERSION(3, 0, 16):
1014 case IP_VERSION(3, 1, 1):
1015 case IP_VERSION(3, 0, 2):
1016 case IP_VERSION(3, 0, 192):
1017 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1018 if (!amdgpu_sriov_vf(adev))
1019 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
1021 case IP_VERSION(3, 0, 33):
1022 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1026 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
1027 adev->ip_versions[UVD_HWIP][0]);
1034 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
1036 switch (adev->ip_versions[GC_HWIP][0]) {
1037 case IP_VERSION(10, 1, 10):
1038 case IP_VERSION(10, 1, 1):
1039 case IP_VERSION(10, 1, 2):
1040 case IP_VERSION(10, 1, 3):
1041 case IP_VERSION(10, 3, 0):
1042 case IP_VERSION(10, 3, 1):
1043 case IP_VERSION(10, 3, 2):
1044 case IP_VERSION(10, 3, 3):
1045 case IP_VERSION(10, 3, 4):
1046 case IP_VERSION(10, 3, 5):
1047 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
1055 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
1059 switch (adev->asic_type) {
1061 vega10_reg_base_init(adev);
1062 adev->sdma.num_instances = 2;
1063 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1064 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1065 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
1066 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
1067 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
1068 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
1069 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1070 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
1071 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
1072 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1073 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1074 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1075 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
1076 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
1077 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1078 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1079 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
1082 vega10_reg_base_init(adev);
1083 adev->sdma.num_instances = 2;
1084 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1085 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1086 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
1087 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
1088 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
1089 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
1090 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
1091 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
1092 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
1093 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1094 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1095 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1096 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
1097 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
1098 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1099 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1100 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
1103 vega10_reg_base_init(adev);
1104 adev->sdma.num_instances = 1;
1105 adev->vcn.num_vcn_inst = 1;
1106 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1107 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1108 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1109 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
1110 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
1111 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
1112 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
1113 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
1114 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
1115 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
1116 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
1117 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
1118 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
1119 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
1120 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
1121 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
1123 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1124 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1125 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
1126 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
1127 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
1128 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1129 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
1130 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
1131 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
1132 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
1133 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
1134 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
1135 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
1136 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
1137 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
1141 vega20_reg_base_init(adev);
1142 adev->sdma.num_instances = 2;
1143 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1144 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1145 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
1146 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
1147 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
1148 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
1149 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
1150 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
1151 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
1152 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
1153 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1154 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
1155 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
1156 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
1157 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
1158 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
1159 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
1160 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
1163 arct_reg_base_init(adev);
1164 adev->sdma.num_instances = 8;
1165 adev->vcn.num_vcn_inst = 2;
1166 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1167 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1168 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
1169 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
1170 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
1171 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
1172 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
1173 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
1174 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
1175 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
1176 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
1177 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
1178 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
1179 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
1180 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
1181 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
1182 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1183 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
1184 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
1185 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
1186 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
1187 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
1189 case CHIP_ALDEBARAN:
1190 aldebaran_reg_base_init(adev);
1191 adev->sdma.num_instances = 5;
1192 adev->vcn.num_vcn_inst = 2;
1193 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1194 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1195 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
1196 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
1197 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
1198 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
1199 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
1200 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
1201 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
1202 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
1203 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
1204 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
1205 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
1206 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
1207 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
1208 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
1209 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
1210 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
1211 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
1212 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
1215 r = amdgpu_discovery_reg_base_init(adev);
1219 amdgpu_discovery_harvest_ip(adev);
1221 if (!adev->mman.discovery_bin) {
1222 DRM_ERROR("ip discovery uninitialized\n");
1228 switch (adev->ip_versions[GC_HWIP][0]) {
1229 case IP_VERSION(9, 0, 1):
1230 case IP_VERSION(9, 2, 1):
1231 case IP_VERSION(9, 4, 0):
1232 case IP_VERSION(9, 4, 1):
1233 case IP_VERSION(9, 4, 2):
1234 adev->family = AMDGPU_FAMILY_AI;
1236 case IP_VERSION(9, 1, 0):
1237 case IP_VERSION(9, 2, 2):
1238 case IP_VERSION(9, 3, 0):
1239 adev->family = AMDGPU_FAMILY_RV;
1241 case IP_VERSION(10, 1, 10):
1242 case IP_VERSION(10, 1, 1):
1243 case IP_VERSION(10, 1, 2):
1244 case IP_VERSION(10, 1, 3):
1245 case IP_VERSION(10, 3, 0):
1246 case IP_VERSION(10, 3, 2):
1247 case IP_VERSION(10, 3, 4):
1248 case IP_VERSION(10, 3, 5):
1249 adev->family = AMDGPU_FAMILY_NV;
1251 case IP_VERSION(10, 3, 1):
1252 adev->family = AMDGPU_FAMILY_VGH;
1254 case IP_VERSION(10, 3, 3):
1255 adev->family = AMDGPU_FAMILY_YC;
1261 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
1262 adev->gmc.xgmi.supported = true;
1264 /* set NBIO version */
1265 switch (adev->ip_versions[NBIO_HWIP][0]) {
1266 case IP_VERSION(6, 1, 0):
1267 case IP_VERSION(6, 2, 0):
1268 adev->nbio.funcs = &nbio_v6_1_funcs;
1269 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
1271 case IP_VERSION(7, 0, 0):
1272 case IP_VERSION(7, 0, 1):
1273 case IP_VERSION(2, 5, 0):
1274 adev->nbio.funcs = &nbio_v7_0_funcs;
1275 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
1277 case IP_VERSION(7, 4, 0):
1278 case IP_VERSION(7, 4, 1):
1279 adev->nbio.funcs = &nbio_v7_4_funcs;
1280 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
1282 case IP_VERSION(7, 4, 4):
1283 adev->nbio.funcs = &nbio_v7_4_funcs;
1284 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
1286 case IP_VERSION(7, 2, 0):
1287 case IP_VERSION(7, 2, 1):
1288 case IP_VERSION(7, 5, 0):
1289 adev->nbio.funcs = &nbio_v7_2_funcs;
1290 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
1292 case IP_VERSION(2, 1, 1):
1293 case IP_VERSION(2, 3, 0):
1294 case IP_VERSION(2, 3, 1):
1295 case IP_VERSION(2, 3, 2):
1296 adev->nbio.funcs = &nbio_v2_3_funcs;
1297 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
1299 case IP_VERSION(3, 3, 0):
1300 case IP_VERSION(3, 3, 1):
1301 case IP_VERSION(3, 3, 2):
1302 case IP_VERSION(3, 3, 3):
1303 adev->nbio.funcs = &nbio_v2_3_funcs;
1304 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
1310 switch (adev->ip_versions[HDP_HWIP][0]) {
1311 case IP_VERSION(4, 0, 0):
1312 case IP_VERSION(4, 0, 1):
1313 case IP_VERSION(4, 1, 0):
1314 case IP_VERSION(4, 1, 1):
1315 case IP_VERSION(4, 1, 2):
1316 case IP_VERSION(4, 2, 0):
1317 case IP_VERSION(4, 2, 1):
1318 case IP_VERSION(4, 4, 0):
1319 adev->hdp.funcs = &hdp_v4_0_funcs;
1321 case IP_VERSION(5, 0, 0):
1322 case IP_VERSION(5, 0, 1):
1323 case IP_VERSION(5, 0, 2):
1324 case IP_VERSION(5, 0, 3):
1325 case IP_VERSION(5, 0, 4):
1326 case IP_VERSION(5, 2, 0):
1327 adev->hdp.funcs = &hdp_v5_0_funcs;
1333 switch (adev->ip_versions[DF_HWIP][0]) {
1334 case IP_VERSION(3, 6, 0):
1335 case IP_VERSION(3, 6, 1):
1336 case IP_VERSION(3, 6, 2):
1337 adev->df.funcs = &df_v3_6_funcs;
1339 case IP_VERSION(2, 1, 0):
1340 case IP_VERSION(2, 1, 1):
1341 case IP_VERSION(2, 5, 0):
1342 case IP_VERSION(3, 5, 1):
1343 case IP_VERSION(3, 5, 2):
1344 adev->df.funcs = &df_v1_7_funcs;
1350 switch (adev->ip_versions[SMUIO_HWIP][0]) {
1351 case IP_VERSION(9, 0, 0):
1352 case IP_VERSION(9, 0, 1):
1353 case IP_VERSION(10, 0, 0):
1354 case IP_VERSION(10, 0, 1):
1355 case IP_VERSION(10, 0, 2):
1356 adev->smuio.funcs = &smuio_v9_0_funcs;
1358 case IP_VERSION(11, 0, 0):
1359 case IP_VERSION(11, 0, 2):
1360 case IP_VERSION(11, 0, 3):
1361 case IP_VERSION(11, 0, 4):
1362 case IP_VERSION(11, 0, 7):
1363 case IP_VERSION(11, 0, 8):
1364 adev->smuio.funcs = &smuio_v11_0_funcs;
1366 case IP_VERSION(11, 0, 6):
1367 case IP_VERSION(11, 0, 10):
1368 case IP_VERSION(11, 0, 11):
1369 case IP_VERSION(11, 5, 0):
1370 case IP_VERSION(13, 0, 1):
1371 adev->smuio.funcs = &smuio_v11_0_6_funcs;
1373 case IP_VERSION(13, 0, 2):
1374 adev->smuio.funcs = &smuio_v13_0_funcs;
1380 r = amdgpu_discovery_set_common_ip_blocks(adev);
1384 r = amdgpu_discovery_set_gmc_ip_blocks(adev);
1388 /* For SR-IOV, PSP needs to be initialized before IH */
1389 if (amdgpu_sriov_vf(adev)) {
1390 r = amdgpu_discovery_set_psp_ip_blocks(adev);
1393 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1397 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1401 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1402 r = amdgpu_discovery_set_psp_ip_blocks(adev);
1408 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1409 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1414 r = amdgpu_discovery_set_display_ip_blocks(adev);
1418 r = amdgpu_discovery_set_gc_ip_blocks(adev);
1422 r = amdgpu_discovery_set_sdma_ip_blocks(adev);
1426 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
1427 !amdgpu_sriov_vf(adev)) {
1428 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1433 r = amdgpu_discovery_set_mm_ip_blocks(adev);
1437 if (adev->enable_mes) {
1438 r = amdgpu_discovery_set_mes_ip_blocks(adev);