drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30
  31 #include "soc15.h"
  32 #include "gfx_v9_0.h"
  33 #include "gmc_v9_0.h"
  34 #include "df_v1_7.h"
  35 #include "df_v3_6.h"
  36 #include "nbio_v6_1.h"
  37 #include "nbio_v7_0.h"
  38 #include "nbio_v7_4.h"
  39 #include "hdp_v4_0.h"
  40 #include "vega10_ih.h"
  41 #include "vega20_ih.h"
  42 #include "sdma_v4_0.h"
  43 #include "uvd_v7_0.h"
  44 #include "vce_v4_0.h"
  45 #include "vcn_v1_0.h"
  46 #include "vcn_v2_5.h"
  47 #include "jpeg_v2_5.h"
  48 #include "smuio_v9_0.h"
  49 #include "gmc_v10_0.h"
  50 #include "gfxhub_v2_0.h"
  51 #include "mmhub_v2_0.h"
  52 #include "nbio_v2_3.h"
  53 #include "nbio_v7_2.h"
  54 #include "hdp_v5_0.h"
  55 #include "nv.h"
  56 #include "navi10_ih.h"
  57 #include "gfx_v10_0.h"
  58 #include "sdma_v5_0.h"
  59 #include "sdma_v5_2.h"
  60 #include "vcn_v2_0.h"
  61 #include "jpeg_v2_0.h"
  62 #include "vcn_v3_0.h"
  63 #include "jpeg_v3_0.h"
  64 #include "amdgpu_vkms.h"
  65 #include "mes_v10_1.h"
  66 #include "smuio_v11_0.h"
  67 #include "smuio_v11_0_6.h"
  68 #include "smuio_v13_0.h"
  69
  70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
  71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
  72
  73 #define mmRCC_CONFIG_MEMSIZE    0xde3
  74 #define mmMM_INDEX              0x0
  75 #define mmMM_INDEX_HI           0x6
  76 #define mmMM_DATA               0x1
  77
  78 static const char *hw_id_names[HW_ID_MAX] = {
  79         [MP1_HWID]              = "MP1",
  80         [MP2_HWID]              = "MP2",
  81         [THM_HWID]              = "THM",
  82         [SMUIO_HWID]            = "SMUIO",
  83         [FUSE_HWID]             = "FUSE",
  84         [CLKA_HWID]             = "CLKA",
  85         [PWR_HWID]              = "PWR",
  86         [GC_HWID]               = "GC",
  87         [UVD_HWID]              = "UVD",
  88         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
  89         [ACP_HWID]              = "ACP",
  90         [DCI_HWID]              = "DCI",
  91         [DMU_HWID]              = "DMU",
  92         [DCO_HWID]              = "DCO",
  93         [DIO_HWID]              = "DIO",
  94         [XDMA_HWID]             = "XDMA",
  95         [DCEAZ_HWID]            = "DCEAZ",
  96         [DAZ_HWID]              = "DAZ",
  97         [SDPMUX_HWID]           = "SDPMUX",
  98         [NTB_HWID]              = "NTB",
  99         [IOHC_HWID]             = "IOHC",
 100         [L2IMU_HWID]            = "L2IMU",
 101         [VCE_HWID]              = "VCE",
 102         [MMHUB_HWID]            = "MMHUB",
 103         [ATHUB_HWID]            = "ATHUB",
 104         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 105         [DFX_HWID]              = "DFX",
 106         [DBGU0_HWID]            = "DBGU0",
 107         [DBGU1_HWID]            = "DBGU1",
 108         [OSSSYS_HWID]           = "OSSSYS",
 109         [HDP_HWID]              = "HDP",
 110         [SDMA0_HWID]            = "SDMA0",
 111         [SDMA1_HWID]            = "SDMA1",
 112         [SDMA2_HWID]            = "SDMA2",
 113         [SDMA3_HWID]            = "SDMA3",
 114         [ISP_HWID]              = "ISP",
 115         [DBGU_IO_HWID]          = "DBGU_IO",
 116         [DF_HWID]               = "DF",
 117         [CLKB_HWID]             = "CLKB",
 118         [FCH_HWID]              = "FCH",
 119         [DFX_DAP_HWID]          = "DFX_DAP",
 120         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 121         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 122         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 123         [L1IMU3_HWID]           = "L1IMU3",
 124         [L1IMU4_HWID]           = "L1IMU4",
 125         [L1IMU5_HWID]           = "L1IMU5",
 126         [L1IMU6_HWID]           = "L1IMU6",
 127         [L1IMU7_HWID]           = "L1IMU7",
 128         [L1IMU8_HWID]           = "L1IMU8",
 129         [L1IMU9_HWID]           = "L1IMU9",
 130         [L1IMU10_HWID]          = "L1IMU10",
 131         [L1IMU11_HWID]          = "L1IMU11",
 132         [L1IMU12_HWID]          = "L1IMU12",
 133         [L1IMU13_HWID]          = "L1IMU13",
 134         [L1IMU14_HWID]          = "L1IMU14",
 135         [L1IMU15_HWID]          = "L1IMU15",
 136         [WAFLC_HWID]            = "WAFLC",
 137         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 138         [PCIE_HWID]             = "PCIE",
 139         [PCS_HWID]              = "PCS",
 140         [DDCL_HWID]             = "DDCL",
 141         [SST_HWID]              = "SST",
 142         [IOAGR_HWID]            = "IOAGR",
 143         [NBIF_HWID]             = "NBIF",
 144         [IOAPIC_HWID]           = "IOAPIC",
 145         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 146         [NTBCCP_HWID]           = "NTBCCP",
 147         [UMC_HWID]              = "UMC",
 148         [SATA_HWID]             = "SATA",
 149         [USB_HWID]              = "USB",
 150         [CCXSEC_HWID]           = "CCXSEC",
 151         [XGMI_HWID]             = "XGMI",
 152         [XGBE_HWID]             = "XGBE",
 153         [MP0_HWID]              = "MP0",
 154 };
 155
 156 static int hw_id_map[MAX_HWIP] = {
 157         [GC_HWIP]       = GC_HWID,
 158         [HDP_HWIP]      = HDP_HWID,
 159         [SDMA0_HWIP]    = SDMA0_HWID,
 160         [SDMA1_HWIP]    = SDMA1_HWID,
 161         [SDMA2_HWIP]    = SDMA2_HWID,
 162         [SDMA3_HWIP]    = SDMA3_HWID,
 163         [MMHUB_HWIP]    = MMHUB_HWID,
 164         [ATHUB_HWIP]    = ATHUB_HWID,
 165         [NBIO_HWIP]     = NBIF_HWID,
 166         [MP0_HWIP]      = MP0_HWID,
 167         [MP1_HWIP]      = MP1_HWID,
 168         [UVD_HWIP]      = UVD_HWID,
 169         [VCE_HWIP]      = VCE_HWID,
 170         [DF_HWIP]       = DF_HWID,
 171         [DCE_HWIP]      = DMU_HWID,
 172         [OSSSYS_HWIP]   = OSSSYS_HWID,
 173         [SMUIO_HWIP]    = SMUIO_HWID,
 174         [PWR_HWIP]      = PWR_HWID,
 175         [NBIF_HWIP]     = NBIF_HWID,
 176         [THM_HWIP]      = THM_HWID,
 177         [CLK_HWIP]      = CLKA_HWID,
 178         [UMC_HWIP]      = UMC_HWID,
 179         [XGMI_HWIP]     = XGMI_HWID,
 180         [DCI_HWIP]      = DCI_HWID,
 181 };
 182
 183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
 184 {
 185         uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 186         uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 187
 188         amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 189                                   adev->mman.discovery_tmr_size, false);
 190         return 0;
 191 }
 192
 193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
 194 {
 195         const struct firmware *fw;
 196         const char *fw_name;
 197         int r;
 198
 199         switch (amdgpu_discovery) {
 200         case 2:
 201                 fw_name = FIRMWARE_IP_DISCOVERY;
 202                 break;
 203         default:
 204                 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
 205                 return -EINVAL;
 206         }
 207
 208         r = request_firmware(&fw, fw_name, adev->dev);
 209         if (r) {
 210                 dev_err(adev->dev, "can't load firmware \"%s\"\n",
 211                         fw_name);
 212                 return r;
 213         }
 214
 215         memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
 216         release_firmware(fw);
 217
 218         return 0;
 219 }
 220
 221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 222 {
 223         uint16_t checksum = 0;
 224         int i;
 225
 226         for (i = 0; i < size; i++)
 227                 checksum += data[i];
 228
 229         return checksum;
 230 }
 231
 232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 233                                                     uint16_t expected)
 234 {
 235         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 236 }
 237
 238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
 239 {
 240         struct binary_header *bhdr;
 241         bhdr = (struct binary_header *)binary;
 242
 243         return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
 244 }
 245
 246 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
 247 {
 248         /*
 249          * So far, apply this quirk only on those Navy Flounder boards which
 250          * have a bad harvest table of VCN config.
 251          */
 252         if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
 253                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
 254                 switch (adev->pdev->revision) {
 255                 case 0xC1:
 256                 case 0xC2:
 257                 case 0xC3:
 258                 case 0xC5:
 259                 case 0xC7:
 260                 case 0xCF:
 261                 case 0xDF:
 262                         adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 263                         break;
 264                 default:
 265                         break;
 266                 }
 267         }
 268 }
 269
 270 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 271 {
 272         struct table_info *info;
 273         struct binary_header *bhdr;
 274         struct ip_discovery_header *ihdr;
 275         struct gpu_info_header *ghdr;
 276         uint16_t offset;
 277         uint16_t size;
 278         uint16_t checksum;
 279         int r;
 280
 281         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 282         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 283         if (!adev->mman.discovery_bin)
 284                 return -ENOMEM;
 285
 286         r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin);
 287         if (r) {
 288                 dev_err(adev->dev, "failed to read ip discovery binary from vram\n");
 289                 r = -EINVAL;
 290                 goto out;
 291         }
 292
 293         if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 294                 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n");
 295                 /* retry read ip discovery binary from file */
 296                 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
 297                 if (r) {
 298                         dev_err(adev->dev, "failed to read ip discovery binary from file\n");
 299                         r = -EINVAL;
 300                         goto out;
 301                 }
 302                 /* check the ip discovery binary signature */
 303                 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 304                         dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n");
 305                         r = -EINVAL;
 306                         goto out;
 307                 }
 308         }
 309
 310         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 311
 312         offset = offsetof(struct binary_header, binary_checksum) +
 313                 sizeof(bhdr->binary_checksum);
 314         size = le16_to_cpu(bhdr->binary_size) - offset;
 315         checksum = le16_to_cpu(bhdr->binary_checksum);
 316
 317         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 318                                               size, checksum)) {
 319                 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
 320                 r = -EINVAL;
 321                 goto out;
 322         }
 323
 324         info = &bhdr->table_list[IP_DISCOVERY];
 325         offset = le16_to_cpu(info->offset);
 326         checksum = le16_to_cpu(info->checksum);
 327         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 328
 329         if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 330                 dev_err(adev->dev, "invalid ip discovery data table signature\n");
 331                 r = -EINVAL;
 332                 goto out;
 333         }
 334
 335         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 336                                               le16_to_cpu(ihdr->size), checksum)) {
 337                 dev_err(adev->dev, "invalid ip discovery data table checksum\n");
 338                 r = -EINVAL;
 339                 goto out;
 340         }
 341
 342         info = &bhdr->table_list[GC];
 343         offset = le16_to_cpu(info->offset);
 344         checksum = le16_to_cpu(info->checksum);
 345         ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 346
 347         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 348                                               le32_to_cpu(ghdr->size), checksum)) {
 349                 dev_err(adev->dev, "invalid gc data table checksum\n");
 350                 r = -EINVAL;
 351                 goto out;
 352         }
 353
 354         return 0;
 355
 356 out:
 357         kfree(adev->mman.discovery_bin);
 358         adev->mman.discovery_bin = NULL;
 359
 360         return r;
 361 }
 362
 363 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
 364
 365 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 366 {
 367         amdgpu_discovery_sysfs_fini(adev);
 368         kfree(adev->mman.discovery_bin);
 369         adev->mman.discovery_bin = NULL;
 370 }
 371
 372 static int amdgpu_discovery_validate_ip(const struct ip *ip)
 373 {
 374         if (ip->number_instance >= HWIP_MAX_INSTANCE) {
 375                 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
 376                           ip->number_instance);
 377                 return -EINVAL;
 378         }
 379         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 380                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 381                           le16_to_cpu(ip->hw_id));
 382                 return -EINVAL;
 383         }
 384
 385         return 0;
 386 }
 387
 388 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
 389                                                 uint32_t *vcn_harvest_count)
 390 {
 391         struct binary_header *bhdr;
 392         struct ip_discovery_header *ihdr;
 393         struct die_header *dhdr;
 394         struct ip *ip;
 395         uint16_t die_offset, ip_offset, num_dies, num_ips;
 396         int i, j;
 397
 398         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 399         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 400                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 401         num_dies = le16_to_cpu(ihdr->num_dies);
 402
 403         /* scan harvest bit of all IP data structures */
 404         for (i = 0; i < num_dies; i++) {
 405                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 406                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 407                 num_ips = le16_to_cpu(dhdr->num_ips);
 408                 ip_offset = die_offset + sizeof(*dhdr);
 409
 410                 for (j = 0; j < num_ips; j++) {
 411                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 412
 413                         if (amdgpu_discovery_validate_ip(ip))
 414                                 goto next_ip;
 415
 416                         if (le16_to_cpu(ip->harvest) == 1) {
 417                                 switch (le16_to_cpu(ip->hw_id)) {
 418                                 case VCN_HWID:
 419                                         (*vcn_harvest_count)++;
 420                                         if (ip->number_instance == 0)
 421                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 422                                         else
 423                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 424                                         break;
 425                                 case DMU_HWID:
 426                                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 427                                         break;
 428                                 default:
 429                                         break;
 430                                 }
 431                         }
 432 next_ip:
 433                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
 434                 }
 435         }
 436 }
 437
 438 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
 439                                                      uint32_t *vcn_harvest_count)
 440 {
 441         struct binary_header *bhdr;
 442         struct harvest_table *harvest_info;
 443         int i;
 444
 445         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 446         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
 447                         le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
 448         for (i = 0; i < 32; i++) {
 449                 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
 450                         break;
 451
 452                 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
 453                 case VCN_HWID:
 454                         (*vcn_harvest_count)++;
 455                         if (harvest_info->list[i].number_instance == 0)
 456                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 457                         else
 458                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 459                         break;
 460                 case DMU_HWID:
 461                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 462                         break;
 463                 default:
 464                         break;
 465                 }
 466         }
 467 }
 468
 469 /* ================================================== */
 470
 471 struct ip_hw_instance {
 472         struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
 473
 474         int hw_id;
 475         u8  num_instance;
 476         u8  major, minor, revision;
 477         u8  harvest;
 478
 479         int num_base_addresses;
 480         u32 base_addr[];
 481 };
 482
 483 struct ip_hw_id {
 484         struct kset hw_id_kset;  /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
 485         int hw_id;
 486 };
 487
 488 struct ip_die_entry {
 489         struct kset ip_kset;     /* ip_discovery/die/#die/, contains ip_hw_id  */
 490         u16 num_ips;
 491 };
 492
 493 /* -------------------------------------------------- */
 494
 495 struct ip_hw_instance_attr {
 496         struct attribute attr;
 497         ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
 498 };
 499
 500 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 501 {
 502         return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
 503 }
 504
 505 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 506 {
 507         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
 508 }
 509
 510 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 511 {
 512         return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
 513 }
 514
 515 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 516 {
 517         return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
 518 }
 519
 520 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 521 {
 522         return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
 523 }
 524
 525 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 526 {
 527         return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
 528 }
 529
 530 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 531 {
 532         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
 533 }
 534
 535 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 536 {
 537         ssize_t res, at;
 538         int ii;
 539
 540         for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
 541                 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
 542                  */
 543                 if (at + 12 > PAGE_SIZE)
 544                         break;
 545                 res = sysfs_emit_at(buf, at, "0x%08X\n",
 546                                     ip_hw_instance->base_addr[ii]);
 547                 if (res <= 0)
 548                         break;
 549                 at += res;
 550         }
 551
 552         return res < 0 ? res : at;
 553 }
 554
 555 static struct ip_hw_instance_attr ip_hw_attr[] = {
 556         __ATTR_RO(hw_id),
 557         __ATTR_RO(num_instance),
 558         __ATTR_RO(major),
 559         __ATTR_RO(minor),
 560         __ATTR_RO(revision),
 561         __ATTR_RO(harvest),
 562         __ATTR_RO(num_base_addresses),
 563         __ATTR_RO(base_addr),
 564 };
 565
 566 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
 567 ATTRIBUTE_GROUPS(ip_hw_instance);
 568
 569 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
 570 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
 571
 572 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
 573                                         struct attribute *attr,
 574                                         char *buf)
 575 {
 576         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 577         struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
 578
 579         if (!ip_hw_attr->show)
 580                 return -EIO;
 581
 582         return ip_hw_attr->show(ip_hw_instance, buf);
 583 }
 584
 585 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
 586         .show = ip_hw_instance_attr_show,
 587 };
 588
 589 static void ip_hw_instance_release(struct kobject *kobj)
 590 {
 591         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 592
 593         kfree(ip_hw_instance);
 594 }
 595
 596 static struct kobj_type ip_hw_instance_ktype = {
 597         .release = ip_hw_instance_release,
 598         .sysfs_ops = &ip_hw_instance_sysfs_ops,
 599         .default_groups = ip_hw_instance_groups,
 600 };
 601
 602 /* -------------------------------------------------- */
 603
 604 #define to_ip_hw_id(x)  container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
 605
 606 static void ip_hw_id_release(struct kobject *kobj)
 607 {
 608         struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
 609
 610         if (!list_empty(&ip_hw_id->hw_id_kset.list))
 611                 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
 612         kfree(ip_hw_id);
 613 }
 614
 615 static struct kobj_type ip_hw_id_ktype = {
 616         .release = ip_hw_id_release,
 617         .sysfs_ops = &kobj_sysfs_ops,
 618 };
 619
 620 /* -------------------------------------------------- */
 621
 622 static void die_kobj_release(struct kobject *kobj);
 623 static void ip_disc_release(struct kobject *kobj);
 624
 625 struct ip_die_entry_attribute {
 626         struct attribute attr;
 627         ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
 628 };
 629
 630 #define to_ip_die_entry_attr(x)  container_of(x, struct ip_die_entry_attribute, attr)
 631
 632 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
 633 {
 634         return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
 635 }
 636
 637 /* If there are more ip_die_entry attrs, other than the number of IPs,
 638  * we can make this intro an array of attrs, and then initialize
 639  * ip_die_entry_attrs in a loop.
 640  */
 641 static struct ip_die_entry_attribute num_ips_attr =
 642         __ATTR_RO(num_ips);
 643
 644 static struct attribute *ip_die_entry_attrs[] = {
 645         &num_ips_attr.attr,
 646         NULL,
 647 };
 648 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
 649
 650 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
 651
 652 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
 653                                       struct attribute *attr,
 654                                       char *buf)
 655 {
 656         struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
 657         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 658
 659         if (!ip_die_entry_attr->show)
 660                 return -EIO;
 661
 662         return ip_die_entry_attr->show(ip_die_entry, buf);
 663 }
 664
 665 static void ip_die_entry_release(struct kobject *kobj)
 666 {
 667         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 668
 669         if (!list_empty(&ip_die_entry->ip_kset.list))
 670                 DRM_ERROR("ip_die_entry->ip_kset is not empty");
 671         kfree(ip_die_entry);
 672 }
 673
 674 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
 675         .show = ip_die_entry_attr_show,
 676 };
 677
 678 static struct kobj_type ip_die_entry_ktype = {
 679         .release = ip_die_entry_release,
 680         .sysfs_ops = &ip_die_entry_sysfs_ops,
 681         .default_groups = ip_die_entry_groups,
 682 };
 683
 684 static struct kobj_type die_kobj_ktype = {
 685         .release = die_kobj_release,
 686         .sysfs_ops = &kobj_sysfs_ops,
 687 };
 688
 689 static struct kobj_type ip_discovery_ktype = {
 690         .release = ip_disc_release,
 691         .sysfs_ops = &kobj_sysfs_ops,
 692 };
 693
 694 struct ip_discovery_top {
 695         struct kobject kobj;    /* ip_discovery/ */
 696         struct kset die_kset;   /* ip_discovery/die/, contains ip_die_entry */
 697         struct amdgpu_device *adev;
 698 };
 699
 700 static void die_kobj_release(struct kobject *kobj)
 701 {
 702         struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
 703                                                        struct ip_discovery_top,
 704                                                        die_kset);
 705         if (!list_empty(&ip_top->die_kset.list))
 706                 DRM_ERROR("ip_top->die_kset is not empty");
 707 }
 708
 709 static void ip_disc_release(struct kobject *kobj)
 710 {
 711         struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
 712                                                        kobj);
 713         struct amdgpu_device *adev = ip_top->adev;
 714
 715         adev->ip_top = NULL;
 716         kfree(ip_top);
 717 }
 718
 719 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
 720                                       struct ip_die_entry *ip_die_entry,
 721                                       const size_t _ip_offset, const int num_ips)
 722 {
 723         int ii, jj, kk, res;
 724
 725         DRM_DEBUG("num_ips:%d", num_ips);
 726
 727         /* Find all IPs of a given HW ID, and add their instance to
 728          * #die/#hw_id/#instance/<attributes>
 729          */
 730         for (ii = 0; ii < HW_ID_MAX; ii++) {
 731                 struct ip_hw_id *ip_hw_id = NULL;
 732                 size_t ip_offset = _ip_offset;
 733
 734                 for (jj = 0; jj < num_ips; jj++) {
 735                         struct ip *ip;
 736                         struct ip_hw_instance *ip_hw_instance;
 737
 738                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 739                         if (amdgpu_discovery_validate_ip(ip) ||
 740                             le16_to_cpu(ip->hw_id) != ii)
 741                                 goto next_ip;
 742
 743                         DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
 744
 745                         /* We have a hw_id match; register the hw
 746                          * block if not yet registered.
 747                          */
 748                         if (!ip_hw_id) {
 749                                 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
 750                                 if (!ip_hw_id)
 751                                         return -ENOMEM;
 752                                 ip_hw_id->hw_id = ii;
 753
 754                                 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
 755                                 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
 756                                 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
 757                                 res = kset_register(&ip_hw_id->hw_id_kset);
 758                                 if (res) {
 759                                         DRM_ERROR("Couldn't register ip_hw_id kset");
 760                                         kfree(ip_hw_id);
 761                                         return res;
 762                                 }
 763                                 if (hw_id_names[ii]) {
 764                                         res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
 765                                                                 &ip_hw_id->hw_id_kset.kobj,
 766                                                                 hw_id_names[ii]);
 767                                         if (res) {
 768                                                 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
 769                                                           hw_id_names[ii],
 770                                                           kobject_name(&ip_die_entry->ip_kset.kobj));
 771                                         }
 772                                 }
 773                         }
 774
 775                         /* Now register its instance.
 776                          */
 777                         ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
 778                                                              base_addr,
 779                                                              ip->num_base_address),
 780                                                  GFP_KERNEL);
 781                         if (!ip_hw_instance) {
 782                                 DRM_ERROR("no memory for ip_hw_instance");
 783                                 return -ENOMEM;
 784                         }
 785                         ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
 786                         ip_hw_instance->num_instance = ip->number_instance;
 787                         ip_hw_instance->major = ip->major;
 788                         ip_hw_instance->minor = ip->minor;
 789                         ip_hw_instance->revision = ip->revision;
 790                         ip_hw_instance->harvest = ip->harvest;
 791                         ip_hw_instance->num_base_addresses = ip->num_base_address;
 792
 793                         for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++)
 794                                 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
 795
 796                         kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
 797                         ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
 798                         res = kobject_add(&ip_hw_instance->kobj, NULL,
 799                                           "%d", ip_hw_instance->num_instance);
 800 next_ip:
 801                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
 802                 }
 803         }
 804
 805         return 0;
 806 }
 807
 808 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
 809 {
 810         struct binary_header *bhdr;
 811         struct ip_discovery_header *ihdr;
 812         struct die_header *dhdr;
 813         struct kset *die_kset = &adev->ip_top->die_kset;
 814         u16 num_dies, die_offset, num_ips;
 815         size_t ip_offset;
 816         int ii, res;
 817
 818         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 819         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 820                                               le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 821         num_dies = le16_to_cpu(ihdr->num_dies);
 822
 823         DRM_DEBUG("number of dies: %d\n", num_dies);
 824
 825         for (ii = 0; ii < num_dies; ii++) {
 826                 struct ip_die_entry *ip_die_entry;
 827
 828                 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
 829                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 830                 num_ips = le16_to_cpu(dhdr->num_ips);
 831                 ip_offset = die_offset + sizeof(*dhdr);
 832
 833                 /* Add the die to the kset.
 834                  *
 835                  * dhdr->die_id == ii, which was checked in
 836                  * amdgpu_discovery_reg_base_init().
 837                  */
 838
 839                 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
 840                 if (!ip_die_entry)
 841                         return -ENOMEM;
 842
 843                 ip_die_entry->num_ips = num_ips;
 844
 845                 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
 846                 ip_die_entry->ip_kset.kobj.kset = die_kset;
 847                 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
 848                 res = kset_register(&ip_die_entry->ip_kset);
 849                 if (res) {
 850                         DRM_ERROR("Couldn't register ip_die_entry kset");
 851                         kfree(ip_die_entry);
 852                         return res;
 853                 }
 854
 855                 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips);
 856         }
 857
 858         return 0;
 859 }
 860
 861 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
 862 {
 863         struct kset *die_kset;
 864         int res, ii;
 865
 866         adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
 867         if (!adev->ip_top)
 868                 return -ENOMEM;
 869
 870         adev->ip_top->adev = adev;
 871
 872         res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
 873                                    &adev->dev->kobj, "ip_discovery");
 874         if (res) {
 875                 DRM_ERROR("Couldn't init and add ip_discovery/");
 876                 goto Err;
 877         }
 878
 879         die_kset = &adev->ip_top->die_kset;
 880         kobject_set_name(&die_kset->kobj, "%s", "die");
 881         die_kset->kobj.parent = &adev->ip_top->kobj;
 882         die_kset->kobj.ktype = &die_kobj_ktype;
 883         res = kset_register(&adev->ip_top->die_kset);
 884         if (res) {
 885                 DRM_ERROR("Couldn't register die_kset");
 886                 goto Err;
 887         }
 888
 889         for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
 890                 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
 891         ip_hw_instance_attrs[ii] = NULL;
 892
 893         res = amdgpu_discovery_sysfs_recurse(adev);
 894
 895         return res;
 896 Err:
 897         kobject_put(&adev->ip_top->kobj);
 898         return res;
 899 }
 900
 901 /* -------------------------------------------------- */
 902
 903 #define list_to_kobj(el) container_of(el, struct kobject, entry)
 904
 905 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
 906 {
 907         struct list_head *el, *tmp;
 908         struct kset *hw_id_kset;
 909
 910         hw_id_kset = &ip_hw_id->hw_id_kset;
 911         spin_lock(&hw_id_kset->list_lock);
 912         list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
 913                 list_del_init(el);
 914                 spin_unlock(&hw_id_kset->list_lock);
 915                 /* kobject is embedded in ip_hw_instance */
 916                 kobject_put(list_to_kobj(el));
 917                 spin_lock(&hw_id_kset->list_lock);
 918         }
 919         spin_unlock(&hw_id_kset->list_lock);
 920         kobject_put(&ip_hw_id->hw_id_kset.kobj);
 921 }
 922
 923 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
 924 {
 925         struct list_head *el, *tmp;
 926         struct kset *ip_kset;
 927
 928         ip_kset = &ip_die_entry->ip_kset;
 929         spin_lock(&ip_kset->list_lock);
 930         list_for_each_prev_safe(el, tmp, &ip_kset->list) {
 931                 list_del_init(el);
 932                 spin_unlock(&ip_kset->list_lock);
 933                 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
 934                 spin_lock(&ip_kset->list_lock);
 935         }
 936         spin_unlock(&ip_kset->list_lock);
 937         kobject_put(&ip_die_entry->ip_kset.kobj);
 938 }
 939
 940 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
 941 {
 942         struct list_head *el, *tmp;
 943         struct kset *die_kset;
 944
 945         die_kset = &adev->ip_top->die_kset;
 946         spin_lock(&die_kset->list_lock);
 947         list_for_each_prev_safe(el, tmp, &die_kset->list) {
 948                 list_del_init(el);
 949                 spin_unlock(&die_kset->list_lock);
 950                 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
 951                 spin_lock(&die_kset->list_lock);
 952         }
 953         spin_unlock(&die_kset->list_lock);
 954         kobject_put(&adev->ip_top->die_kset.kobj);
 955         kobject_put(&adev->ip_top->kobj);
 956 }
 957
 958 /* ================================================== */
 959
 960 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 961 {
 962         struct binary_header *bhdr;
 963         struct ip_discovery_header *ihdr;
 964         struct die_header *dhdr;
 965         struct ip *ip;
 966         uint16_t die_offset;
 967         uint16_t ip_offset;
 968         uint16_t num_dies;
 969         uint16_t num_ips;
 970         uint8_t num_base_address;
 971         int hw_ip;
 972         int i, j, k;
 973         int r;
 974
 975         r = amdgpu_discovery_init(adev);
 976         if (r) {
 977                 DRM_ERROR("amdgpu_discovery_init failed\n");
 978                 return r;
 979         }
 980
 981         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 982         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 983                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 984         num_dies = le16_to_cpu(ihdr->num_dies);
 985
 986         DRM_DEBUG("number of dies: %d\n", num_dies);
 987
 988         for (i = 0; i < num_dies; i++) {
 989                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 990                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 991                 num_ips = le16_to_cpu(dhdr->num_ips);
 992                 ip_offset = die_offset + sizeof(*dhdr);
 993
 994                 if (le16_to_cpu(dhdr->die_id) != i) {
 995                         DRM_ERROR("invalid die id %d, expected %d\n",
 996                                         le16_to_cpu(dhdr->die_id), i);
 997                         return -EINVAL;
 998                 }
 999
1000                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1001                                 le16_to_cpu(dhdr->die_id), num_ips);
1002
1003                 for (j = 0; j < num_ips; j++) {
1004                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1005
1006                         if (amdgpu_discovery_validate_ip(ip))
1007                                 goto next_ip;
1008
1009                         num_base_address = ip->num_base_address;
1010
1011                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1012                                   hw_id_names[le16_to_cpu(ip->hw_id)],
1013                                   le16_to_cpu(ip->hw_id),
1014                                   ip->number_instance,
1015                                   ip->major, ip->minor,
1016                                   ip->revision);
1017
1018                         if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1019                                 /* Bit [5:0]: original revision value
1020                                  * Bit [7:6]: en/decode capability:
1021                                  *     0b00 : VCN function normally
1022                                  *     0b10 : encode is disabled
1023                                  *     0b01 : decode is disabled
1024                                  */
1025                                 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
1026                                         ip->revision & 0xc0;
1027                                 ip->revision &= ~0xc0;
1028                                 adev->vcn.num_vcn_inst++;
1029                         }
1030                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1031                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1032                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1033                             le16_to_cpu(ip->hw_id) == SDMA3_HWID)
1034                                 adev->sdma.num_instances++;
1035
1036                         for (k = 0; k < num_base_address; k++) {
1037                                 /*
1038                                  * convert the endianness of base addresses in place,
1039                                  * so that we don't need to convert them when accessing adev->reg_offset.
1040                                  */
1041                                 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1042                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1043                         }
1044
1045                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1046                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
1047                                         DRM_DEBUG("set register base offset for %s\n",
1048                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
1049                                         adev->reg_offset[hw_ip][ip->number_instance] =
1050                                                 ip->base_address;
1051                                         /* Instance support is somewhat inconsistent.
1052                                          * SDMA is a good example.  Sienna cichlid has 4 total
1053                                          * SDMA instances, each enumerated separately (HWIDs
1054                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
1055                                          * but they are enumerated as multiple instances of the
1056                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
1057                                          * example.  On most chips there are multiple instances
1058                                          * with the same HWID.
1059                                          */
1060                                         adev->ip_versions[hw_ip][ip->number_instance] =
1061                                                 IP_VERSION(ip->major, ip->minor, ip->revision);
1062                                 }
1063                         }
1064
1065 next_ip:
1066                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
1067                 }
1068         }
1069
1070         amdgpu_discovery_sysfs_init(adev);
1071
1072         return 0;
1073 }
1074
1075 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
1076                                     int *major, int *minor, int *revision)
1077 {
1078         struct binary_header *bhdr;
1079         struct ip_discovery_header *ihdr;
1080         struct die_header *dhdr;
1081         struct ip *ip;
1082         uint16_t die_offset;
1083         uint16_t ip_offset;
1084         uint16_t num_dies;
1085         uint16_t num_ips;
1086         int i, j;
1087
1088         if (!adev->mman.discovery_bin) {
1089                 DRM_ERROR("ip discovery uninitialized\n");
1090                 return -EINVAL;
1091         }
1092
1093         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1094         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1095                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1096         num_dies = le16_to_cpu(ihdr->num_dies);
1097
1098         for (i = 0; i < num_dies; i++) {
1099                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1100                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1101                 num_ips = le16_to_cpu(dhdr->num_ips);
1102                 ip_offset = die_offset + sizeof(*dhdr);
1103
1104                 for (j = 0; j < num_ips; j++) {
1105                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1106
1107                         if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
1108                                 if (major)
1109                                         *major = ip->major;
1110                                 if (minor)
1111                                         *minor = ip->minor;
1112                                 if (revision)
1113                                         *revision = ip->revision;
1114                                 return 0;
1115                         }
1116                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
1117                 }
1118         }
1119
1120         return -EINVAL;
1121 }
1122
1123 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1124 {
1125         int vcn_harvest_count = 0;
1126
1127         /*
1128          * Harvest table does not fit Navi1x and legacy GPUs,
1129          * so read harvest bit per IP data structure to set
1130          * harvest configuration.
1131          */
1132         if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
1133                 if ((adev->pdev->device == 0x731E &&
1134                         (adev->pdev->revision == 0xC6 ||
1135                          adev->pdev->revision == 0xC7)) ||
1136                         (adev->pdev->device == 0x7340 &&
1137                          adev->pdev->revision == 0xC9) ||
1138                         (adev->pdev->device == 0x7360 &&
1139                          adev->pdev->revision == 0xC7))
1140                         amdgpu_discovery_read_harvest_bit_per_ip(adev,
1141                                 &vcn_harvest_count);
1142         } else {
1143                 amdgpu_discovery_read_from_harvest_table(adev,
1144                         &vcn_harvest_count);
1145         }
1146
1147         amdgpu_discovery_harvest_config_quirk(adev);
1148
1149         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1150                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1151                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1152         }
1153 }
1154
1155 union gc_info {
1156         struct gc_info_v1_0 v1;
1157         struct gc_info_v2_0 v2;
1158 };
1159
1160 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1161 {
1162         struct binary_header *bhdr;
1163         union gc_info *gc_info;
1164
1165         if (!adev->mman.discovery_bin) {
1166                 DRM_ERROR("ip discovery uninitialized\n");
1167                 return -EINVAL;
1168         }
1169
1170         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1171         gc_info = (union gc_info *)(adev->mman.discovery_bin +
1172                         le16_to_cpu(bhdr->table_list[GC].offset));
1173         switch (gc_info->v1.header.version_major) {
1174         case 1:
1175                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1176                 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1177                                                       le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1178                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1179                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1180                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1181                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1182                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1183                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1184                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1185                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1186                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1187                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1188                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1189                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1190                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1191                         le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1192                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1193                 break;
1194         case 2:
1195                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1196                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1197                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1198                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1199                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1200                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1201                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1202                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1203                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1204                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1205                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1206                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1207                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1208                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1209                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1210                         le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1211                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1212                 break;
1213         default:
1214                 dev_err(adev->dev,
1215                         "Unhandled GC info table %d.%d\n",
1216                         gc_info->v1.header.version_major,
1217                         gc_info->v1.header.version_minor);
1218                 return -EINVAL;
1219         }
1220         return 0;
1221 }
1222
1223 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1224 {
1225         /* what IP to use for this? */
1226         switch (adev->ip_versions[GC_HWIP][0]) {
1227         case IP_VERSION(9, 0, 1):
1228         case IP_VERSION(9, 1, 0):
1229         case IP_VERSION(9, 2, 1):
1230         case IP_VERSION(9, 2, 2):
1231         case IP_VERSION(9, 3, 0):
1232         case IP_VERSION(9, 4, 0):
1233         case IP_VERSION(9, 4, 1):
1234         case IP_VERSION(9, 4, 2):
1235                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1236                 break;
1237         case IP_VERSION(10, 1, 10):
1238         case IP_VERSION(10, 1, 1):
1239         case IP_VERSION(10, 1, 2):
1240         case IP_VERSION(10, 1, 3):
1241         case IP_VERSION(10, 1, 4):
1242         case IP_VERSION(10, 3, 0):
1243         case IP_VERSION(10, 3, 1):
1244         case IP_VERSION(10, 3, 2):
1245         case IP_VERSION(10, 3, 3):
1246         case IP_VERSION(10, 3, 4):
1247         case IP_VERSION(10, 3, 5):
1248         case IP_VERSION(10, 3, 6):
1249         case IP_VERSION(10, 3, 7):
1250                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1251                 break;
1252         default:
1253                 dev_err(adev->dev,
1254                         "Failed to add common ip block(GC_HWIP:0x%x)\n",
1255                         adev->ip_versions[GC_HWIP][0]);
1256                 return -EINVAL;
1257         }
1258         return 0;
1259 }
1260
1261 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1262 {
1263         /* use GC or MMHUB IP version */
1264         switch (adev->ip_versions[GC_HWIP][0]) {
1265         case IP_VERSION(9, 0, 1):
1266         case IP_VERSION(9, 1, 0):
1267         case IP_VERSION(9, 2, 1):
1268         case IP_VERSION(9, 2, 2):
1269         case IP_VERSION(9, 3, 0):
1270         case IP_VERSION(9, 4, 0):
1271         case IP_VERSION(9, 4, 1):
1272         case IP_VERSION(9, 4, 2):
1273                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1274                 break;
1275         case IP_VERSION(10, 1, 10):
1276         case IP_VERSION(10, 1, 1):
1277         case IP_VERSION(10, 1, 2):
1278         case IP_VERSION(10, 1, 3):
1279         case IP_VERSION(10, 1, 4):
1280         case IP_VERSION(10, 3, 0):
1281         case IP_VERSION(10, 3, 1):
1282         case IP_VERSION(10, 3, 2):
1283         case IP_VERSION(10, 3, 3):
1284         case IP_VERSION(10, 3, 4):
1285         case IP_VERSION(10, 3, 5):
1286         case IP_VERSION(10, 3, 6):
1287         case IP_VERSION(10, 3, 7):
1288                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1289                 break;
1290         default:
1291                 dev_err(adev->dev,
1292                         "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1293                         adev->ip_versions[GC_HWIP][0]);
1294                 return -EINVAL;
1295         }
1296         return 0;
1297 }
1298
1299 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1300 {
1301         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
1302         case IP_VERSION(4, 0, 0):
1303         case IP_VERSION(4, 0, 1):
1304         case IP_VERSION(4, 1, 0):
1305         case IP_VERSION(4, 1, 1):
1306         case IP_VERSION(4, 3, 0):
1307                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1308                 break;
1309         case IP_VERSION(4, 2, 0):
1310         case IP_VERSION(4, 2, 1):
1311         case IP_VERSION(4, 4, 0):
1312                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1313                 break;
1314         case IP_VERSION(5, 0, 0):
1315         case IP_VERSION(5, 0, 1):
1316         case IP_VERSION(5, 0, 2):
1317         case IP_VERSION(5, 0, 3):
1318         case IP_VERSION(5, 2, 0):
1319         case IP_VERSION(5, 2, 1):
1320                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1321                 break;
1322         default:
1323                 dev_err(adev->dev,
1324                         "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1325                         adev->ip_versions[OSSSYS_HWIP][0]);
1326                 return -EINVAL;
1327         }
1328         return 0;
1329 }
1330
1331 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1332 {
1333         switch (adev->ip_versions[MP0_HWIP][0]) {
1334         case IP_VERSION(9, 0, 0):
1335                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1336                 break;
1337         case IP_VERSION(10, 0, 0):
1338         case IP_VERSION(10, 0, 1):
1339                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1340                 break;
1341         case IP_VERSION(11, 0, 0):
1342         case IP_VERSION(11, 0, 2):
1343         case IP_VERSION(11, 0, 4):
1344         case IP_VERSION(11, 0, 5):
1345         case IP_VERSION(11, 0, 9):
1346         case IP_VERSION(11, 0, 7):
1347         case IP_VERSION(11, 0, 11):
1348         case IP_VERSION(11, 0, 12):
1349         case IP_VERSION(11, 0, 13):
1350         case IP_VERSION(11, 5, 0):
1351                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1352                 break;
1353         case IP_VERSION(11, 0, 8):
1354                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1355                 break;
1356         case IP_VERSION(11, 0, 3):
1357         case IP_VERSION(12, 0, 1):
1358                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1359                 break;
1360         case IP_VERSION(13, 0, 1):
1361         case IP_VERSION(13, 0, 2):
1362         case IP_VERSION(13, 0, 3):
1363         case IP_VERSION(13, 0, 5):
1364         case IP_VERSION(13, 0, 8):
1365                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1366                 break;
1367         default:
1368                 dev_err(adev->dev,
1369                         "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1370                         adev->ip_versions[MP0_HWIP][0]);
1371                 return -EINVAL;
1372         }
1373         return 0;
1374 }
1375
1376 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1377 {
1378         switch (adev->ip_versions[MP1_HWIP][0]) {
1379         case IP_VERSION(9, 0, 0):
1380         case IP_VERSION(10, 0, 0):
1381         case IP_VERSION(10, 0, 1):
1382         case IP_VERSION(11, 0, 2):
1383                 if (adev->asic_type == CHIP_ARCTURUS)
1384                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1385                 else
1386                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1387                 break;
1388         case IP_VERSION(11, 0, 0):
1389         case IP_VERSION(11, 0, 5):
1390         case IP_VERSION(11, 0, 9):
1391         case IP_VERSION(11, 0, 7):
1392         case IP_VERSION(11, 0, 8):
1393         case IP_VERSION(11, 0, 11):
1394         case IP_VERSION(11, 0, 12):
1395         case IP_VERSION(11, 0, 13):
1396         case IP_VERSION(11, 5, 0):
1397                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1398                 break;
1399         case IP_VERSION(12, 0, 0):
1400         case IP_VERSION(12, 0, 1):
1401                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1402                 break;
1403         case IP_VERSION(13, 0, 1):
1404         case IP_VERSION(13, 0, 2):
1405         case IP_VERSION(13, 0, 3):
1406         case IP_VERSION(13, 0, 5):
1407         case IP_VERSION(13, 0, 8):
1408                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1409                 break;
1410         default:
1411                 dev_err(adev->dev,
1412                         "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
1413                         adev->ip_versions[MP1_HWIP][0]);
1414                 return -EINVAL;
1415         }
1416         return 0;
1417 }
1418
1419 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
1420 {
1421         if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
1422                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1423                 return 0;
1424         }
1425
1426         if (!amdgpu_device_has_dc_support(adev))
1427                 return 0;
1428
1429 #if defined(CONFIG_DRM_AMD_DC)
1430         if (adev->ip_versions[DCE_HWIP][0]) {
1431                 switch (adev->ip_versions[DCE_HWIP][0]) {
1432                 case IP_VERSION(1, 0, 0):
1433                 case IP_VERSION(1, 0, 1):
1434                 case IP_VERSION(2, 0, 2):
1435                 case IP_VERSION(2, 0, 0):
1436                 case IP_VERSION(2, 0, 3):
1437                 case IP_VERSION(2, 1, 0):
1438                 case IP_VERSION(3, 0, 0):
1439                 case IP_VERSION(3, 0, 2):
1440                 case IP_VERSION(3, 0, 3):
1441                 case IP_VERSION(3, 0, 1):
1442                 case IP_VERSION(3, 1, 2):
1443                 case IP_VERSION(3, 1, 3):
1444                 case IP_VERSION(3, 1, 5):
1445                 case IP_VERSION(3, 1, 6):
1446                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1447                         break;
1448                 default:
1449                         dev_err(adev->dev,
1450                                 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
1451                                 adev->ip_versions[DCE_HWIP][0]);
1452                         return -EINVAL;
1453                 }
1454         } else if (adev->ip_versions[DCI_HWIP][0]) {
1455                 switch (adev->ip_versions[DCI_HWIP][0]) {
1456                 case IP_VERSION(12, 0, 0):
1457                 case IP_VERSION(12, 0, 1):
1458                 case IP_VERSION(12, 1, 0):
1459                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1460                         break;
1461                 default:
1462                         dev_err(adev->dev,
1463                                 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
1464                                 adev->ip_versions[DCI_HWIP][0]);
1465                         return -EINVAL;
1466                 }
1467         }
1468 #endif
1469         return 0;
1470 }
1471
1472 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
1473 {
1474         switch (adev->ip_versions[GC_HWIP][0]) {
1475         case IP_VERSION(9, 0, 1):
1476         case IP_VERSION(9, 1, 0):
1477         case IP_VERSION(9, 2, 1):
1478         case IP_VERSION(9, 2, 2):
1479         case IP_VERSION(9, 3, 0):
1480         case IP_VERSION(9, 4, 0):
1481         case IP_VERSION(9, 4, 1):
1482         case IP_VERSION(9, 4, 2):
1483                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1484                 break;
1485         case IP_VERSION(10, 1, 10):
1486         case IP_VERSION(10, 1, 2):
1487         case IP_VERSION(10, 1, 1):
1488         case IP_VERSION(10, 1, 3):
1489         case IP_VERSION(10, 1, 4):
1490         case IP_VERSION(10, 3, 0):
1491         case IP_VERSION(10, 3, 2):
1492         case IP_VERSION(10, 3, 1):
1493         case IP_VERSION(10, 3, 4):
1494         case IP_VERSION(10, 3, 5):
1495         case IP_VERSION(10, 3, 6):
1496         case IP_VERSION(10, 3, 3):
1497         case IP_VERSION(10, 3, 7):
1498                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1499                 break;
1500         default:
1501                 dev_err(adev->dev,
1502                         "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
1503                         adev->ip_versions[GC_HWIP][0]);
1504                 return -EINVAL;
1505         }
1506         return 0;
1507 }
1508
1509 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
1510 {
1511         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1512         case IP_VERSION(4, 0, 0):
1513         case IP_VERSION(4, 0, 1):
1514         case IP_VERSION(4, 1, 0):
1515         case IP_VERSION(4, 1, 1):
1516         case IP_VERSION(4, 1, 2):
1517         case IP_VERSION(4, 2, 0):
1518         case IP_VERSION(4, 2, 2):
1519         case IP_VERSION(4, 4, 0):
1520                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1521                 break;
1522         case IP_VERSION(5, 0, 0):
1523         case IP_VERSION(5, 0, 1):
1524         case IP_VERSION(5, 0, 2):
1525         case IP_VERSION(5, 0, 5):
1526                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
1527                 break;
1528         case IP_VERSION(5, 2, 0):
1529         case IP_VERSION(5, 2, 2):
1530         case IP_VERSION(5, 2, 4):
1531         case IP_VERSION(5, 2, 5):
1532         case IP_VERSION(5, 2, 6):
1533         case IP_VERSION(5, 2, 3):
1534         case IP_VERSION(5, 2, 1):
1535         case IP_VERSION(5, 2, 7):
1536                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1537                 break;
1538         default:
1539                 dev_err(adev->dev,
1540                         "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
1541                         adev->ip_versions[SDMA0_HWIP][0]);
1542                 return -EINVAL;
1543         }
1544         return 0;
1545 }
1546
1547 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
1548 {
1549         if (adev->ip_versions[VCE_HWIP][0]) {
1550                 switch (adev->ip_versions[UVD_HWIP][0]) {
1551                 case IP_VERSION(7, 0, 0):
1552                 case IP_VERSION(7, 2, 0):
1553                         /* UVD is not supported on vega20 SR-IOV */
1554                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1555                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
1556                         break;
1557                 default:
1558                         dev_err(adev->dev,
1559                                 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
1560                                 adev->ip_versions[UVD_HWIP][0]);
1561                         return -EINVAL;
1562                 }
1563                 switch (adev->ip_versions[VCE_HWIP][0]) {
1564                 case IP_VERSION(4, 0, 0):
1565                 case IP_VERSION(4, 1, 0):
1566                         /* VCE is not supported on vega20 SR-IOV */
1567                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1568                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
1569                         break;
1570                 default:
1571                         dev_err(adev->dev,
1572                                 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
1573                                 adev->ip_versions[VCE_HWIP][0]);
1574                         return -EINVAL;
1575                 }
1576         } else {
1577                 switch (adev->ip_versions[UVD_HWIP][0]) {
1578                 case IP_VERSION(1, 0, 0):
1579                 case IP_VERSION(1, 0, 1):
1580                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1581                         break;
1582                 case IP_VERSION(2, 0, 0):
1583                 case IP_VERSION(2, 0, 2):
1584                 case IP_VERSION(2, 2, 0):
1585                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
1586                         if (!amdgpu_sriov_vf(adev))
1587                                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1588                         break;
1589                 case IP_VERSION(2, 0, 3):
1590                         break;
1591                 case IP_VERSION(2, 5, 0):
1592                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1593                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1594                         break;
1595                 case IP_VERSION(2, 6, 0):
1596                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1597                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1598                         break;
1599                 case IP_VERSION(3, 0, 0):
1600                 case IP_VERSION(3, 0, 16):
1601                 case IP_VERSION(3, 1, 1):
1602                 case IP_VERSION(3, 1, 2):
1603                 case IP_VERSION(3, 0, 2):
1604                 case IP_VERSION(3, 0, 192):
1605                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1606                         if (!amdgpu_sriov_vf(adev))
1607                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
1608                         break;
1609                 case IP_VERSION(3, 0, 33):
1610                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1611                         break;
1612                 default:
1613                         dev_err(adev->dev,
1614                                 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
1615                                 adev->ip_versions[UVD_HWIP][0]);
1616                         return -EINVAL;
1617                 }
1618         }
1619         return 0;
1620 }
1621
1622 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
1623 {
1624         switch (adev->ip_versions[GC_HWIP][0]) {
1625         case IP_VERSION(10, 1, 10):
1626         case IP_VERSION(10, 1, 1):
1627         case IP_VERSION(10, 1, 2):
1628         case IP_VERSION(10, 1, 3):
1629         case IP_VERSION(10, 1, 4):
1630         case IP_VERSION(10, 3, 0):
1631         case IP_VERSION(10, 3, 1):
1632         case IP_VERSION(10, 3, 2):
1633         case IP_VERSION(10, 3, 3):
1634         case IP_VERSION(10, 3, 4):
1635         case IP_VERSION(10, 3, 5):
1636         case IP_VERSION(10, 3, 6):
1637                 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
1638                 break;
1639         default:
1640                 break;
1641         }
1642         return 0;
1643 }
1644
1645 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
1646 {
1647         int r;
1648
1649         switch (adev->asic_type) {
1650         case CHIP_VEGA10:
1651                 vega10_reg_base_init(adev);
1652                 adev->sdma.num_instances = 2;
1653                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1654                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1655                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
1656                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
1657                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
1658                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
1659                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1660                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
1661                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
1662                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1663                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1664                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1665                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
1666                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
1667                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1668                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1669                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
1670                 break;
1671         case CHIP_VEGA12:
1672                 vega10_reg_base_init(adev);
1673                 adev->sdma.num_instances = 2;
1674                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1675                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1676                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
1677                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
1678                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
1679                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
1680                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
1681                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
1682                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
1683                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1684                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1685                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1686                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
1687                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
1688                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1689                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1690                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
1691                 break;
1692         case CHIP_RAVEN:
1693                 vega10_reg_base_init(adev);
1694                 adev->sdma.num_instances = 1;
1695                 adev->vcn.num_vcn_inst = 1;
1696                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1697                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1698                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1699                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
1700                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
1701                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
1702                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
1703                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
1704                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
1705                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
1706                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
1707                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
1708                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
1709                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
1710                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
1711                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
1712                 } else {
1713                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1714                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1715                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
1716                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
1717                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
1718                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1719                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
1720                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
1721                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
1722                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
1723                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
1724                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
1725                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
1726                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
1727                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
1728                 }
1729                 break;
1730         case CHIP_VEGA20:
1731                 vega20_reg_base_init(adev);
1732                 adev->sdma.num_instances = 2;
1733                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1734                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1735                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
1736                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
1737                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
1738                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
1739                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
1740                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
1741                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
1742                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
1743                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1744                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
1745                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
1746                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
1747                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
1748                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
1749                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
1750                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
1751                 break;
1752         case CHIP_ARCTURUS:
1753                 arct_reg_base_init(adev);
1754                 adev->sdma.num_instances = 8;
1755                 adev->vcn.num_vcn_inst = 2;
1756                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1757                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1758                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
1759                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
1760                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
1761                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
1762                 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
1763                 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
1764                 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
1765                 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
1766                 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
1767                 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
1768                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
1769                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
1770                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
1771                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
1772                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1773                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
1774                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
1775                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
1776                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
1777                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
1778                 break;
1779         case CHIP_ALDEBARAN:
1780                 aldebaran_reg_base_init(adev);
1781                 adev->sdma.num_instances = 5;
1782                 adev->vcn.num_vcn_inst = 2;
1783                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1784                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1785                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
1786                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
1787                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
1788                 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
1789                 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
1790                 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
1791                 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
1792                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
1793                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
1794                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
1795                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
1796                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
1797                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
1798                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
1799                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
1800                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
1801                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
1802                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
1803                 break;
1804         default:
1805                 r = amdgpu_discovery_reg_base_init(adev);
1806                 if (r)
1807                         return -EINVAL;
1808
1809                 amdgpu_discovery_harvest_ip(adev);
1810                 break;
1811         }
1812
1813         switch (adev->ip_versions[GC_HWIP][0]) {
1814         case IP_VERSION(9, 0, 1):
1815         case IP_VERSION(9, 2, 1):
1816         case IP_VERSION(9, 4, 0):
1817         case IP_VERSION(9, 4, 1):
1818         case IP_VERSION(9, 4, 2):
1819                 adev->family = AMDGPU_FAMILY_AI;
1820                 break;
1821         case IP_VERSION(9, 1, 0):
1822         case IP_VERSION(9, 2, 2):
1823         case IP_VERSION(9, 3, 0):
1824                 adev->family = AMDGPU_FAMILY_RV;
1825                 break;
1826         case IP_VERSION(10, 1, 10):
1827         case IP_VERSION(10, 1, 1):
1828         case IP_VERSION(10, 1, 2):
1829         case IP_VERSION(10, 1, 3):
1830         case IP_VERSION(10, 1, 4):
1831         case IP_VERSION(10, 3, 0):
1832         case IP_VERSION(10, 3, 2):
1833         case IP_VERSION(10, 3, 4):
1834         case IP_VERSION(10, 3, 5):
1835                 adev->family = AMDGPU_FAMILY_NV;
1836                 break;
1837         case IP_VERSION(10, 3, 1):
1838                 adev->family = AMDGPU_FAMILY_VGH;
1839                 break;
1840         case IP_VERSION(10, 3, 3):
1841                 adev->family = AMDGPU_FAMILY_YC;
1842                 break;
1843         case IP_VERSION(10, 3, 6):
1844                 adev->family = AMDGPU_FAMILY_GC_10_3_6;
1845                 break;
1846         case IP_VERSION(10, 3, 7):
1847                 adev->family = AMDGPU_FAMILY_GC_10_3_7;
1848                 break;
1849         default:
1850                 return -EINVAL;
1851         }
1852
1853         switch (adev->ip_versions[GC_HWIP][0]) {
1854         case IP_VERSION(9, 1, 0):
1855         case IP_VERSION(9, 2, 2):
1856         case IP_VERSION(9, 3, 0):
1857         case IP_VERSION(10, 1, 3):
1858         case IP_VERSION(10, 1, 4):
1859         case IP_VERSION(10, 3, 1):
1860         case IP_VERSION(10, 3, 3):
1861         case IP_VERSION(10, 3, 6):
1862         case IP_VERSION(10, 3, 7):
1863                 adev->flags |= AMD_IS_APU;
1864                 break;
1865         default:
1866                 break;
1867         }
1868
1869         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
1870                 adev->gmc.xgmi.supported = true;
1871
1872         /* set NBIO version */
1873         switch (adev->ip_versions[NBIO_HWIP][0]) {
1874         case IP_VERSION(6, 1, 0):
1875         case IP_VERSION(6, 2, 0):
1876                 adev->nbio.funcs = &nbio_v6_1_funcs;
1877                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
1878                 break;
1879         case IP_VERSION(7, 0, 0):
1880         case IP_VERSION(7, 0, 1):
1881         case IP_VERSION(2, 5, 0):
1882                 adev->nbio.funcs = &nbio_v7_0_funcs;
1883                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
1884                 break;
1885         case IP_VERSION(7, 4, 0):
1886         case IP_VERSION(7, 4, 1):
1887                 adev->nbio.funcs = &nbio_v7_4_funcs;
1888                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
1889                 break;
1890         case IP_VERSION(7, 4, 4):
1891                 adev->nbio.funcs = &nbio_v7_4_funcs;
1892                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
1893                 break;
1894         case IP_VERSION(7, 2, 0):
1895         case IP_VERSION(7, 2, 1):
1896         case IP_VERSION(7, 3, 0):
1897         case IP_VERSION(7, 5, 0):
1898         case IP_VERSION(7, 5, 1):
1899                 adev->nbio.funcs = &nbio_v7_2_funcs;
1900                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
1901                 break;
1902         case IP_VERSION(2, 1, 1):
1903         case IP_VERSION(2, 3, 0):
1904         case IP_VERSION(2, 3, 1):
1905         case IP_VERSION(2, 3, 2):
1906                 adev->nbio.funcs = &nbio_v2_3_funcs;
1907                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
1908                 break;
1909         case IP_VERSION(3, 3, 0):
1910         case IP_VERSION(3, 3, 1):
1911         case IP_VERSION(3, 3, 2):
1912         case IP_VERSION(3, 3, 3):
1913                 adev->nbio.funcs = &nbio_v2_3_funcs;
1914                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
1915                 break;
1916         default:
1917                 break;
1918         }
1919
1920         switch (adev->ip_versions[HDP_HWIP][0]) {
1921         case IP_VERSION(4, 0, 0):
1922         case IP_VERSION(4, 0, 1):
1923         case IP_VERSION(4, 1, 0):
1924         case IP_VERSION(4, 1, 1):
1925         case IP_VERSION(4, 1, 2):
1926         case IP_VERSION(4, 2, 0):
1927         case IP_VERSION(4, 2, 1):
1928         case IP_VERSION(4, 4, 0):
1929                 adev->hdp.funcs = &hdp_v4_0_funcs;
1930                 break;
1931         case IP_VERSION(5, 0, 0):
1932         case IP_VERSION(5, 0, 1):
1933         case IP_VERSION(5, 0, 2):
1934         case IP_VERSION(5, 0, 3):
1935         case IP_VERSION(5, 0, 4):
1936         case IP_VERSION(5, 2, 0):
1937                 adev->hdp.funcs = &hdp_v5_0_funcs;
1938                 break;
1939         default:
1940                 break;
1941         }
1942
1943         switch (adev->ip_versions[DF_HWIP][0]) {
1944         case IP_VERSION(3, 6, 0):
1945         case IP_VERSION(3, 6, 1):
1946         case IP_VERSION(3, 6, 2):
1947                 adev->df.funcs = &df_v3_6_funcs;
1948                 break;
1949         case IP_VERSION(2, 1, 0):
1950         case IP_VERSION(2, 1, 1):
1951         case IP_VERSION(2, 5, 0):
1952         case IP_VERSION(3, 5, 1):
1953         case IP_VERSION(3, 5, 2):
1954                 adev->df.funcs = &df_v1_7_funcs;
1955                 break;
1956         default:
1957                 break;
1958         }
1959
1960         switch (adev->ip_versions[SMUIO_HWIP][0]) {
1961         case IP_VERSION(9, 0, 0):
1962         case IP_VERSION(9, 0, 1):
1963         case IP_VERSION(10, 0, 0):
1964         case IP_VERSION(10, 0, 1):
1965         case IP_VERSION(10, 0, 2):
1966                 adev->smuio.funcs = &smuio_v9_0_funcs;
1967                 break;
1968         case IP_VERSION(11, 0, 0):
1969         case IP_VERSION(11, 0, 2):
1970         case IP_VERSION(11, 0, 3):
1971         case IP_VERSION(11, 0, 4):
1972         case IP_VERSION(11, 0, 7):
1973         case IP_VERSION(11, 0, 8):
1974                 adev->smuio.funcs = &smuio_v11_0_funcs;
1975                 break;
1976         case IP_VERSION(11, 0, 6):
1977         case IP_VERSION(11, 0, 10):
1978         case IP_VERSION(11, 0, 11):
1979         case IP_VERSION(11, 5, 0):
1980         case IP_VERSION(13, 0, 1):
1981         case IP_VERSION(13, 0, 9):
1982         case IP_VERSION(13, 0, 10):
1983                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
1984                 break;
1985         case IP_VERSION(13, 0, 2):
1986                 adev->smuio.funcs = &smuio_v13_0_funcs;
1987                 break;
1988         default:
1989                 break;
1990         }
1991
1992         r = amdgpu_discovery_set_common_ip_blocks(adev);
1993         if (r)
1994                 return r;
1995
1996         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
1997         if (r)
1998                 return r;
1999
2000         /* For SR-IOV, PSP needs to be initialized before IH */
2001         if (amdgpu_sriov_vf(adev)) {
2002                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2003                 if (r)
2004                         return r;
2005                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2006                 if (r)
2007                         return r;
2008         } else {
2009                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2010                 if (r)
2011                         return r;
2012
2013                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2014                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
2015                         if (r)
2016                                 return r;
2017                 }
2018         }
2019
2020         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2021                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2022                 if (r)
2023                         return r;
2024         }
2025
2026         r = amdgpu_discovery_set_display_ip_blocks(adev);
2027         if (r)
2028                 return r;
2029
2030         r = amdgpu_discovery_set_gc_ip_blocks(adev);
2031         if (r)
2032                 return r;
2033
2034         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
2035         if (r)
2036                 return r;
2037
2038         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
2039             !amdgpu_sriov_vf(adev)) {
2040                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2041                 if (r)
2042                         return r;
2043         }
2044
2045         r = amdgpu_discovery_set_mm_ip_blocks(adev);
2046         if (r)
2047                 return r;
2048
2049         if (adev->enable_mes) {
2050                 r = amdgpu_discovery_set_mes_ip_blocks(adev);
2051                 if (r)
2052                         return r;
2053         }
2054
2055         return 0;
2056 }
2057