drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30
  31 #include "soc15.h"
  32 #include "gfx_v9_0.h"
  33 #include "gmc_v9_0.h"
  34 #include "df_v1_7.h"
  35 #include "df_v3_6.h"
  36 #include "nbio_v6_1.h"
  37 #include "nbio_v7_0.h"
  38 #include "nbio_v7_4.h"
  39 #include "hdp_v4_0.h"
  40 #include "vega10_ih.h"
  41 #include "vega20_ih.h"
  42 #include "sdma_v4_0.h"
  43 #include "uvd_v7_0.h"
  44 #include "vce_v4_0.h"
  45 #include "vcn_v1_0.h"
  46 #include "vcn_v2_5.h"
  47 #include "jpeg_v2_5.h"
  48 #include "smuio_v9_0.h"
  49 #include "gmc_v10_0.h"
  50 #include "gfxhub_v2_0.h"
  51 #include "mmhub_v2_0.h"
  52 #include "nbio_v2_3.h"
  53 #include "nbio_v7_2.h"
  54 #include "hdp_v5_0.h"
  55 #include "nv.h"
  56 #include "navi10_ih.h"
  57 #include "gfx_v10_0.h"
  58 #include "sdma_v5_0.h"
  59 #include "sdma_v5_2.h"
  60 #include "vcn_v2_0.h"
  61 #include "jpeg_v2_0.h"
  62 #include "vcn_v3_0.h"
  63 #include "jpeg_v3_0.h"
  64 #include "amdgpu_vkms.h"
  65 #include "mes_v10_1.h"
  66 #include "smuio_v11_0.h"
  67 #include "smuio_v11_0_6.h"
  68 #include "smuio_v13_0.h"
  69
  70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
  71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
  72
  73 #define mmRCC_CONFIG_MEMSIZE    0xde3
  74 #define mmMM_INDEX              0x0
  75 #define mmMM_INDEX_HI           0x6
  76 #define mmMM_DATA               0x1
  77
  78 static const char *hw_id_names[HW_ID_MAX] = {
  79         [MP1_HWID]              = "MP1",
  80         [MP2_HWID]              = "MP2",
  81         [THM_HWID]              = "THM",
  82         [SMUIO_HWID]            = "SMUIO",
  83         [FUSE_HWID]             = "FUSE",
  84         [CLKA_HWID]             = "CLKA",
  85         [PWR_HWID]              = "PWR",
  86         [GC_HWID]               = "GC",
  87         [UVD_HWID]              = "UVD",
  88         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
  89         [ACP_HWID]              = "ACP",
  90         [DCI_HWID]              = "DCI",
  91         [DMU_HWID]              = "DMU",
  92         [DCO_HWID]              = "DCO",
  93         [DIO_HWID]              = "DIO",
  94         [XDMA_HWID]             = "XDMA",
  95         [DCEAZ_HWID]            = "DCEAZ",
  96         [DAZ_HWID]              = "DAZ",
  97         [SDPMUX_HWID]           = "SDPMUX",
  98         [NTB_HWID]              = "NTB",
  99         [IOHC_HWID]             = "IOHC",
 100         [L2IMU_HWID]            = "L2IMU",
 101         [VCE_HWID]              = "VCE",
 102         [MMHUB_HWID]            = "MMHUB",
 103         [ATHUB_HWID]            = "ATHUB",
 104         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 105         [DFX_HWID]              = "DFX",
 106         [DBGU0_HWID]            = "DBGU0",
 107         [DBGU1_HWID]            = "DBGU1",
 108         [OSSSYS_HWID]           = "OSSSYS",
 109         [HDP_HWID]              = "HDP",
 110         [SDMA0_HWID]            = "SDMA0",
 111         [SDMA1_HWID]            = "SDMA1",
 112         [SDMA2_HWID]            = "SDMA2",
 113         [SDMA3_HWID]            = "SDMA3",
 114         [ISP_HWID]              = "ISP",
 115         [DBGU_IO_HWID]          = "DBGU_IO",
 116         [DF_HWID]               = "DF",
 117         [CLKB_HWID]             = "CLKB",
 118         [FCH_HWID]              = "FCH",
 119         [DFX_DAP_HWID]          = "DFX_DAP",
 120         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 121         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 122         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 123         [L1IMU3_HWID]           = "L1IMU3",
 124         [L1IMU4_HWID]           = "L1IMU4",
 125         [L1IMU5_HWID]           = "L1IMU5",
 126         [L1IMU6_HWID]           = "L1IMU6",
 127         [L1IMU7_HWID]           = "L1IMU7",
 128         [L1IMU8_HWID]           = "L1IMU8",
 129         [L1IMU9_HWID]           = "L1IMU9",
 130         [L1IMU10_HWID]          = "L1IMU10",
 131         [L1IMU11_HWID]          = "L1IMU11",
 132         [L1IMU12_HWID]          = "L1IMU12",
 133         [L1IMU13_HWID]          = "L1IMU13",
 134         [L1IMU14_HWID]          = "L1IMU14",
 135         [L1IMU15_HWID]          = "L1IMU15",
 136         [WAFLC_HWID]            = "WAFLC",
 137         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 138         [PCIE_HWID]             = "PCIE",
 139         [PCS_HWID]              = "PCS",
 140         [DDCL_HWID]             = "DDCL",
 141         [SST_HWID]              = "SST",
 142         [IOAGR_HWID]            = "IOAGR",
 143         [NBIF_HWID]             = "NBIF",
 144         [IOAPIC_HWID]           = "IOAPIC",
 145         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 146         [NTBCCP_HWID]           = "NTBCCP",
 147         [UMC_HWID]              = "UMC",
 148         [SATA_HWID]             = "SATA",
 149         [USB_HWID]              = "USB",
 150         [CCXSEC_HWID]           = "CCXSEC",
 151         [XGMI_HWID]             = "XGMI",
 152         [XGBE_HWID]             = "XGBE",
 153         [MP0_HWID]              = "MP0",
 154 };
 155
 156 static int hw_id_map[MAX_HWIP] = {
 157         [GC_HWIP]       = GC_HWID,
 158         [HDP_HWIP]      = HDP_HWID,
 159         [SDMA0_HWIP]    = SDMA0_HWID,
 160         [SDMA1_HWIP]    = SDMA1_HWID,
 161         [SDMA2_HWIP]    = SDMA2_HWID,
 162         [SDMA3_HWIP]    = SDMA3_HWID,
 163         [MMHUB_HWIP]    = MMHUB_HWID,
 164         [ATHUB_HWIP]    = ATHUB_HWID,
 165         [NBIO_HWIP]     = NBIF_HWID,
 166         [MP0_HWIP]      = MP0_HWID,
 167         [MP1_HWIP]      = MP1_HWID,
 168         [UVD_HWIP]      = UVD_HWID,
 169         [VCE_HWIP]      = VCE_HWID,
 170         [DF_HWIP]       = DF_HWID,
 171         [DCE_HWIP]      = DMU_HWID,
 172         [OSSSYS_HWIP]   = OSSSYS_HWID,
 173         [SMUIO_HWIP]    = SMUIO_HWID,
 174         [PWR_HWIP]      = PWR_HWID,
 175         [NBIF_HWIP]     = NBIF_HWID,
 176         [THM_HWIP]      = THM_HWID,
 177         [CLK_HWIP]      = CLKA_HWID,
 178         [UMC_HWIP]      = UMC_HWID,
 179         [XGMI_HWIP]     = XGMI_HWID,
 180         [DCI_HWIP]      = DCI_HWID,
 181 };
 182
 183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
 184 {
 185         uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 186         uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 187
 188         amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 189                                   adev->mman.discovery_tmr_size, false);
 190         return 0;
 191 }
 192
 193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
 194 {
 195         const struct firmware *fw;
 196         const char *fw_name;
 197         int r;
 198
 199         switch (amdgpu_discovery) {
 200         case 2:
 201                 fw_name = FIRMWARE_IP_DISCOVERY;
 202                 break;
 203         default:
 204                 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
 205                 return -EINVAL;
 206         }
 207
 208         r = request_firmware(&fw, fw_name, adev->dev);
 209         if (r) {
 210                 dev_err(adev->dev, "can't load firmware \"%s\"\n",
 211                         fw_name);
 212                 return r;
 213         }
 214
 215         memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
 216         release_firmware(fw);
 217
 218         return 0;
 219 }
 220
 221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 222 {
 223         uint16_t checksum = 0;
 224         int i;
 225
 226         for (i = 0; i < size; i++)
 227                 checksum += data[i];
 228
 229         return checksum;
 230 }
 231
 232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 233                                                     uint16_t expected)
 234 {
 235         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 236 }
 237
 238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
 239 {
 240         struct binary_header *bhdr;
 241         bhdr = (struct binary_header *)binary;
 242
 243         return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
 244 }
 245
 246 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
 247 {
 248         /*
 249          * So far, apply this quirk only on those Navy Flounder boards which
 250          * have a bad harvest table of VCN config.
 251          */
 252         if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
 253                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
 254                 switch (adev->pdev->revision) {
 255                 case 0xC1:
 256                 case 0xC2:
 257                 case 0xC3:
 258                 case 0xC5:
 259                 case 0xC7:
 260                 case 0xCF:
 261                 case 0xDF:
 262                         adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 263                         break;
 264                 default:
 265                         break;
 266                 }
 267         }
 268 }
 269
 270 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 271 {
 272         struct table_info *info;
 273         struct binary_header *bhdr;
 274         struct ip_discovery_header *ihdr;
 275         struct gpu_info_header *ghdr;
 276         uint16_t offset;
 277         uint16_t size;
 278         uint16_t checksum;
 279         int r;
 280
 281         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 282         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 283         if (!adev->mman.discovery_bin)
 284                 return -ENOMEM;
 285
 286         r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin);
 287         if (r) {
 288                 dev_err(adev->dev, "failed to read ip discovery binary from vram\n");
 289                 r = -EINVAL;
 290                 goto out;
 291         }
 292
 293         if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 294                 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n");
 295                 /* retry read ip discovery binary from file */
 296                 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
 297                 if (r) {
 298                         dev_err(adev->dev, "failed to read ip discovery binary from file\n");
 299                         r = -EINVAL;
 300                         goto out;
 301                 }
 302                 /* check the ip discovery binary signature */
 303                 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 304                         dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n");
 305                         r = -EINVAL;
 306                         goto out;
 307                 }
 308         }
 309
 310         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 311
 312         offset = offsetof(struct binary_header, binary_checksum) +
 313                 sizeof(bhdr->binary_checksum);
 314         size = le16_to_cpu(bhdr->binary_size) - offset;
 315         checksum = le16_to_cpu(bhdr->binary_checksum);
 316
 317         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 318                                               size, checksum)) {
 319                 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
 320                 r = -EINVAL;
 321                 goto out;
 322         }
 323
 324         info = &bhdr->table_list[IP_DISCOVERY];
 325         offset = le16_to_cpu(info->offset);
 326         checksum = le16_to_cpu(info->checksum);
 327         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 328
 329         if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 330                 dev_err(adev->dev, "invalid ip discovery data table signature\n");
 331                 r = -EINVAL;
 332                 goto out;
 333         }
 334
 335         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 336                                               le16_to_cpu(ihdr->size), checksum)) {
 337                 dev_err(adev->dev, "invalid ip discovery data table checksum\n");
 338                 r = -EINVAL;
 339                 goto out;
 340         }
 341
 342         info = &bhdr->table_list[GC];
 343         offset = le16_to_cpu(info->offset);
 344         checksum = le16_to_cpu(info->checksum);
 345         ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 346
 347         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 348                                               le32_to_cpu(ghdr->size), checksum)) {
 349                 dev_err(adev->dev, "invalid gc data table checksum\n");
 350                 r = -EINVAL;
 351                 goto out;
 352         }
 353
 354         return 0;
 355
 356 out:
 357         kfree(adev->mman.discovery_bin);
 358         adev->mman.discovery_bin = NULL;
 359
 360         return r;
 361 }
 362
 363 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
 364
 365 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 366 {
 367         amdgpu_discovery_sysfs_fini(adev);
 368         kfree(adev->mman.discovery_bin);
 369         adev->mman.discovery_bin = NULL;
 370 }
 371
 372 static int amdgpu_discovery_validate_ip(const struct ip *ip)
 373 {
 374         if (ip->number_instance >= HWIP_MAX_INSTANCE) {
 375                 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
 376                           ip->number_instance);
 377                 return -EINVAL;
 378         }
 379         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 380                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 381                           le16_to_cpu(ip->hw_id));
 382                 return -EINVAL;
 383         }
 384
 385         return 0;
 386 }
 387
 388 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
 389                                                 uint32_t *vcn_harvest_count)
 390 {
 391         struct binary_header *bhdr;
 392         struct ip_discovery_header *ihdr;
 393         struct die_header *dhdr;
 394         struct ip *ip;
 395         uint16_t die_offset, ip_offset, num_dies, num_ips;
 396         int i, j;
 397
 398         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 399         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 400                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 401         num_dies = le16_to_cpu(ihdr->num_dies);
 402
 403         /* scan harvest bit of all IP data structures */
 404         for (i = 0; i < num_dies; i++) {
 405                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 406                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 407                 num_ips = le16_to_cpu(dhdr->num_ips);
 408                 ip_offset = die_offset + sizeof(*dhdr);
 409
 410                 for (j = 0; j < num_ips; j++) {
 411                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 412
 413                         if (amdgpu_discovery_validate_ip(ip))
 414                                 goto next_ip;
 415
 416                         if (le16_to_cpu(ip->harvest) == 1) {
 417                                 switch (le16_to_cpu(ip->hw_id)) {
 418                                 case VCN_HWID:
 419                                         (*vcn_harvest_count)++;
 420                                         if (ip->number_instance == 0)
 421                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 422                                         else
 423                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 424                                         break;
 425                                 case DMU_HWID:
 426                                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 427                                         break;
 428                                 default:
 429                                         break;
 430                                 }
 431                         }
 432 next_ip:
 433                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
 434                 }
 435         }
 436 }
 437
 438 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
 439                                                      uint32_t *vcn_harvest_count,
 440                                                      uint32_t *umc_harvest_count)
 441 {
 442         struct binary_header *bhdr;
 443         struct harvest_table *harvest_info;
 444         int i;
 445
 446         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 447         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
 448                         le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
 449         for (i = 0; i < 32; i++) {
 450                 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
 451                         break;
 452
 453                 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
 454                 case VCN_HWID:
 455                         (*vcn_harvest_count)++;
 456                         if (harvest_info->list[i].number_instance == 0)
 457                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 458                         else
 459                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 460                         break;
 461                 case DMU_HWID:
 462                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 463                         break;
 464                 case UMC_HWID:
 465                         (*umc_harvest_count)++;
 466                         break;
 467                 default:
 468                         break;
 469                 }
 470         }
 471 }
 472
 473 /* ================================================== */
 474
 475 struct ip_hw_instance {
 476         struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
 477
 478         int hw_id;
 479         u8  num_instance;
 480         u8  major, minor, revision;
 481         u8  harvest;
 482
 483         int num_base_addresses;
 484         u32 base_addr[];
 485 };
 486
 487 struct ip_hw_id {
 488         struct kset hw_id_kset;  /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
 489         int hw_id;
 490 };
 491
 492 struct ip_die_entry {
 493         struct kset ip_kset;     /* ip_discovery/die/#die/, contains ip_hw_id  */
 494         u16 num_ips;
 495 };
 496
 497 /* -------------------------------------------------- */
 498
 499 struct ip_hw_instance_attr {
 500         struct attribute attr;
 501         ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
 502 };
 503
 504 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 505 {
 506         return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
 507 }
 508
 509 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 510 {
 511         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
 512 }
 513
 514 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 515 {
 516         return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
 517 }
 518
 519 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 520 {
 521         return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
 522 }
 523
 524 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 525 {
 526         return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
 527 }
 528
 529 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 530 {
 531         return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
 532 }
 533
 534 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 535 {
 536         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
 537 }
 538
 539 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 540 {
 541         ssize_t res, at;
 542         int ii;
 543
 544         for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
 545                 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
 546                  */
 547                 if (at + 12 > PAGE_SIZE)
 548                         break;
 549                 res = sysfs_emit_at(buf, at, "0x%08X\n",
 550                                     ip_hw_instance->base_addr[ii]);
 551                 if (res <= 0)
 552                         break;
 553                 at += res;
 554         }
 555
 556         return res < 0 ? res : at;
 557 }
 558
 559 static struct ip_hw_instance_attr ip_hw_attr[] = {
 560         __ATTR_RO(hw_id),
 561         __ATTR_RO(num_instance),
 562         __ATTR_RO(major),
 563         __ATTR_RO(minor),
 564         __ATTR_RO(revision),
 565         __ATTR_RO(harvest),
 566         __ATTR_RO(num_base_addresses),
 567         __ATTR_RO(base_addr),
 568 };
 569
 570 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
 571 ATTRIBUTE_GROUPS(ip_hw_instance);
 572
 573 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
 574 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
 575
 576 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
 577                                         struct attribute *attr,
 578                                         char *buf)
 579 {
 580         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 581         struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
 582
 583         if (!ip_hw_attr->show)
 584                 return -EIO;
 585
 586         return ip_hw_attr->show(ip_hw_instance, buf);
 587 }
 588
 589 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
 590         .show = ip_hw_instance_attr_show,
 591 };
 592
 593 static void ip_hw_instance_release(struct kobject *kobj)
 594 {
 595         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 596
 597         kfree(ip_hw_instance);
 598 }
 599
 600 static struct kobj_type ip_hw_instance_ktype = {
 601         .release = ip_hw_instance_release,
 602         .sysfs_ops = &ip_hw_instance_sysfs_ops,
 603         .default_groups = ip_hw_instance_groups,
 604 };
 605
 606 /* -------------------------------------------------- */
 607
 608 #define to_ip_hw_id(x)  container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
 609
 610 static void ip_hw_id_release(struct kobject *kobj)
 611 {
 612         struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
 613
 614         if (!list_empty(&ip_hw_id->hw_id_kset.list))
 615                 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
 616         kfree(ip_hw_id);
 617 }
 618
 619 static struct kobj_type ip_hw_id_ktype = {
 620         .release = ip_hw_id_release,
 621         .sysfs_ops = &kobj_sysfs_ops,
 622 };
 623
 624 /* -------------------------------------------------- */
 625
 626 static void die_kobj_release(struct kobject *kobj);
 627 static void ip_disc_release(struct kobject *kobj);
 628
 629 struct ip_die_entry_attribute {
 630         struct attribute attr;
 631         ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
 632 };
 633
 634 #define to_ip_die_entry_attr(x)  container_of(x, struct ip_die_entry_attribute, attr)
 635
 636 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
 637 {
 638         return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
 639 }
 640
 641 /* If there are more ip_die_entry attrs, other than the number of IPs,
 642  * we can make this intro an array of attrs, and then initialize
 643  * ip_die_entry_attrs in a loop.
 644  */
 645 static struct ip_die_entry_attribute num_ips_attr =
 646         __ATTR_RO(num_ips);
 647
 648 static struct attribute *ip_die_entry_attrs[] = {
 649         &num_ips_attr.attr,
 650         NULL,
 651 };
 652 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
 653
 654 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
 655
 656 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
 657                                       struct attribute *attr,
 658                                       char *buf)
 659 {
 660         struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
 661         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 662
 663         if (!ip_die_entry_attr->show)
 664                 return -EIO;
 665
 666         return ip_die_entry_attr->show(ip_die_entry, buf);
 667 }
 668
 669 static void ip_die_entry_release(struct kobject *kobj)
 670 {
 671         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 672
 673         if (!list_empty(&ip_die_entry->ip_kset.list))
 674                 DRM_ERROR("ip_die_entry->ip_kset is not empty");
 675         kfree(ip_die_entry);
 676 }
 677
 678 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
 679         .show = ip_die_entry_attr_show,
 680 };
 681
 682 static struct kobj_type ip_die_entry_ktype = {
 683         .release = ip_die_entry_release,
 684         .sysfs_ops = &ip_die_entry_sysfs_ops,
 685         .default_groups = ip_die_entry_groups,
 686 };
 687
 688 static struct kobj_type die_kobj_ktype = {
 689         .release = die_kobj_release,
 690         .sysfs_ops = &kobj_sysfs_ops,
 691 };
 692
 693 static struct kobj_type ip_discovery_ktype = {
 694         .release = ip_disc_release,
 695         .sysfs_ops = &kobj_sysfs_ops,
 696 };
 697
 698 struct ip_discovery_top {
 699         struct kobject kobj;    /* ip_discovery/ */
 700         struct kset die_kset;   /* ip_discovery/die/, contains ip_die_entry */
 701         struct amdgpu_device *adev;
 702 };
 703
 704 static void die_kobj_release(struct kobject *kobj)
 705 {
 706         struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
 707                                                        struct ip_discovery_top,
 708                                                        die_kset);
 709         if (!list_empty(&ip_top->die_kset.list))
 710                 DRM_ERROR("ip_top->die_kset is not empty");
 711 }
 712
 713 static void ip_disc_release(struct kobject *kobj)
 714 {
 715         struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
 716                                                        kobj);
 717         struct amdgpu_device *adev = ip_top->adev;
 718
 719         adev->ip_top = NULL;
 720         kfree(ip_top);
 721 }
 722
 723 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
 724                                       struct ip_die_entry *ip_die_entry,
 725                                       const size_t _ip_offset, const int num_ips)
 726 {
 727         int ii, jj, kk, res;
 728
 729         DRM_DEBUG("num_ips:%d", num_ips);
 730
 731         /* Find all IPs of a given HW ID, and add their instance to
 732          * #die/#hw_id/#instance/<attributes>
 733          */
 734         for (ii = 0; ii < HW_ID_MAX; ii++) {
 735                 struct ip_hw_id *ip_hw_id = NULL;
 736                 size_t ip_offset = _ip_offset;
 737
 738                 for (jj = 0; jj < num_ips; jj++) {
 739                         struct ip *ip;
 740                         struct ip_hw_instance *ip_hw_instance;
 741
 742                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 743                         if (amdgpu_discovery_validate_ip(ip) ||
 744                             le16_to_cpu(ip->hw_id) != ii)
 745                                 goto next_ip;
 746
 747                         DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
 748
 749                         /* We have a hw_id match; register the hw
 750                          * block if not yet registered.
 751                          */
 752                         if (!ip_hw_id) {
 753                                 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
 754                                 if (!ip_hw_id)
 755                                         return -ENOMEM;
 756                                 ip_hw_id->hw_id = ii;
 757
 758                                 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
 759                                 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
 760                                 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
 761                                 res = kset_register(&ip_hw_id->hw_id_kset);
 762                                 if (res) {
 763                                         DRM_ERROR("Couldn't register ip_hw_id kset");
 764                                         kfree(ip_hw_id);
 765                                         return res;
 766                                 }
 767                                 if (hw_id_names[ii]) {
 768                                         res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
 769                                                                 &ip_hw_id->hw_id_kset.kobj,
 770                                                                 hw_id_names[ii]);
 771                                         if (res) {
 772                                                 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
 773                                                           hw_id_names[ii],
 774                                                           kobject_name(&ip_die_entry->ip_kset.kobj));
 775                                         }
 776                                 }
 777                         }
 778
 779                         /* Now register its instance.
 780                          */
 781                         ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
 782                                                              base_addr,
 783                                                              ip->num_base_address),
 784                                                  GFP_KERNEL);
 785                         if (!ip_hw_instance) {
 786                                 DRM_ERROR("no memory for ip_hw_instance");
 787                                 return -ENOMEM;
 788                         }
 789                         ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
 790                         ip_hw_instance->num_instance = ip->number_instance;
 791                         ip_hw_instance->major = ip->major;
 792                         ip_hw_instance->minor = ip->minor;
 793                         ip_hw_instance->revision = ip->revision;
 794                         ip_hw_instance->harvest = ip->harvest;
 795                         ip_hw_instance->num_base_addresses = ip->num_base_address;
 796
 797                         for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++)
 798                                 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
 799
 800                         kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
 801                         ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
 802                         res = kobject_add(&ip_hw_instance->kobj, NULL,
 803                                           "%d", ip_hw_instance->num_instance);
 804 next_ip:
 805                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
 806                 }
 807         }
 808
 809         return 0;
 810 }
 811
 812 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
 813 {
 814         struct binary_header *bhdr;
 815         struct ip_discovery_header *ihdr;
 816         struct die_header *dhdr;
 817         struct kset *die_kset = &adev->ip_top->die_kset;
 818         u16 num_dies, die_offset, num_ips;
 819         size_t ip_offset;
 820         int ii, res;
 821
 822         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 823         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 824                                               le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 825         num_dies = le16_to_cpu(ihdr->num_dies);
 826
 827         DRM_DEBUG("number of dies: %d\n", num_dies);
 828
 829         for (ii = 0; ii < num_dies; ii++) {
 830                 struct ip_die_entry *ip_die_entry;
 831
 832                 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
 833                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 834                 num_ips = le16_to_cpu(dhdr->num_ips);
 835                 ip_offset = die_offset + sizeof(*dhdr);
 836
 837                 /* Add the die to the kset.
 838                  *
 839                  * dhdr->die_id == ii, which was checked in
 840                  * amdgpu_discovery_reg_base_init().
 841                  */
 842
 843                 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
 844                 if (!ip_die_entry)
 845                         return -ENOMEM;
 846
 847                 ip_die_entry->num_ips = num_ips;
 848
 849                 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
 850                 ip_die_entry->ip_kset.kobj.kset = die_kset;
 851                 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
 852                 res = kset_register(&ip_die_entry->ip_kset);
 853                 if (res) {
 854                         DRM_ERROR("Couldn't register ip_die_entry kset");
 855                         kfree(ip_die_entry);
 856                         return res;
 857                 }
 858
 859                 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips);
 860         }
 861
 862         return 0;
 863 }
 864
 865 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
 866 {
 867         struct kset *die_kset;
 868         int res, ii;
 869
 870         adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
 871         if (!adev->ip_top)
 872                 return -ENOMEM;
 873
 874         adev->ip_top->adev = adev;
 875
 876         res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
 877                                    &adev->dev->kobj, "ip_discovery");
 878         if (res) {
 879                 DRM_ERROR("Couldn't init and add ip_discovery/");
 880                 goto Err;
 881         }
 882
 883         die_kset = &adev->ip_top->die_kset;
 884         kobject_set_name(&die_kset->kobj, "%s", "die");
 885         die_kset->kobj.parent = &adev->ip_top->kobj;
 886         die_kset->kobj.ktype = &die_kobj_ktype;
 887         res = kset_register(&adev->ip_top->die_kset);
 888         if (res) {
 889                 DRM_ERROR("Couldn't register die_kset");
 890                 goto Err;
 891         }
 892
 893         for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
 894                 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
 895         ip_hw_instance_attrs[ii] = NULL;
 896
 897         res = amdgpu_discovery_sysfs_recurse(adev);
 898
 899         return res;
 900 Err:
 901         kobject_put(&adev->ip_top->kobj);
 902         return res;
 903 }
 904
 905 /* -------------------------------------------------- */
 906
 907 #define list_to_kobj(el) container_of(el, struct kobject, entry)
 908
 909 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
 910 {
 911         struct list_head *el, *tmp;
 912         struct kset *hw_id_kset;
 913
 914         hw_id_kset = &ip_hw_id->hw_id_kset;
 915         spin_lock(&hw_id_kset->list_lock);
 916         list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
 917                 list_del_init(el);
 918                 spin_unlock(&hw_id_kset->list_lock);
 919                 /* kobject is embedded in ip_hw_instance */
 920                 kobject_put(list_to_kobj(el));
 921                 spin_lock(&hw_id_kset->list_lock);
 922         }
 923         spin_unlock(&hw_id_kset->list_lock);
 924         kobject_put(&ip_hw_id->hw_id_kset.kobj);
 925 }
 926
 927 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
 928 {
 929         struct list_head *el, *tmp;
 930         struct kset *ip_kset;
 931
 932         ip_kset = &ip_die_entry->ip_kset;
 933         spin_lock(&ip_kset->list_lock);
 934         list_for_each_prev_safe(el, tmp, &ip_kset->list) {
 935                 list_del_init(el);
 936                 spin_unlock(&ip_kset->list_lock);
 937                 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
 938                 spin_lock(&ip_kset->list_lock);
 939         }
 940         spin_unlock(&ip_kset->list_lock);
 941         kobject_put(&ip_die_entry->ip_kset.kobj);
 942 }
 943
 944 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
 945 {
 946         struct list_head *el, *tmp;
 947         struct kset *die_kset;
 948
 949         die_kset = &adev->ip_top->die_kset;
 950         spin_lock(&die_kset->list_lock);
 951         list_for_each_prev_safe(el, tmp, &die_kset->list) {
 952                 list_del_init(el);
 953                 spin_unlock(&die_kset->list_lock);
 954                 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
 955                 spin_lock(&die_kset->list_lock);
 956         }
 957         spin_unlock(&die_kset->list_lock);
 958         kobject_put(&adev->ip_top->die_kset.kobj);
 959         kobject_put(&adev->ip_top->kobj);
 960 }
 961
 962 /* ================================================== */
 963
 964 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 965 {
 966         struct binary_header *bhdr;
 967         struct ip_discovery_header *ihdr;
 968         struct die_header *dhdr;
 969         struct ip *ip;
 970         uint16_t die_offset;
 971         uint16_t ip_offset;
 972         uint16_t num_dies;
 973         uint16_t num_ips;
 974         uint8_t num_base_address;
 975         int hw_ip;
 976         int i, j, k;
 977         int r;
 978
 979         r = amdgpu_discovery_init(adev);
 980         if (r) {
 981                 DRM_ERROR("amdgpu_discovery_init failed\n");
 982                 return r;
 983         }
 984
 985         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 986         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 987                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 988         num_dies = le16_to_cpu(ihdr->num_dies);
 989
 990         DRM_DEBUG("number of dies: %d\n", num_dies);
 991
 992         for (i = 0; i < num_dies; i++) {
 993                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 994                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 995                 num_ips = le16_to_cpu(dhdr->num_ips);
 996                 ip_offset = die_offset + sizeof(*dhdr);
 997
 998                 if (le16_to_cpu(dhdr->die_id) != i) {
 999                         DRM_ERROR("invalid die id %d, expected %d\n",
1000                                         le16_to_cpu(dhdr->die_id), i);
1001                         return -EINVAL;
1002                 }
1003
1004                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1005                                 le16_to_cpu(dhdr->die_id), num_ips);
1006
1007                 for (j = 0; j < num_ips; j++) {
1008                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1009
1010                         if (amdgpu_discovery_validate_ip(ip))
1011                                 goto next_ip;
1012
1013                         num_base_address = ip->num_base_address;
1014
1015                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1016                                   hw_id_names[le16_to_cpu(ip->hw_id)],
1017                                   le16_to_cpu(ip->hw_id),
1018                                   ip->number_instance,
1019                                   ip->major, ip->minor,
1020                                   ip->revision);
1021
1022                         if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1023                                 /* Bit [5:0]: original revision value
1024                                  * Bit [7:6]: en/decode capability:
1025                                  *     0b00 : VCN function normally
1026                                  *     0b10 : encode is disabled
1027                                  *     0b01 : decode is disabled
1028                                  */
1029                                 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
1030                                         ip->revision & 0xc0;
1031                                 ip->revision &= ~0xc0;
1032                                 adev->vcn.num_vcn_inst++;
1033                         }
1034                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1035                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1036                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1037                             le16_to_cpu(ip->hw_id) == SDMA3_HWID)
1038                                 adev->sdma.num_instances++;
1039
1040                         if (le16_to_cpu(ip->hw_id) == UMC_HWID)
1041                                 adev->gmc.num_umc++;
1042
1043                         for (k = 0; k < num_base_address; k++) {
1044                                 /*
1045                                  * convert the endianness of base addresses in place,
1046                                  * so that we don't need to convert them when accessing adev->reg_offset.
1047                                  */
1048                                 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1049                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1050                         }
1051
1052                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1053                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
1054                                         DRM_DEBUG("set register base offset for %s\n",
1055                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
1056                                         adev->reg_offset[hw_ip][ip->number_instance] =
1057                                                 ip->base_address;
1058                                         /* Instance support is somewhat inconsistent.
1059                                          * SDMA is a good example.  Sienna cichlid has 4 total
1060                                          * SDMA instances, each enumerated separately (HWIDs
1061                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
1062                                          * but they are enumerated as multiple instances of the
1063                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
1064                                          * example.  On most chips there are multiple instances
1065                                          * with the same HWID.
1066                                          */
1067                                         adev->ip_versions[hw_ip][ip->number_instance] =
1068                                                 IP_VERSION(ip->major, ip->minor, ip->revision);
1069                                 }
1070                         }
1071
1072 next_ip:
1073                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
1074                 }
1075         }
1076
1077         amdgpu_discovery_sysfs_init(adev);
1078
1079         return 0;
1080 }
1081
1082 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
1083                                     int *major, int *minor, int *revision)
1084 {
1085         struct binary_header *bhdr;
1086         struct ip_discovery_header *ihdr;
1087         struct die_header *dhdr;
1088         struct ip *ip;
1089         uint16_t die_offset;
1090         uint16_t ip_offset;
1091         uint16_t num_dies;
1092         uint16_t num_ips;
1093         int i, j;
1094
1095         if (!adev->mman.discovery_bin) {
1096                 DRM_ERROR("ip discovery uninitialized\n");
1097                 return -EINVAL;
1098         }
1099
1100         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1101         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1102                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1103         num_dies = le16_to_cpu(ihdr->num_dies);
1104
1105         for (i = 0; i < num_dies; i++) {
1106                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1107                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1108                 num_ips = le16_to_cpu(dhdr->num_ips);
1109                 ip_offset = die_offset + sizeof(*dhdr);
1110
1111                 for (j = 0; j < num_ips; j++) {
1112                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1113
1114                         if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
1115                                 if (major)
1116                                         *major = ip->major;
1117                                 if (minor)
1118                                         *minor = ip->minor;
1119                                 if (revision)
1120                                         *revision = ip->revision;
1121                                 return 0;
1122                         }
1123                         ip_offset += struct_size(ip, base_address, ip->num_base_address);
1124                 }
1125         }
1126
1127         return -EINVAL;
1128 }
1129
1130 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1131 {
1132         int vcn_harvest_count = 0;
1133         int umc_harvest_count = 0;
1134
1135         /*
1136          * Harvest table does not fit Navi1x and legacy GPUs,
1137          * so read harvest bit per IP data structure to set
1138          * harvest configuration.
1139          */
1140         if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
1141                 if ((adev->pdev->device == 0x731E &&
1142                         (adev->pdev->revision == 0xC6 ||
1143                          adev->pdev->revision == 0xC7)) ||
1144                         (adev->pdev->device == 0x7340 &&
1145                          adev->pdev->revision == 0xC9) ||
1146                         (adev->pdev->device == 0x7360 &&
1147                          adev->pdev->revision == 0xC7))
1148                         amdgpu_discovery_read_harvest_bit_per_ip(adev,
1149                                 &vcn_harvest_count);
1150         } else {
1151                 amdgpu_discovery_read_from_harvest_table(adev,
1152                                                          &vcn_harvest_count,
1153                                                          &umc_harvest_count);
1154         }
1155
1156         amdgpu_discovery_harvest_config_quirk(adev);
1157
1158         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1159                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1160                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1161         }
1162
1163         if (umc_harvest_count < adev->gmc.num_umc) {
1164                 adev->gmc.num_umc -= umc_harvest_count;
1165         }
1166 }
1167
1168 union gc_info {
1169         struct gc_info_v1_0 v1;
1170         struct gc_info_v1_1 v1_1;
1171         struct gc_info_v1_2 v1_2;
1172         struct gc_info_v2_0 v2;
1173 };
1174
1175 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1176 {
1177         struct binary_header *bhdr;
1178         union gc_info *gc_info;
1179
1180         if (!adev->mman.discovery_bin) {
1181                 DRM_ERROR("ip discovery uninitialized\n");
1182                 return -EINVAL;
1183         }
1184
1185         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1186         gc_info = (union gc_info *)(adev->mman.discovery_bin +
1187                         le16_to_cpu(bhdr->table_list[GC].offset));
1188         switch (le16_to_cpu(gc_info->v1.header.version_major)) {
1189         case 1:
1190                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1191                 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1192                                                       le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1193                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1194                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1195                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1196                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1197                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1198                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1199                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1200                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1201                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1202                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1203                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1204                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1205                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1206                         le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1207                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1208                 if (gc_info->v1.header.version_minor >= 1) {
1209                         adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
1210                         adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
1211                         adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
1212                 }
1213                 if (gc_info->v1.header.version_minor >= 2) {
1214                         adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
1215                         adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
1216                         adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
1217                         adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
1218                         adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
1219                         adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1220                         adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1221                         adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1222                 }
1223                 break;
1224         case 2:
1225                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1226                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1227                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1228                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1229                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1230                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1231                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1232                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1233                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1234                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1235                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1236                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1237                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1238                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1239                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1240                         le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1241                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1242                 break;
1243         default:
1244                 dev_err(adev->dev,
1245                         "Unhandled GC info table %d.%d\n",
1246                         le16_to_cpu(gc_info->v1.header.version_major),
1247                         le16_to_cpu(gc_info->v1.header.version_minor));
1248                 return -EINVAL;
1249         }
1250         return 0;
1251 }
1252
1253 union mall_info {
1254         struct mall_info_v1_0 v1;
1255 };
1256
1257 int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
1258 {
1259         struct binary_header *bhdr;
1260         union mall_info *mall_info;
1261         u32 u, mall_size_per_umc, m_s_present, half_use;
1262         u64 mall_size;
1263
1264         if (!adev->mman.discovery_bin) {
1265                 DRM_ERROR("ip discovery uninitialized\n");
1266                 return -EINVAL;
1267         }
1268
1269         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1270         mall_info = (union mall_info *)(adev->mman.discovery_bin +
1271                         le16_to_cpu(bhdr->table_list[MALL_INFO].offset));
1272
1273         switch (le16_to_cpu(mall_info->v1.header.version_major)) {
1274         case 1:
1275                 mall_size = 0;
1276                 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
1277                 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
1278                 half_use = le32_to_cpu(mall_info->v1.m_half_use);
1279                 for (u = 0; u < adev->gmc.num_umc; u++) {
1280                         if (m_s_present & (1 << u))
1281                                 mall_size += mall_size_per_umc * 2;
1282                         else if (half_use & (1 << u))
1283                                 mall_size += mall_size_per_umc / 2;
1284                         else
1285                                 mall_size += mall_size_per_umc;
1286                 }
1287                 adev->gmc.mall_size = mall_size;
1288                 break;
1289         default:
1290                 dev_err(adev->dev,
1291                         "Unhandled MALL info table %d.%d\n",
1292                         le16_to_cpu(mall_info->v1.header.version_major),
1293                         le16_to_cpu(mall_info->v1.header.version_minor));
1294                 return -EINVAL;
1295         }
1296         return 0;
1297 }
1298
1299 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1300 {
1301         /* what IP to use for this? */
1302         switch (adev->ip_versions[GC_HWIP][0]) {
1303         case IP_VERSION(9, 0, 1):
1304         case IP_VERSION(9, 1, 0):
1305         case IP_VERSION(9, 2, 1):
1306         case IP_VERSION(9, 2, 2):
1307         case IP_VERSION(9, 3, 0):
1308         case IP_VERSION(9, 4, 0):
1309         case IP_VERSION(9, 4, 1):
1310         case IP_VERSION(9, 4, 2):
1311                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1312                 break;
1313         case IP_VERSION(10, 1, 10):
1314         case IP_VERSION(10, 1, 1):
1315         case IP_VERSION(10, 1, 2):
1316         case IP_VERSION(10, 1, 3):
1317         case IP_VERSION(10, 1, 4):
1318         case IP_VERSION(10, 3, 0):
1319         case IP_VERSION(10, 3, 1):
1320         case IP_VERSION(10, 3, 2):
1321         case IP_VERSION(10, 3, 3):
1322         case IP_VERSION(10, 3, 4):
1323         case IP_VERSION(10, 3, 5):
1324         case IP_VERSION(10, 3, 6):
1325         case IP_VERSION(10, 3, 7):
1326                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1327                 break;
1328         default:
1329                 dev_err(adev->dev,
1330                         "Failed to add common ip block(GC_HWIP:0x%x)\n",
1331                         adev->ip_versions[GC_HWIP][0]);
1332                 return -EINVAL;
1333         }
1334         return 0;
1335 }
1336
1337 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1338 {
1339         /* use GC or MMHUB IP version */
1340         switch (adev->ip_versions[GC_HWIP][0]) {
1341         case IP_VERSION(9, 0, 1):
1342         case IP_VERSION(9, 1, 0):
1343         case IP_VERSION(9, 2, 1):
1344         case IP_VERSION(9, 2, 2):
1345         case IP_VERSION(9, 3, 0):
1346         case IP_VERSION(9, 4, 0):
1347         case IP_VERSION(9, 4, 1):
1348         case IP_VERSION(9, 4, 2):
1349                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1350                 break;
1351         case IP_VERSION(10, 1, 10):
1352         case IP_VERSION(10, 1, 1):
1353         case IP_VERSION(10, 1, 2):
1354         case IP_VERSION(10, 1, 3):
1355         case IP_VERSION(10, 1, 4):
1356         case IP_VERSION(10, 3, 0):
1357         case IP_VERSION(10, 3, 1):
1358         case IP_VERSION(10, 3, 2):
1359         case IP_VERSION(10, 3, 3):
1360         case IP_VERSION(10, 3, 4):
1361         case IP_VERSION(10, 3, 5):
1362         case IP_VERSION(10, 3, 6):
1363         case IP_VERSION(10, 3, 7):
1364                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1365                 break;
1366         default:
1367                 dev_err(adev->dev,
1368                         "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1369                         adev->ip_versions[GC_HWIP][0]);
1370                 return -EINVAL;
1371         }
1372         return 0;
1373 }
1374
1375 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1376 {
1377         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
1378         case IP_VERSION(4, 0, 0):
1379         case IP_VERSION(4, 0, 1):
1380         case IP_VERSION(4, 1, 0):
1381         case IP_VERSION(4, 1, 1):
1382         case IP_VERSION(4, 3, 0):
1383                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1384                 break;
1385         case IP_VERSION(4, 2, 0):
1386         case IP_VERSION(4, 2, 1):
1387         case IP_VERSION(4, 4, 0):
1388                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1389                 break;
1390         case IP_VERSION(5, 0, 0):
1391         case IP_VERSION(5, 0, 1):
1392         case IP_VERSION(5, 0, 2):
1393         case IP_VERSION(5, 0, 3):
1394         case IP_VERSION(5, 2, 0):
1395         case IP_VERSION(5, 2, 1):
1396                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1397                 break;
1398         default:
1399                 dev_err(adev->dev,
1400                         "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1401                         adev->ip_versions[OSSSYS_HWIP][0]);
1402                 return -EINVAL;
1403         }
1404         return 0;
1405 }
1406
1407 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1408 {
1409         switch (adev->ip_versions[MP0_HWIP][0]) {
1410         case IP_VERSION(9, 0, 0):
1411                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1412                 break;
1413         case IP_VERSION(10, 0, 0):
1414         case IP_VERSION(10, 0, 1):
1415                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1416                 break;
1417         case IP_VERSION(11, 0, 0):
1418         case IP_VERSION(11, 0, 2):
1419         case IP_VERSION(11, 0, 4):
1420         case IP_VERSION(11, 0, 5):
1421         case IP_VERSION(11, 0, 9):
1422         case IP_VERSION(11, 0, 7):
1423         case IP_VERSION(11, 0, 11):
1424         case IP_VERSION(11, 0, 12):
1425         case IP_VERSION(11, 0, 13):
1426         case IP_VERSION(11, 5, 0):
1427                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1428                 break;
1429         case IP_VERSION(11, 0, 8):
1430                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1431                 break;
1432         case IP_VERSION(11, 0, 3):
1433         case IP_VERSION(12, 0, 1):
1434                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1435                 break;
1436         case IP_VERSION(13, 0, 1):
1437         case IP_VERSION(13, 0, 2):
1438         case IP_VERSION(13, 0, 3):
1439         case IP_VERSION(13, 0, 5):
1440         case IP_VERSION(13, 0, 8):
1441                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1442                 break;
1443         default:
1444                 dev_err(adev->dev,
1445                         "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1446                         adev->ip_versions[MP0_HWIP][0]);
1447                 return -EINVAL;
1448         }
1449         return 0;
1450 }
1451
1452 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1453 {
1454         switch (adev->ip_versions[MP1_HWIP][0]) {
1455         case IP_VERSION(9, 0, 0):
1456         case IP_VERSION(10, 0, 0):
1457         case IP_VERSION(10, 0, 1):
1458         case IP_VERSION(11, 0, 2):
1459                 if (adev->asic_type == CHIP_ARCTURUS)
1460                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1461                 else
1462                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1463                 break;
1464         case IP_VERSION(11, 0, 0):
1465         case IP_VERSION(11, 0, 5):
1466         case IP_VERSION(11, 0, 9):
1467         case IP_VERSION(11, 0, 7):
1468         case IP_VERSION(11, 0, 8):
1469         case IP_VERSION(11, 0, 11):
1470         case IP_VERSION(11, 0, 12):
1471         case IP_VERSION(11, 0, 13):
1472         case IP_VERSION(11, 5, 0):
1473                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1474                 break;
1475         case IP_VERSION(12, 0, 0):
1476         case IP_VERSION(12, 0, 1):
1477                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1478                 break;
1479         case IP_VERSION(13, 0, 1):
1480         case IP_VERSION(13, 0, 2):
1481         case IP_VERSION(13, 0, 3):
1482         case IP_VERSION(13, 0, 5):
1483         case IP_VERSION(13, 0, 8):
1484                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1485                 break;
1486         default:
1487                 dev_err(adev->dev,
1488                         "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
1489                         adev->ip_versions[MP1_HWIP][0]);
1490                 return -EINVAL;
1491         }
1492         return 0;
1493 }
1494
1495 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
1496 {
1497         if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
1498                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1499                 return 0;
1500         }
1501
1502         if (!amdgpu_device_has_dc_support(adev))
1503                 return 0;
1504
1505 #if defined(CONFIG_DRM_AMD_DC)
1506         if (adev->ip_versions[DCE_HWIP][0]) {
1507                 switch (adev->ip_versions[DCE_HWIP][0]) {
1508                 case IP_VERSION(1, 0, 0):
1509                 case IP_VERSION(1, 0, 1):
1510                 case IP_VERSION(2, 0, 2):
1511                 case IP_VERSION(2, 0, 0):
1512                 case IP_VERSION(2, 0, 3):
1513                 case IP_VERSION(2, 1, 0):
1514                 case IP_VERSION(3, 0, 0):
1515                 case IP_VERSION(3, 0, 2):
1516                 case IP_VERSION(3, 0, 3):
1517                 case IP_VERSION(3, 0, 1):
1518                 case IP_VERSION(3, 1, 2):
1519                 case IP_VERSION(3, 1, 3):
1520                 case IP_VERSION(3, 1, 5):
1521                 case IP_VERSION(3, 1, 6):
1522                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1523                         break;
1524                 default:
1525                         dev_err(adev->dev,
1526                                 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
1527                                 adev->ip_versions[DCE_HWIP][0]);
1528                         return -EINVAL;
1529                 }
1530         } else if (adev->ip_versions[DCI_HWIP][0]) {
1531                 switch (adev->ip_versions[DCI_HWIP][0]) {
1532                 case IP_VERSION(12, 0, 0):
1533                 case IP_VERSION(12, 0, 1):
1534                 case IP_VERSION(12, 1, 0):
1535                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
1536                         break;
1537                 default:
1538                         dev_err(adev->dev,
1539                                 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
1540                                 adev->ip_versions[DCI_HWIP][0]);
1541                         return -EINVAL;
1542                 }
1543         }
1544 #endif
1545         return 0;
1546 }
1547
1548 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
1549 {
1550         switch (adev->ip_versions[GC_HWIP][0]) {
1551         case IP_VERSION(9, 0, 1):
1552         case IP_VERSION(9, 1, 0):
1553         case IP_VERSION(9, 2, 1):
1554         case IP_VERSION(9, 2, 2):
1555         case IP_VERSION(9, 3, 0):
1556         case IP_VERSION(9, 4, 0):
1557         case IP_VERSION(9, 4, 1):
1558         case IP_VERSION(9, 4, 2):
1559                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1560                 break;
1561         case IP_VERSION(10, 1, 10):
1562         case IP_VERSION(10, 1, 2):
1563         case IP_VERSION(10, 1, 1):
1564         case IP_VERSION(10, 1, 3):
1565         case IP_VERSION(10, 1, 4):
1566         case IP_VERSION(10, 3, 0):
1567         case IP_VERSION(10, 3, 2):
1568         case IP_VERSION(10, 3, 1):
1569         case IP_VERSION(10, 3, 4):
1570         case IP_VERSION(10, 3, 5):
1571         case IP_VERSION(10, 3, 6):
1572         case IP_VERSION(10, 3, 3):
1573         case IP_VERSION(10, 3, 7):
1574                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1575                 break;
1576         default:
1577                 dev_err(adev->dev,
1578                         "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
1579                         adev->ip_versions[GC_HWIP][0]);
1580                 return -EINVAL;
1581         }
1582         return 0;
1583 }
1584
1585 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
1586 {
1587         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1588         case IP_VERSION(4, 0, 0):
1589         case IP_VERSION(4, 0, 1):
1590         case IP_VERSION(4, 1, 0):
1591         case IP_VERSION(4, 1, 1):
1592         case IP_VERSION(4, 1, 2):
1593         case IP_VERSION(4, 2, 0):
1594         case IP_VERSION(4, 2, 2):
1595         case IP_VERSION(4, 4, 0):
1596                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1597                 break;
1598         case IP_VERSION(5, 0, 0):
1599         case IP_VERSION(5, 0, 1):
1600         case IP_VERSION(5, 0, 2):
1601         case IP_VERSION(5, 0, 5):
1602                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
1603                 break;
1604         case IP_VERSION(5, 2, 0):
1605         case IP_VERSION(5, 2, 2):
1606         case IP_VERSION(5, 2, 4):
1607         case IP_VERSION(5, 2, 5):
1608         case IP_VERSION(5, 2, 6):
1609         case IP_VERSION(5, 2, 3):
1610         case IP_VERSION(5, 2, 1):
1611         case IP_VERSION(5, 2, 7):
1612                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1613                 break;
1614         default:
1615                 dev_err(adev->dev,
1616                         "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
1617                         adev->ip_versions[SDMA0_HWIP][0]);
1618                 return -EINVAL;
1619         }
1620         return 0;
1621 }
1622
1623 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
1624 {
1625         if (adev->ip_versions[VCE_HWIP][0]) {
1626                 switch (adev->ip_versions[UVD_HWIP][0]) {
1627                 case IP_VERSION(7, 0, 0):
1628                 case IP_VERSION(7, 2, 0):
1629                         /* UVD is not supported on vega20 SR-IOV */
1630                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1631                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
1632                         break;
1633                 default:
1634                         dev_err(adev->dev,
1635                                 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
1636                                 adev->ip_versions[UVD_HWIP][0]);
1637                         return -EINVAL;
1638                 }
1639                 switch (adev->ip_versions[VCE_HWIP][0]) {
1640                 case IP_VERSION(4, 0, 0):
1641                 case IP_VERSION(4, 1, 0):
1642                         /* VCE is not supported on vega20 SR-IOV */
1643                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1644                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
1645                         break;
1646                 default:
1647                         dev_err(adev->dev,
1648                                 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
1649                                 adev->ip_versions[VCE_HWIP][0]);
1650                         return -EINVAL;
1651                 }
1652         } else {
1653                 switch (adev->ip_versions[UVD_HWIP][0]) {
1654                 case IP_VERSION(1, 0, 0):
1655                 case IP_VERSION(1, 0, 1):
1656                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1657                         break;
1658                 case IP_VERSION(2, 0, 0):
1659                 case IP_VERSION(2, 0, 2):
1660                 case IP_VERSION(2, 2, 0):
1661                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
1662                         if (!amdgpu_sriov_vf(adev))
1663                                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1664                         break;
1665                 case IP_VERSION(2, 0, 3):
1666                         break;
1667                 case IP_VERSION(2, 5, 0):
1668                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1669                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1670                         break;
1671                 case IP_VERSION(2, 6, 0):
1672                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1673                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1674                         break;
1675                 case IP_VERSION(3, 0, 0):
1676                 case IP_VERSION(3, 0, 16):
1677                 case IP_VERSION(3, 1, 1):
1678                 case IP_VERSION(3, 1, 2):
1679                 case IP_VERSION(3, 0, 2):
1680                 case IP_VERSION(3, 0, 192):
1681                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1682                         if (!amdgpu_sriov_vf(adev))
1683                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
1684                         break;
1685                 case IP_VERSION(3, 0, 33):
1686                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1687                         break;
1688                 default:
1689                         dev_err(adev->dev,
1690                                 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
1691                                 adev->ip_versions[UVD_HWIP][0]);
1692                         return -EINVAL;
1693                 }
1694         }
1695         return 0;
1696 }
1697
1698 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
1699 {
1700         switch (adev->ip_versions[GC_HWIP][0]) {
1701         case IP_VERSION(10, 1, 10):
1702         case IP_VERSION(10, 1, 1):
1703         case IP_VERSION(10, 1, 2):
1704         case IP_VERSION(10, 1, 3):
1705         case IP_VERSION(10, 1, 4):
1706         case IP_VERSION(10, 3, 0):
1707         case IP_VERSION(10, 3, 1):
1708         case IP_VERSION(10, 3, 2):
1709         case IP_VERSION(10, 3, 3):
1710         case IP_VERSION(10, 3, 4):
1711         case IP_VERSION(10, 3, 5):
1712         case IP_VERSION(10, 3, 6):
1713                 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
1714                 break;
1715         default:
1716                 break;
1717         }
1718         return 0;
1719 }
1720
1721 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
1722 {
1723         int r;
1724
1725         switch (adev->asic_type) {
1726         case CHIP_VEGA10:
1727                 vega10_reg_base_init(adev);
1728                 adev->sdma.num_instances = 2;
1729                 adev->gmc.num_umc = 4;
1730                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1731                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1732                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
1733                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
1734                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
1735                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
1736                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1737                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
1738                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
1739                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1740                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1741                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1742                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
1743                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
1744                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1745                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1746                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
1747                 break;
1748         case CHIP_VEGA12:
1749                 vega10_reg_base_init(adev);
1750                 adev->sdma.num_instances = 2;
1751                 adev->gmc.num_umc = 4;
1752                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1753                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1754                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
1755                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
1756                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
1757                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
1758                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
1759                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
1760                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
1761                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1762                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1763                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1764                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
1765                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
1766                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1767                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1768                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
1769                 break;
1770         case CHIP_RAVEN:
1771                 vega10_reg_base_init(adev);
1772                 adev->sdma.num_instances = 1;
1773                 adev->vcn.num_vcn_inst = 1;
1774                 adev->gmc.num_umc = 2;
1775                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1776                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1777                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1778                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
1779                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
1780                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
1781                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
1782                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
1783                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
1784                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
1785                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
1786                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
1787                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
1788                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
1789                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
1790                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
1791                 } else {
1792                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1793                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1794                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
1795                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
1796                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
1797                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1798                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
1799                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
1800                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
1801                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
1802                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
1803                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
1804                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
1805                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
1806                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
1807                 }
1808                 break;
1809         case CHIP_VEGA20:
1810                 vega20_reg_base_init(adev);
1811                 adev->sdma.num_instances = 2;
1812                 adev->gmc.num_umc = 8;
1813                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1814                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1815                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
1816                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
1817                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
1818                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
1819                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
1820                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
1821                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
1822                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
1823                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1824                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
1825                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
1826                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
1827                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
1828                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
1829                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
1830                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
1831                 break;
1832         case CHIP_ARCTURUS:
1833                 arct_reg_base_init(adev);
1834                 adev->sdma.num_instances = 8;
1835                 adev->vcn.num_vcn_inst = 2;
1836                 adev->gmc.num_umc = 8;
1837                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1838                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1839                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
1840                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
1841                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
1842                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
1843                 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
1844                 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
1845                 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
1846                 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
1847                 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
1848                 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
1849                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
1850                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
1851                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
1852                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
1853                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1854                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
1855                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
1856                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
1857                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
1858                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
1859                 break;
1860         case CHIP_ALDEBARAN:
1861                 aldebaran_reg_base_init(adev);
1862                 adev->sdma.num_instances = 5;
1863                 adev->vcn.num_vcn_inst = 2;
1864                 adev->gmc.num_umc = 4;
1865                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1866                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1867                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
1868                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
1869                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
1870                 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
1871                 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
1872                 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
1873                 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
1874                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
1875                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
1876                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
1877                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
1878                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
1879                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
1880                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
1881                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
1882                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
1883                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
1884                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
1885                 break;
1886         default:
1887                 r = amdgpu_discovery_reg_base_init(adev);
1888                 if (r)
1889                         return -EINVAL;
1890
1891                 amdgpu_discovery_harvest_ip(adev);
1892                 break;
1893         }
1894
1895         switch (adev->ip_versions[GC_HWIP][0]) {
1896         case IP_VERSION(9, 0, 1):
1897         case IP_VERSION(9, 2, 1):
1898         case IP_VERSION(9, 4, 0):
1899         case IP_VERSION(9, 4, 1):
1900         case IP_VERSION(9, 4, 2):
1901                 adev->family = AMDGPU_FAMILY_AI;
1902                 break;
1903         case IP_VERSION(9, 1, 0):
1904         case IP_VERSION(9, 2, 2):
1905         case IP_VERSION(9, 3, 0):
1906                 adev->family = AMDGPU_FAMILY_RV;
1907                 break;
1908         case IP_VERSION(10, 1, 10):
1909         case IP_VERSION(10, 1, 1):
1910         case IP_VERSION(10, 1, 2):
1911         case IP_VERSION(10, 1, 3):
1912         case IP_VERSION(10, 1, 4):
1913         case IP_VERSION(10, 3, 0):
1914         case IP_VERSION(10, 3, 2):
1915         case IP_VERSION(10, 3, 4):
1916         case IP_VERSION(10, 3, 5):
1917                 adev->family = AMDGPU_FAMILY_NV;
1918                 break;
1919         case IP_VERSION(10, 3, 1):
1920                 adev->family = AMDGPU_FAMILY_VGH;
1921                 break;
1922         case IP_VERSION(10, 3, 3):
1923                 adev->family = AMDGPU_FAMILY_YC;
1924                 break;
1925         case IP_VERSION(10, 3, 6):
1926                 adev->family = AMDGPU_FAMILY_GC_10_3_6;
1927                 break;
1928         case IP_VERSION(10, 3, 7):
1929                 adev->family = AMDGPU_FAMILY_GC_10_3_7;
1930                 break;
1931         default:
1932                 return -EINVAL;
1933         }
1934
1935         switch (adev->ip_versions[GC_HWIP][0]) {
1936         case IP_VERSION(9, 1, 0):
1937         case IP_VERSION(9, 2, 2):
1938         case IP_VERSION(9, 3, 0):
1939         case IP_VERSION(10, 1, 3):
1940         case IP_VERSION(10, 1, 4):
1941         case IP_VERSION(10, 3, 1):
1942         case IP_VERSION(10, 3, 3):
1943         case IP_VERSION(10, 3, 6):
1944         case IP_VERSION(10, 3, 7):
1945                 adev->flags |= AMD_IS_APU;
1946                 break;
1947         default:
1948                 break;
1949         }
1950
1951         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
1952                 adev->gmc.xgmi.supported = true;
1953
1954         /* set NBIO version */
1955         switch (adev->ip_versions[NBIO_HWIP][0]) {
1956         case IP_VERSION(6, 1, 0):
1957         case IP_VERSION(6, 2, 0):
1958                 adev->nbio.funcs = &nbio_v6_1_funcs;
1959                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
1960                 break;
1961         case IP_VERSION(7, 0, 0):
1962         case IP_VERSION(7, 0, 1):
1963         case IP_VERSION(2, 5, 0):
1964                 adev->nbio.funcs = &nbio_v7_0_funcs;
1965                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
1966                 break;
1967         case IP_VERSION(7, 4, 0):
1968         case IP_VERSION(7, 4, 1):
1969                 adev->nbio.funcs = &nbio_v7_4_funcs;
1970                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
1971                 break;
1972         case IP_VERSION(7, 4, 4):
1973                 adev->nbio.funcs = &nbio_v7_4_funcs;
1974                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
1975                 break;
1976         case IP_VERSION(7, 2, 0):
1977         case IP_VERSION(7, 2, 1):
1978         case IP_VERSION(7, 3, 0):
1979         case IP_VERSION(7, 5, 0):
1980         case IP_VERSION(7, 5, 1):
1981                 adev->nbio.funcs = &nbio_v7_2_funcs;
1982                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
1983                 break;
1984         case IP_VERSION(2, 1, 1):
1985         case IP_VERSION(2, 3, 0):
1986         case IP_VERSION(2, 3, 1):
1987         case IP_VERSION(2, 3, 2):
1988                 adev->nbio.funcs = &nbio_v2_3_funcs;
1989                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
1990                 break;
1991         case IP_VERSION(3, 3, 0):
1992         case IP_VERSION(3, 3, 1):
1993         case IP_VERSION(3, 3, 2):
1994         case IP_VERSION(3, 3, 3):
1995                 adev->nbio.funcs = &nbio_v2_3_funcs;
1996                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
1997                 break;
1998         default:
1999                 break;
2000         }
2001
2002         switch (adev->ip_versions[HDP_HWIP][0]) {
2003         case IP_VERSION(4, 0, 0):
2004         case IP_VERSION(4, 0, 1):
2005         case IP_VERSION(4, 1, 0):
2006         case IP_VERSION(4, 1, 1):
2007         case IP_VERSION(4, 1, 2):
2008         case IP_VERSION(4, 2, 0):
2009         case IP_VERSION(4, 2, 1):
2010         case IP_VERSION(4, 4, 0):
2011                 adev->hdp.funcs = &hdp_v4_0_funcs;
2012                 break;
2013         case IP_VERSION(5, 0, 0):
2014         case IP_VERSION(5, 0, 1):
2015         case IP_VERSION(5, 0, 2):
2016         case IP_VERSION(5, 0, 3):
2017         case IP_VERSION(5, 0, 4):
2018         case IP_VERSION(5, 2, 0):
2019                 adev->hdp.funcs = &hdp_v5_0_funcs;
2020                 break;
2021         default:
2022                 break;
2023         }
2024
2025         switch (adev->ip_versions[DF_HWIP][0]) {
2026         case IP_VERSION(3, 6, 0):
2027         case IP_VERSION(3, 6, 1):
2028         case IP_VERSION(3, 6, 2):
2029                 adev->df.funcs = &df_v3_6_funcs;
2030                 break;
2031         case IP_VERSION(2, 1, 0):
2032         case IP_VERSION(2, 1, 1):
2033         case IP_VERSION(2, 5, 0):
2034         case IP_VERSION(3, 5, 1):
2035         case IP_VERSION(3, 5, 2):
2036                 adev->df.funcs = &df_v1_7_funcs;
2037                 break;
2038         default:
2039                 break;
2040         }
2041
2042         switch (adev->ip_versions[SMUIO_HWIP][0]) {
2043         case IP_VERSION(9, 0, 0):
2044         case IP_VERSION(9, 0, 1):
2045         case IP_VERSION(10, 0, 0):
2046         case IP_VERSION(10, 0, 1):
2047         case IP_VERSION(10, 0, 2):
2048                 adev->smuio.funcs = &smuio_v9_0_funcs;
2049                 break;
2050         case IP_VERSION(11, 0, 0):
2051         case IP_VERSION(11, 0, 2):
2052         case IP_VERSION(11, 0, 3):
2053         case IP_VERSION(11, 0, 4):
2054         case IP_VERSION(11, 0, 7):
2055         case IP_VERSION(11, 0, 8):
2056                 adev->smuio.funcs = &smuio_v11_0_funcs;
2057                 break;
2058         case IP_VERSION(11, 0, 6):
2059         case IP_VERSION(11, 0, 10):
2060         case IP_VERSION(11, 0, 11):
2061         case IP_VERSION(11, 5, 0):
2062         case IP_VERSION(13, 0, 1):
2063         case IP_VERSION(13, 0, 9):
2064         case IP_VERSION(13, 0, 10):
2065                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
2066                 break;
2067         case IP_VERSION(13, 0, 2):
2068                 adev->smuio.funcs = &smuio_v13_0_funcs;
2069                 break;
2070         default:
2071                 break;
2072         }
2073
2074         r = amdgpu_discovery_set_common_ip_blocks(adev);
2075         if (r)
2076                 return r;
2077
2078         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
2079         if (r)
2080                 return r;
2081
2082         /* For SR-IOV, PSP needs to be initialized before IH */
2083         if (amdgpu_sriov_vf(adev)) {
2084                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2085                 if (r)
2086                         return r;
2087                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2088                 if (r)
2089                         return r;
2090         } else {
2091                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2092                 if (r)
2093                         return r;
2094
2095                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2096                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
2097                         if (r)
2098                                 return r;
2099                 }
2100         }
2101
2102         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2103                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2104                 if (r)
2105                         return r;
2106         }
2107
2108         r = amdgpu_discovery_set_display_ip_blocks(adev);
2109         if (r)
2110                 return r;
2111
2112         r = amdgpu_discovery_set_gc_ip_blocks(adev);
2113         if (r)
2114                 return r;
2115
2116         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
2117         if (r)
2118                 return r;
2119
2120         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
2121             !amdgpu_sriov_vf(adev)) {
2122                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2123                 if (r)
2124                         return r;
2125         }
2126
2127         r = amdgpu_discovery_set_mm_ip_blocks(adev);
2128         if (r)
2129                 return r;
2130
2131         if (adev->enable_mes) {
2132                 r = amdgpu_discovery_set_mes_ip_blocks(adev);
2133                 if (r)
2134                         return r;
2135         }
2136
2137         return 0;
2138 }
2139