2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_discovery.h"
28 #include "soc15_hw_ip.h"
29 #include "discovery.h"
36 #include "nbio_v6_1.h"
37 #include "nbio_v7_0.h"
38 #include "nbio_v7_4.h"
40 #include "vega10_ih.h"
41 #include "vega20_ih.h"
42 #include "sdma_v4_0.h"
47 #include "jpeg_v2_5.h"
48 #include "smuio_v9_0.h"
49 #include "gmc_v10_0.h"
50 #include "gfxhub_v2_0.h"
51 #include "mmhub_v2_0.h"
52 #include "nbio_v2_3.h"
53 #include "nbio_v7_2.h"
56 #include "navi10_ih.h"
57 #include "gfx_v10_0.h"
58 #include "sdma_v5_0.h"
59 #include "sdma_v5_2.h"
61 #include "jpeg_v2_0.h"
63 #include "jpeg_v3_0.h"
64 #include "amdgpu_vkms.h"
65 #include "mes_v10_1.h"
66 #include "smuio_v11_0.h"
67 #include "smuio_v11_0_6.h"
68 #include "smuio_v13_0.h"
70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
73 #define mmRCC_CONFIG_MEMSIZE 0xde3
74 #define mmMM_INDEX 0x0
75 #define mmMM_INDEX_HI 0x6
78 static const char *hw_id_names[HW_ID_MAX] = {
82 [SMUIO_HWID] = "SMUIO",
88 [AUDIO_AZ_HWID] = "AUDIO_AZ",
95 [DCEAZ_HWID] = "DCEAZ",
97 [SDPMUX_HWID] = "SDPMUX",
100 [L2IMU_HWID] = "L2IMU",
102 [MMHUB_HWID] = "MMHUB",
103 [ATHUB_HWID] = "ATHUB",
104 [DBGU_NBIO_HWID] = "DBGU_NBIO",
106 [DBGU0_HWID] = "DBGU0",
107 [DBGU1_HWID] = "DBGU1",
108 [OSSSYS_HWID] = "OSSSYS",
110 [SDMA0_HWID] = "SDMA0",
111 [SDMA1_HWID] = "SDMA1",
112 [SDMA2_HWID] = "SDMA2",
113 [SDMA3_HWID] = "SDMA3",
115 [DBGU_IO_HWID] = "DBGU_IO",
117 [CLKB_HWID] = "CLKB",
119 [DFX_DAP_HWID] = "DFX_DAP",
120 [L1IMU_PCIE_HWID] = "L1IMU_PCIE",
121 [L1IMU_NBIF_HWID] = "L1IMU_NBIF",
122 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
123 [L1IMU3_HWID] = "L1IMU3",
124 [L1IMU4_HWID] = "L1IMU4",
125 [L1IMU5_HWID] = "L1IMU5",
126 [L1IMU6_HWID] = "L1IMU6",
127 [L1IMU7_HWID] = "L1IMU7",
128 [L1IMU8_HWID] = "L1IMU8",
129 [L1IMU9_HWID] = "L1IMU9",
130 [L1IMU10_HWID] = "L1IMU10",
131 [L1IMU11_HWID] = "L1IMU11",
132 [L1IMU12_HWID] = "L1IMU12",
133 [L1IMU13_HWID] = "L1IMU13",
134 [L1IMU14_HWID] = "L1IMU14",
135 [L1IMU15_HWID] = "L1IMU15",
136 [WAFLC_HWID] = "WAFLC",
137 [FCH_USB_PD_HWID] = "FCH_USB_PD",
138 [PCIE_HWID] = "PCIE",
140 [DDCL_HWID] = "DDCL",
142 [IOAGR_HWID] = "IOAGR",
143 [NBIF_HWID] = "NBIF",
144 [IOAPIC_HWID] = "IOAPIC",
145 [SYSTEMHUB_HWID] = "SYSTEMHUB",
146 [NTBCCP_HWID] = "NTBCCP",
148 [SATA_HWID] = "SATA",
150 [CCXSEC_HWID] = "CCXSEC",
151 [XGMI_HWID] = "XGMI",
152 [XGBE_HWID] = "XGBE",
156 static int hw_id_map[MAX_HWIP] = {
158 [HDP_HWIP] = HDP_HWID,
159 [SDMA0_HWIP] = SDMA0_HWID,
160 [SDMA1_HWIP] = SDMA1_HWID,
161 [SDMA2_HWIP] = SDMA2_HWID,
162 [SDMA3_HWIP] = SDMA3_HWID,
163 [MMHUB_HWIP] = MMHUB_HWID,
164 [ATHUB_HWIP] = ATHUB_HWID,
165 [NBIO_HWIP] = NBIF_HWID,
166 [MP0_HWIP] = MP0_HWID,
167 [MP1_HWIP] = MP1_HWID,
168 [UVD_HWIP] = UVD_HWID,
169 [VCE_HWIP] = VCE_HWID,
171 [DCE_HWIP] = DMU_HWID,
172 [OSSSYS_HWIP] = OSSSYS_HWID,
173 [SMUIO_HWIP] = SMUIO_HWID,
174 [PWR_HWIP] = PWR_HWID,
175 [NBIF_HWIP] = NBIF_HWID,
176 [THM_HWIP] = THM_HWID,
177 [CLK_HWIP] = CLKA_HWID,
178 [UMC_HWIP] = UMC_HWID,
179 [XGMI_HWIP] = XGMI_HWID,
180 [DCI_HWIP] = DCI_HWID,
183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
185 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
186 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
188 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
189 adev->mman.discovery_tmr_size, false);
193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
195 const struct firmware *fw;
199 switch (amdgpu_discovery) {
201 fw_name = FIRMWARE_IP_DISCOVERY;
204 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
208 r = request_firmware(&fw, fw_name, adev->dev);
210 dev_err(adev->dev, "can't load firmware \"%s\"\n",
215 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
216 release_firmware(fw);
221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
223 uint16_t checksum = 0;
226 for (i = 0; i < size; i++)
232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
235 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
240 struct binary_header *bhdr;
241 bhdr = (struct binary_header *)binary;
243 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
246 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
249 * So far, apply this quirk only on those Navy Flounder boards which
250 * have a bad harvest table of VCN config.
252 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
253 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
254 switch (adev->pdev->revision) {
262 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
270 static int amdgpu_discovery_init(struct amdgpu_device *adev)
272 struct table_info *info;
273 struct binary_header *bhdr;
274 struct ip_discovery_header *ihdr;
275 struct gpu_info_header *ghdr;
281 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
282 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
283 if (!adev->mman.discovery_bin)
286 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin);
288 dev_err(adev->dev, "failed to read ip discovery binary from vram\n");
293 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
294 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n");
295 /* retry read ip discovery binary from file */
296 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
298 dev_err(adev->dev, "failed to read ip discovery binary from file\n");
302 /* check the ip discovery binary signature */
303 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
304 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n");
310 bhdr = (struct binary_header *)adev->mman.discovery_bin;
312 offset = offsetof(struct binary_header, binary_checksum) +
313 sizeof(bhdr->binary_checksum);
314 size = le16_to_cpu(bhdr->binary_size) - offset;
315 checksum = le16_to_cpu(bhdr->binary_checksum);
317 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
319 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
324 info = &bhdr->table_list[IP_DISCOVERY];
325 offset = le16_to_cpu(info->offset);
326 checksum = le16_to_cpu(info->checksum);
327 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
329 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
330 dev_err(adev->dev, "invalid ip discovery data table signature\n");
335 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
336 le16_to_cpu(ihdr->size), checksum)) {
337 dev_err(adev->dev, "invalid ip discovery data table checksum\n");
342 info = &bhdr->table_list[GC];
343 offset = le16_to_cpu(info->offset);
344 checksum = le16_to_cpu(info->checksum);
345 ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
347 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
348 le32_to_cpu(ghdr->size), checksum)) {
349 dev_err(adev->dev, "invalid gc data table checksum\n");
357 kfree(adev->mman.discovery_bin);
358 adev->mman.discovery_bin = NULL;
363 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
365 void amdgpu_discovery_fini(struct amdgpu_device *adev)
367 amdgpu_discovery_sysfs_fini(adev);
368 kfree(adev->mman.discovery_bin);
369 adev->mman.discovery_bin = NULL;
372 static int amdgpu_discovery_validate_ip(const struct ip *ip)
374 if (ip->number_instance >= HWIP_MAX_INSTANCE) {
375 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
376 ip->number_instance);
379 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
380 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
381 le16_to_cpu(ip->hw_id));
388 /* ================================================== */
390 struct ip_hw_instance {
391 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
395 u8 major, minor, revision;
398 int num_base_addresses;
403 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
407 struct ip_die_entry {
408 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */
412 /* -------------------------------------------------- */
414 struct ip_hw_instance_attr {
415 struct attribute attr;
416 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
419 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
421 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
424 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
426 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
429 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
431 return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
434 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
436 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
439 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
441 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
444 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
446 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
449 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
451 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
454 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
459 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
460 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
462 if (at + 12 > PAGE_SIZE)
464 res = sysfs_emit_at(buf, at, "0x%08X\n",
465 ip_hw_instance->base_addr[ii]);
471 return res < 0 ? res : at;
474 static struct ip_hw_instance_attr ip_hw_attr[] = {
476 __ATTR_RO(num_instance),
481 __ATTR_RO(num_base_addresses),
482 __ATTR_RO(base_addr),
485 static struct attribute *ip_hw_instance_attrs[] = {
495 ATTRIBUTE_GROUPS(ip_hw_instance);
497 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
498 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
500 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
501 struct attribute *attr,
504 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
505 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
507 if (!ip_hw_attr->show)
510 return ip_hw_attr->show(ip_hw_instance, buf);
513 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
514 .show = ip_hw_instance_attr_show,
517 static void ip_hw_instance_release(struct kobject *kobj)
519 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
521 kfree(ip_hw_instance);
524 static struct kobj_type ip_hw_instance_ktype = {
525 .release = ip_hw_instance_release,
526 .sysfs_ops = &ip_hw_instance_sysfs_ops,
527 .default_groups = ip_hw_instance_groups,
530 /* -------------------------------------------------- */
532 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
534 static void ip_hw_id_release(struct kobject *kobj)
536 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
538 if (!list_empty(&ip_hw_id->hw_id_kset.list))
539 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
543 static struct kobj_type ip_hw_id_ktype = {
544 .release = ip_hw_id_release,
545 .sysfs_ops = &kobj_sysfs_ops,
548 /* -------------------------------------------------- */
550 static void die_kobj_release(struct kobject *kobj);
551 static void ip_disc_release(struct kobject *kobj);
553 struct ip_die_entry_attribute {
554 struct attribute attr;
555 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
558 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr)
560 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
562 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
565 /* If there are more ip_die_entry attrs, other than the number of IPs,
566 * we can make this intro an array of attrs, and then initialize
567 * ip_die_entry_attrs in a loop.
569 static struct ip_die_entry_attribute num_ips_attr =
572 static struct attribute *ip_die_entry_attrs[] = {
576 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
578 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
580 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
581 struct attribute *attr,
584 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
585 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
587 if (!ip_die_entry_attr->show)
590 return ip_die_entry_attr->show(ip_die_entry, buf);
593 static void ip_die_entry_release(struct kobject *kobj)
595 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
597 if (!list_empty(&ip_die_entry->ip_kset.list))
598 DRM_ERROR("ip_die_entry->ip_kset is not empty");
602 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
603 .show = ip_die_entry_attr_show,
606 static struct kobj_type ip_die_entry_ktype = {
607 .release = ip_die_entry_release,
608 .sysfs_ops = &ip_die_entry_sysfs_ops,
609 .default_groups = ip_die_entry_groups,
612 static struct kobj_type die_kobj_ktype = {
613 .release = die_kobj_release,
614 .sysfs_ops = &kobj_sysfs_ops,
617 static struct kobj_type ip_discovery_ktype = {
618 .release = ip_disc_release,
619 .sysfs_ops = &kobj_sysfs_ops,
622 struct ip_discovery_top {
623 struct kobject kobj; /* ip_discovery/ */
624 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */
625 struct amdgpu_device *adev;
628 static void die_kobj_release(struct kobject *kobj)
630 struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
631 struct ip_discovery_top,
633 if (!list_empty(&ip_top->die_kset.list))
634 DRM_ERROR("ip_top->die_kset is not empty");
637 static void ip_disc_release(struct kobject *kobj)
639 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
641 struct amdgpu_device *adev = ip_top->adev;
647 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
648 struct ip_die_entry *ip_die_entry,
649 const size_t _ip_offset, const int num_ips)
653 DRM_DEBUG("num_ips:%d", num_ips);
655 /* Find all IPs of a given HW ID, and add their instance to
656 * #die/#hw_id/#instance/<attributes>
658 for (ii = 0; ii < HW_ID_MAX; ii++) {
659 struct ip_hw_id *ip_hw_id = NULL;
660 size_t ip_offset = _ip_offset;
662 for (jj = 0; jj < num_ips; jj++) {
664 struct ip_hw_instance *ip_hw_instance;
666 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
667 if (amdgpu_discovery_validate_ip(ip) ||
668 le16_to_cpu(ip->hw_id) != ii)
671 DRM_DEBUG("match:%d @ ip_offset:%ld", ii, ip_offset);
673 /* We have a hw_id match; register the hw
674 * block if not yet registered.
677 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
680 ip_hw_id->hw_id = ii;
682 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
683 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
684 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
685 res = kset_register(&ip_hw_id->hw_id_kset);
687 DRM_ERROR("Couldn't register ip_hw_id kset");
691 if (hw_id_names[ii]) {
692 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
693 &ip_hw_id->hw_id_kset.kobj,
696 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
698 kobject_name(&ip_die_entry->ip_kset.kobj));
703 /* Now register its instance.
705 ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
707 ip->num_base_address),
709 if (!ip_hw_instance) {
710 DRM_ERROR("no memory for ip_hw_instance");
713 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
714 ip_hw_instance->num_instance = ip->number_instance;
715 ip_hw_instance->major = ip->major;
716 ip_hw_instance->minor = ip->minor;
717 ip_hw_instance->revision = ip->revision;
718 ip_hw_instance->harvest = ip->harvest;
719 ip_hw_instance->num_base_addresses = ip->num_base_address;
721 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++)
722 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
724 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
725 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
726 res = kobject_add(&ip_hw_instance->kobj, NULL,
727 "%d", ip_hw_instance->num_instance);
729 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
736 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
738 struct binary_header *bhdr;
739 struct ip_discovery_header *ihdr;
740 struct die_header *dhdr;
741 struct kset *die_kset = &adev->ip_top->die_kset;
742 u16 num_dies, die_offset, num_ips;
746 bhdr = (struct binary_header *)adev->mman.discovery_bin;
747 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
748 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
749 num_dies = le16_to_cpu(ihdr->num_dies);
751 DRM_DEBUG("number of dies: %d\n", num_dies);
753 for (ii = 0; ii < num_dies; ii++) {
754 struct ip_die_entry *ip_die_entry;
756 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
757 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
758 num_ips = le16_to_cpu(dhdr->num_ips);
759 ip_offset = die_offset + sizeof(*dhdr);
761 /* Add the die to the kset.
763 * dhdr->die_id == ii, which was checked in
764 * amdgpu_discovery_reg_base_init().
767 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
771 ip_die_entry->num_ips = num_ips;
773 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
774 ip_die_entry->ip_kset.kobj.kset = die_kset;
775 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
776 res = kset_register(&ip_die_entry->ip_kset);
778 DRM_ERROR("Couldn't register ip_die_entry kset");
783 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips);
789 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
791 struct kset *die_kset;
794 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
798 adev->ip_top->adev = adev;
800 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
801 &adev->dev->kobj, "ip_discovery");
803 DRM_ERROR("Couldn't init and add ip_discovery/");
807 die_kset = &adev->ip_top->die_kset;
808 kobject_set_name(&die_kset->kobj, "%s", "die");
809 die_kset->kobj.parent = &adev->ip_top->kobj;
810 die_kset->kobj.ktype = &die_kobj_ktype;
811 res = kset_register(&adev->ip_top->die_kset);
813 DRM_ERROR("Couldn't register die_kset");
817 res = amdgpu_discovery_sysfs_recurse(adev);
821 kobject_put(&adev->ip_top->kobj);
825 /* -------------------------------------------------- */
827 #define list_to_kobj(el) container_of(el, struct kobject, entry)
829 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
831 struct list_head *el, *tmp;
832 struct kset *hw_id_kset;
834 hw_id_kset = &ip_hw_id->hw_id_kset;
835 spin_lock(&hw_id_kset->list_lock);
836 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
838 spin_unlock(&hw_id_kset->list_lock);
839 /* kobject is embedded in ip_hw_instance */
840 kobject_put(list_to_kobj(el));
841 spin_lock(&hw_id_kset->list_lock);
843 spin_unlock(&hw_id_kset->list_lock);
844 kobject_put(&ip_hw_id->hw_id_kset.kobj);
847 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
849 struct list_head *el, *tmp;
850 struct kset *ip_kset;
852 ip_kset = &ip_die_entry->ip_kset;
853 spin_lock(&ip_kset->list_lock);
854 list_for_each_prev_safe(el, tmp, &ip_kset->list) {
856 spin_unlock(&ip_kset->list_lock);
857 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
858 spin_lock(&ip_kset->list_lock);
860 spin_unlock(&ip_kset->list_lock);
861 kobject_put(&ip_die_entry->ip_kset.kobj);
864 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
866 struct list_head *el, *tmp;
867 struct kset *die_kset;
869 die_kset = &adev->ip_top->die_kset;
870 spin_lock(&die_kset->list_lock);
871 list_for_each_prev_safe(el, tmp, &die_kset->list) {
873 spin_unlock(&die_kset->list_lock);
874 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
875 spin_lock(&die_kset->list_lock);
877 spin_unlock(&die_kset->list_lock);
878 kobject_put(&adev->ip_top->die_kset.kobj);
879 kobject_put(&adev->ip_top->kobj);
882 /* ================================================== */
884 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
886 struct binary_header *bhdr;
887 struct ip_discovery_header *ihdr;
888 struct die_header *dhdr;
894 uint8_t num_base_address;
899 r = amdgpu_discovery_init(adev);
901 DRM_ERROR("amdgpu_discovery_init failed\n");
905 bhdr = (struct binary_header *)adev->mman.discovery_bin;
906 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
907 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
908 num_dies = le16_to_cpu(ihdr->num_dies);
910 DRM_DEBUG("number of dies: %d\n", num_dies);
912 for (i = 0; i < num_dies; i++) {
913 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
914 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
915 num_ips = le16_to_cpu(dhdr->num_ips);
916 ip_offset = die_offset + sizeof(*dhdr);
918 if (le16_to_cpu(dhdr->die_id) != i) {
919 DRM_ERROR("invalid die id %d, expected %d\n",
920 le16_to_cpu(dhdr->die_id), i);
924 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
925 le16_to_cpu(dhdr->die_id), num_ips);
927 for (j = 0; j < num_ips; j++) {
928 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
930 if (amdgpu_discovery_validate_ip(ip))
933 num_base_address = ip->num_base_address;
935 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
936 hw_id_names[le16_to_cpu(ip->hw_id)],
937 le16_to_cpu(ip->hw_id),
939 ip->major, ip->minor,
942 if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
943 /* Bit [5:0]: original revision value
944 * Bit [7:6]: en/decode capability:
945 * 0b00 : VCN function normally
946 * 0b10 : encode is disabled
947 * 0b01 : decode is disabled
949 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
951 ip->revision &= ~0xc0;
952 adev->vcn.num_vcn_inst++;
954 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
955 le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
956 le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
957 le16_to_cpu(ip->hw_id) == SDMA3_HWID)
958 adev->sdma.num_instances++;
960 for (k = 0; k < num_base_address; k++) {
962 * convert the endianness of base addresses in place,
963 * so that we don't need to convert them when accessing adev->reg_offset.
965 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
966 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
969 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
970 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
971 DRM_DEBUG("set register base offset for %s\n",
972 hw_id_names[le16_to_cpu(ip->hw_id)]);
973 adev->reg_offset[hw_ip][ip->number_instance] =
975 /* Instance support is somewhat inconsistent.
976 * SDMA is a good example. Sienna cichlid has 4 total
977 * SDMA instances, each enumerated separately (HWIDs
978 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances,
979 * but they are enumerated as multiple instances of the
980 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another
981 * example. On most chips there are multiple instances
982 * with the same HWID.
984 adev->ip_versions[hw_ip][ip->number_instance] =
985 IP_VERSION(ip->major, ip->minor, ip->revision);
990 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
994 amdgpu_discovery_sysfs_init(adev);
999 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
1000 int *major, int *minor, int *revision)
1002 struct binary_header *bhdr;
1003 struct ip_discovery_header *ihdr;
1004 struct die_header *dhdr;
1006 uint16_t die_offset;
1012 if (!adev->mman.discovery_bin) {
1013 DRM_ERROR("ip discovery uninitialized\n");
1017 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1018 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1019 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1020 num_dies = le16_to_cpu(ihdr->num_dies);
1022 for (i = 0; i < num_dies; i++) {
1023 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1024 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1025 num_ips = le16_to_cpu(dhdr->num_ips);
1026 ip_offset = die_offset + sizeof(*dhdr);
1028 for (j = 0; j < num_ips; j++) {
1029 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
1031 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
1037 *revision = ip->revision;
1040 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
1047 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1049 struct binary_header *bhdr;
1050 struct harvest_table *harvest_info;
1051 int i, vcn_harvest_count = 0;
1053 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1054 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
1055 le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
1057 for (i = 0; i < 32; i++) {
1058 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
1061 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
1063 vcn_harvest_count++;
1064 if (harvest_info->list[i].number_instance == 0)
1065 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
1067 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
1070 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
1077 amdgpu_discovery_harvest_config_quirk(adev);
1079 if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1080 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1081 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1083 if ((adev->pdev->device == 0x731E &&
1084 (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) ||
1085 (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9) ||
1086 (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) {
1087 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1088 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1093 struct gc_info_v1_0 v1;
1094 struct gc_info_v2_0 v2;
1097 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1099 struct binary_header *bhdr;
1100 union gc_info *gc_info;
1102 if (!adev->mman.discovery_bin) {
1103 DRM_ERROR("ip discovery uninitialized\n");
1107 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1108 gc_info = (union gc_info *)(adev->mman.discovery_bin +
1109 le16_to_cpu(bhdr->table_list[GC].offset));
1110 switch (gc_info->v1.header.version_major) {
1112 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1113 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1114 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1115 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1116 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1117 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1118 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1119 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1120 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1121 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1122 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1123 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1124 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1125 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1126 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1127 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1128 le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1129 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1132 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1133 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1134 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1135 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1136 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1137 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1138 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1139 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1140 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1141 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1142 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1143 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1144 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1145 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1146 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1147 le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1148 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1152 "Unhandled GC info table %d.%d\n",
1153 gc_info->v1.header.version_major,
1154 gc_info->v1.header.version_minor);
1160 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1162 /* what IP to use for this? */
1163 switch (adev->ip_versions[GC_HWIP][0]) {
1164 case IP_VERSION(9, 0, 1):
1165 case IP_VERSION(9, 1, 0):
1166 case IP_VERSION(9, 2, 1):
1167 case IP_VERSION(9, 2, 2):
1168 case IP_VERSION(9, 3, 0):
1169 case IP_VERSION(9, 4, 0):
1170 case IP_VERSION(9, 4, 1):
1171 case IP_VERSION(9, 4, 2):
1172 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1174 case IP_VERSION(10, 1, 10):
1175 case IP_VERSION(10, 1, 1):
1176 case IP_VERSION(10, 1, 2):
1177 case IP_VERSION(10, 1, 3):
1178 case IP_VERSION(10, 1, 4):
1179 case IP_VERSION(10, 3, 0):
1180 case IP_VERSION(10, 3, 1):
1181 case IP_VERSION(10, 3, 2):
1182 case IP_VERSION(10, 3, 3):
1183 case IP_VERSION(10, 3, 4):
1184 case IP_VERSION(10, 3, 5):
1185 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1189 "Failed to add common ip block(GC_HWIP:0x%x)\n",
1190 adev->ip_versions[GC_HWIP][0]);
1196 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1198 /* use GC or MMHUB IP version */
1199 switch (adev->ip_versions[GC_HWIP][0]) {
1200 case IP_VERSION(9, 0, 1):
1201 case IP_VERSION(9, 1, 0):
1202 case IP_VERSION(9, 2, 1):
1203 case IP_VERSION(9, 2, 2):
1204 case IP_VERSION(9, 3, 0):
1205 case IP_VERSION(9, 4, 0):
1206 case IP_VERSION(9, 4, 1):
1207 case IP_VERSION(9, 4, 2):
1208 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1210 case IP_VERSION(10, 1, 10):
1211 case IP_VERSION(10, 1, 1):
1212 case IP_VERSION(10, 1, 2):
1213 case IP_VERSION(10, 1, 3):
1214 case IP_VERSION(10, 1, 4):
1215 case IP_VERSION(10, 3, 0):
1216 case IP_VERSION(10, 3, 1):
1217 case IP_VERSION(10, 3, 2):
1218 case IP_VERSION(10, 3, 3):
1219 case IP_VERSION(10, 3, 4):
1220 case IP_VERSION(10, 3, 5):
1221 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1225 "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1226 adev->ip_versions[GC_HWIP][0]);
1232 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1234 switch (adev->ip_versions[OSSSYS_HWIP][0]) {
1235 case IP_VERSION(4, 0, 0):
1236 case IP_VERSION(4, 0, 1):
1237 case IP_VERSION(4, 1, 0):
1238 case IP_VERSION(4, 1, 1):
1239 case IP_VERSION(4, 3, 0):
1240 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1242 case IP_VERSION(4, 2, 0):
1243 case IP_VERSION(4, 2, 1):
1244 case IP_VERSION(4, 4, 0):
1245 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1247 case IP_VERSION(5, 0, 0):
1248 case IP_VERSION(5, 0, 1):
1249 case IP_VERSION(5, 0, 2):
1250 case IP_VERSION(5, 0, 3):
1251 case IP_VERSION(5, 2, 0):
1252 case IP_VERSION(5, 2, 1):
1253 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1257 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1258 adev->ip_versions[OSSSYS_HWIP][0]);
1264 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1266 switch (adev->ip_versions[MP0_HWIP][0]) {
1267 case IP_VERSION(9, 0, 0):
1268 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1270 case IP_VERSION(10, 0, 0):
1271 case IP_VERSION(10, 0, 1):
1272 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1274 case IP_VERSION(11, 0, 0):
1275 case IP_VERSION(11, 0, 2):
1276 case IP_VERSION(11, 0, 4):
1277 case IP_VERSION(11, 0, 5):
1278 case IP_VERSION(11, 0, 9):
1279 case IP_VERSION(11, 0, 7):
1280 case IP_VERSION(11, 0, 11):
1281 case IP_VERSION(11, 0, 12):
1282 case IP_VERSION(11, 0, 13):
1283 case IP_VERSION(11, 5, 0):
1284 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1286 case IP_VERSION(11, 0, 8):
1287 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1289 case IP_VERSION(11, 0, 3):
1290 case IP_VERSION(12, 0, 1):
1291 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1293 case IP_VERSION(13, 0, 1):
1294 case IP_VERSION(13, 0, 2):
1295 case IP_VERSION(13, 0, 3):
1296 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1300 "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1301 adev->ip_versions[MP0_HWIP][0]);
1307 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1309 switch (adev->ip_versions[MP1_HWIP][0]) {
1310 case IP_VERSION(9, 0, 0):
1311 case IP_VERSION(10, 0, 0):
1312 case IP_VERSION(10, 0, 1):
1313 case IP_VERSION(11, 0, 2):
1314 if (adev->asic_type == CHIP_ARCTURUS)
1315 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1317 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1319 case IP_VERSION(11, 0, 0):
1320 case IP_VERSION(11, 0, 5):
1321 case IP_VERSION(11, 0, 9):
1322 case IP_VERSION(11, 0, 7):
1323 case IP_VERSION(11, 0, 8):
1324 case IP_VERSION(11, 0, 11):
1325 case IP_VERSION(11, 0, 12):
1326 case IP_VERSION(11, 0, 13):
1327 case IP_VERSION(11, 5, 0):
1328 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1330 case IP_VERSION(12, 0, 0):
1331 case IP_VERSION(12, 0, 1):
1332 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1334 case IP_VERSION(13, 0, 1):
1335 case IP_VERSION(13, 0, 2):
1336 case IP_VERSION(13, 0, 3):
1337 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1341 "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
1342 adev->ip_versions[MP1_HWIP][0]);
1348 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
1350 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
1351 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1355 if (!amdgpu_device_has_dc_support(adev))
1358 #if defined(CONFIG_DRM_AMD_DC)
1359 if (adev->ip_versions[DCE_HWIP][0]) {
1360 switch (adev->ip_versions[DCE_HWIP][0]) {
1361 case IP_VERSION(1, 0, 0):
1362 case IP_VERSION(1, 0, 1):
1363 case IP_VERSION(2, 0, 2):
1364 case IP_VERSION(2, 0, 0):
1365 case IP_VERSION(2, 0, 3):
1366 case IP_VERSION(2, 1, 0):
1367 case IP_VERSION(3, 0, 0):
1368 case IP_VERSION(3, 0, 2):
1369 case IP_VERSION(3, 0, 3):
1370 case IP_VERSION(3, 0, 1):
1371 case IP_VERSION(3, 1, 2):
1372 case IP_VERSION(3, 1, 3):
1373 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1377 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
1378 adev->ip_versions[DCE_HWIP][0]);
1381 } else if (adev->ip_versions[DCI_HWIP][0]) {
1382 switch (adev->ip_versions[DCI_HWIP][0]) {
1383 case IP_VERSION(12, 0, 0):
1384 case IP_VERSION(12, 0, 1):
1385 case IP_VERSION(12, 1, 0):
1386 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1390 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
1391 adev->ip_versions[DCI_HWIP][0]);
1399 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
1401 switch (adev->ip_versions[GC_HWIP][0]) {
1402 case IP_VERSION(9, 0, 1):
1403 case IP_VERSION(9, 1, 0):
1404 case IP_VERSION(9, 2, 1):
1405 case IP_VERSION(9, 2, 2):
1406 case IP_VERSION(9, 3, 0):
1407 case IP_VERSION(9, 4, 0):
1408 case IP_VERSION(9, 4, 1):
1409 case IP_VERSION(9, 4, 2):
1410 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1412 case IP_VERSION(10, 1, 10):
1413 case IP_VERSION(10, 1, 2):
1414 case IP_VERSION(10, 1, 1):
1415 case IP_VERSION(10, 1, 3):
1416 case IP_VERSION(10, 1, 4):
1417 case IP_VERSION(10, 3, 0):
1418 case IP_VERSION(10, 3, 2):
1419 case IP_VERSION(10, 3, 1):
1420 case IP_VERSION(10, 3, 4):
1421 case IP_VERSION(10, 3, 5):
1422 case IP_VERSION(10, 3, 3):
1423 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1427 "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
1428 adev->ip_versions[GC_HWIP][0]);
1434 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
1436 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1437 case IP_VERSION(4, 0, 0):
1438 case IP_VERSION(4, 0, 1):
1439 case IP_VERSION(4, 1, 0):
1440 case IP_VERSION(4, 1, 1):
1441 case IP_VERSION(4, 1, 2):
1442 case IP_VERSION(4, 2, 0):
1443 case IP_VERSION(4, 2, 2):
1444 case IP_VERSION(4, 4, 0):
1445 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1447 case IP_VERSION(5, 0, 0):
1448 case IP_VERSION(5, 0, 1):
1449 case IP_VERSION(5, 0, 2):
1450 case IP_VERSION(5, 0, 5):
1451 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
1453 case IP_VERSION(5, 2, 0):
1454 case IP_VERSION(5, 2, 2):
1455 case IP_VERSION(5, 2, 4):
1456 case IP_VERSION(5, 2, 5):
1457 case IP_VERSION(5, 2, 3):
1458 case IP_VERSION(5, 2, 1):
1459 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1463 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
1464 adev->ip_versions[SDMA0_HWIP][0]);
1470 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
1472 if (adev->ip_versions[VCE_HWIP][0]) {
1473 switch (adev->ip_versions[UVD_HWIP][0]) {
1474 case IP_VERSION(7, 0, 0):
1475 case IP_VERSION(7, 2, 0):
1476 /* UVD is not supported on vega20 SR-IOV */
1477 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1478 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
1482 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
1483 adev->ip_versions[UVD_HWIP][0]);
1486 switch (adev->ip_versions[VCE_HWIP][0]) {
1487 case IP_VERSION(4, 0, 0):
1488 case IP_VERSION(4, 1, 0):
1489 /* VCE is not supported on vega20 SR-IOV */
1490 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1491 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
1495 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
1496 adev->ip_versions[VCE_HWIP][0]);
1500 switch (adev->ip_versions[UVD_HWIP][0]) {
1501 case IP_VERSION(1, 0, 0):
1502 case IP_VERSION(1, 0, 1):
1503 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1505 case IP_VERSION(2, 0, 0):
1506 case IP_VERSION(2, 0, 2):
1507 case IP_VERSION(2, 2, 0):
1508 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
1509 if (!amdgpu_sriov_vf(adev))
1510 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1512 case IP_VERSION(2, 0, 3):
1514 case IP_VERSION(2, 5, 0):
1515 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1516 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1518 case IP_VERSION(2, 6, 0):
1519 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1520 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1522 case IP_VERSION(3, 0, 0):
1523 case IP_VERSION(3, 0, 16):
1524 case IP_VERSION(3, 1, 1):
1525 case IP_VERSION(3, 0, 2):
1526 case IP_VERSION(3, 0, 192):
1527 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1528 if (!amdgpu_sriov_vf(adev))
1529 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
1531 case IP_VERSION(3, 0, 33):
1532 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1536 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
1537 adev->ip_versions[UVD_HWIP][0]);
1544 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
1546 switch (adev->ip_versions[GC_HWIP][0]) {
1547 case IP_VERSION(10, 1, 10):
1548 case IP_VERSION(10, 1, 1):
1549 case IP_VERSION(10, 1, 2):
1550 case IP_VERSION(10, 1, 3):
1551 case IP_VERSION(10, 1, 4):
1552 case IP_VERSION(10, 3, 0):
1553 case IP_VERSION(10, 3, 1):
1554 case IP_VERSION(10, 3, 2):
1555 case IP_VERSION(10, 3, 3):
1556 case IP_VERSION(10, 3, 4):
1557 case IP_VERSION(10, 3, 5):
1558 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
1566 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
1570 switch (adev->asic_type) {
1572 vega10_reg_base_init(adev);
1573 adev->sdma.num_instances = 2;
1574 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1575 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
1576 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
1577 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
1578 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
1579 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
1580 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1581 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
1582 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
1583 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1584 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1585 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1586 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
1587 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
1588 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1589 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1590 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
1593 vega10_reg_base_init(adev);
1594 adev->sdma.num_instances = 2;
1595 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1596 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
1597 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
1598 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
1599 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
1600 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
1601 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
1602 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
1603 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
1604 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
1605 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
1606 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
1607 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
1608 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
1609 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
1610 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
1611 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
1614 vega10_reg_base_init(adev);
1615 adev->sdma.num_instances = 1;
1616 adev->vcn.num_vcn_inst = 1;
1617 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1618 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1619 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
1620 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
1621 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
1622 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
1623 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
1624 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
1625 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
1626 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
1627 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
1628 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
1629 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
1630 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
1631 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
1632 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
1634 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1635 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
1636 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
1637 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
1638 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
1639 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
1640 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
1641 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
1642 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
1643 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
1644 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
1645 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
1646 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
1647 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
1648 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
1652 vega20_reg_base_init(adev);
1653 adev->sdma.num_instances = 2;
1654 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1655 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1656 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
1657 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
1658 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
1659 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
1660 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
1661 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
1662 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
1663 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
1664 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1665 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
1666 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
1667 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
1668 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
1669 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
1670 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
1671 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
1674 arct_reg_base_init(adev);
1675 adev->sdma.num_instances = 8;
1676 adev->vcn.num_vcn_inst = 2;
1677 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1678 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1679 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
1680 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
1681 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
1682 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
1683 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
1684 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
1685 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
1686 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
1687 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
1688 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
1689 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
1690 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
1691 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
1692 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
1693 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1694 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
1695 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
1696 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
1697 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
1698 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
1700 case CHIP_ALDEBARAN:
1701 aldebaran_reg_base_init(adev);
1702 adev->sdma.num_instances = 5;
1703 adev->vcn.num_vcn_inst = 2;
1704 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1705 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1706 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
1707 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
1708 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
1709 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
1710 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
1711 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
1712 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
1713 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
1714 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
1715 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
1716 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
1717 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
1718 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
1719 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
1720 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
1721 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
1722 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
1723 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
1726 r = amdgpu_discovery_reg_base_init(adev);
1730 amdgpu_discovery_harvest_ip(adev);
1734 switch (adev->ip_versions[GC_HWIP][0]) {
1735 case IP_VERSION(9, 0, 1):
1736 case IP_VERSION(9, 2, 1):
1737 case IP_VERSION(9, 4, 0):
1738 case IP_VERSION(9, 4, 1):
1739 case IP_VERSION(9, 4, 2):
1740 adev->family = AMDGPU_FAMILY_AI;
1742 case IP_VERSION(9, 1, 0):
1743 case IP_VERSION(9, 2, 2):
1744 case IP_VERSION(9, 3, 0):
1745 adev->family = AMDGPU_FAMILY_RV;
1747 case IP_VERSION(10, 1, 10):
1748 case IP_VERSION(10, 1, 1):
1749 case IP_VERSION(10, 1, 2):
1750 case IP_VERSION(10, 1, 3):
1751 case IP_VERSION(10, 1, 4):
1752 case IP_VERSION(10, 3, 0):
1753 case IP_VERSION(10, 3, 2):
1754 case IP_VERSION(10, 3, 4):
1755 case IP_VERSION(10, 3, 5):
1756 adev->family = AMDGPU_FAMILY_NV;
1758 case IP_VERSION(10, 3, 1):
1759 adev->family = AMDGPU_FAMILY_VGH;
1761 case IP_VERSION(10, 3, 3):
1762 adev->family = AMDGPU_FAMILY_YC;
1768 switch (adev->ip_versions[GC_HWIP][0]) {
1769 case IP_VERSION(9, 1, 0):
1770 case IP_VERSION(9, 2, 2):
1771 case IP_VERSION(9, 3, 0):
1772 case IP_VERSION(10, 1, 3):
1773 case IP_VERSION(10, 1, 4):
1774 case IP_VERSION(10, 3, 1):
1775 case IP_VERSION(10, 3, 3):
1776 adev->flags |= AMD_IS_APU;
1782 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
1783 adev->gmc.xgmi.supported = true;
1785 /* set NBIO version */
1786 switch (adev->ip_versions[NBIO_HWIP][0]) {
1787 case IP_VERSION(6, 1, 0):
1788 case IP_VERSION(6, 2, 0):
1789 adev->nbio.funcs = &nbio_v6_1_funcs;
1790 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
1792 case IP_VERSION(7, 0, 0):
1793 case IP_VERSION(7, 0, 1):
1794 case IP_VERSION(2, 5, 0):
1795 adev->nbio.funcs = &nbio_v7_0_funcs;
1796 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
1798 case IP_VERSION(7, 4, 0):
1799 case IP_VERSION(7, 4, 1):
1800 adev->nbio.funcs = &nbio_v7_4_funcs;
1801 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
1803 case IP_VERSION(7, 4, 4):
1804 adev->nbio.funcs = &nbio_v7_4_funcs;
1805 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald;
1807 case IP_VERSION(7, 2, 0):
1808 case IP_VERSION(7, 2, 1):
1809 case IP_VERSION(7, 5, 0):
1810 case IP_VERSION(7, 5, 1):
1811 adev->nbio.funcs = &nbio_v7_2_funcs;
1812 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
1814 case IP_VERSION(2, 1, 1):
1815 case IP_VERSION(2, 3, 0):
1816 case IP_VERSION(2, 3, 1):
1817 case IP_VERSION(2, 3, 2):
1818 adev->nbio.funcs = &nbio_v2_3_funcs;
1819 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
1821 case IP_VERSION(3, 3, 0):
1822 case IP_VERSION(3, 3, 1):
1823 case IP_VERSION(3, 3, 2):
1824 case IP_VERSION(3, 3, 3):
1825 adev->nbio.funcs = &nbio_v2_3_funcs;
1826 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
1832 switch (adev->ip_versions[HDP_HWIP][0]) {
1833 case IP_VERSION(4, 0, 0):
1834 case IP_VERSION(4, 0, 1):
1835 case IP_VERSION(4, 1, 0):
1836 case IP_VERSION(4, 1, 1):
1837 case IP_VERSION(4, 1, 2):
1838 case IP_VERSION(4, 2, 0):
1839 case IP_VERSION(4, 2, 1):
1840 case IP_VERSION(4, 4, 0):
1841 adev->hdp.funcs = &hdp_v4_0_funcs;
1843 case IP_VERSION(5, 0, 0):
1844 case IP_VERSION(5, 0, 1):
1845 case IP_VERSION(5, 0, 2):
1846 case IP_VERSION(5, 0, 3):
1847 case IP_VERSION(5, 0, 4):
1848 case IP_VERSION(5, 2, 0):
1849 adev->hdp.funcs = &hdp_v5_0_funcs;
1855 switch (adev->ip_versions[DF_HWIP][0]) {
1856 case IP_VERSION(3, 6, 0):
1857 case IP_VERSION(3, 6, 1):
1858 case IP_VERSION(3, 6, 2):
1859 adev->df.funcs = &df_v3_6_funcs;
1861 case IP_VERSION(2, 1, 0):
1862 case IP_VERSION(2, 1, 1):
1863 case IP_VERSION(2, 5, 0):
1864 case IP_VERSION(3, 5, 1):
1865 case IP_VERSION(3, 5, 2):
1866 adev->df.funcs = &df_v1_7_funcs;
1872 switch (adev->ip_versions[SMUIO_HWIP][0]) {
1873 case IP_VERSION(9, 0, 0):
1874 case IP_VERSION(9, 0, 1):
1875 case IP_VERSION(10, 0, 0):
1876 case IP_VERSION(10, 0, 1):
1877 case IP_VERSION(10, 0, 2):
1878 adev->smuio.funcs = &smuio_v9_0_funcs;
1880 case IP_VERSION(11, 0, 0):
1881 case IP_VERSION(11, 0, 2):
1882 case IP_VERSION(11, 0, 3):
1883 case IP_VERSION(11, 0, 4):
1884 case IP_VERSION(11, 0, 7):
1885 case IP_VERSION(11, 0, 8):
1886 adev->smuio.funcs = &smuio_v11_0_funcs;
1888 case IP_VERSION(11, 0, 6):
1889 case IP_VERSION(11, 0, 10):
1890 case IP_VERSION(11, 0, 11):
1891 case IP_VERSION(11, 5, 0):
1892 case IP_VERSION(13, 0, 1):
1893 case IP_VERSION(13, 0, 9):
1894 adev->smuio.funcs = &smuio_v11_0_6_funcs;
1896 case IP_VERSION(13, 0, 2):
1897 adev->smuio.funcs = &smuio_v13_0_funcs;
1903 r = amdgpu_discovery_set_common_ip_blocks(adev);
1907 r = amdgpu_discovery_set_gmc_ip_blocks(adev);
1911 /* For SR-IOV, PSP needs to be initialized before IH */
1912 if (amdgpu_sriov_vf(adev)) {
1913 r = amdgpu_discovery_set_psp_ip_blocks(adev);
1916 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1920 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1924 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1925 r = amdgpu_discovery_set_psp_ip_blocks(adev);
1931 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1932 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1937 r = amdgpu_discovery_set_display_ip_blocks(adev);
1941 r = amdgpu_discovery_set_gc_ip_blocks(adev);
1945 r = amdgpu_discovery_set_sdma_ip_blocks(adev);
1949 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
1950 !amdgpu_sriov_vf(adev)) {
1951 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1956 r = amdgpu_discovery_set_mm_ip_blocks(adev);
1960 if (adev->enable_mes) {
1961 r = amdgpu_discovery_set_mes_ip_blocks(adev);