2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/amdgpu_drm.h>
37 #include <linux/vgaarb.h>
38 #include <linux/vga_switcheroo.h>
39 #include <linux/efi.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_i2c.h"
44 #include "amdgpu_atombios.h"
45 #include "amdgpu_atomfirmware.h"
47 #ifdef CONFIG_DRM_AMDGPU_SI
50 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #include "bif/bif_4_1_d.h"
57 #include <linux/pci.h>
58 #include <linux/firmware.h>
59 #include "amdgpu_vf_error.h"
61 #include "amdgpu_amdkfd.h"
62 #include "amdgpu_pm.h"
64 #include "amdgpu_xgmi.h"
65 #include "amdgpu_ras.h"
66 #include "amdgpu_pmu.h"
67 #include "amdgpu_fru_eeprom.h"
69 #include <linux/suspend.h>
70 #include <drm/task_barrier.h>
71 #include <linux/pm_runtime.h>
73 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
74 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
75 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
76 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
77 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
78 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
79 MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
80 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
81 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
82 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
83 MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
85 #define AMDGPU_RESUME_MS 2000
87 const char *amdgpu_asic_name[] = {
124 * DOC: pcie_replay_count
126 * The amdgpu driver provides a sysfs API for reporting the total number
127 * of PCIe replays (NAKs)
128 * The file pcie_replay_count is used for this and returns the total
129 * number of replays as a sum of the NAKs generated and NAKs received
132 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
133 struct device_attribute *attr, char *buf)
135 struct drm_device *ddev = dev_get_drvdata(dev);
136 struct amdgpu_device *adev = drm_to_adev(ddev);
137 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
139 return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
142 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
143 amdgpu_device_get_pcie_replay_count, NULL);
145 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
150 * The amdgpu driver provides a sysfs API for reporting the product name
152 * The file serial_number is used for this and returns the product name
153 * as returned from the FRU.
154 * NOTE: This is only available for certain server cards
157 static ssize_t amdgpu_device_get_product_name(struct device *dev,
158 struct device_attribute *attr, char *buf)
160 struct drm_device *ddev = dev_get_drvdata(dev);
161 struct amdgpu_device *adev = drm_to_adev(ddev);
163 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name);
166 static DEVICE_ATTR(product_name, S_IRUGO,
167 amdgpu_device_get_product_name, NULL);
170 * DOC: product_number
172 * The amdgpu driver provides a sysfs API for reporting the part number
174 * The file serial_number is used for this and returns the part number
175 * as returned from the FRU.
176 * NOTE: This is only available for certain server cards
179 static ssize_t amdgpu_device_get_product_number(struct device *dev,
180 struct device_attribute *attr, char *buf)
182 struct drm_device *ddev = dev_get_drvdata(dev);
183 struct amdgpu_device *adev = drm_to_adev(ddev);
185 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number);
188 static DEVICE_ATTR(product_number, S_IRUGO,
189 amdgpu_device_get_product_number, NULL);
194 * The amdgpu driver provides a sysfs API for reporting the serial number
196 * The file serial_number is used for this and returns the serial number
197 * as returned from the FRU.
198 * NOTE: This is only available for certain server cards
201 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
202 struct device_attribute *attr, char *buf)
204 struct drm_device *ddev = dev_get_drvdata(dev);
205 struct amdgpu_device *adev = drm_to_adev(ddev);
207 return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial);
210 static DEVICE_ATTR(serial_number, S_IRUGO,
211 amdgpu_device_get_serial_number, NULL);
214 * amdgpu_device_supports_atpx - Is the device a dGPU with HG/PX power control
216 * @dev: drm_device pointer
218 * Returns true if the device is a dGPU with HG/PX power control,
219 * otherwise return false.
221 bool amdgpu_device_supports_atpx(struct drm_device *dev)
223 struct amdgpu_device *adev = drm_to_adev(dev);
225 if (adev->flags & AMD_IS_PX)
231 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
233 * @dev: drm_device pointer
235 * Returns true if the device is a dGPU with HG/PX power control,
236 * otherwise return false.
238 bool amdgpu_device_supports_boco(struct drm_device *dev)
240 struct amdgpu_device *adev = drm_to_adev(dev);
248 * amdgpu_device_supports_baco - Does the device support BACO
250 * @dev: drm_device pointer
252 * Returns true if the device supporte BACO,
253 * otherwise return false.
255 bool amdgpu_device_supports_baco(struct drm_device *dev)
257 struct amdgpu_device *adev = drm_to_adev(dev);
259 return amdgpu_asic_supports_baco(adev);
263 * VRAM access helper functions
267 * amdgpu_device_vram_access - read/write a buffer in vram
269 * @adev: amdgpu_device pointer
270 * @pos: offset of the buffer in vram
271 * @buf: virtual address of the buffer in system memory
272 * @size: read/write size, sizeof(@buf) must > @size
273 * @write: true - write to vram, otherwise - read from vram
275 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
276 uint32_t *buf, size_t size, bool write)
284 last = min(pos + size, adev->gmc.visible_vram_size);
286 void __iomem *addr = adev->mman.aper_base_kaddr + pos;
287 size_t count = last - pos;
290 memcpy_toio(addr, buf, count);
292 amdgpu_asic_flush_hdp(adev, NULL);
294 amdgpu_asic_invalidate_hdp(adev, NULL);
296 memcpy_fromio(buf, addr, count);
308 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
309 for (last = pos + size; pos < last; pos += 4) {
310 uint32_t tmp = pos >> 31;
312 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
314 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
318 WREG32_NO_KIQ(mmMM_DATA, *buf++);
320 *buf++ = RREG32_NO_KIQ(mmMM_DATA);
322 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
326 * register access helper functions.
329 * amdgpu_device_rreg - read a memory mapped IO or indirect register
331 * @adev: amdgpu_device pointer
332 * @reg: dword aligned register offset
333 * @acc_flags: access flags which require special behavior
335 * Returns the 32 bit value from the offset specified.
337 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
338 uint32_t reg, uint32_t acc_flags)
342 if (adev->in_pci_err_recovery)
345 if ((reg * 4) < adev->rmmio_size) {
346 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
347 amdgpu_sriov_runtime(adev) &&
348 down_read_trylock(&adev->reset_sem)) {
349 ret = amdgpu_kiq_rreg(adev, reg);
350 up_read(&adev->reset_sem);
352 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
355 ret = adev->pcie_rreg(adev, reg * 4);
358 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
364 * MMIO register read with bytes helper functions
365 * @offset:bytes offset from MMIO start
370 * amdgpu_mm_rreg8 - read a memory mapped IO register
372 * @adev: amdgpu_device pointer
373 * @offset: byte aligned register offset
375 * Returns the 8 bit value from the offset specified.
377 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
379 if (adev->in_pci_err_recovery)
382 if (offset < adev->rmmio_size)
383 return (readb(adev->rmmio + offset));
388 * MMIO register write with bytes helper functions
389 * @offset:bytes offset from MMIO start
390 * @value: the value want to be written to the register
394 * amdgpu_mm_wreg8 - read a memory mapped IO register
396 * @adev: amdgpu_device pointer
397 * @offset: byte aligned register offset
398 * @value: 8 bit value to write
400 * Writes the value specified to the offset specified.
402 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
404 if (adev->in_pci_err_recovery)
407 if (offset < adev->rmmio_size)
408 writeb(value, adev->rmmio + offset);
414 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
416 * @adev: amdgpu_device pointer
417 * @reg: dword aligned register offset
418 * @v: 32 bit value to write to the register
419 * @acc_flags: access flags which require special behavior
421 * Writes the value specified to the offset specified.
423 void amdgpu_device_wreg(struct amdgpu_device *adev,
424 uint32_t reg, uint32_t v,
427 if (adev->in_pci_err_recovery)
430 if ((reg * 4) < adev->rmmio_size) {
431 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
432 amdgpu_sriov_runtime(adev) &&
433 down_read_trylock(&adev->reset_sem)) {
434 amdgpu_kiq_wreg(adev, reg, v);
435 up_read(&adev->reset_sem);
437 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
440 adev->pcie_wreg(adev, reg * 4, v);
443 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
447 * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range
449 * this function is invoked only the debugfs register access
451 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
452 uint32_t reg, uint32_t v)
454 if (adev->in_pci_err_recovery)
457 if (amdgpu_sriov_fullaccess(adev) &&
458 adev->gfx.rlc.funcs &&
459 adev->gfx.rlc.funcs->is_rlcg_access_range) {
460 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
461 return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);
463 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
468 * amdgpu_io_rreg - read an IO register
470 * @adev: amdgpu_device pointer
471 * @reg: dword aligned register offset
473 * Returns the 32 bit value from the offset specified.
475 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
477 if (adev->in_pci_err_recovery)
480 if ((reg * 4) < adev->rio_mem_size)
481 return ioread32(adev->rio_mem + (reg * 4));
483 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
484 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
489 * amdgpu_io_wreg - write to an IO register
491 * @adev: amdgpu_device pointer
492 * @reg: dword aligned register offset
493 * @v: 32 bit value to write to the register
495 * Writes the value specified to the offset specified.
497 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
499 if (adev->in_pci_err_recovery)
502 if ((reg * 4) < adev->rio_mem_size)
503 iowrite32(v, adev->rio_mem + (reg * 4));
505 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
506 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
511 * amdgpu_mm_rdoorbell - read a doorbell dword
513 * @adev: amdgpu_device pointer
514 * @index: doorbell index
516 * Returns the value in the doorbell aperture at the
517 * requested doorbell index (CIK).
519 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
521 if (adev->in_pci_err_recovery)
524 if (index < adev->doorbell.num_doorbells) {
525 return readl(adev->doorbell.ptr + index);
527 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
533 * amdgpu_mm_wdoorbell - write a doorbell dword
535 * @adev: amdgpu_device pointer
536 * @index: doorbell index
539 * Writes @v to the doorbell aperture at the
540 * requested doorbell index (CIK).
542 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
544 if (adev->in_pci_err_recovery)
547 if (index < adev->doorbell.num_doorbells) {
548 writel(v, adev->doorbell.ptr + index);
550 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
555 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
557 * @adev: amdgpu_device pointer
558 * @index: doorbell index
560 * Returns the value in the doorbell aperture at the
561 * requested doorbell index (VEGA10+).
563 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
565 if (adev->in_pci_err_recovery)
568 if (index < adev->doorbell.num_doorbells) {
569 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
571 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
577 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
579 * @adev: amdgpu_device pointer
580 * @index: doorbell index
583 * Writes @v to the doorbell aperture at the
584 * requested doorbell index (VEGA10+).
586 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
588 if (adev->in_pci_err_recovery)
591 if (index < adev->doorbell.num_doorbells) {
592 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
594 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
599 * amdgpu_device_indirect_rreg - read an indirect register
601 * @adev: amdgpu_device pointer
602 * @pcie_index: mmio register offset
603 * @pcie_data: mmio register offset
604 * @reg_addr: indirect register address to read from
606 * Returns the value of indirect register @reg_addr
608 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
609 u32 pcie_index, u32 pcie_data,
614 void __iomem *pcie_index_offset;
615 void __iomem *pcie_data_offset;
617 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
618 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
619 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
621 writel(reg_addr, pcie_index_offset);
622 readl(pcie_index_offset);
623 r = readl(pcie_data_offset);
624 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
630 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
632 * @adev: amdgpu_device pointer
633 * @pcie_index: mmio register offset
634 * @pcie_data: mmio register offset
635 * @reg_addr: indirect register address to read from
637 * Returns the value of indirect register @reg_addr
639 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
640 u32 pcie_index, u32 pcie_data,
645 void __iomem *pcie_index_offset;
646 void __iomem *pcie_data_offset;
648 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
649 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
650 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
652 /* read low 32 bits */
653 writel(reg_addr, pcie_index_offset);
654 readl(pcie_index_offset);
655 r = readl(pcie_data_offset);
656 /* read high 32 bits */
657 writel(reg_addr + 4, pcie_index_offset);
658 readl(pcie_index_offset);
659 r |= ((u64)readl(pcie_data_offset) << 32);
660 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
666 * amdgpu_device_indirect_wreg - write an indirect register address
668 * @adev: amdgpu_device pointer
669 * @pcie_index: mmio register offset
670 * @pcie_data: mmio register offset
671 * @reg_addr: indirect register offset
672 * @reg_data: indirect register data
675 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
676 u32 pcie_index, u32 pcie_data,
677 u32 reg_addr, u32 reg_data)
680 void __iomem *pcie_index_offset;
681 void __iomem *pcie_data_offset;
683 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
684 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
685 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
687 writel(reg_addr, pcie_index_offset);
688 readl(pcie_index_offset);
689 writel(reg_data, pcie_data_offset);
690 readl(pcie_data_offset);
691 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
695 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
697 * @adev: amdgpu_device pointer
698 * @pcie_index: mmio register offset
699 * @pcie_data: mmio register offset
700 * @reg_addr: indirect register offset
701 * @reg_data: indirect register data
704 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
705 u32 pcie_index, u32 pcie_data,
706 u32 reg_addr, u64 reg_data)
709 void __iomem *pcie_index_offset;
710 void __iomem *pcie_data_offset;
712 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
713 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
714 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
716 /* write low 32 bits */
717 writel(reg_addr, pcie_index_offset);
718 readl(pcie_index_offset);
719 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
720 readl(pcie_data_offset);
721 /* write high 32 bits */
722 writel(reg_addr + 4, pcie_index_offset);
723 readl(pcie_index_offset);
724 writel((u32)(reg_data >> 32), pcie_data_offset);
725 readl(pcie_data_offset);
726 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
730 * amdgpu_invalid_rreg - dummy reg read function
732 * @adev: amdgpu_device pointer
733 * @reg: offset of register
735 * Dummy register read function. Used for register blocks
736 * that certain asics don't have (all asics).
737 * Returns the value in the register.
739 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
741 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
747 * amdgpu_invalid_wreg - dummy reg write function
749 * @adev: amdgpu_device pointer
750 * @reg: offset of register
751 * @v: value to write to the register
753 * Dummy register read function. Used for register blocks
754 * that certain asics don't have (all asics).
756 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
758 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
764 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
766 * @adev: amdgpu_device pointer
767 * @reg: offset of register
769 * Dummy register read function. Used for register blocks
770 * that certain asics don't have (all asics).
771 * Returns the value in the register.
773 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
775 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
781 * amdgpu_invalid_wreg64 - dummy reg write function
783 * @adev: amdgpu_device pointer
784 * @reg: offset of register
785 * @v: value to write to the register
787 * Dummy register read function. Used for register blocks
788 * that certain asics don't have (all asics).
790 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
792 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
798 * amdgpu_block_invalid_rreg - dummy reg read function
800 * @adev: amdgpu_device pointer
801 * @block: offset of instance
802 * @reg: offset of register
804 * Dummy register read function. Used for register blocks
805 * that certain asics don't have (all asics).
806 * Returns the value in the register.
808 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
809 uint32_t block, uint32_t reg)
811 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
818 * amdgpu_block_invalid_wreg - dummy reg write function
820 * @adev: amdgpu_device pointer
821 * @block: offset of instance
822 * @reg: offset of register
823 * @v: value to write to the register
825 * Dummy register read function. Used for register blocks
826 * that certain asics don't have (all asics).
828 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
830 uint32_t reg, uint32_t v)
832 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
838 * amdgpu_device_asic_init - Wrapper for atom asic_init
840 * @adev: amdgpu_device pointer
842 * Does any asic specific work and then calls atom asic init.
844 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
846 amdgpu_asic_pre_asic_init(adev);
848 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
852 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
854 * @adev: amdgpu_device pointer
856 * Allocates a scratch page of VRAM for use by various things in the
859 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
861 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
862 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
863 &adev->vram_scratch.robj,
864 &adev->vram_scratch.gpu_addr,
865 (void **)&adev->vram_scratch.ptr);
869 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
871 * @adev: amdgpu_device pointer
873 * Frees the VRAM scratch page.
875 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
877 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
881 * amdgpu_device_program_register_sequence - program an array of registers.
883 * @adev: amdgpu_device pointer
884 * @registers: pointer to the register array
885 * @array_size: size of the register array
887 * Programs an array or registers with and and or masks.
888 * This is a helper for setting golden registers.
890 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
891 const u32 *registers,
892 const u32 array_size)
894 u32 tmp, reg, and_mask, or_mask;
900 for (i = 0; i < array_size; i +=3) {
901 reg = registers[i + 0];
902 and_mask = registers[i + 1];
903 or_mask = registers[i + 2];
905 if (and_mask == 0xffffffff) {
910 if (adev->family >= AMDGPU_FAMILY_AI)
911 tmp |= (or_mask & and_mask);
920 * amdgpu_device_pci_config_reset - reset the GPU
922 * @adev: amdgpu_device pointer
924 * Resets the GPU using the pci config reset sequence.
925 * Only applicable to asics prior to vega10.
927 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
929 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
933 * GPU doorbell aperture helpers function.
936 * amdgpu_device_doorbell_init - Init doorbell driver information.
938 * @adev: amdgpu_device pointer
940 * Init doorbell driver information (CIK)
941 * Returns 0 on success, error on failure.
943 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
946 /* No doorbell on SI hardware generation */
947 if (adev->asic_type < CHIP_BONAIRE) {
948 adev->doorbell.base = 0;
949 adev->doorbell.size = 0;
950 adev->doorbell.num_doorbells = 0;
951 adev->doorbell.ptr = NULL;
955 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
958 amdgpu_asic_init_doorbell_index(adev);
960 /* doorbell bar mapping */
961 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
962 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
964 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
965 adev->doorbell_index.max_assignment+1);
966 if (adev->doorbell.num_doorbells == 0)
969 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
970 * paging queue doorbell use the second page. The
971 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
972 * doorbells are in the first page. So with paging queue enabled,
973 * the max num_doorbells should + 1 page (0x400 in dword)
975 if (adev->asic_type >= CHIP_VEGA10)
976 adev->doorbell.num_doorbells += 0x400;
978 adev->doorbell.ptr = ioremap(adev->doorbell.base,
979 adev->doorbell.num_doorbells *
981 if (adev->doorbell.ptr == NULL)
988 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
990 * @adev: amdgpu_device pointer
992 * Tear down doorbell driver information (CIK)
994 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
996 iounmap(adev->doorbell.ptr);
997 adev->doorbell.ptr = NULL;
1003 * amdgpu_device_wb_*()
1004 * Writeback is the method by which the GPU updates special pages in memory
1005 * with the status of certain GPU events (fences, ring pointers,etc.).
1009 * amdgpu_device_wb_fini - Disable Writeback and free memory
1011 * @adev: amdgpu_device pointer
1013 * Disables Writeback and frees the Writeback memory (all asics).
1014 * Used at driver shutdown.
1016 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1018 if (adev->wb.wb_obj) {
1019 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1021 (void **)&adev->wb.wb);
1022 adev->wb.wb_obj = NULL;
1027 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
1029 * @adev: amdgpu_device pointer
1031 * Initializes writeback and allocates writeback memory (all asics).
1032 * Used at driver startup.
1033 * Returns 0 on success or an -error on failure.
1035 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1039 if (adev->wb.wb_obj == NULL) {
1040 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1041 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1042 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1043 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1044 (void **)&adev->wb.wb);
1046 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1050 adev->wb.num_wb = AMDGPU_MAX_WB;
1051 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1053 /* clear wb memory */
1054 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1061 * amdgpu_device_wb_get - Allocate a wb entry
1063 * @adev: amdgpu_device pointer
1066 * Allocate a wb slot for use by the driver (all asics).
1067 * Returns 0 on success or -EINVAL on failure.
1069 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1071 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1073 if (offset < adev->wb.num_wb) {
1074 __set_bit(offset, adev->wb.used);
1075 *wb = offset << 3; /* convert to dw offset */
1083 * amdgpu_device_wb_free - Free a wb entry
1085 * @adev: amdgpu_device pointer
1088 * Free a wb slot allocated for use by the driver (all asics)
1090 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1093 if (wb < adev->wb.num_wb)
1094 __clear_bit(wb, adev->wb.used);
1098 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1100 * @adev: amdgpu_device pointer
1102 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1103 * to fail, but if any of the BARs is not accessible after the size we abort
1104 * driver loading by returning -ENODEV.
1106 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1108 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1109 struct pci_bus *root;
1110 struct resource *res;
1116 if (amdgpu_sriov_vf(adev))
1119 /* skip if the bios has already enabled large BAR */
1120 if (adev->gmc.real_vram_size &&
1121 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1124 /* Check if the root BUS has 64bit memory resources */
1125 root = adev->pdev->bus;
1126 while (root->parent)
1127 root = root->parent;
1129 pci_bus_for_each_resource(root, res, i) {
1130 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1131 res->start > 0x100000000ull)
1135 /* Trying to resize is pointless without a root hub window above 4GB */
1139 /* Limit the BAR size to what is available */
1140 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1143 /* Disable memory decoding while we change the BAR addresses and size */
1144 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1145 pci_write_config_word(adev->pdev, PCI_COMMAND,
1146 cmd & ~PCI_COMMAND_MEMORY);
1148 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1149 amdgpu_device_doorbell_fini(adev);
1150 if (adev->asic_type >= CHIP_BONAIRE)
1151 pci_release_resource(adev->pdev, 2);
1153 pci_release_resource(adev->pdev, 0);
1155 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1157 DRM_INFO("Not enough PCI address space for a large BAR.");
1158 else if (r && r != -ENOTSUPP)
1159 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1161 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1163 /* When the doorbell or fb BAR isn't available we have no chance of
1166 r = amdgpu_device_doorbell_init(adev);
1167 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1170 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1176 * GPU helpers function.
1179 * amdgpu_device_need_post - check if the hw need post or not
1181 * @adev: amdgpu_device pointer
1183 * Check if the asic has been initialized (all asics) at driver startup
1184 * or post is needed if hw reset is performed.
1185 * Returns true if need or false if not.
1187 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1191 if (amdgpu_sriov_vf(adev))
1194 if (amdgpu_passthrough(adev)) {
1195 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1196 * some old smc fw still need driver do vPost otherwise gpu hang, while
1197 * those smc fw version above 22.15 doesn't have this flaw, so we force
1198 * vpost executed for smc version below 22.15
1200 if (adev->asic_type == CHIP_FIJI) {
1203 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1204 /* force vPost if error occured */
1208 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1209 if (fw_ver < 0x00160e00)
1214 if (adev->has_hw_reset) {
1215 adev->has_hw_reset = false;
1219 /* bios scratch used on CIK+ */
1220 if (adev->asic_type >= CHIP_BONAIRE)
1221 return amdgpu_atombios_scratch_need_asic_init(adev);
1223 /* check MEM_SIZE for older asics */
1224 reg = amdgpu_asic_get_config_memsize(adev);
1226 if ((reg != 0) && (reg != 0xffffffff))
1232 /* if we get transitioned to only one device, take VGA back */
1234 * amdgpu_device_vga_set_decode - enable/disable vga decode
1236 * @cookie: amdgpu_device pointer
1237 * @state: enable/disable vga decode
1239 * Enable/disable vga decode (all asics).
1240 * Returns VGA resource flags.
1242 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
1244 struct amdgpu_device *adev = cookie;
1245 amdgpu_asic_set_vga_state(adev, state);
1247 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1248 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1250 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1254 * amdgpu_device_check_block_size - validate the vm block size
1256 * @adev: amdgpu_device pointer
1258 * Validates the vm block size specified via module parameter.
1259 * The vm block size defines number of bits in page table versus page directory,
1260 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1261 * page table and the remaining bits are in the page directory.
1263 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1265 /* defines number of bits in page table versus page directory,
1266 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1267 * page table and the remaining bits are in the page directory */
1268 if (amdgpu_vm_block_size == -1)
1271 if (amdgpu_vm_block_size < 9) {
1272 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1273 amdgpu_vm_block_size);
1274 amdgpu_vm_block_size = -1;
1279 * amdgpu_device_check_vm_size - validate the vm size
1281 * @adev: amdgpu_device pointer
1283 * Validates the vm size in GB specified via module parameter.
1284 * The VM size is the size of the GPU virtual memory space in GB.
1286 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1288 /* no need to check the default value */
1289 if (amdgpu_vm_size == -1)
1292 if (amdgpu_vm_size < 1) {
1293 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1295 amdgpu_vm_size = -1;
1299 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1302 bool is_os_64 = (sizeof(void *) == 8);
1303 uint64_t total_memory;
1304 uint64_t dram_size_seven_GB = 0x1B8000000;
1305 uint64_t dram_size_three_GB = 0xB8000000;
1307 if (amdgpu_smu_memory_pool_size == 0)
1311 DRM_WARN("Not 64-bit OS, feature not supported\n");
1315 total_memory = (uint64_t)si.totalram * si.mem_unit;
1317 if ((amdgpu_smu_memory_pool_size == 1) ||
1318 (amdgpu_smu_memory_pool_size == 2)) {
1319 if (total_memory < dram_size_three_GB)
1321 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1322 (amdgpu_smu_memory_pool_size == 8)) {
1323 if (total_memory < dram_size_seven_GB)
1326 DRM_WARN("Smu memory pool size not supported\n");
1329 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1334 DRM_WARN("No enough system memory\n");
1336 adev->pm.smu_prv_buffer_size = 0;
1340 * amdgpu_device_check_arguments - validate module params
1342 * @adev: amdgpu_device pointer
1344 * Validates certain module parameters and updates
1345 * the associated values used by the driver (all asics).
1347 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1349 if (amdgpu_sched_jobs < 4) {
1350 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1352 amdgpu_sched_jobs = 4;
1353 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1354 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1356 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1359 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1360 /* gart size must be greater or equal to 32M */
1361 dev_warn(adev->dev, "gart size (%d) too small\n",
1363 amdgpu_gart_size = -1;
1366 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1367 /* gtt size must be greater or equal to 32M */
1368 dev_warn(adev->dev, "gtt size (%d) too small\n",
1370 amdgpu_gtt_size = -1;
1373 /* valid range is between 4 and 9 inclusive */
1374 if (amdgpu_vm_fragment_size != -1 &&
1375 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1376 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1377 amdgpu_vm_fragment_size = -1;
1380 if (amdgpu_sched_hw_submission < 2) {
1381 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1382 amdgpu_sched_hw_submission);
1383 amdgpu_sched_hw_submission = 2;
1384 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1385 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1386 amdgpu_sched_hw_submission);
1387 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1390 amdgpu_device_check_smu_prv_buffer_size(adev);
1392 amdgpu_device_check_vm_size(adev);
1394 amdgpu_device_check_block_size(adev);
1396 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1398 amdgpu_gmc_tmz_set(adev);
1400 amdgpu_gmc_noretry_set(adev);
1406 * amdgpu_switcheroo_set_state - set switcheroo state
1408 * @pdev: pci dev pointer
1409 * @state: vga_switcheroo state
1411 * Callback for the switcheroo driver. Suspends or resumes the
1412 * the asics before or after it is powered up using ACPI methods.
1414 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1415 enum vga_switcheroo_state state)
1417 struct drm_device *dev = pci_get_drvdata(pdev);
1420 if (amdgpu_device_supports_atpx(dev) && state == VGA_SWITCHEROO_OFF)
1423 if (state == VGA_SWITCHEROO_ON) {
1424 pr_info("switched on\n");
1425 /* don't suspend or resume card normally */
1426 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1428 pci_set_power_state(pdev, PCI_D0);
1429 amdgpu_device_load_pci_state(pdev);
1430 r = pci_enable_device(pdev);
1432 DRM_WARN("pci_enable_device failed (%d)\n", r);
1433 amdgpu_device_resume(dev, true);
1435 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1436 drm_kms_helper_poll_enable(dev);
1438 pr_info("switched off\n");
1439 drm_kms_helper_poll_disable(dev);
1440 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1441 amdgpu_device_suspend(dev, true);
1442 amdgpu_device_cache_pci_state(pdev);
1443 /* Shut down the device */
1444 pci_disable_device(pdev);
1445 pci_set_power_state(pdev, PCI_D3cold);
1446 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1451 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1453 * @pdev: pci dev pointer
1455 * Callback for the switcheroo driver. Check of the switcheroo
1456 * state can be changed.
1457 * Returns true if the state can be changed, false if not.
1459 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1461 struct drm_device *dev = pci_get_drvdata(pdev);
1464 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1465 * locking inversion with the driver load path. And the access here is
1466 * completely racy anyway. So don't bother with locking for now.
1468 return atomic_read(&dev->open_count) == 0;
1471 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1472 .set_gpu_state = amdgpu_switcheroo_set_state,
1474 .can_switch = amdgpu_switcheroo_can_switch,
1478 * amdgpu_device_ip_set_clockgating_state - set the CG state
1480 * @dev: amdgpu_device pointer
1481 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1482 * @state: clockgating state (gate or ungate)
1484 * Sets the requested clockgating state for all instances of
1485 * the hardware IP specified.
1486 * Returns the error code from the last instance.
1488 int amdgpu_device_ip_set_clockgating_state(void *dev,
1489 enum amd_ip_block_type block_type,
1490 enum amd_clockgating_state state)
1492 struct amdgpu_device *adev = dev;
1495 for (i = 0; i < adev->num_ip_blocks; i++) {
1496 if (!adev->ip_blocks[i].status.valid)
1498 if (adev->ip_blocks[i].version->type != block_type)
1500 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1502 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1503 (void *)adev, state);
1505 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1506 adev->ip_blocks[i].version->funcs->name, r);
1512 * amdgpu_device_ip_set_powergating_state - set the PG state
1514 * @dev: amdgpu_device pointer
1515 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1516 * @state: powergating state (gate or ungate)
1518 * Sets the requested powergating state for all instances of
1519 * the hardware IP specified.
1520 * Returns the error code from the last instance.
1522 int amdgpu_device_ip_set_powergating_state(void *dev,
1523 enum amd_ip_block_type block_type,
1524 enum amd_powergating_state state)
1526 struct amdgpu_device *adev = dev;
1529 for (i = 0; i < adev->num_ip_blocks; i++) {
1530 if (!adev->ip_blocks[i].status.valid)
1532 if (adev->ip_blocks[i].version->type != block_type)
1534 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1536 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1537 (void *)adev, state);
1539 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1540 adev->ip_blocks[i].version->funcs->name, r);
1546 * amdgpu_device_ip_get_clockgating_state - get the CG state
1548 * @adev: amdgpu_device pointer
1549 * @flags: clockgating feature flags
1551 * Walks the list of IPs on the device and updates the clockgating
1552 * flags for each IP.
1553 * Updates @flags with the feature flags for each hardware IP where
1554 * clockgating is enabled.
1556 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1561 for (i = 0; i < adev->num_ip_blocks; i++) {
1562 if (!adev->ip_blocks[i].status.valid)
1564 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1565 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1570 * amdgpu_device_ip_wait_for_idle - wait for idle
1572 * @adev: amdgpu_device pointer
1573 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1575 * Waits for the request hardware IP to be idle.
1576 * Returns 0 for success or a negative error code on failure.
1578 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1579 enum amd_ip_block_type block_type)
1583 for (i = 0; i < adev->num_ip_blocks; i++) {
1584 if (!adev->ip_blocks[i].status.valid)
1586 if (adev->ip_blocks[i].version->type == block_type) {
1587 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1598 * amdgpu_device_ip_is_idle - is the hardware IP idle
1600 * @adev: amdgpu_device pointer
1601 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1603 * Check if the hardware IP is idle or not.
1604 * Returns true if it the IP is idle, false if not.
1606 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1607 enum amd_ip_block_type block_type)
1611 for (i = 0; i < adev->num_ip_blocks; i++) {
1612 if (!adev->ip_blocks[i].status.valid)
1614 if (adev->ip_blocks[i].version->type == block_type)
1615 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1622 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1624 * @adev: amdgpu_device pointer
1625 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1627 * Returns a pointer to the hardware IP block structure
1628 * if it exists for the asic, otherwise NULL.
1630 struct amdgpu_ip_block *
1631 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1632 enum amd_ip_block_type type)
1636 for (i = 0; i < adev->num_ip_blocks; i++)
1637 if (adev->ip_blocks[i].version->type == type)
1638 return &adev->ip_blocks[i];
1644 * amdgpu_device_ip_block_version_cmp
1646 * @adev: amdgpu_device pointer
1647 * @type: enum amd_ip_block_type
1648 * @major: major version
1649 * @minor: minor version
1651 * return 0 if equal or greater
1652 * return 1 if smaller or the ip_block doesn't exist
1654 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1655 enum amd_ip_block_type type,
1656 u32 major, u32 minor)
1658 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1660 if (ip_block && ((ip_block->version->major > major) ||
1661 ((ip_block->version->major == major) &&
1662 (ip_block->version->minor >= minor))))
1669 * amdgpu_device_ip_block_add
1671 * @adev: amdgpu_device pointer
1672 * @ip_block_version: pointer to the IP to add
1674 * Adds the IP block driver information to the collection of IPs
1677 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1678 const struct amdgpu_ip_block_version *ip_block_version)
1680 if (!ip_block_version)
1683 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1684 ip_block_version->funcs->name);
1686 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1692 * amdgpu_device_enable_virtual_display - enable virtual display feature
1694 * @adev: amdgpu_device pointer
1696 * Enabled the virtual display feature if the user has enabled it via
1697 * the module parameter virtual_display. This feature provides a virtual
1698 * display hardware on headless boards or in virtualized environments.
1699 * This function parses and validates the configuration string specified by
1700 * the user and configues the virtual display configuration (number of
1701 * virtual connectors, crtcs, etc.) specified.
1703 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1705 adev->enable_virtual_display = false;
1707 if (amdgpu_virtual_display) {
1708 const char *pci_address_name = pci_name(adev->pdev);
1709 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1711 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1712 pciaddstr_tmp = pciaddstr;
1713 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1714 pciaddname = strsep(&pciaddname_tmp, ",");
1715 if (!strcmp("all", pciaddname)
1716 || !strcmp(pci_address_name, pciaddname)) {
1720 adev->enable_virtual_display = true;
1723 res = kstrtol(pciaddname_tmp, 10,
1731 adev->mode_info.num_crtc = num_crtc;
1733 adev->mode_info.num_crtc = 1;
1739 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1740 amdgpu_virtual_display, pci_address_name,
1741 adev->enable_virtual_display, adev->mode_info.num_crtc);
1748 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1750 * @adev: amdgpu_device pointer
1752 * Parses the asic configuration parameters specified in the gpu info
1753 * firmware and makes them availale to the driver for use in configuring
1755 * Returns 0 on success, -EINVAL on failure.
1757 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1759 const char *chip_name;
1762 const struct gpu_info_firmware_header_v1_0 *hdr;
1764 adev->firmware.gpu_info_fw = NULL;
1766 if (adev->mman.discovery_bin) {
1767 amdgpu_discovery_get_gfx_info(adev);
1770 * FIXME: The bounding box is still needed by Navi12, so
1771 * temporarily read it from gpu_info firmware. Should be droped
1772 * when DAL no longer needs it.
1774 if (adev->asic_type != CHIP_NAVI12)
1778 switch (adev->asic_type) {
1779 #ifdef CONFIG_DRM_AMDGPU_SI
1786 #ifdef CONFIG_DRM_AMDGPU_CIK
1796 case CHIP_POLARIS10:
1797 case CHIP_POLARIS11:
1798 case CHIP_POLARIS12:
1803 case CHIP_SIENNA_CICHLID:
1804 case CHIP_NAVY_FLOUNDER:
1805 case CHIP_DIMGREY_CAVEFISH:
1809 chip_name = "vega10";
1812 chip_name = "vega12";
1815 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1816 chip_name = "raven2";
1817 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1818 chip_name = "picasso";
1820 chip_name = "raven";
1823 chip_name = "arcturus";
1826 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1827 chip_name = "renoir";
1829 chip_name = "green_sardine";
1832 chip_name = "navi10";
1835 chip_name = "navi14";
1838 chip_name = "navi12";
1841 chip_name = "vangogh";
1845 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1846 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1849 "Failed to load gpu_info firmware \"%s\"\n",
1853 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1856 "Failed to validate gpu_info firmware \"%s\"\n",
1861 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1862 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1864 switch (hdr->version_major) {
1867 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1868 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1869 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1872 * Should be droped when DAL no longer needs it.
1874 if (adev->asic_type == CHIP_NAVI12)
1875 goto parse_soc_bounding_box;
1877 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1878 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1879 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1880 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1881 adev->gfx.config.max_texture_channel_caches =
1882 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1883 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1884 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1885 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1886 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1887 adev->gfx.config.double_offchip_lds_buf =
1888 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1889 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1890 adev->gfx.cu_info.max_waves_per_simd =
1891 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1892 adev->gfx.cu_info.max_scratch_slots_per_cu =
1893 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1894 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1895 if (hdr->version_minor >= 1) {
1896 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1897 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1898 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1899 adev->gfx.config.num_sc_per_sh =
1900 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1901 adev->gfx.config.num_packer_per_sc =
1902 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1905 parse_soc_bounding_box:
1907 * soc bounding box info is not integrated in disocovery table,
1908 * we always need to parse it from gpu info firmware if needed.
1910 if (hdr->version_minor == 2) {
1911 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1912 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1913 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1914 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1920 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1929 * amdgpu_device_ip_early_init - run early init for hardware IPs
1931 * @adev: amdgpu_device pointer
1933 * Early initialization pass for hardware IPs. The hardware IPs that make
1934 * up each asic are discovered each IP's early_init callback is run. This
1935 * is the first stage in initializing the asic.
1936 * Returns 0 on success, negative error code on failure.
1938 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1942 amdgpu_device_enable_virtual_display(adev);
1944 if (amdgpu_sriov_vf(adev)) {
1945 r = amdgpu_virt_request_full_gpu(adev, true);
1950 switch (adev->asic_type) {
1951 #ifdef CONFIG_DRM_AMDGPU_SI
1957 adev->family = AMDGPU_FAMILY_SI;
1958 r = si_set_ip_blocks(adev);
1963 #ifdef CONFIG_DRM_AMDGPU_CIK
1969 if (adev->flags & AMD_IS_APU)
1970 adev->family = AMDGPU_FAMILY_KV;
1972 adev->family = AMDGPU_FAMILY_CI;
1974 r = cik_set_ip_blocks(adev);
1982 case CHIP_POLARIS10:
1983 case CHIP_POLARIS11:
1984 case CHIP_POLARIS12:
1988 if (adev->flags & AMD_IS_APU)
1989 adev->family = AMDGPU_FAMILY_CZ;
1991 adev->family = AMDGPU_FAMILY_VI;
1993 r = vi_set_ip_blocks(adev);
2003 if (adev->flags & AMD_IS_APU)
2004 adev->family = AMDGPU_FAMILY_RV;
2006 adev->family = AMDGPU_FAMILY_AI;
2008 r = soc15_set_ip_blocks(adev);
2015 case CHIP_SIENNA_CICHLID:
2016 case CHIP_NAVY_FLOUNDER:
2017 case CHIP_DIMGREY_CAVEFISH:
2019 if (adev->asic_type == CHIP_VANGOGH)
2020 adev->family = AMDGPU_FAMILY_VGH;
2022 adev->family = AMDGPU_FAMILY_NV;
2024 r = nv_set_ip_blocks(adev);
2029 /* FIXME: not supported yet */
2033 amdgpu_amdkfd_device_probe(adev);
2035 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2036 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2037 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2039 for (i = 0; i < adev->num_ip_blocks; i++) {
2040 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2041 DRM_ERROR("disabled ip block: %d <%s>\n",
2042 i, adev->ip_blocks[i].version->funcs->name);
2043 adev->ip_blocks[i].status.valid = false;
2045 if (adev->ip_blocks[i].version->funcs->early_init) {
2046 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2048 adev->ip_blocks[i].status.valid = false;
2050 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2051 adev->ip_blocks[i].version->funcs->name, r);
2054 adev->ip_blocks[i].status.valid = true;
2057 adev->ip_blocks[i].status.valid = true;
2060 /* get the vbios after the asic_funcs are set up */
2061 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2062 r = amdgpu_device_parse_gpu_info_fw(adev);
2067 if (!amdgpu_get_bios(adev))
2070 r = amdgpu_atombios_init(adev);
2072 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2073 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2079 adev->cg_flags &= amdgpu_cg_mask;
2080 adev->pg_flags &= amdgpu_pg_mask;
2085 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2089 for (i = 0; i < adev->num_ip_blocks; i++) {
2090 if (!adev->ip_blocks[i].status.sw)
2092 if (adev->ip_blocks[i].status.hw)
2094 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2095 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2096 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2097 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2099 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2100 adev->ip_blocks[i].version->funcs->name, r);
2103 adev->ip_blocks[i].status.hw = true;
2110 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2114 for (i = 0; i < adev->num_ip_blocks; i++) {
2115 if (!adev->ip_blocks[i].status.sw)
2117 if (adev->ip_blocks[i].status.hw)
2119 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2121 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2122 adev->ip_blocks[i].version->funcs->name, r);
2125 adev->ip_blocks[i].status.hw = true;
2131 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2135 uint32_t smu_version;
2137 if (adev->asic_type >= CHIP_VEGA10) {
2138 for (i = 0; i < adev->num_ip_blocks; i++) {
2139 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2142 /* no need to do the fw loading again if already done*/
2143 if (adev->ip_blocks[i].status.hw == true)
2146 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2147 r = adev->ip_blocks[i].version->funcs->resume(adev);
2149 DRM_ERROR("resume of IP block <%s> failed %d\n",
2150 adev->ip_blocks[i].version->funcs->name, r);
2154 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2156 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2157 adev->ip_blocks[i].version->funcs->name, r);
2162 adev->ip_blocks[i].status.hw = true;
2167 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2168 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2174 * amdgpu_device_ip_init - run init for hardware IPs
2176 * @adev: amdgpu_device pointer
2178 * Main initialization pass for hardware IPs. The list of all the hardware
2179 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2180 * are run. sw_init initializes the software state associated with each IP
2181 * and hw_init initializes the hardware associated with each IP.
2182 * Returns 0 on success, negative error code on failure.
2184 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2188 r = amdgpu_ras_init(adev);
2192 for (i = 0; i < adev->num_ip_blocks; i++) {
2193 if (!adev->ip_blocks[i].status.valid)
2195 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2197 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2198 adev->ip_blocks[i].version->funcs->name, r);
2201 adev->ip_blocks[i].status.sw = true;
2203 /* need to do gmc hw init early so we can allocate gpu mem */
2204 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2205 r = amdgpu_device_vram_scratch_init(adev);
2207 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
2210 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2212 DRM_ERROR("hw_init %d failed %d\n", i, r);
2215 r = amdgpu_device_wb_init(adev);
2217 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2220 adev->ip_blocks[i].status.hw = true;
2222 /* right after GMC hw init, we create CSA */
2223 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
2224 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2225 AMDGPU_GEM_DOMAIN_VRAM,
2228 DRM_ERROR("allocate CSA failed %d\n", r);
2235 if (amdgpu_sriov_vf(adev))
2236 amdgpu_virt_init_data_exchange(adev);
2238 r = amdgpu_ib_pool_init(adev);
2240 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2241 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2245 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2249 r = amdgpu_device_ip_hw_init_phase1(adev);
2253 r = amdgpu_device_fw_loading(adev);
2257 r = amdgpu_device_ip_hw_init_phase2(adev);
2262 * retired pages will be loaded from eeprom and reserved here,
2263 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2264 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2265 * for I2C communication which only true at this point.
2267 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2268 * failure from bad gpu situation and stop amdgpu init process
2269 * accordingly. For other failed cases, it will still release all
2270 * the resource and print error message, rather than returning one
2271 * negative value to upper level.
2273 * Note: theoretically, this should be called before all vram allocations
2274 * to protect retired page from abusing
2276 r = amdgpu_ras_recovery_init(adev);
2280 if (adev->gmc.xgmi.num_physical_nodes > 1)
2281 amdgpu_xgmi_add_device(adev);
2282 amdgpu_amdkfd_device_init(adev);
2284 amdgpu_fru_get_product_info(adev);
2287 if (amdgpu_sriov_vf(adev))
2288 amdgpu_virt_release_full_gpu(adev, true);
2294 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2296 * @adev: amdgpu_device pointer
2298 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2299 * this function before a GPU reset. If the value is retained after a
2300 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2302 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2304 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2308 * amdgpu_device_check_vram_lost - check if vram is valid
2310 * @adev: amdgpu_device pointer
2312 * Checks the reset magic value written to the gart pointer in VRAM.
2313 * The driver calls this after a GPU reset to see if the contents of
2314 * VRAM is lost or now.
2315 * returns true if vram is lost, false if not.
2317 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2319 if (memcmp(adev->gart.ptr, adev->reset_magic,
2320 AMDGPU_RESET_MAGIC_NUM))
2323 if (!amdgpu_in_reset(adev))
2327 * For all ASICs with baco/mode1 reset, the VRAM is
2328 * always assumed to be lost.
2330 switch (amdgpu_asic_reset_method(adev)) {
2331 case AMD_RESET_METHOD_BACO:
2332 case AMD_RESET_METHOD_MODE1:
2340 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2342 * @adev: amdgpu_device pointer
2343 * @state: clockgating state (gate or ungate)
2345 * The list of all the hardware IPs that make up the asic is walked and the
2346 * set_clockgating_state callbacks are run.
2347 * Late initialization pass enabling clockgating for hardware IPs.
2348 * Fini or suspend, pass disabling clockgating for hardware IPs.
2349 * Returns 0 on success, negative error code on failure.
2352 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2353 enum amd_clockgating_state state)
2357 if (amdgpu_emu_mode == 1)
2360 for (j = 0; j < adev->num_ip_blocks; j++) {
2361 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2362 if (!adev->ip_blocks[i].status.late_initialized)
2364 /* skip CG for VCE/UVD, it's handled specially */
2365 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2366 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2367 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2368 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2369 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2370 /* enable clockgating to save power */
2371 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2374 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2375 adev->ip_blocks[i].version->funcs->name, r);
2384 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
2388 if (amdgpu_emu_mode == 1)
2391 for (j = 0; j < adev->num_ip_blocks; j++) {
2392 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2393 if (!adev->ip_blocks[i].status.late_initialized)
2395 /* skip CG for VCE/UVD, it's handled specially */
2396 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2397 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2398 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2399 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2400 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2401 /* enable powergating to save power */
2402 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2405 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2406 adev->ip_blocks[i].version->funcs->name, r);
2414 static int amdgpu_device_enable_mgpu_fan_boost(void)
2416 struct amdgpu_gpu_instance *gpu_ins;
2417 struct amdgpu_device *adev;
2420 mutex_lock(&mgpu_info.mutex);
2423 * MGPU fan boost feature should be enabled
2424 * only when there are two or more dGPUs in
2427 if (mgpu_info.num_dgpu < 2)
2430 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2431 gpu_ins = &(mgpu_info.gpu_ins[i]);
2432 adev = gpu_ins->adev;
2433 if (!(adev->flags & AMD_IS_APU) &&
2434 !gpu_ins->mgpu_fan_enabled) {
2435 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2439 gpu_ins->mgpu_fan_enabled = 1;
2444 mutex_unlock(&mgpu_info.mutex);
2450 * amdgpu_device_ip_late_init - run late init for hardware IPs
2452 * @adev: amdgpu_device pointer
2454 * Late initialization pass for hardware IPs. The list of all the hardware
2455 * IPs that make up the asic is walked and the late_init callbacks are run.
2456 * late_init covers any special initialization that an IP requires
2457 * after all of the have been initialized or something that needs to happen
2458 * late in the init process.
2459 * Returns 0 on success, negative error code on failure.
2461 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2463 struct amdgpu_gpu_instance *gpu_instance;
2466 for (i = 0; i < adev->num_ip_blocks; i++) {
2467 if (!adev->ip_blocks[i].status.hw)
2469 if (adev->ip_blocks[i].version->funcs->late_init) {
2470 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2472 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2473 adev->ip_blocks[i].version->funcs->name, r);
2477 adev->ip_blocks[i].status.late_initialized = true;
2480 amdgpu_ras_set_error_query_ready(adev, true);
2482 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2483 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2485 amdgpu_device_fill_reset_magic(adev);
2487 r = amdgpu_device_enable_mgpu_fan_boost();
2489 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2492 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2493 mutex_lock(&mgpu_info.mutex);
2496 * Reset device p-state to low as this was booted with high.
2498 * This should be performed only after all devices from the same
2499 * hive get initialized.
2501 * However, it's unknown how many device in the hive in advance.
2502 * As this is counted one by one during devices initializations.
2504 * So, we wait for all XGMI interlinked devices initialized.
2505 * This may bring some delays as those devices may come from
2506 * different hives. But that should be OK.
2508 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2509 for (i = 0; i < mgpu_info.num_gpu; i++) {
2510 gpu_instance = &(mgpu_info.gpu_ins[i]);
2511 if (gpu_instance->adev->flags & AMD_IS_APU)
2514 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2515 AMDGPU_XGMI_PSTATE_MIN);
2517 DRM_ERROR("pstate setting failed (%d).\n", r);
2523 mutex_unlock(&mgpu_info.mutex);
2530 * amdgpu_device_ip_fini - run fini for hardware IPs
2532 * @adev: amdgpu_device pointer
2534 * Main teardown pass for hardware IPs. The list of all the hardware
2535 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2536 * are run. hw_fini tears down the hardware associated with each IP
2537 * and sw_fini tears down any software state associated with each IP.
2538 * Returns 0 on success, negative error code on failure.
2540 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2544 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2545 amdgpu_virt_release_ras_err_handler_data(adev);
2547 amdgpu_ras_pre_fini(adev);
2549 if (adev->gmc.xgmi.num_physical_nodes > 1)
2550 amdgpu_xgmi_remove_device(adev);
2552 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2553 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2555 amdgpu_amdkfd_device_fini(adev);
2557 /* need to disable SMC first */
2558 for (i = 0; i < adev->num_ip_blocks; i++) {
2559 if (!adev->ip_blocks[i].status.hw)
2561 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2562 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2563 /* XXX handle errors */
2565 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2566 adev->ip_blocks[i].version->funcs->name, r);
2568 adev->ip_blocks[i].status.hw = false;
2573 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2574 if (!adev->ip_blocks[i].status.hw)
2577 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2578 /* XXX handle errors */
2580 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2581 adev->ip_blocks[i].version->funcs->name, r);
2584 adev->ip_blocks[i].status.hw = false;
2588 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2589 if (!adev->ip_blocks[i].status.sw)
2592 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2593 amdgpu_ucode_free_bo(adev);
2594 amdgpu_free_static_csa(&adev->virt.csa_obj);
2595 amdgpu_device_wb_fini(adev);
2596 amdgpu_device_vram_scratch_fini(adev);
2597 amdgpu_ib_pool_fini(adev);
2600 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2601 /* XXX handle errors */
2603 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2604 adev->ip_blocks[i].version->funcs->name, r);
2606 adev->ip_blocks[i].status.sw = false;
2607 adev->ip_blocks[i].status.valid = false;
2610 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2611 if (!adev->ip_blocks[i].status.late_initialized)
2613 if (adev->ip_blocks[i].version->funcs->late_fini)
2614 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2615 adev->ip_blocks[i].status.late_initialized = false;
2618 amdgpu_ras_fini(adev);
2620 if (amdgpu_sriov_vf(adev))
2621 if (amdgpu_virt_release_full_gpu(adev, false))
2622 DRM_ERROR("failed to release exclusive mode on fini\n");
2628 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2630 * @work: work_struct.
2632 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2634 struct amdgpu_device *adev =
2635 container_of(work, struct amdgpu_device, delayed_init_work.work);
2638 r = amdgpu_ib_ring_tests(adev);
2640 DRM_ERROR("ib ring test failed (%d).\n", r);
2643 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2645 struct amdgpu_device *adev =
2646 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2648 mutex_lock(&adev->gfx.gfx_off_mutex);
2649 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2650 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2651 adev->gfx.gfx_off_state = true;
2653 mutex_unlock(&adev->gfx.gfx_off_mutex);
2657 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2659 * @adev: amdgpu_device pointer
2661 * Main suspend function for hardware IPs. The list of all the hardware
2662 * IPs that make up the asic is walked, clockgating is disabled and the
2663 * suspend callbacks are run. suspend puts the hardware and software state
2664 * in each IP into a state suitable for suspend.
2665 * Returns 0 on success, negative error code on failure.
2667 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2671 if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) {
2672 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2673 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2676 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2677 if (!adev->ip_blocks[i].status.valid)
2680 /* displays are handled separately */
2681 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2684 /* XXX handle errors */
2685 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2686 /* XXX handle errors */
2688 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2689 adev->ip_blocks[i].version->funcs->name, r);
2693 adev->ip_blocks[i].status.hw = false;
2700 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2702 * @adev: amdgpu_device pointer
2704 * Main suspend function for hardware IPs. The list of all the hardware
2705 * IPs that make up the asic is walked, clockgating is disabled and the
2706 * suspend callbacks are run. suspend puts the hardware and software state
2707 * in each IP into a state suitable for suspend.
2708 * Returns 0 on success, negative error code on failure.
2710 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2714 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2715 if (!adev->ip_blocks[i].status.valid)
2717 /* displays are handled in phase1 */
2718 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2720 /* PSP lost connection when err_event_athub occurs */
2721 if (amdgpu_ras_intr_triggered() &&
2722 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2723 adev->ip_blocks[i].status.hw = false;
2726 /* XXX handle errors */
2727 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2728 /* XXX handle errors */
2730 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2731 adev->ip_blocks[i].version->funcs->name, r);
2733 adev->ip_blocks[i].status.hw = false;
2734 /* handle putting the SMC in the appropriate state */
2735 if(!amdgpu_sriov_vf(adev)){
2736 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2737 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
2739 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2740 adev->mp1_state, r);
2745 adev->ip_blocks[i].status.hw = false;
2752 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2754 * @adev: amdgpu_device pointer
2756 * Main suspend function for hardware IPs. The list of all the hardware
2757 * IPs that make up the asic is walked, clockgating is disabled and the
2758 * suspend callbacks are run. suspend puts the hardware and software state
2759 * in each IP into a state suitable for suspend.
2760 * Returns 0 on success, negative error code on failure.
2762 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2766 if (amdgpu_sriov_vf(adev))
2767 amdgpu_virt_request_full_gpu(adev, false);
2769 r = amdgpu_device_ip_suspend_phase1(adev);
2772 r = amdgpu_device_ip_suspend_phase2(adev);
2774 if (amdgpu_sriov_vf(adev))
2775 amdgpu_virt_release_full_gpu(adev, false);
2780 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2784 static enum amd_ip_block_type ip_order[] = {
2785 AMD_IP_BLOCK_TYPE_GMC,
2786 AMD_IP_BLOCK_TYPE_COMMON,
2787 AMD_IP_BLOCK_TYPE_PSP,
2788 AMD_IP_BLOCK_TYPE_IH,
2791 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2793 struct amdgpu_ip_block *block;
2795 block = &adev->ip_blocks[i];
2796 block->status.hw = false;
2798 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
2800 if (block->version->type != ip_order[j] ||
2801 !block->status.valid)
2804 r = block->version->funcs->hw_init(adev);
2805 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2808 block->status.hw = true;
2815 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2819 static enum amd_ip_block_type ip_order[] = {
2820 AMD_IP_BLOCK_TYPE_SMC,
2821 AMD_IP_BLOCK_TYPE_DCE,
2822 AMD_IP_BLOCK_TYPE_GFX,
2823 AMD_IP_BLOCK_TYPE_SDMA,
2824 AMD_IP_BLOCK_TYPE_UVD,
2825 AMD_IP_BLOCK_TYPE_VCE,
2826 AMD_IP_BLOCK_TYPE_VCN
2829 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2831 struct amdgpu_ip_block *block;
2833 for (j = 0; j < adev->num_ip_blocks; j++) {
2834 block = &adev->ip_blocks[j];
2836 if (block->version->type != ip_order[i] ||
2837 !block->status.valid ||
2841 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
2842 r = block->version->funcs->resume(adev);
2844 r = block->version->funcs->hw_init(adev);
2846 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2849 block->status.hw = true;
2857 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2859 * @adev: amdgpu_device pointer
2861 * First resume function for hardware IPs. The list of all the hardware
2862 * IPs that make up the asic is walked and the resume callbacks are run for
2863 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2864 * after a suspend and updates the software state as necessary. This
2865 * function is also used for restoring the GPU after a GPU reset.
2866 * Returns 0 on success, negative error code on failure.
2868 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2872 for (i = 0; i < adev->num_ip_blocks; i++) {
2873 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2875 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2876 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2877 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2879 r = adev->ip_blocks[i].version->funcs->resume(adev);
2881 DRM_ERROR("resume of IP block <%s> failed %d\n",
2882 adev->ip_blocks[i].version->funcs->name, r);
2885 adev->ip_blocks[i].status.hw = true;
2893 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2895 * @adev: amdgpu_device pointer
2897 * First resume function for hardware IPs. The list of all the hardware
2898 * IPs that make up the asic is walked and the resume callbacks are run for
2899 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2900 * functional state after a suspend and updates the software state as
2901 * necessary. This function is also used for restoring the GPU after a GPU
2903 * Returns 0 on success, negative error code on failure.
2905 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2909 for (i = 0; i < adev->num_ip_blocks; i++) {
2910 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2912 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2913 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2914 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2915 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2917 r = adev->ip_blocks[i].version->funcs->resume(adev);
2919 DRM_ERROR("resume of IP block <%s> failed %d\n",
2920 adev->ip_blocks[i].version->funcs->name, r);
2923 adev->ip_blocks[i].status.hw = true;
2930 * amdgpu_device_ip_resume - run resume for hardware IPs
2932 * @adev: amdgpu_device pointer
2934 * Main resume function for hardware IPs. The hardware IPs
2935 * are split into two resume functions because they are
2936 * are also used in in recovering from a GPU reset and some additional
2937 * steps need to be take between them. In this case (S3/S4) they are
2939 * Returns 0 on success, negative error code on failure.
2941 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2945 r = amdgpu_device_ip_resume_phase1(adev);
2949 r = amdgpu_device_fw_loading(adev);
2953 r = amdgpu_device_ip_resume_phase2(adev);
2959 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2961 * @adev: amdgpu_device pointer
2963 * Query the VBIOS data tables to determine if the board supports SR-IOV.
2965 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2967 if (amdgpu_sriov_vf(adev)) {
2968 if (adev->is_atom_fw) {
2969 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2970 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2972 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2973 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2976 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2977 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2982 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2984 * @asic_type: AMD asic type
2986 * Check if there is DC (new modesetting infrastructre) support for an asic.
2987 * returns true if DC has support, false if not.
2989 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2991 switch (asic_type) {
2992 #if defined(CONFIG_DRM_AMD_DC)
2993 #if defined(CONFIG_DRM_AMD_DC_SI)
3004 * We have systems in the wild with these ASICs that require
3005 * LVDS and VGA support which is not supported with DC.
3007 * Fallback to the non-DC driver here by default so as not to
3008 * cause regressions.
3010 return amdgpu_dc > 0;
3014 case CHIP_POLARIS10:
3015 case CHIP_POLARIS11:
3016 case CHIP_POLARIS12:
3023 #if defined(CONFIG_DRM_AMD_DC_DCN)
3029 case CHIP_SIENNA_CICHLID:
3030 case CHIP_NAVY_FLOUNDER:
3031 case CHIP_DIMGREY_CAVEFISH:
3034 return amdgpu_dc != 0;
3038 DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
3039 "but isn't supported by ASIC, ignoring\n");
3045 * amdgpu_device_has_dc_support - check if dc is supported
3047 * @adev: amdgpu_device pointer
3049 * Returns true for supported, false for not supported
3051 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3053 if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display)
3056 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3060 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3062 struct amdgpu_device *adev =
3063 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3064 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3066 /* It's a bug to not have a hive within this function */
3071 * Use task barrier to synchronize all xgmi reset works across the
3072 * hive. task_barrier_enter and task_barrier_exit will block
3073 * until all the threads running the xgmi reset works reach
3074 * those points. task_barrier_full will do both blocks.
3076 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3078 task_barrier_enter(&hive->tb);
3079 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3081 if (adev->asic_reset_res)
3084 task_barrier_exit(&hive->tb);
3085 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3087 if (adev->asic_reset_res)
3090 if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
3091 adev->mmhub.funcs->reset_ras_error_count(adev);
3094 task_barrier_full(&hive->tb);
3095 adev->asic_reset_res = amdgpu_asic_reset(adev);
3099 if (adev->asic_reset_res)
3100 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3101 adev->asic_reset_res, adev_to_drm(adev)->unique);
3102 amdgpu_put_xgmi_hive(hive);
3105 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3107 char *input = amdgpu_lockup_timeout;
3108 char *timeout_setting = NULL;
3114 * By default timeout for non compute jobs is 10000.
3115 * And there is no timeout enforced on compute jobs.
3116 * In SR-IOV or passthrough mode, timeout for compute
3117 * jobs are 60000 by default.
3119 adev->gfx_timeout = msecs_to_jiffies(10000);
3120 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3121 if (amdgpu_sriov_vf(adev))
3122 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3123 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3124 else if (amdgpu_passthrough(adev))
3125 adev->compute_timeout = msecs_to_jiffies(60000);
3127 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
3129 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3130 while ((timeout_setting = strsep(&input, ",")) &&
3131 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3132 ret = kstrtol(timeout_setting, 0, &timeout);
3139 } else if (timeout < 0) {
3140 timeout = MAX_SCHEDULE_TIMEOUT;
3142 timeout = msecs_to_jiffies(timeout);
3147 adev->gfx_timeout = timeout;
3150 adev->compute_timeout = timeout;
3153 adev->sdma_timeout = timeout;
3156 adev->video_timeout = timeout;
3163 * There is only one value specified and
3164 * it should apply to all non-compute jobs.
3167 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3168 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3169 adev->compute_timeout = adev->gfx_timeout;
3176 static const struct attribute *amdgpu_dev_attributes[] = {
3177 &dev_attr_product_name.attr,
3178 &dev_attr_product_number.attr,
3179 &dev_attr_serial_number.attr,
3180 &dev_attr_pcie_replay_count.attr,
3186 * amdgpu_device_init - initialize the driver
3188 * @adev: amdgpu_device pointer
3189 * @flags: driver flags
3191 * Initializes the driver info and hw (all asics).
3192 * Returns 0 for success or an error on failure.
3193 * Called at driver startup.
3195 int amdgpu_device_init(struct amdgpu_device *adev,
3198 struct drm_device *ddev = adev_to_drm(adev);
3199 struct pci_dev *pdev = adev->pdev;
3204 adev->shutdown = false;
3205 adev->flags = flags;
3207 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3208 adev->asic_type = amdgpu_force_asic_type;
3210 adev->asic_type = flags & AMD_ASIC_MASK;
3212 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3213 if (amdgpu_emu_mode == 1)
3214 adev->usec_timeout *= 10;
3215 adev->gmc.gart_size = 512 * 1024 * 1024;
3216 adev->accel_working = false;
3217 adev->num_rings = 0;
3218 adev->mman.buffer_funcs = NULL;
3219 adev->mman.buffer_funcs_ring = NULL;
3220 adev->vm_manager.vm_pte_funcs = NULL;
3221 adev->vm_manager.vm_pte_num_scheds = 0;
3222 adev->gmc.gmc_funcs = NULL;
3223 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3224 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3226 adev->smc_rreg = &amdgpu_invalid_rreg;
3227 adev->smc_wreg = &amdgpu_invalid_wreg;
3228 adev->pcie_rreg = &amdgpu_invalid_rreg;
3229 adev->pcie_wreg = &amdgpu_invalid_wreg;
3230 adev->pciep_rreg = &amdgpu_invalid_rreg;
3231 adev->pciep_wreg = &amdgpu_invalid_wreg;
3232 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3233 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3234 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3235 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3236 adev->didt_rreg = &amdgpu_invalid_rreg;
3237 adev->didt_wreg = &amdgpu_invalid_wreg;
3238 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3239 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3240 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3241 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3243 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3244 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3245 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3247 /* mutex initialization are all done here so we
3248 * can recall function without having locking issues */
3249 atomic_set(&adev->irq.ih.lock, 0);
3250 mutex_init(&adev->firmware.mutex);
3251 mutex_init(&adev->pm.mutex);
3252 mutex_init(&adev->gfx.gpu_clock_mutex);
3253 mutex_init(&adev->srbm_mutex);
3254 mutex_init(&adev->gfx.pipe_reserve_mutex);
3255 mutex_init(&adev->gfx.gfx_off_mutex);
3256 mutex_init(&adev->grbm_idx_mutex);
3257 mutex_init(&adev->mn_lock);
3258 mutex_init(&adev->virt.vf_errors.lock);
3259 hash_init(adev->mn_hash);
3260 atomic_set(&adev->in_gpu_reset, 0);
3261 init_rwsem(&adev->reset_sem);
3262 mutex_init(&adev->psp.mutex);
3263 mutex_init(&adev->notifier_lock);
3265 r = amdgpu_device_check_arguments(adev);
3269 spin_lock_init(&adev->mmio_idx_lock);
3270 spin_lock_init(&adev->smc_idx_lock);
3271 spin_lock_init(&adev->pcie_idx_lock);
3272 spin_lock_init(&adev->uvd_ctx_idx_lock);
3273 spin_lock_init(&adev->didt_idx_lock);
3274 spin_lock_init(&adev->gc_cac_idx_lock);
3275 spin_lock_init(&adev->se_cac_idx_lock);
3276 spin_lock_init(&adev->audio_endpt_idx_lock);
3277 spin_lock_init(&adev->mm_stats.lock);
3279 INIT_LIST_HEAD(&adev->shadow_list);
3280 mutex_init(&adev->shadow_list_lock);
3282 INIT_DELAYED_WORK(&adev->delayed_init_work,
3283 amdgpu_device_delayed_init_work_handler);
3284 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3285 amdgpu_device_delay_enable_gfx_off);
3287 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3289 adev->gfx.gfx_off_req_count = 1;
3290 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3292 atomic_set(&adev->throttling_logging_enabled, 1);
3294 * If throttling continues, logging will be performed every minute
3295 * to avoid log flooding. "-1" is subtracted since the thermal
3296 * throttling interrupt comes every second. Thus, the total logging
3297 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3298 * for throttling interrupt) = 60 seconds.
3300 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3301 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3303 /* Registers mapping */
3304 /* TODO: block userspace mapping of io register */
3305 if (adev->asic_type >= CHIP_BONAIRE) {
3306 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3307 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3309 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3310 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3313 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3314 if (adev->rmmio == NULL) {
3317 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3318 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3320 /* io port mapping */
3321 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3322 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
3323 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
3324 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
3328 if (adev->rio_mem == NULL)
3329 DRM_INFO("PCI I/O BAR is not found.\n");
3331 /* enable PCIE atomic ops */
3332 r = pci_enable_atomic_ops_to_root(adev->pdev,
3333 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3334 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3336 adev->have_atomics_support = false;
3337 DRM_INFO("PCIE atomic ops is not supported\n");
3339 adev->have_atomics_support = true;
3342 amdgpu_device_get_pcie_info(adev);
3345 DRM_INFO("MCBP is enabled\n");
3347 if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
3348 adev->enable_mes = true;
3350 /* detect hw virtualization here */
3351 amdgpu_detect_virtualization(adev);
3353 r = amdgpu_device_get_job_timeout_settings(adev);
3355 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3359 /* early init functions */
3360 r = amdgpu_device_ip_early_init(adev);
3364 /* doorbell bar mapping and doorbell index init*/
3365 amdgpu_device_doorbell_init(adev);
3367 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3368 /* this will fail for cards that aren't VGA class devices, just
3370 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3371 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
3373 if (amdgpu_device_supports_atpx(ddev))
3375 if (amdgpu_has_atpx() &&
3376 (amdgpu_is_atpx_hybrid() ||
3377 amdgpu_has_atpx_dgpu_power_cntl()) &&
3378 !pci_is_thunderbolt_attached(adev->pdev))
3379 vga_switcheroo_register_client(adev->pdev,
3380 &amdgpu_switcheroo_ops, atpx);
3382 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3384 if (amdgpu_emu_mode == 1) {
3385 /* post the asic on emulation mode */
3386 emu_soc_asic_init(adev);
3387 goto fence_driver_init;
3390 /* detect if we are with an SRIOV vbios */
3391 amdgpu_device_detect_sriov_bios(adev);
3393 /* check if we need to reset the asic
3394 * E.g., driver was not cleanly unloaded previously, etc.
3396 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3397 r = amdgpu_asic_reset(adev);
3399 dev_err(adev->dev, "asic reset on init failed\n");
3404 pci_enable_pcie_error_reporting(adev->pdev);
3406 /* Post card if necessary */
3407 if (amdgpu_device_need_post(adev)) {
3409 dev_err(adev->dev, "no vBIOS found\n");
3413 DRM_INFO("GPU posting now...\n");
3414 r = amdgpu_device_asic_init(adev);
3416 dev_err(adev->dev, "gpu post error!\n");
3421 if (adev->is_atom_fw) {
3422 /* Initialize clocks */
3423 r = amdgpu_atomfirmware_get_clock_info(adev);
3425 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3426 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3430 /* Initialize clocks */
3431 r = amdgpu_atombios_get_clock_info(adev);
3433 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3434 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3437 /* init i2c buses */
3438 if (!amdgpu_device_has_dc_support(adev))
3439 amdgpu_atombios_i2c_init(adev);
3444 r = amdgpu_fence_driver_init(adev);
3446 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
3447 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3451 /* init the mode config */
3452 drm_mode_config_init(adev_to_drm(adev));
3454 r = amdgpu_device_ip_init(adev);
3456 /* failed in exclusive mode due to timeout */
3457 if (amdgpu_sriov_vf(adev) &&
3458 !amdgpu_sriov_runtime(adev) &&
3459 amdgpu_virt_mmio_blocked(adev) &&
3460 !amdgpu_virt_wait_reset(adev)) {
3461 dev_err(adev->dev, "VF exclusive mode timeout\n");
3462 /* Don't send request since VF is inactive. */
3463 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3464 adev->virt.ops = NULL;
3468 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3469 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3474 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3475 adev->gfx.config.max_shader_engines,
3476 adev->gfx.config.max_sh_per_se,
3477 adev->gfx.config.max_cu_per_sh,
3478 adev->gfx.cu_info.number);
3480 adev->accel_working = true;
3482 amdgpu_vm_check_compute_bug(adev);
3484 /* Initialize the buffer migration limit. */
3485 if (amdgpu_moverate >= 0)
3486 max_MBps = amdgpu_moverate;
3488 max_MBps = 8; /* Allow 8 MB/s. */
3489 /* Get a log2 for easy divisions. */
3490 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3492 amdgpu_fbdev_init(adev);
3494 r = amdgpu_pm_sysfs_init(adev);
3496 adev->pm_sysfs_en = false;
3497 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3499 adev->pm_sysfs_en = true;
3501 r = amdgpu_ucode_sysfs_init(adev);
3503 adev->ucode_sysfs_en = false;
3504 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3506 adev->ucode_sysfs_en = true;
3508 if ((amdgpu_testing & 1)) {
3509 if (adev->accel_working)
3510 amdgpu_test_moves(adev);
3512 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
3514 if (amdgpu_benchmarking) {
3515 if (adev->accel_working)
3516 amdgpu_benchmark(adev, amdgpu_benchmarking);
3518 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
3522 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3523 * Otherwise the mgpu fan boost feature will be skipped due to the
3524 * gpu instance is counted less.
3526 amdgpu_register_gpu_instance(adev);
3528 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3529 * explicit gating rather than handling it automatically.
3531 r = amdgpu_device_ip_late_init(adev);
3533 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3534 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3539 amdgpu_ras_resume(adev);
3541 queue_delayed_work(system_wq, &adev->delayed_init_work,
3542 msecs_to_jiffies(AMDGPU_RESUME_MS));
3544 if (amdgpu_sriov_vf(adev))
3545 flush_delayed_work(&adev->delayed_init_work);
3547 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3549 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3551 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3552 r = amdgpu_pmu_init(adev);
3554 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3556 /* Have stored pci confspace at hand for restore in sudden PCI error */
3557 if (amdgpu_device_cache_pci_state(adev->pdev))
3558 pci_restore_state(pdev);
3563 amdgpu_vf_error_trans_all(adev);
3565 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3568 iounmap(adev->rmmio);
3575 * amdgpu_device_fini - tear down the driver
3577 * @adev: amdgpu_device pointer
3579 * Tear down the driver info (all asics).
3580 * Called at driver shutdown.
3582 void amdgpu_device_fini(struct amdgpu_device *adev)
3584 dev_info(adev->dev, "amdgpu: finishing device.\n");
3585 flush_delayed_work(&adev->delayed_init_work);
3586 adev->shutdown = true;
3588 kfree(adev->pci_state);
3590 /* make sure IB test finished before entering exclusive mode
3591 * to avoid preemption on IB test
3593 if (amdgpu_sriov_vf(adev)) {
3594 amdgpu_virt_request_full_gpu(adev, false);
3595 amdgpu_virt_fini_data_exchange(adev);
3598 /* disable all interrupts */
3599 amdgpu_irq_disable_all(adev);
3600 if (adev->mode_info.mode_config_initialized){
3601 if (!amdgpu_device_has_dc_support(adev))
3602 drm_helper_force_disable_all(adev_to_drm(adev));
3604 drm_atomic_helper_shutdown(adev_to_drm(adev));
3606 amdgpu_fence_driver_fini(adev);
3607 if (adev->pm_sysfs_en)
3608 amdgpu_pm_sysfs_fini(adev);
3609 amdgpu_fbdev_fini(adev);
3610 amdgpu_device_ip_fini(adev);
3611 release_firmware(adev->firmware.gpu_info_fw);
3612 adev->firmware.gpu_info_fw = NULL;
3613 adev->accel_working = false;
3614 /* free i2c buses */
3615 if (!amdgpu_device_has_dc_support(adev))
3616 amdgpu_i2c_fini(adev);
3618 if (amdgpu_emu_mode != 1)
3619 amdgpu_atombios_fini(adev);
3623 if (amdgpu_has_atpx() &&
3624 (amdgpu_is_atpx_hybrid() ||
3625 amdgpu_has_atpx_dgpu_power_cntl()) &&
3626 !pci_is_thunderbolt_attached(adev->pdev))
3627 vga_switcheroo_unregister_client(adev->pdev);
3628 if (amdgpu_device_supports_atpx(adev_to_drm(adev)))
3629 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3630 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3631 vga_client_register(adev->pdev, NULL, NULL, NULL);
3633 pci_iounmap(adev->pdev, adev->rio_mem);
3634 adev->rio_mem = NULL;
3635 iounmap(adev->rmmio);
3637 amdgpu_device_doorbell_fini(adev);
3639 if (adev->ucode_sysfs_en)
3640 amdgpu_ucode_sysfs_fini(adev);
3642 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
3643 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3644 amdgpu_pmu_fini(adev);
3645 if (adev->mman.discovery_bin)
3646 amdgpu_discovery_fini(adev);
3654 * amdgpu_device_suspend - initiate device suspend
3656 * @dev: drm dev pointer
3657 * @fbcon : notify the fbdev of suspend
3659 * Puts the hw in the suspend state (all asics).
3660 * Returns 0 for success or an error on failure.
3661 * Called at driver suspend.
3663 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
3665 struct amdgpu_device *adev;
3666 struct drm_crtc *crtc;
3667 struct drm_connector *connector;
3668 struct drm_connector_list_iter iter;
3671 adev = drm_to_adev(dev);
3673 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3676 adev->in_suspend = true;
3677 drm_kms_helper_poll_disable(dev);
3680 amdgpu_fbdev_set_suspend(adev, 1);
3682 cancel_delayed_work_sync(&adev->delayed_init_work);
3684 if (!amdgpu_device_has_dc_support(adev)) {
3685 /* turn off display hw */
3686 drm_modeset_lock_all(dev);
3687 drm_connector_list_iter_begin(dev, &iter);
3688 drm_for_each_connector_iter(connector, &iter)
3689 drm_helper_connector_dpms(connector,
3691 drm_connector_list_iter_end(&iter);
3692 drm_modeset_unlock_all(dev);
3693 /* unpin the front buffers and cursors */
3694 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3695 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3696 struct drm_framebuffer *fb = crtc->primary->fb;
3697 struct amdgpu_bo *robj;
3699 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3700 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3701 r = amdgpu_bo_reserve(aobj, true);
3703 amdgpu_bo_unpin(aobj);
3704 amdgpu_bo_unreserve(aobj);
3708 if (fb == NULL || fb->obj[0] == NULL) {
3711 robj = gem_to_amdgpu_bo(fb->obj[0]);
3712 /* don't unpin kernel fb objects */
3713 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
3714 r = amdgpu_bo_reserve(robj, true);
3716 amdgpu_bo_unpin(robj);
3717 amdgpu_bo_unreserve(robj);
3723 amdgpu_ras_suspend(adev);
3725 r = amdgpu_device_ip_suspend_phase1(adev);
3727 amdgpu_amdkfd_suspend(adev, !fbcon);
3729 /* evict vram memory */
3730 amdgpu_bo_evict_vram(adev);
3732 amdgpu_fence_driver_suspend(adev);
3734 if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev))
3735 r = amdgpu_device_ip_suspend_phase2(adev);
3737 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
3738 /* evict remaining vram memory
3739 * This second call to evict vram is to evict the gart page table
3742 amdgpu_bo_evict_vram(adev);
3748 * amdgpu_device_resume - initiate device resume
3750 * @dev: drm dev pointer
3751 * @fbcon : notify the fbdev of resume
3753 * Bring the hw back to operating state (all asics).
3754 * Returns 0 for success or an error on failure.
3755 * Called at driver resume.
3757 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
3759 struct drm_connector *connector;
3760 struct drm_connector_list_iter iter;
3761 struct amdgpu_device *adev = drm_to_adev(dev);
3762 struct drm_crtc *crtc;
3765 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3768 if (amdgpu_acpi_is_s0ix_supported(adev))
3769 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
3772 if (amdgpu_device_need_post(adev)) {
3773 r = amdgpu_device_asic_init(adev);
3775 dev_err(adev->dev, "amdgpu asic init failed\n");
3778 r = amdgpu_device_ip_resume(adev);
3780 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
3783 amdgpu_fence_driver_resume(adev);
3786 r = amdgpu_device_ip_late_init(adev);
3790 queue_delayed_work(system_wq, &adev->delayed_init_work,
3791 msecs_to_jiffies(AMDGPU_RESUME_MS));
3793 if (!amdgpu_device_has_dc_support(adev)) {
3795 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3796 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3798 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3799 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3800 r = amdgpu_bo_reserve(aobj, true);
3802 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3804 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
3805 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3806 amdgpu_bo_unreserve(aobj);
3811 r = amdgpu_amdkfd_resume(adev, !fbcon);
3815 /* Make sure IB tests flushed */
3816 flush_delayed_work(&adev->delayed_init_work);
3818 /* blat the mode back in */
3820 if (!amdgpu_device_has_dc_support(adev)) {
3822 drm_helper_resume_force_mode(dev);
3824 /* turn on display hw */
3825 drm_modeset_lock_all(dev);
3827 drm_connector_list_iter_begin(dev, &iter);
3828 drm_for_each_connector_iter(connector, &iter)
3829 drm_helper_connector_dpms(connector,
3831 drm_connector_list_iter_end(&iter);
3833 drm_modeset_unlock_all(dev);
3835 amdgpu_fbdev_set_suspend(adev, 0);
3838 drm_kms_helper_poll_enable(dev);
3840 amdgpu_ras_resume(adev);
3843 * Most of the connector probing functions try to acquire runtime pm
3844 * refs to ensure that the GPU is powered on when connector polling is
3845 * performed. Since we're calling this from a runtime PM callback,
3846 * trying to acquire rpm refs will cause us to deadlock.
3848 * Since we're guaranteed to be holding the rpm lock, it's safe to
3849 * temporarily disable the rpm helpers so this doesn't deadlock us.
3852 dev->dev->power.disable_depth++;
3854 if (!amdgpu_device_has_dc_support(adev))
3855 drm_helper_hpd_irq_event(dev);
3857 drm_kms_helper_hotplug_event(dev);
3859 dev->dev->power.disable_depth--;
3861 adev->in_suspend = false;
3867 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3869 * @adev: amdgpu_device pointer
3871 * The list of all the hardware IPs that make up the asic is walked and
3872 * the check_soft_reset callbacks are run. check_soft_reset determines
3873 * if the asic is still hung or not.
3874 * Returns true if any of the IPs are still in a hung state, false if not.
3876 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3879 bool asic_hang = false;
3881 if (amdgpu_sriov_vf(adev))
3884 if (amdgpu_asic_need_full_reset(adev))
3887 for (i = 0; i < adev->num_ip_blocks; i++) {
3888 if (!adev->ip_blocks[i].status.valid)
3890 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3891 adev->ip_blocks[i].status.hang =
3892 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3893 if (adev->ip_blocks[i].status.hang) {
3894 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3902 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3904 * @adev: amdgpu_device pointer
3906 * The list of all the hardware IPs that make up the asic is walked and the
3907 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3908 * handles any IP specific hardware or software state changes that are
3909 * necessary for a soft reset to succeed.
3910 * Returns 0 on success, negative error code on failure.
3912 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3916 for (i = 0; i < adev->num_ip_blocks; i++) {
3917 if (!adev->ip_blocks[i].status.valid)
3919 if (adev->ip_blocks[i].status.hang &&
3920 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3921 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3931 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3933 * @adev: amdgpu_device pointer
3935 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
3936 * reset is necessary to recover.
3937 * Returns true if a full asic reset is required, false if not.
3939 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3943 if (amdgpu_asic_need_full_reset(adev))
3946 for (i = 0; i < adev->num_ip_blocks; i++) {
3947 if (!adev->ip_blocks[i].status.valid)
3949 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3950 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3951 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3952 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3953 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3954 if (adev->ip_blocks[i].status.hang) {
3955 dev_info(adev->dev, "Some block need full reset!\n");
3964 * amdgpu_device_ip_soft_reset - do a soft reset
3966 * @adev: amdgpu_device pointer
3968 * The list of all the hardware IPs that make up the asic is walked and the
3969 * soft_reset callbacks are run if the block is hung. soft_reset handles any
3970 * IP specific hardware or software state changes that are necessary to soft
3972 * Returns 0 on success, negative error code on failure.
3974 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3978 for (i = 0; i < adev->num_ip_blocks; i++) {
3979 if (!adev->ip_blocks[i].status.valid)
3981 if (adev->ip_blocks[i].status.hang &&
3982 adev->ip_blocks[i].version->funcs->soft_reset) {
3983 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3993 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3995 * @adev: amdgpu_device pointer
3997 * The list of all the hardware IPs that make up the asic is walked and the
3998 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
3999 * handles any IP specific hardware or software state changes that are
4000 * necessary after the IP has been soft reset.
4001 * Returns 0 on success, negative error code on failure.
4003 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4007 for (i = 0; i < adev->num_ip_blocks; i++) {
4008 if (!adev->ip_blocks[i].status.valid)
4010 if (adev->ip_blocks[i].status.hang &&
4011 adev->ip_blocks[i].version->funcs->post_soft_reset)
4012 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4021 * amdgpu_device_recover_vram - Recover some VRAM contents
4023 * @adev: amdgpu_device pointer
4025 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4026 * restore things like GPUVM page tables after a GPU reset where
4027 * the contents of VRAM might be lost.
4030 * 0 on success, negative error code on failure.
4032 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4034 struct dma_fence *fence = NULL, *next = NULL;
4035 struct amdgpu_bo *shadow;
4038 if (amdgpu_sriov_runtime(adev))
4039 tmo = msecs_to_jiffies(8000);
4041 tmo = msecs_to_jiffies(100);
4043 dev_info(adev->dev, "recover vram bo from shadow start\n");
4044 mutex_lock(&adev->shadow_list_lock);
4045 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
4047 /* No need to recover an evicted BO */
4048 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
4049 shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
4050 shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
4053 r = amdgpu_bo_restore_shadow(shadow, &next);
4058 tmo = dma_fence_wait_timeout(fence, false, tmo);
4059 dma_fence_put(fence);
4064 } else if (tmo < 0) {
4072 mutex_unlock(&adev->shadow_list_lock);
4075 tmo = dma_fence_wait_timeout(fence, false, tmo);
4076 dma_fence_put(fence);
4078 if (r < 0 || tmo <= 0) {
4079 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4083 dev_info(adev->dev, "recover vram bo from shadow done\n");
4089 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4091 * @adev: amdgpu_device pointer
4092 * @from_hypervisor: request from hypervisor
4094 * do VF FLR and reinitialize Asic
4095 * return 0 means succeeded otherwise failed
4097 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4098 bool from_hypervisor)
4102 if (from_hypervisor)
4103 r = amdgpu_virt_request_full_gpu(adev, true);
4105 r = amdgpu_virt_reset_gpu(adev);
4109 amdgpu_amdkfd_pre_reset(adev);
4111 /* Resume IP prior to SMC */
4112 r = amdgpu_device_ip_reinit_early_sriov(adev);
4116 amdgpu_virt_init_data_exchange(adev);
4117 /* we need recover gart prior to run SMC/CP/SDMA resume */
4118 amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
4120 r = amdgpu_device_fw_loading(adev);
4124 /* now we are okay to resume SMC/CP/SDMA */
4125 r = amdgpu_device_ip_reinit_late_sriov(adev);
4129 amdgpu_irq_gpu_reset_resume_helper(adev);
4130 r = amdgpu_ib_ring_tests(adev);
4131 amdgpu_amdkfd_post_reset(adev);
4134 amdgpu_virt_release_full_gpu(adev, true);
4135 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4136 amdgpu_inc_vram_lost(adev);
4137 r = amdgpu_device_recover_vram(adev);
4144 * amdgpu_device_has_job_running - check if there is any job in mirror list
4146 * @adev: amdgpu_device pointer
4148 * check if there is any job in mirror list
4150 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4153 struct drm_sched_job *job;
4155 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4156 struct amdgpu_ring *ring = adev->rings[i];
4158 if (!ring || !ring->sched.thread)
4161 spin_lock(&ring->sched.job_list_lock);
4162 job = list_first_entry_or_null(&ring->sched.pending_list,
4163 struct drm_sched_job, list);
4164 spin_unlock(&ring->sched.job_list_lock);
4172 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4174 * @adev: amdgpu_device pointer
4176 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4179 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4181 if (!amdgpu_device_ip_check_soft_reset(adev)) {
4182 dev_info(adev->dev, "Timeout, but no hardware hang detected.\n");
4186 if (amdgpu_gpu_recovery == 0)
4189 if (amdgpu_sriov_vf(adev))
4192 if (amdgpu_gpu_recovery == -1) {
4193 switch (adev->asic_type) {
4199 case CHIP_POLARIS10:
4200 case CHIP_POLARIS11:
4201 case CHIP_POLARIS12:
4212 case CHIP_SIENNA_CICHLID:
4213 case CHIP_NAVY_FLOUNDER:
4224 dev_info(adev->dev, "GPU recovery disabled.\n");
4229 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4230 struct amdgpu_job *job,
4231 bool *need_full_reset_arg)
4234 bool need_full_reset = *need_full_reset_arg;
4236 amdgpu_debugfs_wait_dump(adev);
4238 if (amdgpu_sriov_vf(adev)) {
4239 /* stop the data exchange thread */
4240 amdgpu_virt_fini_data_exchange(adev);
4243 /* block all schedulers and reset given job's ring */
4244 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4245 struct amdgpu_ring *ring = adev->rings[i];
4247 if (!ring || !ring->sched.thread)
4250 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4251 amdgpu_fence_driver_force_completion(ring);
4255 drm_sched_increase_karma(&job->base);
4257 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4258 if (!amdgpu_sriov_vf(adev)) {
4260 if (!need_full_reset)
4261 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4263 if (!need_full_reset) {
4264 amdgpu_device_ip_pre_soft_reset(adev);
4265 r = amdgpu_device_ip_soft_reset(adev);
4266 amdgpu_device_ip_post_soft_reset(adev);
4267 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4268 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4269 need_full_reset = true;
4273 if (need_full_reset)
4274 r = amdgpu_device_ip_suspend(adev);
4276 *need_full_reset_arg = need_full_reset;
4282 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
4283 struct list_head *device_list_handle,
4284 bool *need_full_reset_arg,
4287 struct amdgpu_device *tmp_adev = NULL;
4288 bool need_full_reset = *need_full_reset_arg, vram_lost = false;
4292 * ASIC reset has to be done on all HGMI hive nodes ASAP
4293 * to allow proper links negotiation in FW (within 1 sec)
4295 if (!skip_hw_reset && need_full_reset) {
4296 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4297 /* For XGMI run all resets in parallel to speed up the process */
4298 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4299 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4302 r = amdgpu_asic_reset(tmp_adev);
4305 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4306 r, adev_to_drm(tmp_adev)->unique);
4311 /* For XGMI wait for all resets to complete before proceed */
4313 list_for_each_entry(tmp_adev, device_list_handle,
4315 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4316 flush_work(&tmp_adev->xgmi_reset_work);
4317 r = tmp_adev->asic_reset_res;
4325 if (!r && amdgpu_ras_intr_triggered()) {
4326 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4327 if (tmp_adev->mmhub.funcs &&
4328 tmp_adev->mmhub.funcs->reset_ras_error_count)
4329 tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev);
4332 amdgpu_ras_intr_cleared();
4335 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4336 if (need_full_reset) {
4338 if (amdgpu_device_asic_init(tmp_adev))
4339 dev_warn(tmp_adev->dev, "asic atom init failed!");
4342 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4343 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4347 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4349 DRM_INFO("VRAM is lost due to GPU reset!\n");
4350 amdgpu_inc_vram_lost(tmp_adev);
4353 r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT));
4357 r = amdgpu_device_fw_loading(tmp_adev);
4361 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4366 amdgpu_device_fill_reset_magic(tmp_adev);
4369 * Add this ASIC as tracked as reset was already
4370 * complete successfully.
4372 amdgpu_register_gpu_instance(tmp_adev);
4374 r = amdgpu_device_ip_late_init(tmp_adev);
4378 amdgpu_fbdev_set_suspend(tmp_adev, 0);
4381 * The GPU enters bad state once faulty pages
4382 * by ECC has reached the threshold, and ras
4383 * recovery is scheduled next. So add one check
4384 * here to break recovery if it indeed exceeds
4385 * bad page threshold, and remind user to
4386 * retire this GPU or setting one bigger
4387 * bad_page_threshold value to fix this once
4388 * probing driver again.
4390 if (!amdgpu_ras_check_err_threshold(tmp_adev)) {
4392 amdgpu_ras_resume(tmp_adev);
4398 /* Update PSP FW topology after reset */
4399 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4400 r = amdgpu_xgmi_update_topology(hive, tmp_adev);
4406 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
4407 r = amdgpu_ib_ring_tests(tmp_adev);
4409 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
4410 r = amdgpu_device_ip_suspend(tmp_adev);
4411 need_full_reset = true;
4418 r = amdgpu_device_recover_vram(tmp_adev);
4420 tmp_adev->asic_reset_res = r;
4424 *need_full_reset_arg = need_full_reset;
4428 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev,
4429 struct amdgpu_hive_info *hive)
4431 if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)
4435 down_write_nest_lock(&adev->reset_sem, &hive->hive_lock);
4437 down_write(&adev->reset_sem);
4440 atomic_inc(&adev->gpu_reset_counter);
4441 switch (amdgpu_asic_reset_method(adev)) {
4442 case AMD_RESET_METHOD_MODE1:
4443 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
4445 case AMD_RESET_METHOD_MODE2:
4446 adev->mp1_state = PP_MP1_STATE_RESET;
4449 adev->mp1_state = PP_MP1_STATE_NONE;
4456 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
4458 amdgpu_vf_error_trans_all(adev);
4459 adev->mp1_state = PP_MP1_STATE_NONE;
4460 atomic_set(&adev->in_gpu_reset, 0);
4461 up_write(&adev->reset_sem);
4464 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
4466 struct pci_dev *p = NULL;
4468 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4469 adev->pdev->bus->number, 1);
4471 pm_runtime_enable(&(p->dev));
4472 pm_runtime_resume(&(p->dev));
4476 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
4478 enum amd_reset_method reset_method;
4479 struct pci_dev *p = NULL;
4483 * For now, only BACO and mode1 reset are confirmed
4484 * to suffer the audio issue without proper suspended.
4486 reset_method = amdgpu_asic_reset_method(adev);
4487 if ((reset_method != AMD_RESET_METHOD_BACO) &&
4488 (reset_method != AMD_RESET_METHOD_MODE1))
4491 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4492 adev->pdev->bus->number, 1);
4496 expires = pm_runtime_autosuspend_expiration(&(p->dev));
4499 * If we cannot get the audio device autosuspend delay,
4500 * a fixed 4S interval will be used. Considering 3S is
4501 * the audio controller default autosuspend delay setting.
4502 * 4S used here is guaranteed to cover that.
4504 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
4506 while (!pm_runtime_status_suspended(&(p->dev))) {
4507 if (!pm_runtime_suspend(&(p->dev)))
4510 if (expires < ktime_get_mono_fast_ns()) {
4511 dev_warn(adev->dev, "failed to suspend display audio\n");
4512 /* TODO: abort the succeeding gpu reset? */
4517 pm_runtime_disable(&(p->dev));
4523 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
4525 * @adev: amdgpu_device pointer
4526 * @job: which job trigger hang
4528 * Attempt to reset the GPU if it has hung (all asics).
4529 * Attempt to do soft-reset or full-reset and reinitialize Asic
4530 * Returns 0 for success or an error on failure.
4533 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
4534 struct amdgpu_job *job)
4536 struct list_head device_list, *device_list_handle = NULL;
4537 bool need_full_reset = false;
4538 bool job_signaled = false;
4539 struct amdgpu_hive_info *hive = NULL;
4540 struct amdgpu_device *tmp_adev = NULL;
4542 bool need_emergency_restart = false;
4543 bool audio_suspended = false;
4546 * Special case: RAS triggered and full reset isn't supported
4548 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
4551 * Flush RAM to disk so that after reboot
4552 * the user can read log and see why the system rebooted.
4554 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
4555 DRM_WARN("Emergency reboot.");
4558 emergency_restart();
4561 dev_info(adev->dev, "GPU %s begin!\n",
4562 need_emergency_restart ? "jobs stop":"reset");
4565 * Here we trylock to avoid chain of resets executing from
4566 * either trigger by jobs on different adevs in XGMI hive or jobs on
4567 * different schedulers for same device while this TO handler is running.
4568 * We always reset all schedulers for device and all devices for XGMI
4569 * hive so that should take care of them too.
4571 hive = amdgpu_get_xgmi_hive(adev);
4573 if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) {
4574 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
4575 job ? job->base.id : -1, hive->hive_id);
4576 amdgpu_put_xgmi_hive(hive);
4579 mutex_lock(&hive->hive_lock);
4583 * Build list of devices to reset.
4584 * In case we are in XGMI hive mode, resort the device list
4585 * to put adev in the 1st position.
4587 INIT_LIST_HEAD(&device_list);
4588 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4591 if (!list_is_first(&adev->gmc.xgmi.head, &hive->device_list))
4592 list_rotate_to_front(&adev->gmc.xgmi.head, &hive->device_list);
4593 device_list_handle = &hive->device_list;
4595 list_add_tail(&adev->gmc.xgmi.head, &device_list);
4596 device_list_handle = &device_list;
4599 /* block all schedulers and reset given job's ring */
4600 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4601 if (!amdgpu_device_lock_adev(tmp_adev, hive)) {
4602 dev_info(tmp_adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress",
4603 job ? job->base.id : -1);
4609 * Try to put the audio codec into suspend state
4610 * before gpu reset started.
4612 * Due to the power domain of the graphics device
4613 * is shared with AZ power domain. Without this,
4614 * we may change the audio hardware from behind
4615 * the audio driver's back. That will trigger
4616 * some audio codec errors.
4618 if (!amdgpu_device_suspend_display_audio(tmp_adev))
4619 audio_suspended = true;
4621 amdgpu_ras_set_error_query_ready(tmp_adev, false);
4623 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
4625 if (!amdgpu_sriov_vf(tmp_adev))
4626 amdgpu_amdkfd_pre_reset(tmp_adev);
4629 * Mark these ASICs to be reseted as untracked first
4630 * And add them back after reset completed
4632 amdgpu_unregister_gpu_instance(tmp_adev);
4634 amdgpu_fbdev_set_suspend(tmp_adev, 1);
4636 /* disable ras on ALL IPs */
4637 if (!need_emergency_restart &&
4638 amdgpu_device_ip_need_full_reset(tmp_adev))
4639 amdgpu_ras_suspend(tmp_adev);
4641 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4642 struct amdgpu_ring *ring = tmp_adev->rings[i];
4644 if (!ring || !ring->sched.thread)
4647 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
4649 if (need_emergency_restart)
4650 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
4654 if (need_emergency_restart)
4655 goto skip_sched_resume;
4658 * Must check guilty signal here since after this point all old
4659 * HW fences are force signaled.
4661 * job->base holds a reference to parent fence
4663 if (job && job->base.s_fence->parent &&
4664 dma_fence_is_signaled(job->base.s_fence->parent)) {
4665 job_signaled = true;
4666 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
4670 retry: /* Rest of adevs pre asic reset from XGMI hive. */
4671 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4672 r = amdgpu_device_pre_asic_reset(tmp_adev,
4673 (tmp_adev == adev) ? job : NULL,
4675 /*TODO Should we stop ?*/
4677 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
4678 r, adev_to_drm(tmp_adev)->unique);
4679 tmp_adev->asic_reset_res = r;
4683 /* Actual ASIC resets if needed.*/
4684 /* TODO Implement XGMI hive reset logic for SRIOV */
4685 if (amdgpu_sriov_vf(adev)) {
4686 r = amdgpu_device_reset_sriov(adev, job ? false : true);
4688 adev->asic_reset_res = r;
4690 r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset, false);
4691 if (r && r == -EAGAIN)
4697 /* Post ASIC reset for all devs .*/
4698 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4700 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4701 struct amdgpu_ring *ring = tmp_adev->rings[i];
4703 if (!ring || !ring->sched.thread)
4706 /* No point to resubmit jobs if we didn't HW reset*/
4707 if (!tmp_adev->asic_reset_res && !job_signaled)
4708 drm_sched_resubmit_jobs(&ring->sched);
4710 drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
4713 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
4714 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
4717 tmp_adev->asic_reset_res = 0;
4720 /* bad news, how to tell it to userspace ? */
4721 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
4722 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
4724 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
4729 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4730 /*unlock kfd: SRIOV would do it separately */
4731 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
4732 amdgpu_amdkfd_post_reset(tmp_adev);
4733 if (audio_suspended)
4734 amdgpu_device_resume_display_audio(tmp_adev);
4735 amdgpu_device_unlock_adev(tmp_adev);
4740 atomic_set(&hive->in_reset, 0);
4741 mutex_unlock(&hive->hive_lock);
4742 amdgpu_put_xgmi_hive(hive);
4746 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
4751 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
4753 * @adev: amdgpu_device pointer
4755 * Fetchs and stores in the driver the PCIE capabilities (gen speed
4756 * and lanes) of the slot the device is in. Handles APUs and
4757 * virtualized environments where PCIE config space may not be available.
4759 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
4761 struct pci_dev *pdev;
4762 enum pci_bus_speed speed_cap, platform_speed_cap;
4763 enum pcie_link_width platform_link_width;
4765 if (amdgpu_pcie_gen_cap)
4766 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
4768 if (amdgpu_pcie_lane_cap)
4769 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
4771 /* covers APUs as well */
4772 if (pci_is_root_bus(adev->pdev->bus)) {
4773 if (adev->pm.pcie_gen_mask == 0)
4774 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
4775 if (adev->pm.pcie_mlw_mask == 0)
4776 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4780 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
4783 pcie_bandwidth_available(adev->pdev, NULL,
4784 &platform_speed_cap, &platform_link_width);
4786 if (adev->pm.pcie_gen_mask == 0) {
4789 speed_cap = pcie_get_speed_cap(pdev);
4790 if (speed_cap == PCI_SPEED_UNKNOWN) {
4791 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4792 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4793 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4795 if (speed_cap == PCIE_SPEED_32_0GT)
4796 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4797 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4798 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4799 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
4800 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
4801 else if (speed_cap == PCIE_SPEED_16_0GT)
4802 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4803 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4804 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4805 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
4806 else if (speed_cap == PCIE_SPEED_8_0GT)
4807 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4808 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4809 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4810 else if (speed_cap == PCIE_SPEED_5_0GT)
4811 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4812 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
4814 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
4817 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
4818 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4819 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4821 if (platform_speed_cap == PCIE_SPEED_32_0GT)
4822 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4823 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4824 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4825 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
4826 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
4827 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
4828 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4829 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4830 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4831 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
4832 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
4833 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4834 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4835 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
4836 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
4837 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4838 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4840 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
4844 if (adev->pm.pcie_mlw_mask == 0) {
4845 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
4846 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
4848 switch (platform_link_width) {
4850 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
4851 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4852 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4853 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4854 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4855 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4856 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4859 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4860 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4861 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4862 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4863 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4864 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4867 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4868 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4869 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4870 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4871 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4874 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4875 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4876 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4877 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4880 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4881 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4882 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4885 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4886 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4889 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
4898 int amdgpu_device_baco_enter(struct drm_device *dev)
4900 struct amdgpu_device *adev = drm_to_adev(dev);
4901 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4903 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
4906 if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
4907 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
4909 return amdgpu_dpm_baco_enter(adev);
4912 int amdgpu_device_baco_exit(struct drm_device *dev)
4914 struct amdgpu_device *adev = drm_to_adev(dev);
4915 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4918 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
4921 ret = amdgpu_dpm_baco_exit(adev);
4925 if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
4926 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
4931 static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev)
4935 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4936 struct amdgpu_ring *ring = adev->rings[i];
4938 if (!ring || !ring->sched.thread)
4941 cancel_delayed_work_sync(&ring->sched.work_tdr);
4946 * amdgpu_pci_error_detected - Called when a PCI error is detected.
4947 * @pdev: PCI device struct
4948 * @state: PCI channel state
4950 * Description: Called when a PCI error is detected.
4952 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
4954 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4956 struct drm_device *dev = pci_get_drvdata(pdev);
4957 struct amdgpu_device *adev = drm_to_adev(dev);
4960 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
4962 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4963 DRM_WARN("No support for XGMI hive yet...");
4964 return PCI_ERS_RESULT_DISCONNECT;
4968 case pci_channel_io_normal:
4969 return PCI_ERS_RESULT_CAN_RECOVER;
4970 /* Fatal error, prepare for slot reset */
4971 case pci_channel_io_frozen:
4973 * Cancel and wait for all TDRs in progress if failing to
4974 * set adev->in_gpu_reset in amdgpu_device_lock_adev
4976 * Locking adev->reset_sem will prevent any external access
4977 * to GPU during PCI error recovery
4979 while (!amdgpu_device_lock_adev(adev, NULL))
4980 amdgpu_cancel_all_tdr(adev);
4983 * Block any work scheduling as we do for regular GPU reset
4984 * for the duration of the recovery
4986 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4987 struct amdgpu_ring *ring = adev->rings[i];
4989 if (!ring || !ring->sched.thread)
4992 drm_sched_stop(&ring->sched, NULL);
4994 return PCI_ERS_RESULT_NEED_RESET;
4995 case pci_channel_io_perm_failure:
4996 /* Permanent error, prepare for device removal */
4997 return PCI_ERS_RESULT_DISCONNECT;
5000 return PCI_ERS_RESULT_NEED_RESET;
5004 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
5005 * @pdev: pointer to PCI device
5007 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
5010 DRM_INFO("PCI error: mmio enabled callback!!\n");
5012 /* TODO - dump whatever for debugging purposes */
5014 /* This called only if amdgpu_pci_error_detected returns
5015 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
5016 * works, no need to reset slot.
5019 return PCI_ERS_RESULT_RECOVERED;
5023 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5024 * @pdev: PCI device struct
5026 * Description: This routine is called by the pci error recovery
5027 * code after the PCI slot has been reset, just before we
5028 * should resume normal operations.
5030 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5032 struct drm_device *dev = pci_get_drvdata(pdev);
5033 struct amdgpu_device *adev = drm_to_adev(dev);
5035 bool need_full_reset = true;
5037 struct list_head device_list;
5039 DRM_INFO("PCI error: slot reset callback!!\n");
5041 INIT_LIST_HEAD(&device_list);
5042 list_add_tail(&adev->gmc.xgmi.head, &device_list);
5044 /* wait for asic to come out of reset */
5047 /* Restore PCI confspace */
5048 amdgpu_device_load_pci_state(pdev);
5050 /* confirm ASIC came out of reset */
5051 for (i = 0; i < adev->usec_timeout; i++) {
5052 memsize = amdgpu_asic_get_config_memsize(adev);
5054 if (memsize != 0xffffffff)
5058 if (memsize == 0xffffffff) {
5063 adev->in_pci_err_recovery = true;
5064 r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset);
5065 adev->in_pci_err_recovery = false;
5069 r = amdgpu_do_asic_reset(NULL, &device_list, &need_full_reset, true);
5073 if (amdgpu_device_cache_pci_state(adev->pdev))
5074 pci_restore_state(adev->pdev);
5076 DRM_INFO("PCIe error recovery succeeded\n");
5078 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5079 amdgpu_device_unlock_adev(adev);
5082 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5086 * amdgpu_pci_resume() - resume normal ops after PCI reset
5087 * @pdev: pointer to PCI device
5089 * Called when the error recovery driver tells us that its
5090 * OK to resume normal operation.
5092 void amdgpu_pci_resume(struct pci_dev *pdev)
5094 struct drm_device *dev = pci_get_drvdata(pdev);
5095 struct amdgpu_device *adev = drm_to_adev(dev);
5099 DRM_INFO("PCI error: resume callback!!\n");
5101 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5102 struct amdgpu_ring *ring = adev->rings[i];
5104 if (!ring || !ring->sched.thread)
5108 drm_sched_resubmit_jobs(&ring->sched);
5109 drm_sched_start(&ring->sched, true);
5112 amdgpu_device_unlock_adev(adev);
5115 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5117 struct drm_device *dev = pci_get_drvdata(pdev);
5118 struct amdgpu_device *adev = drm_to_adev(dev);
5121 r = pci_save_state(pdev);
5123 kfree(adev->pci_state);
5125 adev->pci_state = pci_store_saved_state(pdev);
5127 if (!adev->pci_state) {
5128 DRM_ERROR("Failed to store PCI saved state");
5132 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5139 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5141 struct drm_device *dev = pci_get_drvdata(pdev);
5142 struct amdgpu_device *adev = drm_to_adev(dev);
5145 if (!adev->pci_state)
5148 r = pci_load_saved_state(pdev, adev->pci_state);
5151 pci_restore_state(pdev);
5153 DRM_WARN("Failed to load PCI state, err:%d\n", r);