2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/amdgpu_drm.h>
37 #include <linux/vgaarb.h>
38 #include <linux/vga_switcheroo.h>
39 #include <linux/efi.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_i2c.h"
44 #include "amdgpu_atombios.h"
45 #include "amdgpu_atomfirmware.h"
47 #ifdef CONFIG_DRM_AMDGPU_SI
50 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #include "bif/bif_4_1_d.h"
57 #include <linux/pci.h>
58 #include <linux/firmware.h>
59 #include "amdgpu_vf_error.h"
61 #include "amdgpu_amdkfd.h"
62 #include "amdgpu_pm.h"
64 #include "amdgpu_xgmi.h"
65 #include "amdgpu_ras.h"
66 #include "amdgpu_pmu.h"
67 #include "amdgpu_fru_eeprom.h"
69 #include <linux/suspend.h>
70 #include <drm/task_barrier.h>
71 #include <linux/pm_runtime.h>
73 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
74 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
75 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
76 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
77 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
78 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
79 MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
80 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
81 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
82 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
83 MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
84 MODULE_FIRMWARE("amdgpu/green_sardine_gpu_info.bin");
86 #define AMDGPU_RESUME_MS 2000
88 const char *amdgpu_asic_name[] = {
125 * DOC: pcie_replay_count
127 * The amdgpu driver provides a sysfs API for reporting the total number
128 * of PCIe replays (NAKs)
129 * The file pcie_replay_count is used for this and returns the total
130 * number of replays as a sum of the NAKs generated and NAKs received
133 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
134 struct device_attribute *attr, char *buf)
136 struct drm_device *ddev = dev_get_drvdata(dev);
137 struct amdgpu_device *adev = drm_to_adev(ddev);
138 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
140 return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
143 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
144 amdgpu_device_get_pcie_replay_count, NULL);
146 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
151 * The amdgpu driver provides a sysfs API for reporting the product name
153 * The file serial_number is used for this and returns the product name
154 * as returned from the FRU.
155 * NOTE: This is only available for certain server cards
158 static ssize_t amdgpu_device_get_product_name(struct device *dev,
159 struct device_attribute *attr, char *buf)
161 struct drm_device *ddev = dev_get_drvdata(dev);
162 struct amdgpu_device *adev = drm_to_adev(ddev);
164 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name);
167 static DEVICE_ATTR(product_name, S_IRUGO,
168 amdgpu_device_get_product_name, NULL);
171 * DOC: product_number
173 * The amdgpu driver provides a sysfs API for reporting the part number
175 * The file serial_number is used for this and returns the part number
176 * as returned from the FRU.
177 * NOTE: This is only available for certain server cards
180 static ssize_t amdgpu_device_get_product_number(struct device *dev,
181 struct device_attribute *attr, char *buf)
183 struct drm_device *ddev = dev_get_drvdata(dev);
184 struct amdgpu_device *adev = drm_to_adev(ddev);
186 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number);
189 static DEVICE_ATTR(product_number, S_IRUGO,
190 amdgpu_device_get_product_number, NULL);
195 * The amdgpu driver provides a sysfs API for reporting the serial number
197 * The file serial_number is used for this and returns the serial number
198 * as returned from the FRU.
199 * NOTE: This is only available for certain server cards
202 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
203 struct device_attribute *attr, char *buf)
205 struct drm_device *ddev = dev_get_drvdata(dev);
206 struct amdgpu_device *adev = drm_to_adev(ddev);
208 return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial);
211 static DEVICE_ATTR(serial_number, S_IRUGO,
212 amdgpu_device_get_serial_number, NULL);
215 * amdgpu_device_supports_atpx - Is the device a dGPU with HG/PX power control
217 * @dev: drm_device pointer
219 * Returns true if the device is a dGPU with HG/PX power control,
220 * otherwise return false.
222 bool amdgpu_device_supports_atpx(struct drm_device *dev)
224 struct amdgpu_device *adev = drm_to_adev(dev);
226 if (adev->flags & AMD_IS_PX)
232 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
234 * @dev: drm_device pointer
236 * Returns true if the device is a dGPU with HG/PX power control,
237 * otherwise return false.
239 bool amdgpu_device_supports_boco(struct drm_device *dev)
241 struct amdgpu_device *adev = drm_to_adev(dev);
249 * amdgpu_device_supports_baco - Does the device support BACO
251 * @dev: drm_device pointer
253 * Returns true if the device supporte BACO,
254 * otherwise return false.
256 bool amdgpu_device_supports_baco(struct drm_device *dev)
258 struct amdgpu_device *adev = drm_to_adev(dev);
260 return amdgpu_asic_supports_baco(adev);
264 * VRAM access helper functions
268 * amdgpu_device_vram_access - read/write a buffer in vram
270 * @adev: amdgpu_device pointer
271 * @pos: offset of the buffer in vram
272 * @buf: virtual address of the buffer in system memory
273 * @size: read/write size, sizeof(@buf) must > @size
274 * @write: true - write to vram, otherwise - read from vram
276 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
277 uint32_t *buf, size_t size, bool write)
285 last = min(pos + size, adev->gmc.visible_vram_size);
287 void __iomem *addr = adev->mman.aper_base_kaddr + pos;
288 size_t count = last - pos;
291 memcpy_toio(addr, buf, count);
293 amdgpu_asic_flush_hdp(adev, NULL);
295 amdgpu_asic_invalidate_hdp(adev, NULL);
297 memcpy_fromio(buf, addr, count);
309 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
310 for (last = pos + size; pos < last; pos += 4) {
311 uint32_t tmp = pos >> 31;
313 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
315 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
319 WREG32_NO_KIQ(mmMM_DATA, *buf++);
321 *buf++ = RREG32_NO_KIQ(mmMM_DATA);
323 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
327 * register access helper functions.
330 * amdgpu_device_rreg - read a memory mapped IO or indirect register
332 * @adev: amdgpu_device pointer
333 * @reg: dword aligned register offset
334 * @acc_flags: access flags which require special behavior
336 * Returns the 32 bit value from the offset specified.
338 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
339 uint32_t reg, uint32_t acc_flags)
343 if (adev->in_pci_err_recovery)
346 if ((reg * 4) < adev->rmmio_size) {
347 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
348 amdgpu_sriov_runtime(adev) &&
349 down_read_trylock(&adev->reset_sem)) {
350 ret = amdgpu_kiq_rreg(adev, reg);
351 up_read(&adev->reset_sem);
353 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
356 ret = adev->pcie_rreg(adev, reg * 4);
359 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
365 * MMIO register read with bytes helper functions
366 * @offset:bytes offset from MMIO start
371 * amdgpu_mm_rreg8 - read a memory mapped IO register
373 * @adev: amdgpu_device pointer
374 * @offset: byte aligned register offset
376 * Returns the 8 bit value from the offset specified.
378 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
380 if (adev->in_pci_err_recovery)
383 if (offset < adev->rmmio_size)
384 return (readb(adev->rmmio + offset));
389 * MMIO register write with bytes helper functions
390 * @offset:bytes offset from MMIO start
391 * @value: the value want to be written to the register
395 * amdgpu_mm_wreg8 - read a memory mapped IO register
397 * @adev: amdgpu_device pointer
398 * @offset: byte aligned register offset
399 * @value: 8 bit value to write
401 * Writes the value specified to the offset specified.
403 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
405 if (adev->in_pci_err_recovery)
408 if (offset < adev->rmmio_size)
409 writeb(value, adev->rmmio + offset);
415 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
417 * @adev: amdgpu_device pointer
418 * @reg: dword aligned register offset
419 * @v: 32 bit value to write to the register
420 * @acc_flags: access flags which require special behavior
422 * Writes the value specified to the offset specified.
424 void amdgpu_device_wreg(struct amdgpu_device *adev,
425 uint32_t reg, uint32_t v,
428 if (adev->in_pci_err_recovery)
431 if ((reg * 4) < adev->rmmio_size) {
432 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
433 amdgpu_sriov_runtime(adev) &&
434 down_read_trylock(&adev->reset_sem)) {
435 amdgpu_kiq_wreg(adev, reg, v);
436 up_read(&adev->reset_sem);
438 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
441 adev->pcie_wreg(adev, reg * 4, v);
444 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
448 * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range
450 * this function is invoked only the debugfs register access
452 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
453 uint32_t reg, uint32_t v)
455 if (adev->in_pci_err_recovery)
458 if (amdgpu_sriov_fullaccess(adev) &&
459 adev->gfx.rlc.funcs &&
460 adev->gfx.rlc.funcs->is_rlcg_access_range) {
461 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
462 return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);
464 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
469 * amdgpu_io_rreg - read an IO register
471 * @adev: amdgpu_device pointer
472 * @reg: dword aligned register offset
474 * Returns the 32 bit value from the offset specified.
476 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
478 if (adev->in_pci_err_recovery)
481 if ((reg * 4) < adev->rio_mem_size)
482 return ioread32(adev->rio_mem + (reg * 4));
484 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
485 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
490 * amdgpu_io_wreg - write to an IO register
492 * @adev: amdgpu_device pointer
493 * @reg: dword aligned register offset
494 * @v: 32 bit value to write to the register
496 * Writes the value specified to the offset specified.
498 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
500 if (adev->in_pci_err_recovery)
503 if ((reg * 4) < adev->rio_mem_size)
504 iowrite32(v, adev->rio_mem + (reg * 4));
506 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
507 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
512 * amdgpu_mm_rdoorbell - read a doorbell dword
514 * @adev: amdgpu_device pointer
515 * @index: doorbell index
517 * Returns the value in the doorbell aperture at the
518 * requested doorbell index (CIK).
520 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
522 if (adev->in_pci_err_recovery)
525 if (index < adev->doorbell.num_doorbells) {
526 return readl(adev->doorbell.ptr + index);
528 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
534 * amdgpu_mm_wdoorbell - write a doorbell dword
536 * @adev: amdgpu_device pointer
537 * @index: doorbell index
540 * Writes @v to the doorbell aperture at the
541 * requested doorbell index (CIK).
543 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
545 if (adev->in_pci_err_recovery)
548 if (index < adev->doorbell.num_doorbells) {
549 writel(v, adev->doorbell.ptr + index);
551 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
556 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
558 * @adev: amdgpu_device pointer
559 * @index: doorbell index
561 * Returns the value in the doorbell aperture at the
562 * requested doorbell index (VEGA10+).
564 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
566 if (adev->in_pci_err_recovery)
569 if (index < adev->doorbell.num_doorbells) {
570 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
572 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
578 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
580 * @adev: amdgpu_device pointer
581 * @index: doorbell index
584 * Writes @v to the doorbell aperture at the
585 * requested doorbell index (VEGA10+).
587 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
589 if (adev->in_pci_err_recovery)
592 if (index < adev->doorbell.num_doorbells) {
593 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
595 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
600 * amdgpu_device_indirect_rreg - read an indirect register
602 * @adev: amdgpu_device pointer
603 * @pcie_index: mmio register offset
604 * @pcie_data: mmio register offset
605 * @reg_addr: indirect register address to read from
607 * Returns the value of indirect register @reg_addr
609 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
610 u32 pcie_index, u32 pcie_data,
615 void __iomem *pcie_index_offset;
616 void __iomem *pcie_data_offset;
618 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
619 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
620 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
622 writel(reg_addr, pcie_index_offset);
623 readl(pcie_index_offset);
624 r = readl(pcie_data_offset);
625 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
631 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
633 * @adev: amdgpu_device pointer
634 * @pcie_index: mmio register offset
635 * @pcie_data: mmio register offset
636 * @reg_addr: indirect register address to read from
638 * Returns the value of indirect register @reg_addr
640 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
641 u32 pcie_index, u32 pcie_data,
646 void __iomem *pcie_index_offset;
647 void __iomem *pcie_data_offset;
649 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
650 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
651 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
653 /* read low 32 bits */
654 writel(reg_addr, pcie_index_offset);
655 readl(pcie_index_offset);
656 r = readl(pcie_data_offset);
657 /* read high 32 bits */
658 writel(reg_addr + 4, pcie_index_offset);
659 readl(pcie_index_offset);
660 r |= ((u64)readl(pcie_data_offset) << 32);
661 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
667 * amdgpu_device_indirect_wreg - write an indirect register address
669 * @adev: amdgpu_device pointer
670 * @pcie_index: mmio register offset
671 * @pcie_data: mmio register offset
672 * @reg_addr: indirect register offset
673 * @reg_data: indirect register data
676 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
677 u32 pcie_index, u32 pcie_data,
678 u32 reg_addr, u32 reg_data)
681 void __iomem *pcie_index_offset;
682 void __iomem *pcie_data_offset;
684 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
685 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
686 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
688 writel(reg_addr, pcie_index_offset);
689 readl(pcie_index_offset);
690 writel(reg_data, pcie_data_offset);
691 readl(pcie_data_offset);
692 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
696 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
698 * @adev: amdgpu_device pointer
699 * @pcie_index: mmio register offset
700 * @pcie_data: mmio register offset
701 * @reg_addr: indirect register offset
702 * @reg_data: indirect register data
705 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
706 u32 pcie_index, u32 pcie_data,
707 u32 reg_addr, u64 reg_data)
710 void __iomem *pcie_index_offset;
711 void __iomem *pcie_data_offset;
713 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
714 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
715 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
717 /* write low 32 bits */
718 writel(reg_addr, pcie_index_offset);
719 readl(pcie_index_offset);
720 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
721 readl(pcie_data_offset);
722 /* write high 32 bits */
723 writel(reg_addr + 4, pcie_index_offset);
724 readl(pcie_index_offset);
725 writel((u32)(reg_data >> 32), pcie_data_offset);
726 readl(pcie_data_offset);
727 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
731 * amdgpu_invalid_rreg - dummy reg read function
733 * @adev: amdgpu_device pointer
734 * @reg: offset of register
736 * Dummy register read function. Used for register blocks
737 * that certain asics don't have (all asics).
738 * Returns the value in the register.
740 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
742 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
748 * amdgpu_invalid_wreg - dummy reg write function
750 * @adev: amdgpu_device pointer
751 * @reg: offset of register
752 * @v: value to write to the register
754 * Dummy register read function. Used for register blocks
755 * that certain asics don't have (all asics).
757 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
759 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
765 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
767 * @adev: amdgpu_device pointer
768 * @reg: offset of register
770 * Dummy register read function. Used for register blocks
771 * that certain asics don't have (all asics).
772 * Returns the value in the register.
774 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
776 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
782 * amdgpu_invalid_wreg64 - dummy reg write function
784 * @adev: amdgpu_device pointer
785 * @reg: offset of register
786 * @v: value to write to the register
788 * Dummy register read function. Used for register blocks
789 * that certain asics don't have (all asics).
791 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
793 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
799 * amdgpu_block_invalid_rreg - dummy reg read function
801 * @adev: amdgpu_device pointer
802 * @block: offset of instance
803 * @reg: offset of register
805 * Dummy register read function. Used for register blocks
806 * that certain asics don't have (all asics).
807 * Returns the value in the register.
809 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
810 uint32_t block, uint32_t reg)
812 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
819 * amdgpu_block_invalid_wreg - dummy reg write function
821 * @adev: amdgpu_device pointer
822 * @block: offset of instance
823 * @reg: offset of register
824 * @v: value to write to the register
826 * Dummy register read function. Used for register blocks
827 * that certain asics don't have (all asics).
829 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
831 uint32_t reg, uint32_t v)
833 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
839 * amdgpu_device_asic_init - Wrapper for atom asic_init
841 * @adev: amdgpu_device pointer
843 * Does any asic specific work and then calls atom asic init.
845 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
847 amdgpu_asic_pre_asic_init(adev);
849 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
853 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
855 * @adev: amdgpu_device pointer
857 * Allocates a scratch page of VRAM for use by various things in the
860 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
862 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
863 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
864 &adev->vram_scratch.robj,
865 &adev->vram_scratch.gpu_addr,
866 (void **)&adev->vram_scratch.ptr);
870 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
872 * @adev: amdgpu_device pointer
874 * Frees the VRAM scratch page.
876 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
878 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
882 * amdgpu_device_program_register_sequence - program an array of registers.
884 * @adev: amdgpu_device pointer
885 * @registers: pointer to the register array
886 * @array_size: size of the register array
888 * Programs an array or registers with and and or masks.
889 * This is a helper for setting golden registers.
891 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
892 const u32 *registers,
893 const u32 array_size)
895 u32 tmp, reg, and_mask, or_mask;
901 for (i = 0; i < array_size; i +=3) {
902 reg = registers[i + 0];
903 and_mask = registers[i + 1];
904 or_mask = registers[i + 2];
906 if (and_mask == 0xffffffff) {
911 if (adev->family >= AMDGPU_FAMILY_AI)
912 tmp |= (or_mask & and_mask);
921 * amdgpu_device_pci_config_reset - reset the GPU
923 * @adev: amdgpu_device pointer
925 * Resets the GPU using the pci config reset sequence.
926 * Only applicable to asics prior to vega10.
928 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
930 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
934 * GPU doorbell aperture helpers function.
937 * amdgpu_device_doorbell_init - Init doorbell driver information.
939 * @adev: amdgpu_device pointer
941 * Init doorbell driver information (CIK)
942 * Returns 0 on success, error on failure.
944 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
947 /* No doorbell on SI hardware generation */
948 if (adev->asic_type < CHIP_BONAIRE) {
949 adev->doorbell.base = 0;
950 adev->doorbell.size = 0;
951 adev->doorbell.num_doorbells = 0;
952 adev->doorbell.ptr = NULL;
956 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
959 amdgpu_asic_init_doorbell_index(adev);
961 /* doorbell bar mapping */
962 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
963 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
965 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
966 adev->doorbell_index.max_assignment+1);
967 if (adev->doorbell.num_doorbells == 0)
970 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
971 * paging queue doorbell use the second page. The
972 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
973 * doorbells are in the first page. So with paging queue enabled,
974 * the max num_doorbells should + 1 page (0x400 in dword)
976 if (adev->asic_type >= CHIP_VEGA10)
977 adev->doorbell.num_doorbells += 0x400;
979 adev->doorbell.ptr = ioremap(adev->doorbell.base,
980 adev->doorbell.num_doorbells *
982 if (adev->doorbell.ptr == NULL)
989 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
991 * @adev: amdgpu_device pointer
993 * Tear down doorbell driver information (CIK)
995 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
997 iounmap(adev->doorbell.ptr);
998 adev->doorbell.ptr = NULL;
1004 * amdgpu_device_wb_*()
1005 * Writeback is the method by which the GPU updates special pages in memory
1006 * with the status of certain GPU events (fences, ring pointers,etc.).
1010 * amdgpu_device_wb_fini - Disable Writeback and free memory
1012 * @adev: amdgpu_device pointer
1014 * Disables Writeback and frees the Writeback memory (all asics).
1015 * Used at driver shutdown.
1017 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1019 if (adev->wb.wb_obj) {
1020 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1022 (void **)&adev->wb.wb);
1023 adev->wb.wb_obj = NULL;
1028 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
1030 * @adev: amdgpu_device pointer
1032 * Initializes writeback and allocates writeback memory (all asics).
1033 * Used at driver startup.
1034 * Returns 0 on success or an -error on failure.
1036 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1040 if (adev->wb.wb_obj == NULL) {
1041 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1042 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1043 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1044 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1045 (void **)&adev->wb.wb);
1047 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1051 adev->wb.num_wb = AMDGPU_MAX_WB;
1052 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1054 /* clear wb memory */
1055 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1062 * amdgpu_device_wb_get - Allocate a wb entry
1064 * @adev: amdgpu_device pointer
1067 * Allocate a wb slot for use by the driver (all asics).
1068 * Returns 0 on success or -EINVAL on failure.
1070 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1072 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1074 if (offset < adev->wb.num_wb) {
1075 __set_bit(offset, adev->wb.used);
1076 *wb = offset << 3; /* convert to dw offset */
1084 * amdgpu_device_wb_free - Free a wb entry
1086 * @adev: amdgpu_device pointer
1089 * Free a wb slot allocated for use by the driver (all asics)
1091 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1094 if (wb < adev->wb.num_wb)
1095 __clear_bit(wb, adev->wb.used);
1099 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1101 * @adev: amdgpu_device pointer
1103 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1104 * to fail, but if any of the BARs is not accessible after the size we abort
1105 * driver loading by returning -ENODEV.
1107 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1109 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1110 struct pci_bus *root;
1111 struct resource *res;
1117 if (amdgpu_sriov_vf(adev))
1120 /* skip if the bios has already enabled large BAR */
1121 if (adev->gmc.real_vram_size &&
1122 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1125 /* Check if the root BUS has 64bit memory resources */
1126 root = adev->pdev->bus;
1127 while (root->parent)
1128 root = root->parent;
1130 pci_bus_for_each_resource(root, res, i) {
1131 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1132 res->start > 0x100000000ull)
1136 /* Trying to resize is pointless without a root hub window above 4GB */
1140 /* Limit the BAR size to what is available */
1141 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1144 /* Disable memory decoding while we change the BAR addresses and size */
1145 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1146 pci_write_config_word(adev->pdev, PCI_COMMAND,
1147 cmd & ~PCI_COMMAND_MEMORY);
1149 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1150 amdgpu_device_doorbell_fini(adev);
1151 if (adev->asic_type >= CHIP_BONAIRE)
1152 pci_release_resource(adev->pdev, 2);
1154 pci_release_resource(adev->pdev, 0);
1156 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1158 DRM_INFO("Not enough PCI address space for a large BAR.");
1159 else if (r && r != -ENOTSUPP)
1160 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1162 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1164 /* When the doorbell or fb BAR isn't available we have no chance of
1167 r = amdgpu_device_doorbell_init(adev);
1168 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1171 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1177 * GPU helpers function.
1180 * amdgpu_device_need_post - check if the hw need post or not
1182 * @adev: amdgpu_device pointer
1184 * Check if the asic has been initialized (all asics) at driver startup
1185 * or post is needed if hw reset is performed.
1186 * Returns true if need or false if not.
1188 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1192 if (amdgpu_sriov_vf(adev))
1195 if (amdgpu_passthrough(adev)) {
1196 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1197 * some old smc fw still need driver do vPost otherwise gpu hang, while
1198 * those smc fw version above 22.15 doesn't have this flaw, so we force
1199 * vpost executed for smc version below 22.15
1201 if (adev->asic_type == CHIP_FIJI) {
1204 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1205 /* force vPost if error occured */
1209 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1210 if (fw_ver < 0x00160e00)
1215 if (adev->has_hw_reset) {
1216 adev->has_hw_reset = false;
1220 /* bios scratch used on CIK+ */
1221 if (adev->asic_type >= CHIP_BONAIRE)
1222 return amdgpu_atombios_scratch_need_asic_init(adev);
1224 /* check MEM_SIZE for older asics */
1225 reg = amdgpu_asic_get_config_memsize(adev);
1227 if ((reg != 0) && (reg != 0xffffffff))
1233 /* if we get transitioned to only one device, take VGA back */
1235 * amdgpu_device_vga_set_decode - enable/disable vga decode
1237 * @cookie: amdgpu_device pointer
1238 * @state: enable/disable vga decode
1240 * Enable/disable vga decode (all asics).
1241 * Returns VGA resource flags.
1243 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
1245 struct amdgpu_device *adev = cookie;
1246 amdgpu_asic_set_vga_state(adev, state);
1248 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1249 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1251 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1255 * amdgpu_device_check_block_size - validate the vm block size
1257 * @adev: amdgpu_device pointer
1259 * Validates the vm block size specified via module parameter.
1260 * The vm block size defines number of bits in page table versus page directory,
1261 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1262 * page table and the remaining bits are in the page directory.
1264 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1266 /* defines number of bits in page table versus page directory,
1267 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1268 * page table and the remaining bits are in the page directory */
1269 if (amdgpu_vm_block_size == -1)
1272 if (amdgpu_vm_block_size < 9) {
1273 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1274 amdgpu_vm_block_size);
1275 amdgpu_vm_block_size = -1;
1280 * amdgpu_device_check_vm_size - validate the vm size
1282 * @adev: amdgpu_device pointer
1284 * Validates the vm size in GB specified via module parameter.
1285 * The VM size is the size of the GPU virtual memory space in GB.
1287 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1289 /* no need to check the default value */
1290 if (amdgpu_vm_size == -1)
1293 if (amdgpu_vm_size < 1) {
1294 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1296 amdgpu_vm_size = -1;
1300 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1303 bool is_os_64 = (sizeof(void *) == 8);
1304 uint64_t total_memory;
1305 uint64_t dram_size_seven_GB = 0x1B8000000;
1306 uint64_t dram_size_three_GB = 0xB8000000;
1308 if (amdgpu_smu_memory_pool_size == 0)
1312 DRM_WARN("Not 64-bit OS, feature not supported\n");
1316 total_memory = (uint64_t)si.totalram * si.mem_unit;
1318 if ((amdgpu_smu_memory_pool_size == 1) ||
1319 (amdgpu_smu_memory_pool_size == 2)) {
1320 if (total_memory < dram_size_three_GB)
1322 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1323 (amdgpu_smu_memory_pool_size == 8)) {
1324 if (total_memory < dram_size_seven_GB)
1327 DRM_WARN("Smu memory pool size not supported\n");
1330 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1335 DRM_WARN("No enough system memory\n");
1337 adev->pm.smu_prv_buffer_size = 0;
1341 * amdgpu_device_check_arguments - validate module params
1343 * @adev: amdgpu_device pointer
1345 * Validates certain module parameters and updates
1346 * the associated values used by the driver (all asics).
1348 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1350 if (amdgpu_sched_jobs < 4) {
1351 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1353 amdgpu_sched_jobs = 4;
1354 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1355 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1357 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1360 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1361 /* gart size must be greater or equal to 32M */
1362 dev_warn(adev->dev, "gart size (%d) too small\n",
1364 amdgpu_gart_size = -1;
1367 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1368 /* gtt size must be greater or equal to 32M */
1369 dev_warn(adev->dev, "gtt size (%d) too small\n",
1371 amdgpu_gtt_size = -1;
1374 /* valid range is between 4 and 9 inclusive */
1375 if (amdgpu_vm_fragment_size != -1 &&
1376 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1377 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1378 amdgpu_vm_fragment_size = -1;
1381 if (amdgpu_sched_hw_submission < 2) {
1382 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1383 amdgpu_sched_hw_submission);
1384 amdgpu_sched_hw_submission = 2;
1385 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1386 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1387 amdgpu_sched_hw_submission);
1388 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1391 amdgpu_device_check_smu_prv_buffer_size(adev);
1393 amdgpu_device_check_vm_size(adev);
1395 amdgpu_device_check_block_size(adev);
1397 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1399 amdgpu_gmc_tmz_set(adev);
1401 amdgpu_gmc_noretry_set(adev);
1407 * amdgpu_switcheroo_set_state - set switcheroo state
1409 * @pdev: pci dev pointer
1410 * @state: vga_switcheroo state
1412 * Callback for the switcheroo driver. Suspends or resumes the
1413 * the asics before or after it is powered up using ACPI methods.
1415 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1416 enum vga_switcheroo_state state)
1418 struct drm_device *dev = pci_get_drvdata(pdev);
1421 if (amdgpu_device_supports_atpx(dev) && state == VGA_SWITCHEROO_OFF)
1424 if (state == VGA_SWITCHEROO_ON) {
1425 pr_info("switched on\n");
1426 /* don't suspend or resume card normally */
1427 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1429 pci_set_power_state(pdev, PCI_D0);
1430 amdgpu_device_load_pci_state(pdev);
1431 r = pci_enable_device(pdev);
1433 DRM_WARN("pci_enable_device failed (%d)\n", r);
1434 amdgpu_device_resume(dev, true);
1436 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1437 drm_kms_helper_poll_enable(dev);
1439 pr_info("switched off\n");
1440 drm_kms_helper_poll_disable(dev);
1441 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1442 amdgpu_device_suspend(dev, true);
1443 amdgpu_device_cache_pci_state(pdev);
1444 /* Shut down the device */
1445 pci_disable_device(pdev);
1446 pci_set_power_state(pdev, PCI_D3cold);
1447 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1452 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1454 * @pdev: pci dev pointer
1456 * Callback for the switcheroo driver. Check of the switcheroo
1457 * state can be changed.
1458 * Returns true if the state can be changed, false if not.
1460 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1462 struct drm_device *dev = pci_get_drvdata(pdev);
1465 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1466 * locking inversion with the driver load path. And the access here is
1467 * completely racy anyway. So don't bother with locking for now.
1469 return atomic_read(&dev->open_count) == 0;
1472 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1473 .set_gpu_state = amdgpu_switcheroo_set_state,
1475 .can_switch = amdgpu_switcheroo_can_switch,
1479 * amdgpu_device_ip_set_clockgating_state - set the CG state
1481 * @dev: amdgpu_device pointer
1482 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1483 * @state: clockgating state (gate or ungate)
1485 * Sets the requested clockgating state for all instances of
1486 * the hardware IP specified.
1487 * Returns the error code from the last instance.
1489 int amdgpu_device_ip_set_clockgating_state(void *dev,
1490 enum amd_ip_block_type block_type,
1491 enum amd_clockgating_state state)
1493 struct amdgpu_device *adev = dev;
1496 for (i = 0; i < adev->num_ip_blocks; i++) {
1497 if (!adev->ip_blocks[i].status.valid)
1499 if (adev->ip_blocks[i].version->type != block_type)
1501 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1503 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1504 (void *)adev, state);
1506 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1507 adev->ip_blocks[i].version->funcs->name, r);
1513 * amdgpu_device_ip_set_powergating_state - set the PG state
1515 * @dev: amdgpu_device pointer
1516 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1517 * @state: powergating state (gate or ungate)
1519 * Sets the requested powergating state for all instances of
1520 * the hardware IP specified.
1521 * Returns the error code from the last instance.
1523 int amdgpu_device_ip_set_powergating_state(void *dev,
1524 enum amd_ip_block_type block_type,
1525 enum amd_powergating_state state)
1527 struct amdgpu_device *adev = dev;
1530 for (i = 0; i < adev->num_ip_blocks; i++) {
1531 if (!adev->ip_blocks[i].status.valid)
1533 if (adev->ip_blocks[i].version->type != block_type)
1535 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1537 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1538 (void *)adev, state);
1540 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1541 adev->ip_blocks[i].version->funcs->name, r);
1547 * amdgpu_device_ip_get_clockgating_state - get the CG state
1549 * @adev: amdgpu_device pointer
1550 * @flags: clockgating feature flags
1552 * Walks the list of IPs on the device and updates the clockgating
1553 * flags for each IP.
1554 * Updates @flags with the feature flags for each hardware IP where
1555 * clockgating is enabled.
1557 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1562 for (i = 0; i < adev->num_ip_blocks; i++) {
1563 if (!adev->ip_blocks[i].status.valid)
1565 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1566 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1571 * amdgpu_device_ip_wait_for_idle - wait for idle
1573 * @adev: amdgpu_device pointer
1574 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1576 * Waits for the request hardware IP to be idle.
1577 * Returns 0 for success or a negative error code on failure.
1579 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1580 enum amd_ip_block_type block_type)
1584 for (i = 0; i < adev->num_ip_blocks; i++) {
1585 if (!adev->ip_blocks[i].status.valid)
1587 if (adev->ip_blocks[i].version->type == block_type) {
1588 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1599 * amdgpu_device_ip_is_idle - is the hardware IP idle
1601 * @adev: amdgpu_device pointer
1602 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1604 * Check if the hardware IP is idle or not.
1605 * Returns true if it the IP is idle, false if not.
1607 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1608 enum amd_ip_block_type block_type)
1612 for (i = 0; i < adev->num_ip_blocks; i++) {
1613 if (!adev->ip_blocks[i].status.valid)
1615 if (adev->ip_blocks[i].version->type == block_type)
1616 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1623 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1625 * @adev: amdgpu_device pointer
1626 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1628 * Returns a pointer to the hardware IP block structure
1629 * if it exists for the asic, otherwise NULL.
1631 struct amdgpu_ip_block *
1632 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1633 enum amd_ip_block_type type)
1637 for (i = 0; i < adev->num_ip_blocks; i++)
1638 if (adev->ip_blocks[i].version->type == type)
1639 return &adev->ip_blocks[i];
1645 * amdgpu_device_ip_block_version_cmp
1647 * @adev: amdgpu_device pointer
1648 * @type: enum amd_ip_block_type
1649 * @major: major version
1650 * @minor: minor version
1652 * return 0 if equal or greater
1653 * return 1 if smaller or the ip_block doesn't exist
1655 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1656 enum amd_ip_block_type type,
1657 u32 major, u32 minor)
1659 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1661 if (ip_block && ((ip_block->version->major > major) ||
1662 ((ip_block->version->major == major) &&
1663 (ip_block->version->minor >= minor))))
1670 * amdgpu_device_ip_block_add
1672 * @adev: amdgpu_device pointer
1673 * @ip_block_version: pointer to the IP to add
1675 * Adds the IP block driver information to the collection of IPs
1678 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1679 const struct amdgpu_ip_block_version *ip_block_version)
1681 if (!ip_block_version)
1684 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1685 ip_block_version->funcs->name);
1687 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1693 * amdgpu_device_enable_virtual_display - enable virtual display feature
1695 * @adev: amdgpu_device pointer
1697 * Enabled the virtual display feature if the user has enabled it via
1698 * the module parameter virtual_display. This feature provides a virtual
1699 * display hardware on headless boards or in virtualized environments.
1700 * This function parses and validates the configuration string specified by
1701 * the user and configues the virtual display configuration (number of
1702 * virtual connectors, crtcs, etc.) specified.
1704 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1706 adev->enable_virtual_display = false;
1708 if (amdgpu_virtual_display) {
1709 const char *pci_address_name = pci_name(adev->pdev);
1710 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1712 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1713 pciaddstr_tmp = pciaddstr;
1714 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1715 pciaddname = strsep(&pciaddname_tmp, ",");
1716 if (!strcmp("all", pciaddname)
1717 || !strcmp(pci_address_name, pciaddname)) {
1721 adev->enable_virtual_display = true;
1724 res = kstrtol(pciaddname_tmp, 10,
1732 adev->mode_info.num_crtc = num_crtc;
1734 adev->mode_info.num_crtc = 1;
1740 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1741 amdgpu_virtual_display, pci_address_name,
1742 adev->enable_virtual_display, adev->mode_info.num_crtc);
1749 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1751 * @adev: amdgpu_device pointer
1753 * Parses the asic configuration parameters specified in the gpu info
1754 * firmware and makes them availale to the driver for use in configuring
1756 * Returns 0 on success, -EINVAL on failure.
1758 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1760 const char *chip_name;
1763 const struct gpu_info_firmware_header_v1_0 *hdr;
1765 adev->firmware.gpu_info_fw = NULL;
1767 if (adev->mman.discovery_bin) {
1768 amdgpu_discovery_get_gfx_info(adev);
1771 * FIXME: The bounding box is still needed by Navi12, so
1772 * temporarily read it from gpu_info firmware. Should be droped
1773 * when DAL no longer needs it.
1775 if (adev->asic_type != CHIP_NAVI12)
1779 switch (adev->asic_type) {
1780 #ifdef CONFIG_DRM_AMDGPU_SI
1787 #ifdef CONFIG_DRM_AMDGPU_CIK
1797 case CHIP_POLARIS10:
1798 case CHIP_POLARIS11:
1799 case CHIP_POLARIS12:
1804 case CHIP_SIENNA_CICHLID:
1805 case CHIP_NAVY_FLOUNDER:
1806 case CHIP_DIMGREY_CAVEFISH:
1810 chip_name = "vega10";
1813 chip_name = "vega12";
1816 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1817 chip_name = "raven2";
1818 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1819 chip_name = "picasso";
1821 chip_name = "raven";
1824 chip_name = "arcturus";
1827 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1828 chip_name = "renoir";
1830 chip_name = "green_sardine";
1833 chip_name = "navi10";
1836 chip_name = "navi14";
1839 chip_name = "navi12";
1842 chip_name = "vangogh";
1846 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1847 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1850 "Failed to load gpu_info firmware \"%s\"\n",
1854 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1857 "Failed to validate gpu_info firmware \"%s\"\n",
1862 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1863 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1865 switch (hdr->version_major) {
1868 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1869 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1870 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1873 * Should be droped when DAL no longer needs it.
1875 if (adev->asic_type == CHIP_NAVI12)
1876 goto parse_soc_bounding_box;
1878 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1879 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1880 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1881 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1882 adev->gfx.config.max_texture_channel_caches =
1883 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1884 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1885 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1886 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1887 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1888 adev->gfx.config.double_offchip_lds_buf =
1889 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1890 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1891 adev->gfx.cu_info.max_waves_per_simd =
1892 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1893 adev->gfx.cu_info.max_scratch_slots_per_cu =
1894 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1895 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1896 if (hdr->version_minor >= 1) {
1897 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1898 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1899 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1900 adev->gfx.config.num_sc_per_sh =
1901 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1902 adev->gfx.config.num_packer_per_sc =
1903 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1906 parse_soc_bounding_box:
1908 * soc bounding box info is not integrated in disocovery table,
1909 * we always need to parse it from gpu info firmware if needed.
1911 if (hdr->version_minor == 2) {
1912 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1913 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1914 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1915 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1921 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1930 * amdgpu_device_ip_early_init - run early init for hardware IPs
1932 * @adev: amdgpu_device pointer
1934 * Early initialization pass for hardware IPs. The hardware IPs that make
1935 * up each asic are discovered each IP's early_init callback is run. This
1936 * is the first stage in initializing the asic.
1937 * Returns 0 on success, negative error code on failure.
1939 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1943 amdgpu_device_enable_virtual_display(adev);
1945 if (amdgpu_sriov_vf(adev)) {
1946 r = amdgpu_virt_request_full_gpu(adev, true);
1951 switch (adev->asic_type) {
1952 #ifdef CONFIG_DRM_AMDGPU_SI
1958 adev->family = AMDGPU_FAMILY_SI;
1959 r = si_set_ip_blocks(adev);
1964 #ifdef CONFIG_DRM_AMDGPU_CIK
1970 if (adev->flags & AMD_IS_APU)
1971 adev->family = AMDGPU_FAMILY_KV;
1973 adev->family = AMDGPU_FAMILY_CI;
1975 r = cik_set_ip_blocks(adev);
1983 case CHIP_POLARIS10:
1984 case CHIP_POLARIS11:
1985 case CHIP_POLARIS12:
1989 if (adev->flags & AMD_IS_APU)
1990 adev->family = AMDGPU_FAMILY_CZ;
1992 adev->family = AMDGPU_FAMILY_VI;
1994 r = vi_set_ip_blocks(adev);
2004 if (adev->flags & AMD_IS_APU)
2005 adev->family = AMDGPU_FAMILY_RV;
2007 adev->family = AMDGPU_FAMILY_AI;
2009 r = soc15_set_ip_blocks(adev);
2016 case CHIP_SIENNA_CICHLID:
2017 case CHIP_NAVY_FLOUNDER:
2018 case CHIP_DIMGREY_CAVEFISH:
2020 if (adev->asic_type == CHIP_VANGOGH)
2021 adev->family = AMDGPU_FAMILY_VGH;
2023 adev->family = AMDGPU_FAMILY_NV;
2025 r = nv_set_ip_blocks(adev);
2030 /* FIXME: not supported yet */
2034 amdgpu_amdkfd_device_probe(adev);
2036 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2037 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2038 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2040 for (i = 0; i < adev->num_ip_blocks; i++) {
2041 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2042 DRM_ERROR("disabled ip block: %d <%s>\n",
2043 i, adev->ip_blocks[i].version->funcs->name);
2044 adev->ip_blocks[i].status.valid = false;
2046 if (adev->ip_blocks[i].version->funcs->early_init) {
2047 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2049 adev->ip_blocks[i].status.valid = false;
2051 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2052 adev->ip_blocks[i].version->funcs->name, r);
2055 adev->ip_blocks[i].status.valid = true;
2058 adev->ip_blocks[i].status.valid = true;
2061 /* get the vbios after the asic_funcs are set up */
2062 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2063 r = amdgpu_device_parse_gpu_info_fw(adev);
2068 if (!amdgpu_get_bios(adev))
2071 r = amdgpu_atombios_init(adev);
2073 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2074 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2080 adev->cg_flags &= amdgpu_cg_mask;
2081 adev->pg_flags &= amdgpu_pg_mask;
2086 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2090 for (i = 0; i < adev->num_ip_blocks; i++) {
2091 if (!adev->ip_blocks[i].status.sw)
2093 if (adev->ip_blocks[i].status.hw)
2095 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2096 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2097 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2098 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2100 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2101 adev->ip_blocks[i].version->funcs->name, r);
2104 adev->ip_blocks[i].status.hw = true;
2111 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2115 for (i = 0; i < adev->num_ip_blocks; i++) {
2116 if (!adev->ip_blocks[i].status.sw)
2118 if (adev->ip_blocks[i].status.hw)
2120 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2122 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2123 adev->ip_blocks[i].version->funcs->name, r);
2126 adev->ip_blocks[i].status.hw = true;
2132 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2136 uint32_t smu_version;
2138 if (adev->asic_type >= CHIP_VEGA10) {
2139 for (i = 0; i < adev->num_ip_blocks; i++) {
2140 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2143 /* no need to do the fw loading again if already done*/
2144 if (adev->ip_blocks[i].status.hw == true)
2147 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2148 r = adev->ip_blocks[i].version->funcs->resume(adev);
2150 DRM_ERROR("resume of IP block <%s> failed %d\n",
2151 adev->ip_blocks[i].version->funcs->name, r);
2155 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2157 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2158 adev->ip_blocks[i].version->funcs->name, r);
2163 adev->ip_blocks[i].status.hw = true;
2168 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2169 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2175 * amdgpu_device_ip_init - run init for hardware IPs
2177 * @adev: amdgpu_device pointer
2179 * Main initialization pass for hardware IPs. The list of all the hardware
2180 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2181 * are run. sw_init initializes the software state associated with each IP
2182 * and hw_init initializes the hardware associated with each IP.
2183 * Returns 0 on success, negative error code on failure.
2185 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2189 r = amdgpu_ras_init(adev);
2193 for (i = 0; i < adev->num_ip_blocks; i++) {
2194 if (!adev->ip_blocks[i].status.valid)
2196 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2198 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2199 adev->ip_blocks[i].version->funcs->name, r);
2202 adev->ip_blocks[i].status.sw = true;
2204 /* need to do gmc hw init early so we can allocate gpu mem */
2205 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2206 r = amdgpu_device_vram_scratch_init(adev);
2208 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
2211 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2213 DRM_ERROR("hw_init %d failed %d\n", i, r);
2216 r = amdgpu_device_wb_init(adev);
2218 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2221 adev->ip_blocks[i].status.hw = true;
2223 /* right after GMC hw init, we create CSA */
2224 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
2225 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2226 AMDGPU_GEM_DOMAIN_VRAM,
2229 DRM_ERROR("allocate CSA failed %d\n", r);
2236 if (amdgpu_sriov_vf(adev))
2237 amdgpu_virt_init_data_exchange(adev);
2239 r = amdgpu_ib_pool_init(adev);
2241 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2242 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2246 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2250 r = amdgpu_device_ip_hw_init_phase1(adev);
2254 r = amdgpu_device_fw_loading(adev);
2258 r = amdgpu_device_ip_hw_init_phase2(adev);
2263 * retired pages will be loaded from eeprom and reserved here,
2264 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2265 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2266 * for I2C communication which only true at this point.
2268 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2269 * failure from bad gpu situation and stop amdgpu init process
2270 * accordingly. For other failed cases, it will still release all
2271 * the resource and print error message, rather than returning one
2272 * negative value to upper level.
2274 * Note: theoretically, this should be called before all vram allocations
2275 * to protect retired page from abusing
2277 r = amdgpu_ras_recovery_init(adev);
2281 if (adev->gmc.xgmi.num_physical_nodes > 1)
2282 amdgpu_xgmi_add_device(adev);
2283 amdgpu_amdkfd_device_init(adev);
2285 amdgpu_fru_get_product_info(adev);
2288 if (amdgpu_sriov_vf(adev))
2289 amdgpu_virt_release_full_gpu(adev, true);
2295 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2297 * @adev: amdgpu_device pointer
2299 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2300 * this function before a GPU reset. If the value is retained after a
2301 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2303 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2305 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2309 * amdgpu_device_check_vram_lost - check if vram is valid
2311 * @adev: amdgpu_device pointer
2313 * Checks the reset magic value written to the gart pointer in VRAM.
2314 * The driver calls this after a GPU reset to see if the contents of
2315 * VRAM is lost or now.
2316 * returns true if vram is lost, false if not.
2318 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2320 if (memcmp(adev->gart.ptr, adev->reset_magic,
2321 AMDGPU_RESET_MAGIC_NUM))
2324 if (!amdgpu_in_reset(adev))
2328 * For all ASICs with baco/mode1 reset, the VRAM is
2329 * always assumed to be lost.
2331 switch (amdgpu_asic_reset_method(adev)) {
2332 case AMD_RESET_METHOD_BACO:
2333 case AMD_RESET_METHOD_MODE1:
2341 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2343 * @adev: amdgpu_device pointer
2344 * @state: clockgating state (gate or ungate)
2346 * The list of all the hardware IPs that make up the asic is walked and the
2347 * set_clockgating_state callbacks are run.
2348 * Late initialization pass enabling clockgating for hardware IPs.
2349 * Fini or suspend, pass disabling clockgating for hardware IPs.
2350 * Returns 0 on success, negative error code on failure.
2353 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2354 enum amd_clockgating_state state)
2358 if (amdgpu_emu_mode == 1)
2361 for (j = 0; j < adev->num_ip_blocks; j++) {
2362 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2363 if (!adev->ip_blocks[i].status.late_initialized)
2365 /* skip CG for VCE/UVD, it's handled specially */
2366 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2367 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2368 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2369 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2370 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2371 /* enable clockgating to save power */
2372 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2375 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2376 adev->ip_blocks[i].version->funcs->name, r);
2385 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
2389 if (amdgpu_emu_mode == 1)
2392 for (j = 0; j < adev->num_ip_blocks; j++) {
2393 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2394 if (!adev->ip_blocks[i].status.late_initialized)
2396 /* skip CG for VCE/UVD, it's handled specially */
2397 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2398 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2399 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2400 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2401 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2402 /* enable powergating to save power */
2403 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2406 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2407 adev->ip_blocks[i].version->funcs->name, r);
2415 static int amdgpu_device_enable_mgpu_fan_boost(void)
2417 struct amdgpu_gpu_instance *gpu_ins;
2418 struct amdgpu_device *adev;
2421 mutex_lock(&mgpu_info.mutex);
2424 * MGPU fan boost feature should be enabled
2425 * only when there are two or more dGPUs in
2428 if (mgpu_info.num_dgpu < 2)
2431 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2432 gpu_ins = &(mgpu_info.gpu_ins[i]);
2433 adev = gpu_ins->adev;
2434 if (!(adev->flags & AMD_IS_APU) &&
2435 !gpu_ins->mgpu_fan_enabled) {
2436 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2440 gpu_ins->mgpu_fan_enabled = 1;
2445 mutex_unlock(&mgpu_info.mutex);
2451 * amdgpu_device_ip_late_init - run late init for hardware IPs
2453 * @adev: amdgpu_device pointer
2455 * Late initialization pass for hardware IPs. The list of all the hardware
2456 * IPs that make up the asic is walked and the late_init callbacks are run.
2457 * late_init covers any special initialization that an IP requires
2458 * after all of the have been initialized or something that needs to happen
2459 * late in the init process.
2460 * Returns 0 on success, negative error code on failure.
2462 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2464 struct amdgpu_gpu_instance *gpu_instance;
2467 for (i = 0; i < adev->num_ip_blocks; i++) {
2468 if (!adev->ip_blocks[i].status.hw)
2470 if (adev->ip_blocks[i].version->funcs->late_init) {
2471 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2473 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2474 adev->ip_blocks[i].version->funcs->name, r);
2478 adev->ip_blocks[i].status.late_initialized = true;
2481 amdgpu_ras_set_error_query_ready(adev, true);
2483 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2484 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2486 amdgpu_device_fill_reset_magic(adev);
2488 r = amdgpu_device_enable_mgpu_fan_boost();
2490 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2493 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2494 mutex_lock(&mgpu_info.mutex);
2497 * Reset device p-state to low as this was booted with high.
2499 * This should be performed only after all devices from the same
2500 * hive get initialized.
2502 * However, it's unknown how many device in the hive in advance.
2503 * As this is counted one by one during devices initializations.
2505 * So, we wait for all XGMI interlinked devices initialized.
2506 * This may bring some delays as those devices may come from
2507 * different hives. But that should be OK.
2509 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2510 for (i = 0; i < mgpu_info.num_gpu; i++) {
2511 gpu_instance = &(mgpu_info.gpu_ins[i]);
2512 if (gpu_instance->adev->flags & AMD_IS_APU)
2515 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2516 AMDGPU_XGMI_PSTATE_MIN);
2518 DRM_ERROR("pstate setting failed (%d).\n", r);
2524 mutex_unlock(&mgpu_info.mutex);
2531 * amdgpu_device_ip_fini - run fini for hardware IPs
2533 * @adev: amdgpu_device pointer
2535 * Main teardown pass for hardware IPs. The list of all the hardware
2536 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2537 * are run. hw_fini tears down the hardware associated with each IP
2538 * and sw_fini tears down any software state associated with each IP.
2539 * Returns 0 on success, negative error code on failure.
2541 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2545 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2546 amdgpu_virt_release_ras_err_handler_data(adev);
2548 amdgpu_ras_pre_fini(adev);
2550 if (adev->gmc.xgmi.num_physical_nodes > 1)
2551 amdgpu_xgmi_remove_device(adev);
2553 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2554 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2556 amdgpu_amdkfd_device_fini(adev);
2558 /* need to disable SMC first */
2559 for (i = 0; i < adev->num_ip_blocks; i++) {
2560 if (!adev->ip_blocks[i].status.hw)
2562 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2563 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2564 /* XXX handle errors */
2566 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2567 adev->ip_blocks[i].version->funcs->name, r);
2569 adev->ip_blocks[i].status.hw = false;
2574 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2575 if (!adev->ip_blocks[i].status.hw)
2578 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2579 /* XXX handle errors */
2581 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2582 adev->ip_blocks[i].version->funcs->name, r);
2585 adev->ip_blocks[i].status.hw = false;
2589 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2590 if (!adev->ip_blocks[i].status.sw)
2593 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2594 amdgpu_ucode_free_bo(adev);
2595 amdgpu_free_static_csa(&adev->virt.csa_obj);
2596 amdgpu_device_wb_fini(adev);
2597 amdgpu_device_vram_scratch_fini(adev);
2598 amdgpu_ib_pool_fini(adev);
2601 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2602 /* XXX handle errors */
2604 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2605 adev->ip_blocks[i].version->funcs->name, r);
2607 adev->ip_blocks[i].status.sw = false;
2608 adev->ip_blocks[i].status.valid = false;
2611 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2612 if (!adev->ip_blocks[i].status.late_initialized)
2614 if (adev->ip_blocks[i].version->funcs->late_fini)
2615 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2616 adev->ip_blocks[i].status.late_initialized = false;
2619 amdgpu_ras_fini(adev);
2621 if (amdgpu_sriov_vf(adev))
2622 if (amdgpu_virt_release_full_gpu(adev, false))
2623 DRM_ERROR("failed to release exclusive mode on fini\n");
2629 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2631 * @work: work_struct.
2633 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2635 struct amdgpu_device *adev =
2636 container_of(work, struct amdgpu_device, delayed_init_work.work);
2639 r = amdgpu_ib_ring_tests(adev);
2641 DRM_ERROR("ib ring test failed (%d).\n", r);
2644 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2646 struct amdgpu_device *adev =
2647 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2649 mutex_lock(&adev->gfx.gfx_off_mutex);
2650 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2651 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2652 adev->gfx.gfx_off_state = true;
2654 mutex_unlock(&adev->gfx.gfx_off_mutex);
2658 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2660 * @adev: amdgpu_device pointer
2662 * Main suspend function for hardware IPs. The list of all the hardware
2663 * IPs that make up the asic is walked, clockgating is disabled and the
2664 * suspend callbacks are run. suspend puts the hardware and software state
2665 * in each IP into a state suitable for suspend.
2666 * Returns 0 on success, negative error code on failure.
2668 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2672 if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) {
2673 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2674 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2677 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2678 if (!adev->ip_blocks[i].status.valid)
2681 /* displays are handled separately */
2682 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2685 /* XXX handle errors */
2686 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2687 /* XXX handle errors */
2689 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2690 adev->ip_blocks[i].version->funcs->name, r);
2694 adev->ip_blocks[i].status.hw = false;
2701 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2703 * @adev: amdgpu_device pointer
2705 * Main suspend function for hardware IPs. The list of all the hardware
2706 * IPs that make up the asic is walked, clockgating is disabled and the
2707 * suspend callbacks are run. suspend puts the hardware and software state
2708 * in each IP into a state suitable for suspend.
2709 * Returns 0 on success, negative error code on failure.
2711 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2715 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2716 if (!adev->ip_blocks[i].status.valid)
2718 /* displays are handled in phase1 */
2719 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2721 /* PSP lost connection when err_event_athub occurs */
2722 if (amdgpu_ras_intr_triggered() &&
2723 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2724 adev->ip_blocks[i].status.hw = false;
2727 /* XXX handle errors */
2728 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2729 /* XXX handle errors */
2731 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2732 adev->ip_blocks[i].version->funcs->name, r);
2734 adev->ip_blocks[i].status.hw = false;
2735 /* handle putting the SMC in the appropriate state */
2736 if(!amdgpu_sriov_vf(adev)){
2737 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2738 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
2740 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2741 adev->mp1_state, r);
2746 adev->ip_blocks[i].status.hw = false;
2753 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2755 * @adev: amdgpu_device pointer
2757 * Main suspend function for hardware IPs. The list of all the hardware
2758 * IPs that make up the asic is walked, clockgating is disabled and the
2759 * suspend callbacks are run. suspend puts the hardware and software state
2760 * in each IP into a state suitable for suspend.
2761 * Returns 0 on success, negative error code on failure.
2763 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2767 if (amdgpu_sriov_vf(adev))
2768 amdgpu_virt_request_full_gpu(adev, false);
2770 r = amdgpu_device_ip_suspend_phase1(adev);
2773 r = amdgpu_device_ip_suspend_phase2(adev);
2775 if (amdgpu_sriov_vf(adev))
2776 amdgpu_virt_release_full_gpu(adev, false);
2781 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2785 static enum amd_ip_block_type ip_order[] = {
2786 AMD_IP_BLOCK_TYPE_GMC,
2787 AMD_IP_BLOCK_TYPE_COMMON,
2788 AMD_IP_BLOCK_TYPE_PSP,
2789 AMD_IP_BLOCK_TYPE_IH,
2792 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2794 struct amdgpu_ip_block *block;
2796 block = &adev->ip_blocks[i];
2797 block->status.hw = false;
2799 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
2801 if (block->version->type != ip_order[j] ||
2802 !block->status.valid)
2805 r = block->version->funcs->hw_init(adev);
2806 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2809 block->status.hw = true;
2816 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2820 static enum amd_ip_block_type ip_order[] = {
2821 AMD_IP_BLOCK_TYPE_SMC,
2822 AMD_IP_BLOCK_TYPE_DCE,
2823 AMD_IP_BLOCK_TYPE_GFX,
2824 AMD_IP_BLOCK_TYPE_SDMA,
2825 AMD_IP_BLOCK_TYPE_UVD,
2826 AMD_IP_BLOCK_TYPE_VCE,
2827 AMD_IP_BLOCK_TYPE_VCN
2830 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2832 struct amdgpu_ip_block *block;
2834 for (j = 0; j < adev->num_ip_blocks; j++) {
2835 block = &adev->ip_blocks[j];
2837 if (block->version->type != ip_order[i] ||
2838 !block->status.valid ||
2842 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
2843 r = block->version->funcs->resume(adev);
2845 r = block->version->funcs->hw_init(adev);
2847 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2850 block->status.hw = true;
2858 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2860 * @adev: amdgpu_device pointer
2862 * First resume function for hardware IPs. The list of all the hardware
2863 * IPs that make up the asic is walked and the resume callbacks are run for
2864 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2865 * after a suspend and updates the software state as necessary. This
2866 * function is also used for restoring the GPU after a GPU reset.
2867 * Returns 0 on success, negative error code on failure.
2869 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2873 for (i = 0; i < adev->num_ip_blocks; i++) {
2874 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2876 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2877 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2878 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2880 r = adev->ip_blocks[i].version->funcs->resume(adev);
2882 DRM_ERROR("resume of IP block <%s> failed %d\n",
2883 adev->ip_blocks[i].version->funcs->name, r);
2886 adev->ip_blocks[i].status.hw = true;
2894 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2896 * @adev: amdgpu_device pointer
2898 * First resume function for hardware IPs. The list of all the hardware
2899 * IPs that make up the asic is walked and the resume callbacks are run for
2900 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2901 * functional state after a suspend and updates the software state as
2902 * necessary. This function is also used for restoring the GPU after a GPU
2904 * Returns 0 on success, negative error code on failure.
2906 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2910 for (i = 0; i < adev->num_ip_blocks; i++) {
2911 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2913 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2914 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2915 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2916 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2918 r = adev->ip_blocks[i].version->funcs->resume(adev);
2920 DRM_ERROR("resume of IP block <%s> failed %d\n",
2921 adev->ip_blocks[i].version->funcs->name, r);
2924 adev->ip_blocks[i].status.hw = true;
2931 * amdgpu_device_ip_resume - run resume for hardware IPs
2933 * @adev: amdgpu_device pointer
2935 * Main resume function for hardware IPs. The hardware IPs
2936 * are split into two resume functions because they are
2937 * are also used in in recovering from a GPU reset and some additional
2938 * steps need to be take between them. In this case (S3/S4) they are
2940 * Returns 0 on success, negative error code on failure.
2942 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2946 r = amdgpu_device_ip_resume_phase1(adev);
2950 r = amdgpu_device_fw_loading(adev);
2954 r = amdgpu_device_ip_resume_phase2(adev);
2960 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2962 * @adev: amdgpu_device pointer
2964 * Query the VBIOS data tables to determine if the board supports SR-IOV.
2966 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2968 if (amdgpu_sriov_vf(adev)) {
2969 if (adev->is_atom_fw) {
2970 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2971 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2973 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2974 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2977 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2978 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2983 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2985 * @asic_type: AMD asic type
2987 * Check if there is DC (new modesetting infrastructre) support for an asic.
2988 * returns true if DC has support, false if not.
2990 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2992 switch (asic_type) {
2993 #if defined(CONFIG_DRM_AMD_DC)
2994 #if defined(CONFIG_DRM_AMD_DC_SI)
3005 * We have systems in the wild with these ASICs that require
3006 * LVDS and VGA support which is not supported with DC.
3008 * Fallback to the non-DC driver here by default so as not to
3009 * cause regressions.
3011 return amdgpu_dc > 0;
3015 case CHIP_POLARIS10:
3016 case CHIP_POLARIS11:
3017 case CHIP_POLARIS12:
3024 #if defined(CONFIG_DRM_AMD_DC_DCN)
3030 case CHIP_SIENNA_CICHLID:
3031 case CHIP_NAVY_FLOUNDER:
3032 case CHIP_DIMGREY_CAVEFISH:
3035 return amdgpu_dc != 0;
3039 DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
3040 "but isn't supported by ASIC, ignoring\n");
3046 * amdgpu_device_has_dc_support - check if dc is supported
3048 * @adev: amdgpu_device pointer
3050 * Returns true for supported, false for not supported
3052 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3054 if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display)
3057 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3061 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3063 struct amdgpu_device *adev =
3064 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3065 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3067 /* It's a bug to not have a hive within this function */
3072 * Use task barrier to synchronize all xgmi reset works across the
3073 * hive. task_barrier_enter and task_barrier_exit will block
3074 * until all the threads running the xgmi reset works reach
3075 * those points. task_barrier_full will do both blocks.
3077 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3079 task_barrier_enter(&hive->tb);
3080 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3082 if (adev->asic_reset_res)
3085 task_barrier_exit(&hive->tb);
3086 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3088 if (adev->asic_reset_res)
3091 if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
3092 adev->mmhub.funcs->reset_ras_error_count(adev);
3095 task_barrier_full(&hive->tb);
3096 adev->asic_reset_res = amdgpu_asic_reset(adev);
3100 if (adev->asic_reset_res)
3101 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3102 adev->asic_reset_res, adev_to_drm(adev)->unique);
3103 amdgpu_put_xgmi_hive(hive);
3106 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3108 char *input = amdgpu_lockup_timeout;
3109 char *timeout_setting = NULL;
3115 * By default timeout for non compute jobs is 10000.
3116 * And there is no timeout enforced on compute jobs.
3117 * In SR-IOV or passthrough mode, timeout for compute
3118 * jobs are 60000 by default.
3120 adev->gfx_timeout = msecs_to_jiffies(10000);
3121 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3122 if (amdgpu_sriov_vf(adev))
3123 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3124 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3125 else if (amdgpu_passthrough(adev))
3126 adev->compute_timeout = msecs_to_jiffies(60000);
3128 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
3130 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3131 while ((timeout_setting = strsep(&input, ",")) &&
3132 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3133 ret = kstrtol(timeout_setting, 0, &timeout);
3140 } else if (timeout < 0) {
3141 timeout = MAX_SCHEDULE_TIMEOUT;
3143 timeout = msecs_to_jiffies(timeout);
3148 adev->gfx_timeout = timeout;
3151 adev->compute_timeout = timeout;
3154 adev->sdma_timeout = timeout;
3157 adev->video_timeout = timeout;
3164 * There is only one value specified and
3165 * it should apply to all non-compute jobs.
3168 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3169 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3170 adev->compute_timeout = adev->gfx_timeout;
3177 static const struct attribute *amdgpu_dev_attributes[] = {
3178 &dev_attr_product_name.attr,
3179 &dev_attr_product_number.attr,
3180 &dev_attr_serial_number.attr,
3181 &dev_attr_pcie_replay_count.attr,
3187 * amdgpu_device_init - initialize the driver
3189 * @adev: amdgpu_device pointer
3190 * @flags: driver flags
3192 * Initializes the driver info and hw (all asics).
3193 * Returns 0 for success or an error on failure.
3194 * Called at driver startup.
3196 int amdgpu_device_init(struct amdgpu_device *adev,
3199 struct drm_device *ddev = adev_to_drm(adev);
3200 struct pci_dev *pdev = adev->pdev;
3205 adev->shutdown = false;
3206 adev->flags = flags;
3208 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3209 adev->asic_type = amdgpu_force_asic_type;
3211 adev->asic_type = flags & AMD_ASIC_MASK;
3213 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3214 if (amdgpu_emu_mode == 1)
3215 adev->usec_timeout *= 10;
3216 adev->gmc.gart_size = 512 * 1024 * 1024;
3217 adev->accel_working = false;
3218 adev->num_rings = 0;
3219 adev->mman.buffer_funcs = NULL;
3220 adev->mman.buffer_funcs_ring = NULL;
3221 adev->vm_manager.vm_pte_funcs = NULL;
3222 adev->vm_manager.vm_pte_num_scheds = 0;
3223 adev->gmc.gmc_funcs = NULL;
3224 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3225 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3227 adev->smc_rreg = &amdgpu_invalid_rreg;
3228 adev->smc_wreg = &amdgpu_invalid_wreg;
3229 adev->pcie_rreg = &amdgpu_invalid_rreg;
3230 adev->pcie_wreg = &amdgpu_invalid_wreg;
3231 adev->pciep_rreg = &amdgpu_invalid_rreg;
3232 adev->pciep_wreg = &amdgpu_invalid_wreg;
3233 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3234 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3235 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3236 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3237 adev->didt_rreg = &amdgpu_invalid_rreg;
3238 adev->didt_wreg = &amdgpu_invalid_wreg;
3239 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3240 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3241 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3242 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3244 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3245 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3246 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3248 /* mutex initialization are all done here so we
3249 * can recall function without having locking issues */
3250 atomic_set(&adev->irq.ih.lock, 0);
3251 mutex_init(&adev->firmware.mutex);
3252 mutex_init(&adev->pm.mutex);
3253 mutex_init(&adev->gfx.gpu_clock_mutex);
3254 mutex_init(&adev->srbm_mutex);
3255 mutex_init(&adev->gfx.pipe_reserve_mutex);
3256 mutex_init(&adev->gfx.gfx_off_mutex);
3257 mutex_init(&adev->grbm_idx_mutex);
3258 mutex_init(&adev->mn_lock);
3259 mutex_init(&adev->virt.vf_errors.lock);
3260 hash_init(adev->mn_hash);
3261 atomic_set(&adev->in_gpu_reset, 0);
3262 init_rwsem(&adev->reset_sem);
3263 mutex_init(&adev->psp.mutex);
3264 mutex_init(&adev->notifier_lock);
3266 r = amdgpu_device_check_arguments(adev);
3270 spin_lock_init(&adev->mmio_idx_lock);
3271 spin_lock_init(&adev->smc_idx_lock);
3272 spin_lock_init(&adev->pcie_idx_lock);
3273 spin_lock_init(&adev->uvd_ctx_idx_lock);
3274 spin_lock_init(&adev->didt_idx_lock);
3275 spin_lock_init(&adev->gc_cac_idx_lock);
3276 spin_lock_init(&adev->se_cac_idx_lock);
3277 spin_lock_init(&adev->audio_endpt_idx_lock);
3278 spin_lock_init(&adev->mm_stats.lock);
3280 INIT_LIST_HEAD(&adev->shadow_list);
3281 mutex_init(&adev->shadow_list_lock);
3283 INIT_DELAYED_WORK(&adev->delayed_init_work,
3284 amdgpu_device_delayed_init_work_handler);
3285 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3286 amdgpu_device_delay_enable_gfx_off);
3288 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3290 adev->gfx.gfx_off_req_count = 1;
3291 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3293 atomic_set(&adev->throttling_logging_enabled, 1);
3295 * If throttling continues, logging will be performed every minute
3296 * to avoid log flooding. "-1" is subtracted since the thermal
3297 * throttling interrupt comes every second. Thus, the total logging
3298 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3299 * for throttling interrupt) = 60 seconds.
3301 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3302 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3304 /* Registers mapping */
3305 /* TODO: block userspace mapping of io register */
3306 if (adev->asic_type >= CHIP_BONAIRE) {
3307 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3308 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3310 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3311 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3314 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3315 if (adev->rmmio == NULL) {
3318 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3319 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3321 /* io port mapping */
3322 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3323 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
3324 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
3325 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
3329 if (adev->rio_mem == NULL)
3330 DRM_INFO("PCI I/O BAR is not found.\n");
3332 /* enable PCIE atomic ops */
3333 r = pci_enable_atomic_ops_to_root(adev->pdev,
3334 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3335 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3337 adev->have_atomics_support = false;
3338 DRM_INFO("PCIE atomic ops is not supported\n");
3340 adev->have_atomics_support = true;
3343 amdgpu_device_get_pcie_info(adev);
3346 DRM_INFO("MCBP is enabled\n");
3348 if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
3349 adev->enable_mes = true;
3351 /* detect hw virtualization here */
3352 amdgpu_detect_virtualization(adev);
3354 r = amdgpu_device_get_job_timeout_settings(adev);
3356 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3360 /* early init functions */
3361 r = amdgpu_device_ip_early_init(adev);
3365 /* doorbell bar mapping and doorbell index init*/
3366 amdgpu_device_doorbell_init(adev);
3368 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3369 /* this will fail for cards that aren't VGA class devices, just
3371 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3372 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
3374 if (amdgpu_device_supports_atpx(ddev))
3376 if (amdgpu_has_atpx() &&
3377 (amdgpu_is_atpx_hybrid() ||
3378 amdgpu_has_atpx_dgpu_power_cntl()) &&
3379 !pci_is_thunderbolt_attached(adev->pdev))
3380 vga_switcheroo_register_client(adev->pdev,
3381 &amdgpu_switcheroo_ops, atpx);
3383 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3385 if (amdgpu_emu_mode == 1) {
3386 /* post the asic on emulation mode */
3387 emu_soc_asic_init(adev);
3388 goto fence_driver_init;
3391 /* detect if we are with an SRIOV vbios */
3392 amdgpu_device_detect_sriov_bios(adev);
3394 /* check if we need to reset the asic
3395 * E.g., driver was not cleanly unloaded previously, etc.
3397 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3398 r = amdgpu_asic_reset(adev);
3400 dev_err(adev->dev, "asic reset on init failed\n");
3405 pci_enable_pcie_error_reporting(adev->pdev);
3407 /* Post card if necessary */
3408 if (amdgpu_device_need_post(adev)) {
3410 dev_err(adev->dev, "no vBIOS found\n");
3414 DRM_INFO("GPU posting now...\n");
3415 r = amdgpu_device_asic_init(adev);
3417 dev_err(adev->dev, "gpu post error!\n");
3422 if (adev->is_atom_fw) {
3423 /* Initialize clocks */
3424 r = amdgpu_atomfirmware_get_clock_info(adev);
3426 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3427 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3431 /* Initialize clocks */
3432 r = amdgpu_atombios_get_clock_info(adev);
3434 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3435 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3438 /* init i2c buses */
3439 if (!amdgpu_device_has_dc_support(adev))
3440 amdgpu_atombios_i2c_init(adev);
3445 r = amdgpu_fence_driver_init(adev);
3447 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
3448 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3452 /* init the mode config */
3453 drm_mode_config_init(adev_to_drm(adev));
3455 r = amdgpu_device_ip_init(adev);
3457 /* failed in exclusive mode due to timeout */
3458 if (amdgpu_sriov_vf(adev) &&
3459 !amdgpu_sriov_runtime(adev) &&
3460 amdgpu_virt_mmio_blocked(adev) &&
3461 !amdgpu_virt_wait_reset(adev)) {
3462 dev_err(adev->dev, "VF exclusive mode timeout\n");
3463 /* Don't send request since VF is inactive. */
3464 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3465 adev->virt.ops = NULL;
3469 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3470 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3475 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3476 adev->gfx.config.max_shader_engines,
3477 adev->gfx.config.max_sh_per_se,
3478 adev->gfx.config.max_cu_per_sh,
3479 adev->gfx.cu_info.number);
3481 adev->accel_working = true;
3483 amdgpu_vm_check_compute_bug(adev);
3485 /* Initialize the buffer migration limit. */
3486 if (amdgpu_moverate >= 0)
3487 max_MBps = amdgpu_moverate;
3489 max_MBps = 8; /* Allow 8 MB/s. */
3490 /* Get a log2 for easy divisions. */
3491 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3493 amdgpu_fbdev_init(adev);
3495 r = amdgpu_pm_sysfs_init(adev);
3497 adev->pm_sysfs_en = false;
3498 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3500 adev->pm_sysfs_en = true;
3502 r = amdgpu_ucode_sysfs_init(adev);
3504 adev->ucode_sysfs_en = false;
3505 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3507 adev->ucode_sysfs_en = true;
3509 if ((amdgpu_testing & 1)) {
3510 if (adev->accel_working)
3511 amdgpu_test_moves(adev);
3513 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
3515 if (amdgpu_benchmarking) {
3516 if (adev->accel_working)
3517 amdgpu_benchmark(adev, amdgpu_benchmarking);
3519 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
3523 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3524 * Otherwise the mgpu fan boost feature will be skipped due to the
3525 * gpu instance is counted less.
3527 amdgpu_register_gpu_instance(adev);
3529 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3530 * explicit gating rather than handling it automatically.
3532 r = amdgpu_device_ip_late_init(adev);
3534 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3535 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3540 amdgpu_ras_resume(adev);
3542 queue_delayed_work(system_wq, &adev->delayed_init_work,
3543 msecs_to_jiffies(AMDGPU_RESUME_MS));
3545 if (amdgpu_sriov_vf(adev))
3546 flush_delayed_work(&adev->delayed_init_work);
3548 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3550 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3552 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3553 r = amdgpu_pmu_init(adev);
3555 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3557 /* Have stored pci confspace at hand for restore in sudden PCI error */
3558 if (amdgpu_device_cache_pci_state(adev->pdev))
3559 pci_restore_state(pdev);
3564 amdgpu_vf_error_trans_all(adev);
3566 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3569 iounmap(adev->rmmio);
3576 * amdgpu_device_fini - tear down the driver
3578 * @adev: amdgpu_device pointer
3580 * Tear down the driver info (all asics).
3581 * Called at driver shutdown.
3583 void amdgpu_device_fini(struct amdgpu_device *adev)
3585 dev_info(adev->dev, "amdgpu: finishing device.\n");
3586 flush_delayed_work(&adev->delayed_init_work);
3587 adev->shutdown = true;
3589 kfree(adev->pci_state);
3591 /* make sure IB test finished before entering exclusive mode
3592 * to avoid preemption on IB test
3594 if (amdgpu_sriov_vf(adev)) {
3595 amdgpu_virt_request_full_gpu(adev, false);
3596 amdgpu_virt_fini_data_exchange(adev);
3599 /* disable all interrupts */
3600 amdgpu_irq_disable_all(adev);
3601 if (adev->mode_info.mode_config_initialized){
3602 if (!amdgpu_device_has_dc_support(adev))
3603 drm_helper_force_disable_all(adev_to_drm(adev));
3605 drm_atomic_helper_shutdown(adev_to_drm(adev));
3607 amdgpu_fence_driver_fini(adev);
3608 if (adev->pm_sysfs_en)
3609 amdgpu_pm_sysfs_fini(adev);
3610 amdgpu_fbdev_fini(adev);
3611 amdgpu_device_ip_fini(adev);
3612 release_firmware(adev->firmware.gpu_info_fw);
3613 adev->firmware.gpu_info_fw = NULL;
3614 adev->accel_working = false;
3615 /* free i2c buses */
3616 if (!amdgpu_device_has_dc_support(adev))
3617 amdgpu_i2c_fini(adev);
3619 if (amdgpu_emu_mode != 1)
3620 amdgpu_atombios_fini(adev);
3624 if (amdgpu_has_atpx() &&
3625 (amdgpu_is_atpx_hybrid() ||
3626 amdgpu_has_atpx_dgpu_power_cntl()) &&
3627 !pci_is_thunderbolt_attached(adev->pdev))
3628 vga_switcheroo_unregister_client(adev->pdev);
3629 if (amdgpu_device_supports_atpx(adev_to_drm(adev)))
3630 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3631 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3632 vga_client_register(adev->pdev, NULL, NULL, NULL);
3634 pci_iounmap(adev->pdev, adev->rio_mem);
3635 adev->rio_mem = NULL;
3636 iounmap(adev->rmmio);
3638 amdgpu_device_doorbell_fini(adev);
3640 if (adev->ucode_sysfs_en)
3641 amdgpu_ucode_sysfs_fini(adev);
3643 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
3644 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3645 amdgpu_pmu_fini(adev);
3646 if (adev->mman.discovery_bin)
3647 amdgpu_discovery_fini(adev);
3655 * amdgpu_device_suspend - initiate device suspend
3657 * @dev: drm dev pointer
3658 * @fbcon : notify the fbdev of suspend
3660 * Puts the hw in the suspend state (all asics).
3661 * Returns 0 for success or an error on failure.
3662 * Called at driver suspend.
3664 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
3666 struct amdgpu_device *adev;
3667 struct drm_crtc *crtc;
3668 struct drm_connector *connector;
3669 struct drm_connector_list_iter iter;
3672 adev = drm_to_adev(dev);
3674 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3677 adev->in_suspend = true;
3678 drm_kms_helper_poll_disable(dev);
3681 amdgpu_fbdev_set_suspend(adev, 1);
3683 cancel_delayed_work_sync(&adev->delayed_init_work);
3685 if (!amdgpu_device_has_dc_support(adev)) {
3686 /* turn off display hw */
3687 drm_modeset_lock_all(dev);
3688 drm_connector_list_iter_begin(dev, &iter);
3689 drm_for_each_connector_iter(connector, &iter)
3690 drm_helper_connector_dpms(connector,
3692 drm_connector_list_iter_end(&iter);
3693 drm_modeset_unlock_all(dev);
3694 /* unpin the front buffers and cursors */
3695 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3696 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3697 struct drm_framebuffer *fb = crtc->primary->fb;
3698 struct amdgpu_bo *robj;
3700 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3701 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3702 r = amdgpu_bo_reserve(aobj, true);
3704 amdgpu_bo_unpin(aobj);
3705 amdgpu_bo_unreserve(aobj);
3709 if (fb == NULL || fb->obj[0] == NULL) {
3712 robj = gem_to_amdgpu_bo(fb->obj[0]);
3713 /* don't unpin kernel fb objects */
3714 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
3715 r = amdgpu_bo_reserve(robj, true);
3717 amdgpu_bo_unpin(robj);
3718 amdgpu_bo_unreserve(robj);
3724 amdgpu_ras_suspend(adev);
3726 r = amdgpu_device_ip_suspend_phase1(adev);
3728 amdgpu_amdkfd_suspend(adev, !fbcon);
3730 /* evict vram memory */
3731 amdgpu_bo_evict_vram(adev);
3733 amdgpu_fence_driver_suspend(adev);
3735 if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev))
3736 r = amdgpu_device_ip_suspend_phase2(adev);
3738 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
3739 /* evict remaining vram memory
3740 * This second call to evict vram is to evict the gart page table
3743 amdgpu_bo_evict_vram(adev);
3749 * amdgpu_device_resume - initiate device resume
3751 * @dev: drm dev pointer
3752 * @fbcon : notify the fbdev of resume
3754 * Bring the hw back to operating state (all asics).
3755 * Returns 0 for success or an error on failure.
3756 * Called at driver resume.
3758 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
3760 struct drm_connector *connector;
3761 struct drm_connector_list_iter iter;
3762 struct amdgpu_device *adev = drm_to_adev(dev);
3763 struct drm_crtc *crtc;
3766 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3769 if (amdgpu_acpi_is_s0ix_supported(adev))
3770 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
3773 if (amdgpu_device_need_post(adev)) {
3774 r = amdgpu_device_asic_init(adev);
3776 dev_err(adev->dev, "amdgpu asic init failed\n");
3779 r = amdgpu_device_ip_resume(adev);
3781 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
3784 amdgpu_fence_driver_resume(adev);
3787 r = amdgpu_device_ip_late_init(adev);
3791 queue_delayed_work(system_wq, &adev->delayed_init_work,
3792 msecs_to_jiffies(AMDGPU_RESUME_MS));
3794 if (!amdgpu_device_has_dc_support(adev)) {
3796 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3797 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3799 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3800 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3801 r = amdgpu_bo_reserve(aobj, true);
3803 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3805 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
3806 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3807 amdgpu_bo_unreserve(aobj);
3812 r = amdgpu_amdkfd_resume(adev, !fbcon);
3816 /* Make sure IB tests flushed */
3817 flush_delayed_work(&adev->delayed_init_work);
3819 /* blat the mode back in */
3821 if (!amdgpu_device_has_dc_support(adev)) {
3823 drm_helper_resume_force_mode(dev);
3825 /* turn on display hw */
3826 drm_modeset_lock_all(dev);
3828 drm_connector_list_iter_begin(dev, &iter);
3829 drm_for_each_connector_iter(connector, &iter)
3830 drm_helper_connector_dpms(connector,
3832 drm_connector_list_iter_end(&iter);
3834 drm_modeset_unlock_all(dev);
3836 amdgpu_fbdev_set_suspend(adev, 0);
3839 drm_kms_helper_poll_enable(dev);
3841 amdgpu_ras_resume(adev);
3844 * Most of the connector probing functions try to acquire runtime pm
3845 * refs to ensure that the GPU is powered on when connector polling is
3846 * performed. Since we're calling this from a runtime PM callback,
3847 * trying to acquire rpm refs will cause us to deadlock.
3849 * Since we're guaranteed to be holding the rpm lock, it's safe to
3850 * temporarily disable the rpm helpers so this doesn't deadlock us.
3853 dev->dev->power.disable_depth++;
3855 if (!amdgpu_device_has_dc_support(adev))
3856 drm_helper_hpd_irq_event(dev);
3858 drm_kms_helper_hotplug_event(dev);
3860 dev->dev->power.disable_depth--;
3862 adev->in_suspend = false;
3868 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3870 * @adev: amdgpu_device pointer
3872 * The list of all the hardware IPs that make up the asic is walked and
3873 * the check_soft_reset callbacks are run. check_soft_reset determines
3874 * if the asic is still hung or not.
3875 * Returns true if any of the IPs are still in a hung state, false if not.
3877 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3880 bool asic_hang = false;
3882 if (amdgpu_sriov_vf(adev))
3885 if (amdgpu_asic_need_full_reset(adev))
3888 for (i = 0; i < adev->num_ip_blocks; i++) {
3889 if (!adev->ip_blocks[i].status.valid)
3891 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3892 adev->ip_blocks[i].status.hang =
3893 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3894 if (adev->ip_blocks[i].status.hang) {
3895 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3903 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3905 * @adev: amdgpu_device pointer
3907 * The list of all the hardware IPs that make up the asic is walked and the
3908 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3909 * handles any IP specific hardware or software state changes that are
3910 * necessary for a soft reset to succeed.
3911 * Returns 0 on success, negative error code on failure.
3913 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3917 for (i = 0; i < adev->num_ip_blocks; i++) {
3918 if (!adev->ip_blocks[i].status.valid)
3920 if (adev->ip_blocks[i].status.hang &&
3921 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3922 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3932 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3934 * @adev: amdgpu_device pointer
3936 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
3937 * reset is necessary to recover.
3938 * Returns true if a full asic reset is required, false if not.
3940 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3944 if (amdgpu_asic_need_full_reset(adev))
3947 for (i = 0; i < adev->num_ip_blocks; i++) {
3948 if (!adev->ip_blocks[i].status.valid)
3950 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3951 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3952 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3953 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3954 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3955 if (adev->ip_blocks[i].status.hang) {
3956 dev_info(adev->dev, "Some block need full reset!\n");
3965 * amdgpu_device_ip_soft_reset - do a soft reset
3967 * @adev: amdgpu_device pointer
3969 * The list of all the hardware IPs that make up the asic is walked and the
3970 * soft_reset callbacks are run if the block is hung. soft_reset handles any
3971 * IP specific hardware or software state changes that are necessary to soft
3973 * Returns 0 on success, negative error code on failure.
3975 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3979 for (i = 0; i < adev->num_ip_blocks; i++) {
3980 if (!adev->ip_blocks[i].status.valid)
3982 if (adev->ip_blocks[i].status.hang &&
3983 adev->ip_blocks[i].version->funcs->soft_reset) {
3984 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3994 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3996 * @adev: amdgpu_device pointer
3998 * The list of all the hardware IPs that make up the asic is walked and the
3999 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4000 * handles any IP specific hardware or software state changes that are
4001 * necessary after the IP has been soft reset.
4002 * Returns 0 on success, negative error code on failure.
4004 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4008 for (i = 0; i < adev->num_ip_blocks; i++) {
4009 if (!adev->ip_blocks[i].status.valid)
4011 if (adev->ip_blocks[i].status.hang &&
4012 adev->ip_blocks[i].version->funcs->post_soft_reset)
4013 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4022 * amdgpu_device_recover_vram - Recover some VRAM contents
4024 * @adev: amdgpu_device pointer
4026 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4027 * restore things like GPUVM page tables after a GPU reset where
4028 * the contents of VRAM might be lost.
4031 * 0 on success, negative error code on failure.
4033 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4035 struct dma_fence *fence = NULL, *next = NULL;
4036 struct amdgpu_bo *shadow;
4039 if (amdgpu_sriov_runtime(adev))
4040 tmo = msecs_to_jiffies(8000);
4042 tmo = msecs_to_jiffies(100);
4044 dev_info(adev->dev, "recover vram bo from shadow start\n");
4045 mutex_lock(&adev->shadow_list_lock);
4046 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
4048 /* No need to recover an evicted BO */
4049 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
4050 shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
4051 shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
4054 r = amdgpu_bo_restore_shadow(shadow, &next);
4059 tmo = dma_fence_wait_timeout(fence, false, tmo);
4060 dma_fence_put(fence);
4065 } else if (tmo < 0) {
4073 mutex_unlock(&adev->shadow_list_lock);
4076 tmo = dma_fence_wait_timeout(fence, false, tmo);
4077 dma_fence_put(fence);
4079 if (r < 0 || tmo <= 0) {
4080 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4084 dev_info(adev->dev, "recover vram bo from shadow done\n");
4090 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4092 * @adev: amdgpu_device pointer
4093 * @from_hypervisor: request from hypervisor
4095 * do VF FLR and reinitialize Asic
4096 * return 0 means succeeded otherwise failed
4098 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4099 bool from_hypervisor)
4103 if (from_hypervisor)
4104 r = amdgpu_virt_request_full_gpu(adev, true);
4106 r = amdgpu_virt_reset_gpu(adev);
4110 amdgpu_amdkfd_pre_reset(adev);
4112 /* Resume IP prior to SMC */
4113 r = amdgpu_device_ip_reinit_early_sriov(adev);
4117 amdgpu_virt_init_data_exchange(adev);
4118 /* we need recover gart prior to run SMC/CP/SDMA resume */
4119 amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
4121 r = amdgpu_device_fw_loading(adev);
4125 /* now we are okay to resume SMC/CP/SDMA */
4126 r = amdgpu_device_ip_reinit_late_sriov(adev);
4130 amdgpu_irq_gpu_reset_resume_helper(adev);
4131 r = amdgpu_ib_ring_tests(adev);
4132 amdgpu_amdkfd_post_reset(adev);
4135 amdgpu_virt_release_full_gpu(adev, true);
4136 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4137 amdgpu_inc_vram_lost(adev);
4138 r = amdgpu_device_recover_vram(adev);
4145 * amdgpu_device_has_job_running - check if there is any job in mirror list
4147 * @adev: amdgpu_device pointer
4149 * check if there is any job in mirror list
4151 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4154 struct drm_sched_job *job;
4156 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4157 struct amdgpu_ring *ring = adev->rings[i];
4159 if (!ring || !ring->sched.thread)
4162 spin_lock(&ring->sched.job_list_lock);
4163 job = list_first_entry_or_null(&ring->sched.pending_list,
4164 struct drm_sched_job, list);
4165 spin_unlock(&ring->sched.job_list_lock);
4173 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4175 * @adev: amdgpu_device pointer
4177 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4180 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4182 if (!amdgpu_device_ip_check_soft_reset(adev)) {
4183 dev_info(adev->dev, "Timeout, but no hardware hang detected.\n");
4187 if (amdgpu_gpu_recovery == 0)
4190 if (amdgpu_sriov_vf(adev))
4193 if (amdgpu_gpu_recovery == -1) {
4194 switch (adev->asic_type) {
4200 case CHIP_POLARIS10:
4201 case CHIP_POLARIS11:
4202 case CHIP_POLARIS12:
4213 case CHIP_SIENNA_CICHLID:
4214 case CHIP_NAVY_FLOUNDER:
4225 dev_info(adev->dev, "GPU recovery disabled.\n");
4230 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4231 struct amdgpu_job *job,
4232 bool *need_full_reset_arg)
4235 bool need_full_reset = *need_full_reset_arg;
4237 amdgpu_debugfs_wait_dump(adev);
4239 if (amdgpu_sriov_vf(adev)) {
4240 /* stop the data exchange thread */
4241 amdgpu_virt_fini_data_exchange(adev);
4244 /* block all schedulers and reset given job's ring */
4245 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4246 struct amdgpu_ring *ring = adev->rings[i];
4248 if (!ring || !ring->sched.thread)
4251 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4252 amdgpu_fence_driver_force_completion(ring);
4256 drm_sched_increase_karma(&job->base);
4258 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4259 if (!amdgpu_sriov_vf(adev)) {
4261 if (!need_full_reset)
4262 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4264 if (!need_full_reset) {
4265 amdgpu_device_ip_pre_soft_reset(adev);
4266 r = amdgpu_device_ip_soft_reset(adev);
4267 amdgpu_device_ip_post_soft_reset(adev);
4268 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4269 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4270 need_full_reset = true;
4274 if (need_full_reset)
4275 r = amdgpu_device_ip_suspend(adev);
4277 *need_full_reset_arg = need_full_reset;
4283 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
4284 struct list_head *device_list_handle,
4285 bool *need_full_reset_arg,
4288 struct amdgpu_device *tmp_adev = NULL;
4289 bool need_full_reset = *need_full_reset_arg, vram_lost = false;
4293 * ASIC reset has to be done on all HGMI hive nodes ASAP
4294 * to allow proper links negotiation in FW (within 1 sec)
4296 if (!skip_hw_reset && need_full_reset) {
4297 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4298 /* For XGMI run all resets in parallel to speed up the process */
4299 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4300 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4303 r = amdgpu_asic_reset(tmp_adev);
4306 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4307 r, adev_to_drm(tmp_adev)->unique);
4312 /* For XGMI wait for all resets to complete before proceed */
4314 list_for_each_entry(tmp_adev, device_list_handle,
4316 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4317 flush_work(&tmp_adev->xgmi_reset_work);
4318 r = tmp_adev->asic_reset_res;
4326 if (!r && amdgpu_ras_intr_triggered()) {
4327 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4328 if (tmp_adev->mmhub.funcs &&
4329 tmp_adev->mmhub.funcs->reset_ras_error_count)
4330 tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev);
4333 amdgpu_ras_intr_cleared();
4336 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4337 if (need_full_reset) {
4339 if (amdgpu_device_asic_init(tmp_adev))
4340 dev_warn(tmp_adev->dev, "asic atom init failed!");
4343 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4344 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4348 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4350 DRM_INFO("VRAM is lost due to GPU reset!\n");
4351 amdgpu_inc_vram_lost(tmp_adev);
4354 r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT));
4358 r = amdgpu_device_fw_loading(tmp_adev);
4362 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4367 amdgpu_device_fill_reset_magic(tmp_adev);
4370 * Add this ASIC as tracked as reset was already
4371 * complete successfully.
4373 amdgpu_register_gpu_instance(tmp_adev);
4375 r = amdgpu_device_ip_late_init(tmp_adev);
4379 amdgpu_fbdev_set_suspend(tmp_adev, 0);
4382 * The GPU enters bad state once faulty pages
4383 * by ECC has reached the threshold, and ras
4384 * recovery is scheduled next. So add one check
4385 * here to break recovery if it indeed exceeds
4386 * bad page threshold, and remind user to
4387 * retire this GPU or setting one bigger
4388 * bad_page_threshold value to fix this once
4389 * probing driver again.
4391 if (!amdgpu_ras_check_err_threshold(tmp_adev)) {
4393 amdgpu_ras_resume(tmp_adev);
4399 /* Update PSP FW topology after reset */
4400 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4401 r = amdgpu_xgmi_update_topology(hive, tmp_adev);
4407 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
4408 r = amdgpu_ib_ring_tests(tmp_adev);
4410 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
4411 r = amdgpu_device_ip_suspend(tmp_adev);
4412 need_full_reset = true;
4419 r = amdgpu_device_recover_vram(tmp_adev);
4421 tmp_adev->asic_reset_res = r;
4425 *need_full_reset_arg = need_full_reset;
4429 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev,
4430 struct amdgpu_hive_info *hive)
4432 if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)
4436 down_write_nest_lock(&adev->reset_sem, &hive->hive_lock);
4438 down_write(&adev->reset_sem);
4441 atomic_inc(&adev->gpu_reset_counter);
4442 switch (amdgpu_asic_reset_method(adev)) {
4443 case AMD_RESET_METHOD_MODE1:
4444 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
4446 case AMD_RESET_METHOD_MODE2:
4447 adev->mp1_state = PP_MP1_STATE_RESET;
4450 adev->mp1_state = PP_MP1_STATE_NONE;
4457 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
4459 amdgpu_vf_error_trans_all(adev);
4460 adev->mp1_state = PP_MP1_STATE_NONE;
4461 atomic_set(&adev->in_gpu_reset, 0);
4462 up_write(&adev->reset_sem);
4465 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
4467 struct pci_dev *p = NULL;
4469 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4470 adev->pdev->bus->number, 1);
4472 pm_runtime_enable(&(p->dev));
4473 pm_runtime_resume(&(p->dev));
4477 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
4479 enum amd_reset_method reset_method;
4480 struct pci_dev *p = NULL;
4484 * For now, only BACO and mode1 reset are confirmed
4485 * to suffer the audio issue without proper suspended.
4487 reset_method = amdgpu_asic_reset_method(adev);
4488 if ((reset_method != AMD_RESET_METHOD_BACO) &&
4489 (reset_method != AMD_RESET_METHOD_MODE1))
4492 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4493 adev->pdev->bus->number, 1);
4497 expires = pm_runtime_autosuspend_expiration(&(p->dev));
4500 * If we cannot get the audio device autosuspend delay,
4501 * a fixed 4S interval will be used. Considering 3S is
4502 * the audio controller default autosuspend delay setting.
4503 * 4S used here is guaranteed to cover that.
4505 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
4507 while (!pm_runtime_status_suspended(&(p->dev))) {
4508 if (!pm_runtime_suspend(&(p->dev)))
4511 if (expires < ktime_get_mono_fast_ns()) {
4512 dev_warn(adev->dev, "failed to suspend display audio\n");
4513 /* TODO: abort the succeeding gpu reset? */
4518 pm_runtime_disable(&(p->dev));
4524 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
4526 * @adev: amdgpu_device pointer
4527 * @job: which job trigger hang
4529 * Attempt to reset the GPU if it has hung (all asics).
4530 * Attempt to do soft-reset or full-reset and reinitialize Asic
4531 * Returns 0 for success or an error on failure.
4534 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
4535 struct amdgpu_job *job)
4537 struct list_head device_list, *device_list_handle = NULL;
4538 bool need_full_reset = false;
4539 bool job_signaled = false;
4540 struct amdgpu_hive_info *hive = NULL;
4541 struct amdgpu_device *tmp_adev = NULL;
4543 bool need_emergency_restart = false;
4544 bool audio_suspended = false;
4547 * Special case: RAS triggered and full reset isn't supported
4549 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
4552 * Flush RAM to disk so that after reboot
4553 * the user can read log and see why the system rebooted.
4555 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
4556 DRM_WARN("Emergency reboot.");
4559 emergency_restart();
4562 dev_info(adev->dev, "GPU %s begin!\n",
4563 need_emergency_restart ? "jobs stop":"reset");
4566 * Here we trylock to avoid chain of resets executing from
4567 * either trigger by jobs on different adevs in XGMI hive or jobs on
4568 * different schedulers for same device while this TO handler is running.
4569 * We always reset all schedulers for device and all devices for XGMI
4570 * hive so that should take care of them too.
4572 hive = amdgpu_get_xgmi_hive(adev);
4574 if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) {
4575 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
4576 job ? job->base.id : -1, hive->hive_id);
4577 amdgpu_put_xgmi_hive(hive);
4580 mutex_lock(&hive->hive_lock);
4584 * Build list of devices to reset.
4585 * In case we are in XGMI hive mode, resort the device list
4586 * to put adev in the 1st position.
4588 INIT_LIST_HEAD(&device_list);
4589 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4592 if (!list_is_first(&adev->gmc.xgmi.head, &hive->device_list))
4593 list_rotate_to_front(&adev->gmc.xgmi.head, &hive->device_list);
4594 device_list_handle = &hive->device_list;
4596 list_add_tail(&adev->gmc.xgmi.head, &device_list);
4597 device_list_handle = &device_list;
4600 /* block all schedulers and reset given job's ring */
4601 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4602 if (!amdgpu_device_lock_adev(tmp_adev, hive)) {
4603 dev_info(tmp_adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress",
4604 job ? job->base.id : -1);
4610 * Try to put the audio codec into suspend state
4611 * before gpu reset started.
4613 * Due to the power domain of the graphics device
4614 * is shared with AZ power domain. Without this,
4615 * we may change the audio hardware from behind
4616 * the audio driver's back. That will trigger
4617 * some audio codec errors.
4619 if (!amdgpu_device_suspend_display_audio(tmp_adev))
4620 audio_suspended = true;
4622 amdgpu_ras_set_error_query_ready(tmp_adev, false);
4624 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
4626 if (!amdgpu_sriov_vf(tmp_adev))
4627 amdgpu_amdkfd_pre_reset(tmp_adev);
4630 * Mark these ASICs to be reseted as untracked first
4631 * And add them back after reset completed
4633 amdgpu_unregister_gpu_instance(tmp_adev);
4635 amdgpu_fbdev_set_suspend(tmp_adev, 1);
4637 /* disable ras on ALL IPs */
4638 if (!need_emergency_restart &&
4639 amdgpu_device_ip_need_full_reset(tmp_adev))
4640 amdgpu_ras_suspend(tmp_adev);
4642 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4643 struct amdgpu_ring *ring = tmp_adev->rings[i];
4645 if (!ring || !ring->sched.thread)
4648 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
4650 if (need_emergency_restart)
4651 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
4655 if (need_emergency_restart)
4656 goto skip_sched_resume;
4659 * Must check guilty signal here since after this point all old
4660 * HW fences are force signaled.
4662 * job->base holds a reference to parent fence
4664 if (job && job->base.s_fence->parent &&
4665 dma_fence_is_signaled(job->base.s_fence->parent)) {
4666 job_signaled = true;
4667 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
4671 retry: /* Rest of adevs pre asic reset from XGMI hive. */
4672 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4673 r = amdgpu_device_pre_asic_reset(tmp_adev,
4674 (tmp_adev == adev) ? job : NULL,
4676 /*TODO Should we stop ?*/
4678 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
4679 r, adev_to_drm(tmp_adev)->unique);
4680 tmp_adev->asic_reset_res = r;
4684 /* Actual ASIC resets if needed.*/
4685 /* TODO Implement XGMI hive reset logic for SRIOV */
4686 if (amdgpu_sriov_vf(adev)) {
4687 r = amdgpu_device_reset_sriov(adev, job ? false : true);
4689 adev->asic_reset_res = r;
4691 r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset, false);
4692 if (r && r == -EAGAIN)
4698 /* Post ASIC reset for all devs .*/
4699 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4701 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4702 struct amdgpu_ring *ring = tmp_adev->rings[i];
4704 if (!ring || !ring->sched.thread)
4707 /* No point to resubmit jobs if we didn't HW reset*/
4708 if (!tmp_adev->asic_reset_res && !job_signaled)
4709 drm_sched_resubmit_jobs(&ring->sched);
4711 drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
4714 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
4715 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
4718 tmp_adev->asic_reset_res = 0;
4721 /* bad news, how to tell it to userspace ? */
4722 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
4723 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
4725 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
4730 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4731 /*unlock kfd: SRIOV would do it separately */
4732 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
4733 amdgpu_amdkfd_post_reset(tmp_adev);
4734 if (audio_suspended)
4735 amdgpu_device_resume_display_audio(tmp_adev);
4736 amdgpu_device_unlock_adev(tmp_adev);
4741 atomic_set(&hive->in_reset, 0);
4742 mutex_unlock(&hive->hive_lock);
4743 amdgpu_put_xgmi_hive(hive);
4747 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
4752 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
4754 * @adev: amdgpu_device pointer
4756 * Fetchs and stores in the driver the PCIE capabilities (gen speed
4757 * and lanes) of the slot the device is in. Handles APUs and
4758 * virtualized environments where PCIE config space may not be available.
4760 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
4762 struct pci_dev *pdev;
4763 enum pci_bus_speed speed_cap, platform_speed_cap;
4764 enum pcie_link_width platform_link_width;
4766 if (amdgpu_pcie_gen_cap)
4767 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
4769 if (amdgpu_pcie_lane_cap)
4770 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
4772 /* covers APUs as well */
4773 if (pci_is_root_bus(adev->pdev->bus)) {
4774 if (adev->pm.pcie_gen_mask == 0)
4775 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
4776 if (adev->pm.pcie_mlw_mask == 0)
4777 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4781 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
4784 pcie_bandwidth_available(adev->pdev, NULL,
4785 &platform_speed_cap, &platform_link_width);
4787 if (adev->pm.pcie_gen_mask == 0) {
4790 speed_cap = pcie_get_speed_cap(pdev);
4791 if (speed_cap == PCI_SPEED_UNKNOWN) {
4792 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4793 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4794 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4796 if (speed_cap == PCIE_SPEED_16_0GT)
4797 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4798 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4799 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4800 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
4801 else if (speed_cap == PCIE_SPEED_8_0GT)
4802 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4803 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4804 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4805 else if (speed_cap == PCIE_SPEED_5_0GT)
4806 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4807 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
4809 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
4812 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
4813 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4814 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4816 if (platform_speed_cap == PCIE_SPEED_16_0GT)
4817 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4818 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4819 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4820 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
4821 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
4822 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4823 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4824 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
4825 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
4826 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4827 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4829 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
4833 if (adev->pm.pcie_mlw_mask == 0) {
4834 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
4835 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
4837 switch (platform_link_width) {
4839 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
4840 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4841 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4842 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4843 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4844 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4845 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4848 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4849 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4850 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4851 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4852 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4853 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4856 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4857 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4858 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4859 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4860 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4863 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4864 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4865 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4866 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4869 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4870 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4871 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4874 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4875 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4878 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
4887 int amdgpu_device_baco_enter(struct drm_device *dev)
4889 struct amdgpu_device *adev = drm_to_adev(dev);
4890 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4892 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
4895 if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
4896 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
4898 return amdgpu_dpm_baco_enter(adev);
4901 int amdgpu_device_baco_exit(struct drm_device *dev)
4903 struct amdgpu_device *adev = drm_to_adev(dev);
4904 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4907 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
4910 ret = amdgpu_dpm_baco_exit(adev);
4914 if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
4915 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
4920 static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev)
4924 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4925 struct amdgpu_ring *ring = adev->rings[i];
4927 if (!ring || !ring->sched.thread)
4930 cancel_delayed_work_sync(&ring->sched.work_tdr);
4935 * amdgpu_pci_error_detected - Called when a PCI error is detected.
4936 * @pdev: PCI device struct
4937 * @state: PCI channel state
4939 * Description: Called when a PCI error is detected.
4941 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
4943 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4945 struct drm_device *dev = pci_get_drvdata(pdev);
4946 struct amdgpu_device *adev = drm_to_adev(dev);
4949 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
4951 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4952 DRM_WARN("No support for XGMI hive yet...");
4953 return PCI_ERS_RESULT_DISCONNECT;
4957 case pci_channel_io_normal:
4958 return PCI_ERS_RESULT_CAN_RECOVER;
4959 /* Fatal error, prepare for slot reset */
4960 case pci_channel_io_frozen:
4962 * Cancel and wait for all TDRs in progress if failing to
4963 * set adev->in_gpu_reset in amdgpu_device_lock_adev
4965 * Locking adev->reset_sem will prevent any external access
4966 * to GPU during PCI error recovery
4968 while (!amdgpu_device_lock_adev(adev, NULL))
4969 amdgpu_cancel_all_tdr(adev);
4972 * Block any work scheduling as we do for regular GPU reset
4973 * for the duration of the recovery
4975 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4976 struct amdgpu_ring *ring = adev->rings[i];
4978 if (!ring || !ring->sched.thread)
4981 drm_sched_stop(&ring->sched, NULL);
4983 return PCI_ERS_RESULT_NEED_RESET;
4984 case pci_channel_io_perm_failure:
4985 /* Permanent error, prepare for device removal */
4986 return PCI_ERS_RESULT_DISCONNECT;
4989 return PCI_ERS_RESULT_NEED_RESET;
4993 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
4994 * @pdev: pointer to PCI device
4996 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
4999 DRM_INFO("PCI error: mmio enabled callback!!\n");
5001 /* TODO - dump whatever for debugging purposes */
5003 /* This called only if amdgpu_pci_error_detected returns
5004 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
5005 * works, no need to reset slot.
5008 return PCI_ERS_RESULT_RECOVERED;
5012 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5013 * @pdev: PCI device struct
5015 * Description: This routine is called by the pci error recovery
5016 * code after the PCI slot has been reset, just before we
5017 * should resume normal operations.
5019 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5021 struct drm_device *dev = pci_get_drvdata(pdev);
5022 struct amdgpu_device *adev = drm_to_adev(dev);
5024 bool need_full_reset = true;
5026 struct list_head device_list;
5028 DRM_INFO("PCI error: slot reset callback!!\n");
5030 INIT_LIST_HEAD(&device_list);
5031 list_add_tail(&adev->gmc.xgmi.head, &device_list);
5033 /* wait for asic to come out of reset */
5036 /* Restore PCI confspace */
5037 amdgpu_device_load_pci_state(pdev);
5039 /* confirm ASIC came out of reset */
5040 for (i = 0; i < adev->usec_timeout; i++) {
5041 memsize = amdgpu_asic_get_config_memsize(adev);
5043 if (memsize != 0xffffffff)
5047 if (memsize == 0xffffffff) {
5052 adev->in_pci_err_recovery = true;
5053 r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset);
5054 adev->in_pci_err_recovery = false;
5058 r = amdgpu_do_asic_reset(NULL, &device_list, &need_full_reset, true);
5062 if (amdgpu_device_cache_pci_state(adev->pdev))
5063 pci_restore_state(adev->pdev);
5065 DRM_INFO("PCIe error recovery succeeded\n");
5067 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5068 amdgpu_device_unlock_adev(adev);
5071 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5075 * amdgpu_pci_resume() - resume normal ops after PCI reset
5076 * @pdev: pointer to PCI device
5078 * Called when the error recovery driver tells us that its
5079 * OK to resume normal operation.
5081 void amdgpu_pci_resume(struct pci_dev *pdev)
5083 struct drm_device *dev = pci_get_drvdata(pdev);
5084 struct amdgpu_device *adev = drm_to_adev(dev);
5088 DRM_INFO("PCI error: resume callback!!\n");
5090 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5091 struct amdgpu_ring *ring = adev->rings[i];
5093 if (!ring || !ring->sched.thread)
5097 drm_sched_resubmit_jobs(&ring->sched);
5098 drm_sched_start(&ring->sched, true);
5101 amdgpu_device_unlock_adev(adev);
5104 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5106 struct drm_device *dev = pci_get_drvdata(pdev);
5107 struct amdgpu_device *adev = drm_to_adev(dev);
5110 r = pci_save_state(pdev);
5112 kfree(adev->pci_state);
5114 adev->pci_state = pci_store_saved_state(pdev);
5116 if (!adev->pci_state) {
5117 DRM_ERROR("Failed to store PCI saved state");
5121 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5128 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5130 struct drm_device *dev = pci_get_drvdata(pdev);
5131 struct amdgpu_device *adev = drm_to_adev(dev);
5134 if (!adev->pci_state)
5137 r = pci_load_saved_state(pdev, adev->pci_state);
5140 pci_restore_state(pdev);
5142 DRM_WARN("Failed to load PCI state, err:%d\n", r);