2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
33 #include <linux/iommu.h>
34 #include <linux/pci.h>
35 #include <linux/devcoredump.h>
36 #include <generated/utsrelease.h>
37 #include <linux/pci-p2pdma.h>
38 #include <linux/apple-gmux.h>
40 #include <drm/drm_aperture.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_fb_helper.h>
44 #include <drm/drm_probe_helper.h>
45 #include <drm/amdgpu_drm.h>
46 #include <linux/vgaarb.h>
47 #include <linux/vga_switcheroo.h>
48 #include <linux/efi.h>
50 #include "amdgpu_trace.h"
51 #include "amdgpu_i2c.h"
53 #include "amdgpu_atombios.h"
54 #include "amdgpu_atomfirmware.h"
56 #ifdef CONFIG_DRM_AMDGPU_SI
59 #ifdef CONFIG_DRM_AMDGPU_CIK
65 #include "bif/bif_4_1_d.h"
66 #include <linux/firmware.h>
67 #include "amdgpu_vf_error.h"
69 #include "amdgpu_amdkfd.h"
70 #include "amdgpu_pm.h"
72 #include "amdgpu_xgmi.h"
73 #include "amdgpu_ras.h"
74 #include "amdgpu_pmu.h"
75 #include "amdgpu_fru_eeprom.h"
76 #include "amdgpu_reset.h"
78 #include <linux/suspend.h>
79 #include <drm/task_barrier.h>
80 #include <linux/pm_runtime.h>
82 #include <drm/drm_drv.h>
84 #if IS_ENABLED(CONFIG_X86)
85 #include <asm/intel-family.h>
88 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
89 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
90 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
91 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
92 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
93 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
94 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
96 #define AMDGPU_RESUME_MS 2000
97 #define AMDGPU_MAX_RETRY_LIMIT 2
98 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
100 static const struct drm_driver amdgpu_kms_driver;
102 const char *amdgpu_asic_name[] = {
144 * DOC: pcie_replay_count
146 * The amdgpu driver provides a sysfs API for reporting the total number
147 * of PCIe replays (NAKs)
148 * The file pcie_replay_count is used for this and returns the total
149 * number of replays as a sum of the NAKs generated and NAKs received
152 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
153 struct device_attribute *attr, char *buf)
155 struct drm_device *ddev = dev_get_drvdata(dev);
156 struct amdgpu_device *adev = drm_to_adev(ddev);
157 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
159 return sysfs_emit(buf, "%llu\n", cnt);
162 static DEVICE_ATTR(pcie_replay_count, 0444,
163 amdgpu_device_get_pcie_replay_count, NULL);
165 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
169 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
171 * @dev: drm_device pointer
173 * Returns true if the device is a dGPU with ATPX power control,
174 * otherwise return false.
176 bool amdgpu_device_supports_px(struct drm_device *dev)
178 struct amdgpu_device *adev = drm_to_adev(dev);
180 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
186 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
188 * @dev: drm_device pointer
190 * Returns true if the device is a dGPU with ACPI power control,
191 * otherwise return false.
193 bool amdgpu_device_supports_boco(struct drm_device *dev)
195 struct amdgpu_device *adev = drm_to_adev(dev);
198 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
204 * amdgpu_device_supports_baco - Does the device support BACO
206 * @dev: drm_device pointer
208 * Returns true if the device supporte BACO,
209 * otherwise return false.
211 bool amdgpu_device_supports_baco(struct drm_device *dev)
213 struct amdgpu_device *adev = drm_to_adev(dev);
215 return amdgpu_asic_supports_baco(adev);
219 * amdgpu_device_supports_smart_shift - Is the device dGPU with
220 * smart shift support
222 * @dev: drm_device pointer
224 * Returns true if the device is a dGPU with Smart Shift support,
225 * otherwise returns false.
227 bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
229 return (amdgpu_device_supports_boco(dev) &&
230 amdgpu_acpi_is_power_shift_control_supported());
234 * VRAM access helper functions
238 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
240 * @adev: amdgpu_device pointer
241 * @pos: offset of the buffer in vram
242 * @buf: virtual address of the buffer in system memory
243 * @size: read/write size, sizeof(@buf) must > @size
244 * @write: true - write to vram, otherwise - read from vram
246 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
247 void *buf, size_t size, bool write)
250 uint32_t hi = ~0, tmp = 0;
251 uint32_t *data = buf;
255 if (!drm_dev_enter(adev_to_drm(adev), &idx))
258 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
260 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
261 for (last = pos + size; pos < last; pos += 4) {
264 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
266 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
270 WREG32_NO_KIQ(mmMM_DATA, *data++);
272 *data++ = RREG32_NO_KIQ(mmMM_DATA);
275 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
280 * amdgpu_device_aper_access - access vram by vram aperature
282 * @adev: amdgpu_device pointer
283 * @pos: offset of the buffer in vram
284 * @buf: virtual address of the buffer in system memory
285 * @size: read/write size, sizeof(@buf) must > @size
286 * @write: true - write to vram, otherwise - read from vram
288 * The return value means how many bytes have been transferred.
290 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
291 void *buf, size_t size, bool write)
298 if (!adev->mman.aper_base_kaddr)
301 last = min(pos + size, adev->gmc.visible_vram_size);
303 addr = adev->mman.aper_base_kaddr + pos;
307 memcpy_toio(addr, buf, count);
308 /* Make sure HDP write cache flush happens without any reordering
309 * after the system memory contents are sent over PCIe device
312 amdgpu_device_flush_hdp(adev, NULL);
314 amdgpu_device_invalidate_hdp(adev, NULL);
315 /* Make sure HDP read cache is invalidated before issuing a read
319 memcpy_fromio(buf, addr, count);
331 * amdgpu_device_vram_access - read/write a buffer in vram
333 * @adev: amdgpu_device pointer
334 * @pos: offset of the buffer in vram
335 * @buf: virtual address of the buffer in system memory
336 * @size: read/write size, sizeof(@buf) must > @size
337 * @write: true - write to vram, otherwise - read from vram
339 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
340 void *buf, size_t size, bool write)
344 /* try to using vram apreature to access vram first */
345 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
348 /* using MM to access rest vram */
351 amdgpu_device_mm_access(adev, pos, buf, size, write);
356 * register access helper functions.
359 /* Check if hw access should be skipped because of hotplug or device error */
360 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
362 if (adev->no_hw_access)
365 #ifdef CONFIG_LOCKDEP
367 * This is a bit complicated to understand, so worth a comment. What we assert
368 * here is that the GPU reset is not running on another thread in parallel.
370 * For this we trylock the read side of the reset semaphore, if that succeeds
371 * we know that the reset is not running in paralell.
373 * If the trylock fails we assert that we are either already holding the read
374 * side of the lock or are the reset thread itself and hold the write side of
378 if (down_read_trylock(&adev->reset_domain->sem))
379 up_read(&adev->reset_domain->sem);
381 lockdep_assert_held(&adev->reset_domain->sem);
388 * amdgpu_device_rreg - read a memory mapped IO or indirect register
390 * @adev: amdgpu_device pointer
391 * @reg: dword aligned register offset
392 * @acc_flags: access flags which require special behavior
394 * Returns the 32 bit value from the offset specified.
396 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
397 uint32_t reg, uint32_t acc_flags)
401 if (amdgpu_device_skip_hw_access(adev))
404 if ((reg * 4) < adev->rmmio_size) {
405 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
406 amdgpu_sriov_runtime(adev) &&
407 down_read_trylock(&adev->reset_domain->sem)) {
408 ret = amdgpu_kiq_rreg(adev, reg);
409 up_read(&adev->reset_domain->sem);
411 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
414 ret = adev->pcie_rreg(adev, reg * 4);
417 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
423 * MMIO register read with bytes helper functions
424 * @offset:bytes offset from MMIO start
428 * amdgpu_mm_rreg8 - read a memory mapped IO register
430 * @adev: amdgpu_device pointer
431 * @offset: byte aligned register offset
433 * Returns the 8 bit value from the offset specified.
435 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
437 if (amdgpu_device_skip_hw_access(adev))
440 if (offset < adev->rmmio_size)
441 return (readb(adev->rmmio + offset));
446 * MMIO register write with bytes helper functions
447 * @offset:bytes offset from MMIO start
448 * @value: the value want to be written to the register
452 * amdgpu_mm_wreg8 - read a memory mapped IO register
454 * @adev: amdgpu_device pointer
455 * @offset: byte aligned register offset
456 * @value: 8 bit value to write
458 * Writes the value specified to the offset specified.
460 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
462 if (amdgpu_device_skip_hw_access(adev))
465 if (offset < adev->rmmio_size)
466 writeb(value, adev->rmmio + offset);
472 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
474 * @adev: amdgpu_device pointer
475 * @reg: dword aligned register offset
476 * @v: 32 bit value to write to the register
477 * @acc_flags: access flags which require special behavior
479 * Writes the value specified to the offset specified.
481 void amdgpu_device_wreg(struct amdgpu_device *adev,
482 uint32_t reg, uint32_t v,
485 if (amdgpu_device_skip_hw_access(adev))
488 if ((reg * 4) < adev->rmmio_size) {
489 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
490 amdgpu_sriov_runtime(adev) &&
491 down_read_trylock(&adev->reset_domain->sem)) {
492 amdgpu_kiq_wreg(adev, reg, v);
493 up_read(&adev->reset_domain->sem);
495 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
498 adev->pcie_wreg(adev, reg * 4, v);
501 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
505 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
507 * @adev: amdgpu_device pointer
508 * @reg: mmio/rlc register
511 * this function is invoked only for the debugfs register access
513 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
514 uint32_t reg, uint32_t v,
517 if (amdgpu_device_skip_hw_access(adev))
520 if (amdgpu_sriov_fullaccess(adev) &&
521 adev->gfx.rlc.funcs &&
522 adev->gfx.rlc.funcs->is_rlcg_access_range) {
523 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
524 return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
525 } else if ((reg * 4) >= adev->rmmio_size) {
526 adev->pcie_wreg(adev, reg * 4, v);
528 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
533 * amdgpu_device_indirect_rreg - read an indirect register
535 * @adev: amdgpu_device pointer
536 * @reg_addr: indirect register address to read from
538 * Returns the value of indirect register @reg_addr
540 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
543 unsigned long flags, pcie_index, pcie_data;
544 void __iomem *pcie_index_offset;
545 void __iomem *pcie_data_offset;
548 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
549 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
551 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
552 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
553 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
555 writel(reg_addr, pcie_index_offset);
556 readl(pcie_index_offset);
557 r = readl(pcie_data_offset);
558 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
563 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
566 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
568 void __iomem *pcie_index_offset;
569 void __iomem *pcie_index_hi_offset;
570 void __iomem *pcie_data_offset;
572 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
573 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
574 if (adev->nbio.funcs->get_pcie_index_hi_offset)
575 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
579 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
580 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
581 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
582 if (pcie_index_hi != 0)
583 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
586 writel(reg_addr, pcie_index_offset);
587 readl(pcie_index_offset);
588 if (pcie_index_hi != 0) {
589 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
590 readl(pcie_index_hi_offset);
592 r = readl(pcie_data_offset);
594 /* clear the high bits */
595 if (pcie_index_hi != 0) {
596 writel(0, pcie_index_hi_offset);
597 readl(pcie_index_hi_offset);
600 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
606 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
608 * @adev: amdgpu_device pointer
609 * @reg_addr: indirect register address to read from
611 * Returns the value of indirect register @reg_addr
613 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
616 unsigned long flags, pcie_index, pcie_data;
617 void __iomem *pcie_index_offset;
618 void __iomem *pcie_data_offset;
621 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
622 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
624 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
625 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
626 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
628 /* read low 32 bits */
629 writel(reg_addr, pcie_index_offset);
630 readl(pcie_index_offset);
631 r = readl(pcie_data_offset);
632 /* read high 32 bits */
633 writel(reg_addr + 4, pcie_index_offset);
634 readl(pcie_index_offset);
635 r |= ((u64)readl(pcie_data_offset) << 32);
636 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
642 * amdgpu_device_indirect_wreg - write an indirect register address
644 * @adev: amdgpu_device pointer
645 * @reg_addr: indirect register offset
646 * @reg_data: indirect register data
649 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
650 u32 reg_addr, u32 reg_data)
652 unsigned long flags, pcie_index, pcie_data;
653 void __iomem *pcie_index_offset;
654 void __iomem *pcie_data_offset;
656 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
657 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
659 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
660 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
661 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
663 writel(reg_addr, pcie_index_offset);
664 readl(pcie_index_offset);
665 writel(reg_data, pcie_data_offset);
666 readl(pcie_data_offset);
667 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
670 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
671 u64 reg_addr, u32 reg_data)
673 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
674 void __iomem *pcie_index_offset;
675 void __iomem *pcie_index_hi_offset;
676 void __iomem *pcie_data_offset;
678 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
679 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
680 if (adev->nbio.funcs->get_pcie_index_hi_offset)
681 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
685 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
686 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
687 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
688 if (pcie_index_hi != 0)
689 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
692 writel(reg_addr, pcie_index_offset);
693 readl(pcie_index_offset);
694 if (pcie_index_hi != 0) {
695 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
696 readl(pcie_index_hi_offset);
698 writel(reg_data, pcie_data_offset);
699 readl(pcie_data_offset);
701 /* clear the high bits */
702 if (pcie_index_hi != 0) {
703 writel(0, pcie_index_hi_offset);
704 readl(pcie_index_hi_offset);
707 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
711 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
713 * @adev: amdgpu_device pointer
714 * @reg_addr: indirect register offset
715 * @reg_data: indirect register data
718 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
719 u32 reg_addr, u64 reg_data)
721 unsigned long flags, pcie_index, pcie_data;
722 void __iomem *pcie_index_offset;
723 void __iomem *pcie_data_offset;
725 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
726 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
728 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
729 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
730 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
732 /* write low 32 bits */
733 writel(reg_addr, pcie_index_offset);
734 readl(pcie_index_offset);
735 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
736 readl(pcie_data_offset);
737 /* write high 32 bits */
738 writel(reg_addr + 4, pcie_index_offset);
739 readl(pcie_index_offset);
740 writel((u32)(reg_data >> 32), pcie_data_offset);
741 readl(pcie_data_offset);
742 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
746 * amdgpu_device_get_rev_id - query device rev_id
748 * @adev: amdgpu_device pointer
750 * Return device rev_id
752 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)
754 return adev->nbio.funcs->get_rev_id(adev);
758 * amdgpu_invalid_rreg - dummy reg read function
760 * @adev: amdgpu_device pointer
761 * @reg: offset of register
763 * Dummy register read function. Used for register blocks
764 * that certain asics don't have (all asics).
765 * Returns the value in the register.
767 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
769 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
774 static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
776 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
782 * amdgpu_invalid_wreg - dummy reg write function
784 * @adev: amdgpu_device pointer
785 * @reg: offset of register
786 * @v: value to write to the register
788 * Dummy register read function. Used for register blocks
789 * that certain asics don't have (all asics).
791 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
793 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
798 static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
800 DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",
806 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
808 * @adev: amdgpu_device pointer
809 * @reg: offset of register
811 * Dummy register read function. Used for register blocks
812 * that certain asics don't have (all asics).
813 * Returns the value in the register.
815 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
817 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
823 * amdgpu_invalid_wreg64 - dummy reg write function
825 * @adev: amdgpu_device pointer
826 * @reg: offset of register
827 * @v: value to write to the register
829 * Dummy register read function. Used for register blocks
830 * that certain asics don't have (all asics).
832 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
834 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
840 * amdgpu_block_invalid_rreg - dummy reg read function
842 * @adev: amdgpu_device pointer
843 * @block: offset of instance
844 * @reg: offset of register
846 * Dummy register read function. Used for register blocks
847 * that certain asics don't have (all asics).
848 * Returns the value in the register.
850 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
851 uint32_t block, uint32_t reg)
853 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
860 * amdgpu_block_invalid_wreg - dummy reg write function
862 * @adev: amdgpu_device pointer
863 * @block: offset of instance
864 * @reg: offset of register
865 * @v: value to write to the register
867 * Dummy register read function. Used for register blocks
868 * that certain asics don't have (all asics).
870 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
872 uint32_t reg, uint32_t v)
874 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
880 * amdgpu_device_asic_init - Wrapper for atom asic_init
882 * @adev: amdgpu_device pointer
884 * Does any asic specific work and then calls atom asic init.
886 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
890 amdgpu_asic_pre_asic_init(adev);
892 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) ||
893 adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) {
894 amdgpu_psp_wait_for_bootloader(adev);
895 ret = amdgpu_atomfirmware_asic_init(adev, true);
898 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
905 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
907 * @adev: amdgpu_device pointer
909 * Allocates a scratch page of VRAM for use by various things in the
912 static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
914 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
915 AMDGPU_GEM_DOMAIN_VRAM |
916 AMDGPU_GEM_DOMAIN_GTT,
917 &adev->mem_scratch.robj,
918 &adev->mem_scratch.gpu_addr,
919 (void **)&adev->mem_scratch.ptr);
923 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
925 * @adev: amdgpu_device pointer
927 * Frees the VRAM scratch page.
929 static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
931 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
935 * amdgpu_device_program_register_sequence - program an array of registers.
937 * @adev: amdgpu_device pointer
938 * @registers: pointer to the register array
939 * @array_size: size of the register array
941 * Programs an array or registers with and or masks.
942 * This is a helper for setting golden registers.
944 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
945 const u32 *registers,
946 const u32 array_size)
948 u32 tmp, reg, and_mask, or_mask;
954 for (i = 0; i < array_size; i += 3) {
955 reg = registers[i + 0];
956 and_mask = registers[i + 1];
957 or_mask = registers[i + 2];
959 if (and_mask == 0xffffffff) {
964 if (adev->family >= AMDGPU_FAMILY_AI)
965 tmp |= (or_mask & and_mask);
974 * amdgpu_device_pci_config_reset - reset the GPU
976 * @adev: amdgpu_device pointer
978 * Resets the GPU using the pci config reset sequence.
979 * Only applicable to asics prior to vega10.
981 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
983 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
987 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
989 * @adev: amdgpu_device pointer
991 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
993 int amdgpu_device_pci_reset(struct amdgpu_device *adev)
995 return pci_reset_function(adev->pdev);
999 * amdgpu_device_wb_*()
1000 * Writeback is the method by which the GPU updates special pages in memory
1001 * with the status of certain GPU events (fences, ring pointers,etc.).
1005 * amdgpu_device_wb_fini - Disable Writeback and free memory
1007 * @adev: amdgpu_device pointer
1009 * Disables Writeback and frees the Writeback memory (all asics).
1010 * Used at driver shutdown.
1012 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1014 if (adev->wb.wb_obj) {
1015 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1017 (void **)&adev->wb.wb);
1018 adev->wb.wb_obj = NULL;
1023 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1025 * @adev: amdgpu_device pointer
1027 * Initializes writeback and allocates writeback memory (all asics).
1028 * Used at driver startup.
1029 * Returns 0 on success or an -error on failure.
1031 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1035 if (adev->wb.wb_obj == NULL) {
1036 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1037 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1038 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1039 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1040 (void **)&adev->wb.wb);
1042 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1046 adev->wb.num_wb = AMDGPU_MAX_WB;
1047 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1049 /* clear wb memory */
1050 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1057 * amdgpu_device_wb_get - Allocate a wb entry
1059 * @adev: amdgpu_device pointer
1062 * Allocate a wb slot for use by the driver (all asics).
1063 * Returns 0 on success or -EINVAL on failure.
1065 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1067 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1069 if (offset < adev->wb.num_wb) {
1070 __set_bit(offset, adev->wb.used);
1071 *wb = offset << 3; /* convert to dw offset */
1079 * amdgpu_device_wb_free - Free a wb entry
1081 * @adev: amdgpu_device pointer
1084 * Free a wb slot allocated for use by the driver (all asics)
1086 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1089 if (wb < adev->wb.num_wb)
1090 __clear_bit(wb, adev->wb.used);
1094 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1096 * @adev: amdgpu_device pointer
1098 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1099 * to fail, but if any of the BARs is not accessible after the size we abort
1100 * driver loading by returning -ENODEV.
1102 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1104 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1105 struct pci_bus *root;
1106 struct resource *res;
1111 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
1115 if (amdgpu_sriov_vf(adev))
1118 /* skip if the bios has already enabled large BAR */
1119 if (adev->gmc.real_vram_size &&
1120 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1123 /* Check if the root BUS has 64bit memory resources */
1124 root = adev->pdev->bus;
1125 while (root->parent)
1126 root = root->parent;
1128 pci_bus_for_each_resource(root, res, i) {
1129 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1130 res->start > 0x100000000ull)
1134 /* Trying to resize is pointless without a root hub window above 4GB */
1138 /* Limit the BAR size to what is available */
1139 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1142 /* Disable memory decoding while we change the BAR addresses and size */
1143 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1144 pci_write_config_word(adev->pdev, PCI_COMMAND,
1145 cmd & ~PCI_COMMAND_MEMORY);
1147 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1148 amdgpu_doorbell_fini(adev);
1149 if (adev->asic_type >= CHIP_BONAIRE)
1150 pci_release_resource(adev->pdev, 2);
1152 pci_release_resource(adev->pdev, 0);
1154 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1156 DRM_INFO("Not enough PCI address space for a large BAR.");
1157 else if (r && r != -ENOTSUPP)
1158 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1160 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1162 /* When the doorbell or fb BAR isn't available we have no chance of
1165 r = amdgpu_doorbell_init(adev);
1166 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1169 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1174 static bool amdgpu_device_read_bios(struct amdgpu_device *adev)
1176 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
1183 * GPU helpers function.
1186 * amdgpu_device_need_post - check if the hw need post or not
1188 * @adev: amdgpu_device pointer
1190 * Check if the asic has been initialized (all asics) at driver startup
1191 * or post is needed if hw reset is performed.
1192 * Returns true if need or false if not.
1194 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1198 if (amdgpu_sriov_vf(adev))
1201 if (!amdgpu_device_read_bios(adev))
1204 if (amdgpu_passthrough(adev)) {
1205 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1206 * some old smc fw still need driver do vPost otherwise gpu hang, while
1207 * those smc fw version above 22.15 doesn't have this flaw, so we force
1208 * vpost executed for smc version below 22.15
1210 if (adev->asic_type == CHIP_FIJI) {
1214 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1215 /* force vPost if error occured */
1219 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1220 if (fw_ver < 0x00160e00)
1225 /* Don't post if we need to reset whole hive on init */
1226 if (adev->gmc.xgmi.pending_reset)
1229 if (adev->has_hw_reset) {
1230 adev->has_hw_reset = false;
1234 /* bios scratch used on CIK+ */
1235 if (adev->asic_type >= CHIP_BONAIRE)
1236 return amdgpu_atombios_scratch_need_asic_init(adev);
1238 /* check MEM_SIZE for older asics */
1239 reg = amdgpu_asic_get_config_memsize(adev);
1241 if ((reg != 0) && (reg != 0xffffffff))
1248 * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
1249 * speed switching. Until we have confirmation from Intel that a specific host
1250 * supports it, it's safer that we keep it disabled for all.
1252 * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
1253 * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
1255 bool amdgpu_device_pcie_dynamic_switching_supported(void)
1257 #if IS_ENABLED(CONFIG_X86)
1258 struct cpuinfo_x86 *c = &cpu_data(0);
1260 if (c->x86_vendor == X86_VENDOR_INTEL)
1267 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1269 * @adev: amdgpu_device pointer
1271 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1272 * be set for this device.
1274 * Returns true if it should be used or false if not.
1276 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1278 switch (amdgpu_aspm) {
1288 return pcie_aspm_enabled(adev->pdev);
1291 bool amdgpu_device_aspm_support_quirk(void)
1293 #if IS_ENABLED(CONFIG_X86)
1294 struct cpuinfo_x86 *c = &cpu_data(0);
1296 return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);
1302 /* if we get transitioned to only one device, take VGA back */
1304 * amdgpu_device_vga_set_decode - enable/disable vga decode
1306 * @pdev: PCI device pointer
1307 * @state: enable/disable vga decode
1309 * Enable/disable vga decode (all asics).
1310 * Returns VGA resource flags.
1312 static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1315 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1317 amdgpu_asic_set_vga_state(adev, state);
1319 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1320 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1322 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1326 * amdgpu_device_check_block_size - validate the vm block size
1328 * @adev: amdgpu_device pointer
1330 * Validates the vm block size specified via module parameter.
1331 * The vm block size defines number of bits in page table versus page directory,
1332 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1333 * page table and the remaining bits are in the page directory.
1335 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1337 /* defines number of bits in page table versus page directory,
1338 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1339 * page table and the remaining bits are in the page directory
1341 if (amdgpu_vm_block_size == -1)
1344 if (amdgpu_vm_block_size < 9) {
1345 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1346 amdgpu_vm_block_size);
1347 amdgpu_vm_block_size = -1;
1352 * amdgpu_device_check_vm_size - validate the vm size
1354 * @adev: amdgpu_device pointer
1356 * Validates the vm size in GB specified via module parameter.
1357 * The VM size is the size of the GPU virtual memory space in GB.
1359 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1361 /* no need to check the default value */
1362 if (amdgpu_vm_size == -1)
1365 if (amdgpu_vm_size < 1) {
1366 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1368 amdgpu_vm_size = -1;
1372 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1375 bool is_os_64 = (sizeof(void *) == 8);
1376 uint64_t total_memory;
1377 uint64_t dram_size_seven_GB = 0x1B8000000;
1378 uint64_t dram_size_three_GB = 0xB8000000;
1380 if (amdgpu_smu_memory_pool_size == 0)
1384 DRM_WARN("Not 64-bit OS, feature not supported\n");
1388 total_memory = (uint64_t)si.totalram * si.mem_unit;
1390 if ((amdgpu_smu_memory_pool_size == 1) ||
1391 (amdgpu_smu_memory_pool_size == 2)) {
1392 if (total_memory < dram_size_three_GB)
1394 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1395 (amdgpu_smu_memory_pool_size == 8)) {
1396 if (total_memory < dram_size_seven_GB)
1399 DRM_WARN("Smu memory pool size not supported\n");
1402 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1407 DRM_WARN("No enough system memory\n");
1409 adev->pm.smu_prv_buffer_size = 0;
1412 static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1414 if (!(adev->flags & AMD_IS_APU) ||
1415 adev->asic_type < CHIP_RAVEN)
1418 switch (adev->asic_type) {
1420 if (adev->pdev->device == 0x15dd)
1421 adev->apu_flags |= AMD_APU_IS_RAVEN;
1422 if (adev->pdev->device == 0x15d8)
1423 adev->apu_flags |= AMD_APU_IS_PICASSO;
1426 if ((adev->pdev->device == 0x1636) ||
1427 (adev->pdev->device == 0x164c))
1428 adev->apu_flags |= AMD_APU_IS_RENOIR;
1430 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1433 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1435 case CHIP_YELLOW_CARP:
1437 case CHIP_CYAN_SKILLFISH:
1438 if ((adev->pdev->device == 0x13FE) ||
1439 (adev->pdev->device == 0x143F))
1440 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1450 * amdgpu_device_check_arguments - validate module params
1452 * @adev: amdgpu_device pointer
1454 * Validates certain module parameters and updates
1455 * the associated values used by the driver (all asics).
1457 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1459 if (amdgpu_sched_jobs < 4) {
1460 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1462 amdgpu_sched_jobs = 4;
1463 } else if (!is_power_of_2(amdgpu_sched_jobs)) {
1464 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1466 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1469 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1470 /* gart size must be greater or equal to 32M */
1471 dev_warn(adev->dev, "gart size (%d) too small\n",
1473 amdgpu_gart_size = -1;
1476 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1477 /* gtt size must be greater or equal to 32M */
1478 dev_warn(adev->dev, "gtt size (%d) too small\n",
1480 amdgpu_gtt_size = -1;
1483 /* valid range is between 4 and 9 inclusive */
1484 if (amdgpu_vm_fragment_size != -1 &&
1485 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1486 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1487 amdgpu_vm_fragment_size = -1;
1490 if (amdgpu_sched_hw_submission < 2) {
1491 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1492 amdgpu_sched_hw_submission);
1493 amdgpu_sched_hw_submission = 2;
1494 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1495 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1496 amdgpu_sched_hw_submission);
1497 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1500 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1501 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1502 amdgpu_reset_method = -1;
1505 amdgpu_device_check_smu_prv_buffer_size(adev);
1507 amdgpu_device_check_vm_size(adev);
1509 amdgpu_device_check_block_size(adev);
1511 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1517 * amdgpu_switcheroo_set_state - set switcheroo state
1519 * @pdev: pci dev pointer
1520 * @state: vga_switcheroo state
1522 * Callback for the switcheroo driver. Suspends or resumes
1523 * the asics before or after it is powered up using ACPI methods.
1525 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1526 enum vga_switcheroo_state state)
1528 struct drm_device *dev = pci_get_drvdata(pdev);
1531 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1534 if (state == VGA_SWITCHEROO_ON) {
1535 pr_info("switched on\n");
1536 /* don't suspend or resume card normally */
1537 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1539 pci_set_power_state(pdev, PCI_D0);
1540 amdgpu_device_load_pci_state(pdev);
1541 r = pci_enable_device(pdev);
1543 DRM_WARN("pci_enable_device failed (%d)\n", r);
1544 amdgpu_device_resume(dev, true);
1546 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1548 pr_info("switched off\n");
1549 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1550 amdgpu_device_suspend(dev, true);
1551 amdgpu_device_cache_pci_state(pdev);
1552 /* Shut down the device */
1553 pci_disable_device(pdev);
1554 pci_set_power_state(pdev, PCI_D3cold);
1555 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1560 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1562 * @pdev: pci dev pointer
1564 * Callback for the switcheroo driver. Check of the switcheroo
1565 * state can be changed.
1566 * Returns true if the state can be changed, false if not.
1568 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1570 struct drm_device *dev = pci_get_drvdata(pdev);
1573 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1574 * locking inversion with the driver load path. And the access here is
1575 * completely racy anyway. So don't bother with locking for now.
1577 return atomic_read(&dev->open_count) == 0;
1580 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1581 .set_gpu_state = amdgpu_switcheroo_set_state,
1583 .can_switch = amdgpu_switcheroo_can_switch,
1587 * amdgpu_device_ip_set_clockgating_state - set the CG state
1589 * @dev: amdgpu_device pointer
1590 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1591 * @state: clockgating state (gate or ungate)
1593 * Sets the requested clockgating state for all instances of
1594 * the hardware IP specified.
1595 * Returns the error code from the last instance.
1597 int amdgpu_device_ip_set_clockgating_state(void *dev,
1598 enum amd_ip_block_type block_type,
1599 enum amd_clockgating_state state)
1601 struct amdgpu_device *adev = dev;
1604 for (i = 0; i < adev->num_ip_blocks; i++) {
1605 if (!adev->ip_blocks[i].status.valid)
1607 if (adev->ip_blocks[i].version->type != block_type)
1609 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1611 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1612 (void *)adev, state);
1614 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1615 adev->ip_blocks[i].version->funcs->name, r);
1621 * amdgpu_device_ip_set_powergating_state - set the PG state
1623 * @dev: amdgpu_device pointer
1624 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1625 * @state: powergating state (gate or ungate)
1627 * Sets the requested powergating state for all instances of
1628 * the hardware IP specified.
1629 * Returns the error code from the last instance.
1631 int amdgpu_device_ip_set_powergating_state(void *dev,
1632 enum amd_ip_block_type block_type,
1633 enum amd_powergating_state state)
1635 struct amdgpu_device *adev = dev;
1638 for (i = 0; i < adev->num_ip_blocks; i++) {
1639 if (!adev->ip_blocks[i].status.valid)
1641 if (adev->ip_blocks[i].version->type != block_type)
1643 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1645 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1646 (void *)adev, state);
1648 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1649 adev->ip_blocks[i].version->funcs->name, r);
1655 * amdgpu_device_ip_get_clockgating_state - get the CG state
1657 * @adev: amdgpu_device pointer
1658 * @flags: clockgating feature flags
1660 * Walks the list of IPs on the device and updates the clockgating
1661 * flags for each IP.
1662 * Updates @flags with the feature flags for each hardware IP where
1663 * clockgating is enabled.
1665 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1670 for (i = 0; i < adev->num_ip_blocks; i++) {
1671 if (!adev->ip_blocks[i].status.valid)
1673 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1674 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1679 * amdgpu_device_ip_wait_for_idle - wait for idle
1681 * @adev: amdgpu_device pointer
1682 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1684 * Waits for the request hardware IP to be idle.
1685 * Returns 0 for success or a negative error code on failure.
1687 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1688 enum amd_ip_block_type block_type)
1692 for (i = 0; i < adev->num_ip_blocks; i++) {
1693 if (!adev->ip_blocks[i].status.valid)
1695 if (adev->ip_blocks[i].version->type == block_type) {
1696 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1707 * amdgpu_device_ip_is_idle - is the hardware IP idle
1709 * @adev: amdgpu_device pointer
1710 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1712 * Check if the hardware IP is idle or not.
1713 * Returns true if it the IP is idle, false if not.
1715 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1716 enum amd_ip_block_type block_type)
1720 for (i = 0; i < adev->num_ip_blocks; i++) {
1721 if (!adev->ip_blocks[i].status.valid)
1723 if (adev->ip_blocks[i].version->type == block_type)
1724 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1731 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1733 * @adev: amdgpu_device pointer
1734 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1736 * Returns a pointer to the hardware IP block structure
1737 * if it exists for the asic, otherwise NULL.
1739 struct amdgpu_ip_block *
1740 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1741 enum amd_ip_block_type type)
1745 for (i = 0; i < adev->num_ip_blocks; i++)
1746 if (adev->ip_blocks[i].version->type == type)
1747 return &adev->ip_blocks[i];
1753 * amdgpu_device_ip_block_version_cmp
1755 * @adev: amdgpu_device pointer
1756 * @type: enum amd_ip_block_type
1757 * @major: major version
1758 * @minor: minor version
1760 * return 0 if equal or greater
1761 * return 1 if smaller or the ip_block doesn't exist
1763 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1764 enum amd_ip_block_type type,
1765 u32 major, u32 minor)
1767 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1769 if (ip_block && ((ip_block->version->major > major) ||
1770 ((ip_block->version->major == major) &&
1771 (ip_block->version->minor >= minor))))
1778 * amdgpu_device_ip_block_add
1780 * @adev: amdgpu_device pointer
1781 * @ip_block_version: pointer to the IP to add
1783 * Adds the IP block driver information to the collection of IPs
1786 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1787 const struct amdgpu_ip_block_version *ip_block_version)
1789 if (!ip_block_version)
1792 switch (ip_block_version->type) {
1793 case AMD_IP_BLOCK_TYPE_VCN:
1794 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1797 case AMD_IP_BLOCK_TYPE_JPEG:
1798 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
1805 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1806 ip_block_version->funcs->name);
1808 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1814 * amdgpu_device_enable_virtual_display - enable virtual display feature
1816 * @adev: amdgpu_device pointer
1818 * Enabled the virtual display feature if the user has enabled it via
1819 * the module parameter virtual_display. This feature provides a virtual
1820 * display hardware on headless boards or in virtualized environments.
1821 * This function parses and validates the configuration string specified by
1822 * the user and configues the virtual display configuration (number of
1823 * virtual connectors, crtcs, etc.) specified.
1825 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1827 adev->enable_virtual_display = false;
1829 if (amdgpu_virtual_display) {
1830 const char *pci_address_name = pci_name(adev->pdev);
1831 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1833 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1834 pciaddstr_tmp = pciaddstr;
1835 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1836 pciaddname = strsep(&pciaddname_tmp, ",");
1837 if (!strcmp("all", pciaddname)
1838 || !strcmp(pci_address_name, pciaddname)) {
1842 adev->enable_virtual_display = true;
1845 res = kstrtol(pciaddname_tmp, 10,
1853 adev->mode_info.num_crtc = num_crtc;
1855 adev->mode_info.num_crtc = 1;
1861 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1862 amdgpu_virtual_display, pci_address_name,
1863 adev->enable_virtual_display, adev->mode_info.num_crtc);
1869 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
1871 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
1872 adev->mode_info.num_crtc = 1;
1873 adev->enable_virtual_display = true;
1874 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
1875 adev->enable_virtual_display, adev->mode_info.num_crtc);
1880 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1882 * @adev: amdgpu_device pointer
1884 * Parses the asic configuration parameters specified in the gpu info
1885 * firmware and makes them availale to the driver for use in configuring
1887 * Returns 0 on success, -EINVAL on failure.
1889 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1891 const char *chip_name;
1894 const struct gpu_info_firmware_header_v1_0 *hdr;
1896 adev->firmware.gpu_info_fw = NULL;
1898 if (adev->mman.discovery_bin) {
1900 * FIXME: The bounding box is still needed by Navi12, so
1901 * temporarily read it from gpu_info firmware. Should be dropped
1902 * when DAL no longer needs it.
1904 if (adev->asic_type != CHIP_NAVI12)
1908 switch (adev->asic_type) {
1912 chip_name = "vega10";
1915 chip_name = "vega12";
1918 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1919 chip_name = "raven2";
1920 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1921 chip_name = "picasso";
1923 chip_name = "raven";
1926 chip_name = "arcturus";
1929 chip_name = "navi12";
1933 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1934 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name);
1937 "Failed to get gpu_info firmware \"%s\"\n",
1942 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1943 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1945 switch (hdr->version_major) {
1948 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1949 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1950 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1953 * Should be droped when DAL no longer needs it.
1955 if (adev->asic_type == CHIP_NAVI12)
1956 goto parse_soc_bounding_box;
1958 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1959 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1960 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1961 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1962 adev->gfx.config.max_texture_channel_caches =
1963 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1964 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1965 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1966 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1967 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1968 adev->gfx.config.double_offchip_lds_buf =
1969 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1970 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1971 adev->gfx.cu_info.max_waves_per_simd =
1972 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1973 adev->gfx.cu_info.max_scratch_slots_per_cu =
1974 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1975 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1976 if (hdr->version_minor >= 1) {
1977 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1978 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1979 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1980 adev->gfx.config.num_sc_per_sh =
1981 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1982 adev->gfx.config.num_packer_per_sc =
1983 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1986 parse_soc_bounding_box:
1988 * soc bounding box info is not integrated in disocovery table,
1989 * we always need to parse it from gpu info firmware if needed.
1991 if (hdr->version_minor == 2) {
1992 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1993 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1994 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1995 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2001 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2010 * amdgpu_device_ip_early_init - run early init for hardware IPs
2012 * @adev: amdgpu_device pointer
2014 * Early initialization pass for hardware IPs. The hardware IPs that make
2015 * up each asic are discovered each IP's early_init callback is run. This
2016 * is the first stage in initializing the asic.
2017 * Returns 0 on success, negative error code on failure.
2019 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2021 struct drm_device *dev = adev_to_drm(adev);
2022 struct pci_dev *parent;
2026 amdgpu_device_enable_virtual_display(adev);
2028 if (amdgpu_sriov_vf(adev)) {
2029 r = amdgpu_virt_request_full_gpu(adev, true);
2034 switch (adev->asic_type) {
2035 #ifdef CONFIG_DRM_AMDGPU_SI
2041 adev->family = AMDGPU_FAMILY_SI;
2042 r = si_set_ip_blocks(adev);
2047 #ifdef CONFIG_DRM_AMDGPU_CIK
2053 if (adev->flags & AMD_IS_APU)
2054 adev->family = AMDGPU_FAMILY_KV;
2056 adev->family = AMDGPU_FAMILY_CI;
2058 r = cik_set_ip_blocks(adev);
2066 case CHIP_POLARIS10:
2067 case CHIP_POLARIS11:
2068 case CHIP_POLARIS12:
2072 if (adev->flags & AMD_IS_APU)
2073 adev->family = AMDGPU_FAMILY_CZ;
2075 adev->family = AMDGPU_FAMILY_VI;
2077 r = vi_set_ip_blocks(adev);
2082 r = amdgpu_discovery_set_ip_blocks(adev);
2088 if (amdgpu_has_atpx() &&
2089 (amdgpu_is_atpx_hybrid() ||
2090 amdgpu_has_atpx_dgpu_power_cntl()) &&
2091 ((adev->flags & AMD_IS_APU) == 0) &&
2092 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
2093 adev->flags |= AMD_IS_PX;
2095 if (!(adev->flags & AMD_IS_APU)) {
2096 parent = pci_upstream_bridge(adev->pdev);
2097 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2101 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2102 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2103 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2104 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2105 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2108 for (i = 0; i < adev->num_ip_blocks; i++) {
2109 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2110 DRM_WARN("disabled ip block: %d <%s>\n",
2111 i, adev->ip_blocks[i].version->funcs->name);
2112 adev->ip_blocks[i].status.valid = false;
2114 if (adev->ip_blocks[i].version->funcs->early_init) {
2115 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2117 adev->ip_blocks[i].status.valid = false;
2119 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2120 adev->ip_blocks[i].version->funcs->name, r);
2123 adev->ip_blocks[i].status.valid = true;
2126 adev->ip_blocks[i].status.valid = true;
2129 /* get the vbios after the asic_funcs are set up */
2130 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2131 r = amdgpu_device_parse_gpu_info_fw(adev);
2136 if (amdgpu_device_read_bios(adev)) {
2137 if (!amdgpu_get_bios(adev))
2140 r = amdgpu_atombios_init(adev);
2142 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2143 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2148 /*get pf2vf msg info at it's earliest time*/
2149 if (amdgpu_sriov_vf(adev))
2150 amdgpu_virt_init_data_exchange(adev);
2157 amdgpu_amdkfd_device_probe(adev);
2158 adev->cg_flags &= amdgpu_cg_mask;
2159 adev->pg_flags &= amdgpu_pg_mask;
2164 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2168 for (i = 0; i < adev->num_ip_blocks; i++) {
2169 if (!adev->ip_blocks[i].status.sw)
2171 if (adev->ip_blocks[i].status.hw)
2173 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2174 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2175 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2176 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2178 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2179 adev->ip_blocks[i].version->funcs->name, r);
2182 adev->ip_blocks[i].status.hw = true;
2189 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2193 for (i = 0; i < adev->num_ip_blocks; i++) {
2194 if (!adev->ip_blocks[i].status.sw)
2196 if (adev->ip_blocks[i].status.hw)
2198 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2200 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2201 adev->ip_blocks[i].version->funcs->name, r);
2204 adev->ip_blocks[i].status.hw = true;
2210 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2214 uint32_t smu_version;
2216 if (adev->asic_type >= CHIP_VEGA10) {
2217 for (i = 0; i < adev->num_ip_blocks; i++) {
2218 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2221 if (!adev->ip_blocks[i].status.sw)
2224 /* no need to do the fw loading again if already done*/
2225 if (adev->ip_blocks[i].status.hw == true)
2228 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2229 r = adev->ip_blocks[i].version->funcs->resume(adev);
2231 DRM_ERROR("resume of IP block <%s> failed %d\n",
2232 adev->ip_blocks[i].version->funcs->name, r);
2236 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2238 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2239 adev->ip_blocks[i].version->funcs->name, r);
2244 adev->ip_blocks[i].status.hw = true;
2249 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2250 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2255 static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2260 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2261 struct amdgpu_ring *ring = adev->rings[i];
2263 /* No need to setup the GPU scheduler for rings that don't need it */
2264 if (!ring || ring->no_scheduler)
2267 switch (ring->funcs->type) {
2268 case AMDGPU_RING_TYPE_GFX:
2269 timeout = adev->gfx_timeout;
2271 case AMDGPU_RING_TYPE_COMPUTE:
2272 timeout = adev->compute_timeout;
2274 case AMDGPU_RING_TYPE_SDMA:
2275 timeout = adev->sdma_timeout;
2278 timeout = adev->video_timeout;
2282 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
2283 ring->num_hw_submission, 0,
2284 timeout, adev->reset_domain->wq,
2285 ring->sched_score, ring->name,
2288 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2294 amdgpu_xcp_update_partition_sched_list(adev);
2301 * amdgpu_device_ip_init - run init for hardware IPs
2303 * @adev: amdgpu_device pointer
2305 * Main initialization pass for hardware IPs. The list of all the hardware
2306 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2307 * are run. sw_init initializes the software state associated with each IP
2308 * and hw_init initializes the hardware associated with each IP.
2309 * Returns 0 on success, negative error code on failure.
2311 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2315 r = amdgpu_ras_init(adev);
2319 for (i = 0; i < adev->num_ip_blocks; i++) {
2320 if (!adev->ip_blocks[i].status.valid)
2322 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2324 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2325 adev->ip_blocks[i].version->funcs->name, r);
2328 adev->ip_blocks[i].status.sw = true;
2330 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2331 /* need to do common hw init early so everything is set up for gmc */
2332 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2334 DRM_ERROR("hw_init %d failed %d\n", i, r);
2337 adev->ip_blocks[i].status.hw = true;
2338 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2339 /* need to do gmc hw init early so we can allocate gpu mem */
2340 /* Try to reserve bad pages early */
2341 if (amdgpu_sriov_vf(adev))
2342 amdgpu_virt_exchange_data(adev);
2344 r = amdgpu_device_mem_scratch_init(adev);
2346 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2349 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2351 DRM_ERROR("hw_init %d failed %d\n", i, r);
2354 r = amdgpu_device_wb_init(adev);
2356 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2359 adev->ip_blocks[i].status.hw = true;
2361 /* right after GMC hw init, we create CSA */
2362 if (adev->gfx.mcbp) {
2363 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2364 AMDGPU_GEM_DOMAIN_VRAM |
2365 AMDGPU_GEM_DOMAIN_GTT,
2368 DRM_ERROR("allocate CSA failed %d\n", r);
2375 if (amdgpu_sriov_vf(adev))
2376 amdgpu_virt_init_data_exchange(adev);
2378 r = amdgpu_ib_pool_init(adev);
2380 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2381 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2385 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2389 r = amdgpu_device_ip_hw_init_phase1(adev);
2393 r = amdgpu_device_fw_loading(adev);
2397 r = amdgpu_device_ip_hw_init_phase2(adev);
2402 * retired pages will be loaded from eeprom and reserved here,
2403 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2404 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2405 * for I2C communication which only true at this point.
2407 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2408 * failure from bad gpu situation and stop amdgpu init process
2409 * accordingly. For other failed cases, it will still release all
2410 * the resource and print error message, rather than returning one
2411 * negative value to upper level.
2413 * Note: theoretically, this should be called before all vram allocations
2414 * to protect retired page from abusing
2416 r = amdgpu_ras_recovery_init(adev);
2421 * In case of XGMI grab extra reference for reset domain for this device
2423 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2424 if (amdgpu_xgmi_add_device(adev) == 0) {
2425 if (!amdgpu_sriov_vf(adev)) {
2426 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2428 if (WARN_ON(!hive)) {
2433 if (!hive->reset_domain ||
2434 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2436 amdgpu_put_xgmi_hive(hive);
2440 /* Drop the early temporary reset domain we created for device */
2441 amdgpu_reset_put_reset_domain(adev->reset_domain);
2442 adev->reset_domain = hive->reset_domain;
2443 amdgpu_put_xgmi_hive(hive);
2448 r = amdgpu_device_init_schedulers(adev);
2452 /* Don't init kfd if whole hive need to be reset during init */
2453 if (!adev->gmc.xgmi.pending_reset) {
2454 kgd2kfd_init_zone_device(adev);
2455 amdgpu_amdkfd_device_init(adev);
2458 amdgpu_fru_get_product_info(adev);
2466 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2468 * @adev: amdgpu_device pointer
2470 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2471 * this function before a GPU reset. If the value is retained after a
2472 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2474 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2476 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2480 * amdgpu_device_check_vram_lost - check if vram is valid
2482 * @adev: amdgpu_device pointer
2484 * Checks the reset magic value written to the gart pointer in VRAM.
2485 * The driver calls this after a GPU reset to see if the contents of
2486 * VRAM is lost or now.
2487 * returns true if vram is lost, false if not.
2489 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2491 if (memcmp(adev->gart.ptr, adev->reset_magic,
2492 AMDGPU_RESET_MAGIC_NUM))
2495 if (!amdgpu_in_reset(adev))
2499 * For all ASICs with baco/mode1 reset, the VRAM is
2500 * always assumed to be lost.
2502 switch (amdgpu_asic_reset_method(adev)) {
2503 case AMD_RESET_METHOD_BACO:
2504 case AMD_RESET_METHOD_MODE1:
2512 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2514 * @adev: amdgpu_device pointer
2515 * @state: clockgating state (gate or ungate)
2517 * The list of all the hardware IPs that make up the asic is walked and the
2518 * set_clockgating_state callbacks are run.
2519 * Late initialization pass enabling clockgating for hardware IPs.
2520 * Fini or suspend, pass disabling clockgating for hardware IPs.
2521 * Returns 0 on success, negative error code on failure.
2524 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2525 enum amd_clockgating_state state)
2529 if (amdgpu_emu_mode == 1)
2532 for (j = 0; j < adev->num_ip_blocks; j++) {
2533 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2534 if (!adev->ip_blocks[i].status.late_initialized)
2536 /* skip CG for GFX, SDMA on S0ix */
2537 if (adev->in_s0ix &&
2538 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2539 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2541 /* skip CG for VCE/UVD, it's handled specially */
2542 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2543 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2544 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2545 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2546 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2547 /* enable clockgating to save power */
2548 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2551 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2552 adev->ip_blocks[i].version->funcs->name, r);
2561 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2562 enum amd_powergating_state state)
2566 if (amdgpu_emu_mode == 1)
2569 for (j = 0; j < adev->num_ip_blocks; j++) {
2570 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2571 if (!adev->ip_blocks[i].status.late_initialized)
2573 /* skip PG for GFX, SDMA on S0ix */
2574 if (adev->in_s0ix &&
2575 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2576 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2578 /* skip CG for VCE/UVD, it's handled specially */
2579 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2580 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2581 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2582 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2583 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2584 /* enable powergating to save power */
2585 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2588 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2589 adev->ip_blocks[i].version->funcs->name, r);
2597 static int amdgpu_device_enable_mgpu_fan_boost(void)
2599 struct amdgpu_gpu_instance *gpu_ins;
2600 struct amdgpu_device *adev;
2603 mutex_lock(&mgpu_info.mutex);
2606 * MGPU fan boost feature should be enabled
2607 * only when there are two or more dGPUs in
2610 if (mgpu_info.num_dgpu < 2)
2613 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2614 gpu_ins = &(mgpu_info.gpu_ins[i]);
2615 adev = gpu_ins->adev;
2616 if (!(adev->flags & AMD_IS_APU) &&
2617 !gpu_ins->mgpu_fan_enabled) {
2618 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2622 gpu_ins->mgpu_fan_enabled = 1;
2627 mutex_unlock(&mgpu_info.mutex);
2633 * amdgpu_device_ip_late_init - run late init for hardware IPs
2635 * @adev: amdgpu_device pointer
2637 * Late initialization pass for hardware IPs. The list of all the hardware
2638 * IPs that make up the asic is walked and the late_init callbacks are run.
2639 * late_init covers any special initialization that an IP requires
2640 * after all of the have been initialized or something that needs to happen
2641 * late in the init process.
2642 * Returns 0 on success, negative error code on failure.
2644 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2646 struct amdgpu_gpu_instance *gpu_instance;
2649 for (i = 0; i < adev->num_ip_blocks; i++) {
2650 if (!adev->ip_blocks[i].status.hw)
2652 if (adev->ip_blocks[i].version->funcs->late_init) {
2653 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2655 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2656 adev->ip_blocks[i].version->funcs->name, r);
2660 adev->ip_blocks[i].status.late_initialized = true;
2663 r = amdgpu_ras_late_init(adev);
2665 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
2669 amdgpu_ras_set_error_query_ready(adev, true);
2671 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2672 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2674 amdgpu_device_fill_reset_magic(adev);
2676 r = amdgpu_device_enable_mgpu_fan_boost();
2678 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2680 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
2681 if (amdgpu_passthrough(adev) &&
2682 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
2683 adev->asic_type == CHIP_ALDEBARAN))
2684 amdgpu_dpm_handle_passthrough_sbr(adev, true);
2686 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2687 mutex_lock(&mgpu_info.mutex);
2690 * Reset device p-state to low as this was booted with high.
2692 * This should be performed only after all devices from the same
2693 * hive get initialized.
2695 * However, it's unknown how many device in the hive in advance.
2696 * As this is counted one by one during devices initializations.
2698 * So, we wait for all XGMI interlinked devices initialized.
2699 * This may bring some delays as those devices may come from
2700 * different hives. But that should be OK.
2702 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2703 for (i = 0; i < mgpu_info.num_gpu; i++) {
2704 gpu_instance = &(mgpu_info.gpu_ins[i]);
2705 if (gpu_instance->adev->flags & AMD_IS_APU)
2708 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2709 AMDGPU_XGMI_PSTATE_MIN);
2711 DRM_ERROR("pstate setting failed (%d).\n", r);
2717 mutex_unlock(&mgpu_info.mutex);
2724 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
2726 * @adev: amdgpu_device pointer
2728 * For ASICs need to disable SMC first
2730 static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
2734 if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
2737 for (i = 0; i < adev->num_ip_blocks; i++) {
2738 if (!adev->ip_blocks[i].status.hw)
2740 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2741 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2742 /* XXX handle errors */
2744 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2745 adev->ip_blocks[i].version->funcs->name, r);
2747 adev->ip_blocks[i].status.hw = false;
2753 static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
2757 for (i = 0; i < adev->num_ip_blocks; i++) {
2758 if (!adev->ip_blocks[i].version->funcs->early_fini)
2761 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
2763 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
2764 adev->ip_blocks[i].version->funcs->name, r);
2768 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2769 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2771 amdgpu_amdkfd_suspend(adev, false);
2773 /* Workaroud for ASICs need to disable SMC first */
2774 amdgpu_device_smu_fini_early(adev);
2776 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2777 if (!adev->ip_blocks[i].status.hw)
2780 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2781 /* XXX handle errors */
2783 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2784 adev->ip_blocks[i].version->funcs->name, r);
2787 adev->ip_blocks[i].status.hw = false;
2790 if (amdgpu_sriov_vf(adev)) {
2791 if (amdgpu_virt_release_full_gpu(adev, false))
2792 DRM_ERROR("failed to release exclusive mode on fini\n");
2799 * amdgpu_device_ip_fini - run fini for hardware IPs
2801 * @adev: amdgpu_device pointer
2803 * Main teardown pass for hardware IPs. The list of all the hardware
2804 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2805 * are run. hw_fini tears down the hardware associated with each IP
2806 * and sw_fini tears down any software state associated with each IP.
2807 * Returns 0 on success, negative error code on failure.
2809 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2813 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2814 amdgpu_virt_release_ras_err_handler_data(adev);
2816 if (adev->gmc.xgmi.num_physical_nodes > 1)
2817 amdgpu_xgmi_remove_device(adev);
2819 amdgpu_amdkfd_device_fini_sw(adev);
2821 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2822 if (!adev->ip_blocks[i].status.sw)
2825 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2826 amdgpu_ucode_free_bo(adev);
2827 amdgpu_free_static_csa(&adev->virt.csa_obj);
2828 amdgpu_device_wb_fini(adev);
2829 amdgpu_device_mem_scratch_fini(adev);
2830 amdgpu_ib_pool_fini(adev);
2833 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2834 /* XXX handle errors */
2836 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2837 adev->ip_blocks[i].version->funcs->name, r);
2839 adev->ip_blocks[i].status.sw = false;
2840 adev->ip_blocks[i].status.valid = false;
2843 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2844 if (!adev->ip_blocks[i].status.late_initialized)
2846 if (adev->ip_blocks[i].version->funcs->late_fini)
2847 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2848 adev->ip_blocks[i].status.late_initialized = false;
2851 amdgpu_ras_fini(adev);
2857 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2859 * @work: work_struct.
2861 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2863 struct amdgpu_device *adev =
2864 container_of(work, struct amdgpu_device, delayed_init_work.work);
2867 r = amdgpu_ib_ring_tests(adev);
2869 DRM_ERROR("ib ring test failed (%d).\n", r);
2872 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2874 struct amdgpu_device *adev =
2875 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2877 WARN_ON_ONCE(adev->gfx.gfx_off_state);
2878 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
2880 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2881 adev->gfx.gfx_off_state = true;
2885 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2887 * @adev: amdgpu_device pointer
2889 * Main suspend function for hardware IPs. The list of all the hardware
2890 * IPs that make up the asic is walked, clockgating is disabled and the
2891 * suspend callbacks are run. suspend puts the hardware and software state
2892 * in each IP into a state suitable for suspend.
2893 * Returns 0 on success, negative error code on failure.
2895 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2899 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2900 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2903 * Per PMFW team's suggestion, driver needs to handle gfxoff
2904 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
2905 * scenario. Add the missing df cstate disablement here.
2907 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
2908 dev_warn(adev->dev, "Failed to disallow df cstate");
2910 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2911 if (!adev->ip_blocks[i].status.valid)
2914 /* displays are handled separately */
2915 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2918 /* XXX handle errors */
2919 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2920 /* XXX handle errors */
2922 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2923 adev->ip_blocks[i].version->funcs->name, r);
2927 adev->ip_blocks[i].status.hw = false;
2934 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2936 * @adev: amdgpu_device pointer
2938 * Main suspend function for hardware IPs. The list of all the hardware
2939 * IPs that make up the asic is walked, clockgating is disabled and the
2940 * suspend callbacks are run. suspend puts the hardware and software state
2941 * in each IP into a state suitable for suspend.
2942 * Returns 0 on success, negative error code on failure.
2944 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2949 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
2951 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2952 if (!adev->ip_blocks[i].status.valid)
2954 /* displays are handled in phase1 */
2955 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2957 /* PSP lost connection when err_event_athub occurs */
2958 if (amdgpu_ras_intr_triggered() &&
2959 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2960 adev->ip_blocks[i].status.hw = false;
2964 /* skip unnecessary suspend if we do not initialize them yet */
2965 if (adev->gmc.xgmi.pending_reset &&
2966 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2967 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
2968 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2969 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
2970 adev->ip_blocks[i].status.hw = false;
2974 /* skip suspend of gfx/mes and psp for S0ix
2975 * gfx is in gfxoff state, so on resume it will exit gfxoff just
2976 * like at runtime. PSP is also part of the always on hardware
2977 * so no need to suspend it.
2979 if (adev->in_s0ix &&
2980 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
2981 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2982 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
2985 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
2986 if (adev->in_s0ix &&
2987 (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 0, 0)) &&
2988 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2991 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
2992 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
2993 * from this location and RLC Autoload automatically also gets loaded
2994 * from here based on PMFW -> PSP message during re-init sequence.
2995 * Therefore, the psp suspend & resume should be skipped to avoid destroy
2996 * the TMR and reload FWs again for IMU enabled APU ASICs.
2998 if (amdgpu_in_reset(adev) &&
2999 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3000 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3003 /* XXX handle errors */
3004 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3005 /* XXX handle errors */
3007 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3008 adev->ip_blocks[i].version->funcs->name, r);
3010 adev->ip_blocks[i].status.hw = false;
3011 /* handle putting the SMC in the appropriate state */
3012 if (!amdgpu_sriov_vf(adev)) {
3013 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3014 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3016 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3017 adev->mp1_state, r);
3028 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3030 * @adev: amdgpu_device pointer
3032 * Main suspend function for hardware IPs. The list of all the hardware
3033 * IPs that make up the asic is walked, clockgating is disabled and the
3034 * suspend callbacks are run. suspend puts the hardware and software state
3035 * in each IP into a state suitable for suspend.
3036 * Returns 0 on success, negative error code on failure.
3038 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3042 if (amdgpu_sriov_vf(adev)) {
3043 amdgpu_virt_fini_data_exchange(adev);
3044 amdgpu_virt_request_full_gpu(adev, false);
3047 r = amdgpu_device_ip_suspend_phase1(adev);
3050 r = amdgpu_device_ip_suspend_phase2(adev);
3052 if (amdgpu_sriov_vf(adev))
3053 amdgpu_virt_release_full_gpu(adev, false);
3058 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3062 static enum amd_ip_block_type ip_order[] = {
3063 AMD_IP_BLOCK_TYPE_COMMON,
3064 AMD_IP_BLOCK_TYPE_GMC,
3065 AMD_IP_BLOCK_TYPE_PSP,
3066 AMD_IP_BLOCK_TYPE_IH,
3069 for (i = 0; i < adev->num_ip_blocks; i++) {
3071 struct amdgpu_ip_block *block;
3073 block = &adev->ip_blocks[i];
3074 block->status.hw = false;
3076 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3078 if (block->version->type != ip_order[j] ||
3079 !block->status.valid)
3082 r = block->version->funcs->hw_init(adev);
3083 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3086 block->status.hw = true;
3093 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3097 static enum amd_ip_block_type ip_order[] = {
3098 AMD_IP_BLOCK_TYPE_SMC,
3099 AMD_IP_BLOCK_TYPE_DCE,
3100 AMD_IP_BLOCK_TYPE_GFX,
3101 AMD_IP_BLOCK_TYPE_SDMA,
3102 AMD_IP_BLOCK_TYPE_MES,
3103 AMD_IP_BLOCK_TYPE_UVD,
3104 AMD_IP_BLOCK_TYPE_VCE,
3105 AMD_IP_BLOCK_TYPE_VCN,
3106 AMD_IP_BLOCK_TYPE_JPEG
3109 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3111 struct amdgpu_ip_block *block;
3113 for (j = 0; j < adev->num_ip_blocks; j++) {
3114 block = &adev->ip_blocks[j];
3116 if (block->version->type != ip_order[i] ||
3117 !block->status.valid ||
3121 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3122 r = block->version->funcs->resume(adev);
3124 r = block->version->funcs->hw_init(adev);
3126 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3129 block->status.hw = true;
3137 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3139 * @adev: amdgpu_device pointer
3141 * First resume function for hardware IPs. The list of all the hardware
3142 * IPs that make up the asic is walked and the resume callbacks are run for
3143 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3144 * after a suspend and updates the software state as necessary. This
3145 * function is also used for restoring the GPU after a GPU reset.
3146 * Returns 0 on success, negative error code on failure.
3148 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3152 for (i = 0; i < adev->num_ip_blocks; i++) {
3153 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3155 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3156 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3157 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3158 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3160 r = adev->ip_blocks[i].version->funcs->resume(adev);
3162 DRM_ERROR("resume of IP block <%s> failed %d\n",
3163 adev->ip_blocks[i].version->funcs->name, r);
3166 adev->ip_blocks[i].status.hw = true;
3174 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3176 * @adev: amdgpu_device pointer
3178 * First resume function for hardware IPs. The list of all the hardware
3179 * IPs that make up the asic is walked and the resume callbacks are run for
3180 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3181 * functional state after a suspend and updates the software state as
3182 * necessary. This function is also used for restoring the GPU after a GPU
3184 * Returns 0 on success, negative error code on failure.
3186 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3190 for (i = 0; i < adev->num_ip_blocks; i++) {
3191 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3193 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3194 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3195 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3196 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3198 r = adev->ip_blocks[i].version->funcs->resume(adev);
3200 DRM_ERROR("resume of IP block <%s> failed %d\n",
3201 adev->ip_blocks[i].version->funcs->name, r);
3204 adev->ip_blocks[i].status.hw = true;
3211 * amdgpu_device_ip_resume - run resume for hardware IPs
3213 * @adev: amdgpu_device pointer
3215 * Main resume function for hardware IPs. The hardware IPs
3216 * are split into two resume functions because they are
3217 * also used in recovering from a GPU reset and some additional
3218 * steps need to be take between them. In this case (S3/S4) they are
3220 * Returns 0 on success, negative error code on failure.
3222 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3226 r = amdgpu_device_ip_resume_phase1(adev);
3230 r = amdgpu_device_fw_loading(adev);
3234 r = amdgpu_device_ip_resume_phase2(adev);
3240 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3242 * @adev: amdgpu_device pointer
3244 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3246 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3248 if (amdgpu_sriov_vf(adev)) {
3249 if (adev->is_atom_fw) {
3250 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3251 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3253 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3254 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3257 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3258 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3263 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3265 * @asic_type: AMD asic type
3267 * Check if there is DC (new modesetting infrastructre) support for an asic.
3268 * returns true if DC has support, false if not.
3270 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3272 switch (asic_type) {
3273 #ifdef CONFIG_DRM_AMDGPU_SI
3277 /* chips with no display hardware */
3279 #if defined(CONFIG_DRM_AMD_DC)
3285 * We have systems in the wild with these ASICs that require
3286 * LVDS and VGA support which is not supported with DC.
3288 * Fallback to the non-DC driver here by default so as not to
3289 * cause regressions.
3291 #if defined(CONFIG_DRM_AMD_DC_SI)
3292 return amdgpu_dc > 0;
3301 * We have systems in the wild with these ASICs that require
3302 * VGA support which is not supported with DC.
3304 * Fallback to the non-DC driver here by default so as not to
3305 * cause regressions.
3307 return amdgpu_dc > 0;
3309 return amdgpu_dc != 0;
3313 DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");
3320 * amdgpu_device_has_dc_support - check if dc is supported
3322 * @adev: amdgpu_device pointer
3324 * Returns true for supported, false for not supported
3326 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3328 if (adev->enable_virtual_display ||
3329 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3332 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3335 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3337 struct amdgpu_device *adev =
3338 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3339 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3341 /* It's a bug to not have a hive within this function */
3346 * Use task barrier to synchronize all xgmi reset works across the
3347 * hive. task_barrier_enter and task_barrier_exit will block
3348 * until all the threads running the xgmi reset works reach
3349 * those points. task_barrier_full will do both blocks.
3351 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3353 task_barrier_enter(&hive->tb);
3354 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3356 if (adev->asic_reset_res)
3359 task_barrier_exit(&hive->tb);
3360 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3362 if (adev->asic_reset_res)
3365 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
3366 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
3367 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
3370 task_barrier_full(&hive->tb);
3371 adev->asic_reset_res = amdgpu_asic_reset(adev);
3375 if (adev->asic_reset_res)
3376 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3377 adev->asic_reset_res, adev_to_drm(adev)->unique);
3378 amdgpu_put_xgmi_hive(hive);
3381 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3383 char *input = amdgpu_lockup_timeout;
3384 char *timeout_setting = NULL;
3390 * By default timeout for non compute jobs is 10000
3391 * and 60000 for compute jobs.
3392 * In SR-IOV or passthrough mode, timeout for compute
3393 * jobs are 60000 by default.
3395 adev->gfx_timeout = msecs_to_jiffies(10000);
3396 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3397 if (amdgpu_sriov_vf(adev))
3398 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3399 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3401 adev->compute_timeout = msecs_to_jiffies(60000);
3403 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3404 while ((timeout_setting = strsep(&input, ",")) &&
3405 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3406 ret = kstrtol(timeout_setting, 0, &timeout);
3413 } else if (timeout < 0) {
3414 timeout = MAX_SCHEDULE_TIMEOUT;
3415 dev_warn(adev->dev, "lockup timeout disabled");
3416 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3418 timeout = msecs_to_jiffies(timeout);
3423 adev->gfx_timeout = timeout;
3426 adev->compute_timeout = timeout;
3429 adev->sdma_timeout = timeout;
3432 adev->video_timeout = timeout;
3439 * There is only one value specified and
3440 * it should apply to all non-compute jobs.
3443 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3444 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3445 adev->compute_timeout = adev->gfx_timeout;
3453 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3455 * @adev: amdgpu_device pointer
3457 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3459 static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3461 struct iommu_domain *domain;
3463 domain = iommu_get_domain_for_dev(adev->dev);
3464 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3465 adev->ram_is_direct_mapped = true;
3468 static const struct attribute *amdgpu_dev_attributes[] = {
3469 &dev_attr_pcie_replay_count.attr,
3473 static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
3475 if (amdgpu_mcbp == 1)
3476 adev->gfx.mcbp = true;
3477 else if (amdgpu_mcbp == 0)
3478 adev->gfx.mcbp = false;
3479 else if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 0)) &&
3480 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 0, 0)) &&
3481 adev->gfx.num_gfx_rings)
3482 adev->gfx.mcbp = true;
3484 if (amdgpu_sriov_vf(adev))
3485 adev->gfx.mcbp = true;
3488 DRM_INFO("MCBP is enabled\n");
3492 * amdgpu_device_init - initialize the driver
3494 * @adev: amdgpu_device pointer
3495 * @flags: driver flags
3497 * Initializes the driver info and hw (all asics).
3498 * Returns 0 for success or an error on failure.
3499 * Called at driver startup.
3501 int amdgpu_device_init(struct amdgpu_device *adev,
3504 struct drm_device *ddev = adev_to_drm(adev);
3505 struct pci_dev *pdev = adev->pdev;
3511 adev->shutdown = false;
3512 adev->flags = flags;
3514 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3515 adev->asic_type = amdgpu_force_asic_type;
3517 adev->asic_type = flags & AMD_ASIC_MASK;
3519 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3520 if (amdgpu_emu_mode == 1)
3521 adev->usec_timeout *= 10;
3522 adev->gmc.gart_size = 512 * 1024 * 1024;
3523 adev->accel_working = false;
3524 adev->num_rings = 0;
3525 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3526 adev->mman.buffer_funcs = NULL;
3527 adev->mman.buffer_funcs_ring = NULL;
3528 adev->vm_manager.vm_pte_funcs = NULL;
3529 adev->vm_manager.vm_pte_num_scheds = 0;
3530 adev->gmc.gmc_funcs = NULL;
3531 adev->harvest_ip_mask = 0x0;
3532 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3533 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3535 adev->smc_rreg = &amdgpu_invalid_rreg;
3536 adev->smc_wreg = &amdgpu_invalid_wreg;
3537 adev->pcie_rreg = &amdgpu_invalid_rreg;
3538 adev->pcie_wreg = &amdgpu_invalid_wreg;
3539 adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext;
3540 adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext;
3541 adev->pciep_rreg = &amdgpu_invalid_rreg;
3542 adev->pciep_wreg = &amdgpu_invalid_wreg;
3543 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3544 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3545 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3546 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3547 adev->didt_rreg = &amdgpu_invalid_rreg;
3548 adev->didt_wreg = &amdgpu_invalid_wreg;
3549 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3550 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3551 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3552 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3554 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3555 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3556 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3558 /* mutex initialization are all done here so we
3559 * can recall function without having locking issues
3561 mutex_init(&adev->firmware.mutex);
3562 mutex_init(&adev->pm.mutex);
3563 mutex_init(&adev->gfx.gpu_clock_mutex);
3564 mutex_init(&adev->srbm_mutex);
3565 mutex_init(&adev->gfx.pipe_reserve_mutex);
3566 mutex_init(&adev->gfx.gfx_off_mutex);
3567 mutex_init(&adev->gfx.partition_mutex);
3568 mutex_init(&adev->grbm_idx_mutex);
3569 mutex_init(&adev->mn_lock);
3570 mutex_init(&adev->virt.vf_errors.lock);
3571 hash_init(adev->mn_hash);
3572 mutex_init(&adev->psp.mutex);
3573 mutex_init(&adev->notifier_lock);
3574 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3575 mutex_init(&adev->benchmark_mutex);
3577 amdgpu_device_init_apu_flags(adev);
3579 r = amdgpu_device_check_arguments(adev);
3583 spin_lock_init(&adev->mmio_idx_lock);
3584 spin_lock_init(&adev->smc_idx_lock);
3585 spin_lock_init(&adev->pcie_idx_lock);
3586 spin_lock_init(&adev->uvd_ctx_idx_lock);
3587 spin_lock_init(&adev->didt_idx_lock);
3588 spin_lock_init(&adev->gc_cac_idx_lock);
3589 spin_lock_init(&adev->se_cac_idx_lock);
3590 spin_lock_init(&adev->audio_endpt_idx_lock);
3591 spin_lock_init(&adev->mm_stats.lock);
3593 INIT_LIST_HEAD(&adev->shadow_list);
3594 mutex_init(&adev->shadow_list_lock);
3596 INIT_LIST_HEAD(&adev->reset_list);
3598 INIT_LIST_HEAD(&adev->ras_list);
3600 INIT_DELAYED_WORK(&adev->delayed_init_work,
3601 amdgpu_device_delayed_init_work_handler);
3602 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3603 amdgpu_device_delay_enable_gfx_off);
3605 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3607 adev->gfx.gfx_off_req_count = 1;
3608 adev->gfx.gfx_off_residency = 0;
3609 adev->gfx.gfx_off_entrycount = 0;
3610 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3612 atomic_set(&adev->throttling_logging_enabled, 1);
3614 * If throttling continues, logging will be performed every minute
3615 * to avoid log flooding. "-1" is subtracted since the thermal
3616 * throttling interrupt comes every second. Thus, the total logging
3617 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3618 * for throttling interrupt) = 60 seconds.
3620 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3621 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3623 /* Registers mapping */
3624 /* TODO: block userspace mapping of io register */
3625 if (adev->asic_type >= CHIP_BONAIRE) {
3626 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3627 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3629 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3630 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3633 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
3634 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
3636 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3640 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3641 DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size);
3644 * Reset domain needs to be present early, before XGMI hive discovered
3645 * (if any) and intitialized to use reset sem and in_gpu reset flag
3646 * early on during init and before calling to RREG32.
3648 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
3649 if (!adev->reset_domain)
3652 /* detect hw virtualization here */
3653 amdgpu_detect_virtualization(adev);
3655 amdgpu_device_get_pcie_info(adev);
3657 r = amdgpu_device_get_job_timeout_settings(adev);
3659 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3663 /* early init functions */
3664 r = amdgpu_device_ip_early_init(adev);
3668 amdgpu_device_set_mcbp(adev);
3670 /* Get rid of things like offb */
3671 r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
3675 /* Enable TMZ based on IP_VERSION */
3676 amdgpu_gmc_tmz_set(adev);
3678 amdgpu_gmc_noretry_set(adev);
3679 /* Need to get xgmi info early to decide the reset behavior*/
3680 if (adev->gmc.xgmi.supported) {
3681 r = adev->gfxhub.funcs->get_xgmi_info(adev);
3686 /* enable PCIE atomic ops */
3687 if (amdgpu_sriov_vf(adev)) {
3688 if (adev->virt.fw_reserve.p_pf2vf)
3689 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
3690 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
3691 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3692 /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
3693 * internal path natively support atomics, set have_atomics_support to true.
3695 } else if ((adev->flags & AMD_IS_APU) &&
3696 (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))) {
3697 adev->have_atomics_support = true;
3699 adev->have_atomics_support =
3700 !pci_enable_atomic_ops_to_root(adev->pdev,
3701 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3702 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3705 if (!adev->have_atomics_support)
3706 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
3708 /* doorbell bar mapping and doorbell index init*/
3709 amdgpu_doorbell_init(adev);
3711 if (amdgpu_emu_mode == 1) {
3712 /* post the asic on emulation mode */
3713 emu_soc_asic_init(adev);
3714 goto fence_driver_init;
3717 amdgpu_reset_init(adev);
3719 /* detect if we are with an SRIOV vbios */
3721 amdgpu_device_detect_sriov_bios(adev);
3723 /* check if we need to reset the asic
3724 * E.g., driver was not cleanly unloaded previously, etc.
3726 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3727 if (adev->gmc.xgmi.num_physical_nodes) {
3728 dev_info(adev->dev, "Pending hive reset.\n");
3729 adev->gmc.xgmi.pending_reset = true;
3730 /* Only need to init necessary block for SMU to handle the reset */
3731 for (i = 0; i < adev->num_ip_blocks; i++) {
3732 if (!adev->ip_blocks[i].status.valid)
3734 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3735 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3736 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3737 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
3738 DRM_DEBUG("IP %s disabled for hw_init.\n",
3739 adev->ip_blocks[i].version->funcs->name);
3740 adev->ip_blocks[i].status.hw = true;
3744 tmp = amdgpu_reset_method;
3745 /* It should do a default reset when loading or reloading the driver,
3746 * regardless of the module parameter reset_method.
3748 amdgpu_reset_method = AMD_RESET_METHOD_NONE;
3749 r = amdgpu_asic_reset(adev);
3750 amdgpu_reset_method = tmp;
3752 dev_err(adev->dev, "asic reset on init failed\n");
3758 /* Post card if necessary */
3759 if (amdgpu_device_need_post(adev)) {
3761 dev_err(adev->dev, "no vBIOS found\n");
3765 DRM_INFO("GPU posting now...\n");
3766 r = amdgpu_device_asic_init(adev);
3768 dev_err(adev->dev, "gpu post error!\n");
3774 if (adev->is_atom_fw) {
3775 /* Initialize clocks */
3776 r = amdgpu_atomfirmware_get_clock_info(adev);
3778 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3779 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3783 /* Initialize clocks */
3784 r = amdgpu_atombios_get_clock_info(adev);
3786 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3787 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3790 /* init i2c buses */
3791 if (!amdgpu_device_has_dc_support(adev))
3792 amdgpu_atombios_i2c_init(adev);
3798 r = amdgpu_fence_driver_sw_init(adev);
3800 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
3801 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3805 /* init the mode config */
3806 drm_mode_config_init(adev_to_drm(adev));
3808 r = amdgpu_device_ip_init(adev);
3810 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3811 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3812 goto release_ras_con;
3815 amdgpu_fence_driver_hw_init(adev);
3818 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3819 adev->gfx.config.max_shader_engines,
3820 adev->gfx.config.max_sh_per_se,
3821 adev->gfx.config.max_cu_per_sh,
3822 adev->gfx.cu_info.number);
3824 adev->accel_working = true;
3826 amdgpu_vm_check_compute_bug(adev);
3828 /* Initialize the buffer migration limit. */
3829 if (amdgpu_moverate >= 0)
3830 max_MBps = amdgpu_moverate;
3832 max_MBps = 8; /* Allow 8 MB/s. */
3833 /* Get a log2 for easy divisions. */
3834 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3836 r = amdgpu_atombios_sysfs_init(adev);
3838 drm_err(&adev->ddev,
3839 "registering atombios sysfs failed (%d).\n", r);
3841 r = amdgpu_pm_sysfs_init(adev);
3843 DRM_ERROR("registering pm sysfs failed (%d).\n", r);
3845 r = amdgpu_ucode_sysfs_init(adev);
3847 adev->ucode_sysfs_en = false;
3848 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3850 adev->ucode_sysfs_en = true;
3853 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3854 * Otherwise the mgpu fan boost feature will be skipped due to the
3855 * gpu instance is counted less.
3857 amdgpu_register_gpu_instance(adev);
3859 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3860 * explicit gating rather than handling it automatically.
3862 if (!adev->gmc.xgmi.pending_reset) {
3863 r = amdgpu_device_ip_late_init(adev);
3865 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3866 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3867 goto release_ras_con;
3870 amdgpu_ras_resume(adev);
3871 queue_delayed_work(system_wq, &adev->delayed_init_work,
3872 msecs_to_jiffies(AMDGPU_RESUME_MS));
3875 if (amdgpu_sriov_vf(adev)) {
3876 amdgpu_virt_release_full_gpu(adev, true);
3877 flush_delayed_work(&adev->delayed_init_work);
3880 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3882 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3884 amdgpu_fru_sysfs_init(adev);
3886 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3887 r = amdgpu_pmu_init(adev);
3889 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3891 /* Have stored pci confspace at hand for restore in sudden PCI error */
3892 if (amdgpu_device_cache_pci_state(adev->pdev))
3893 pci_restore_state(pdev);
3895 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3896 /* this will fail for cards that aren't VGA class devices, just
3899 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3900 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
3902 px = amdgpu_device_supports_px(ddev);
3904 if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
3905 apple_gmux_detect(NULL, NULL)))
3906 vga_switcheroo_register_client(adev->pdev,
3907 &amdgpu_switcheroo_ops, px);
3910 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3912 if (adev->gmc.xgmi.pending_reset)
3913 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
3914 msecs_to_jiffies(AMDGPU_RESUME_MS));
3916 amdgpu_device_check_iommu_direct_map(adev);
3921 if (amdgpu_sriov_vf(adev))
3922 amdgpu_virt_release_full_gpu(adev, true);
3924 /* failed in exclusive mode due to timeout */
3925 if (amdgpu_sriov_vf(adev) &&
3926 !amdgpu_sriov_runtime(adev) &&
3927 amdgpu_virt_mmio_blocked(adev) &&
3928 !amdgpu_virt_wait_reset(adev)) {
3929 dev_err(adev->dev, "VF exclusive mode timeout\n");
3930 /* Don't send request since VF is inactive. */
3931 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3932 adev->virt.ops = NULL;
3935 amdgpu_release_ras_context(adev);
3938 amdgpu_vf_error_trans_all(adev);
3943 static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
3946 /* Clear all CPU mappings pointing to this device */
3947 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
3949 /* Unmap all mapped bars - Doorbell, registers and VRAM */
3950 amdgpu_doorbell_fini(adev);
3952 iounmap(adev->rmmio);
3954 if (adev->mman.aper_base_kaddr)
3955 iounmap(adev->mman.aper_base_kaddr);
3956 adev->mman.aper_base_kaddr = NULL;
3958 /* Memory manager related */
3959 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
3960 arch_phys_wc_del(adev->gmc.vram_mtrr);
3961 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
3966 * amdgpu_device_fini_hw - tear down the driver
3968 * @adev: amdgpu_device pointer
3970 * Tear down the driver info (all asics).
3971 * Called at driver shutdown.
3973 void amdgpu_device_fini_hw(struct amdgpu_device *adev)
3975 dev_info(adev->dev, "amdgpu: finishing device.\n");
3976 flush_delayed_work(&adev->delayed_init_work);
3977 adev->shutdown = true;
3979 /* make sure IB test finished before entering exclusive mode
3980 * to avoid preemption on IB test
3982 if (amdgpu_sriov_vf(adev)) {
3983 amdgpu_virt_request_full_gpu(adev, false);
3984 amdgpu_virt_fini_data_exchange(adev);
3987 /* disable all interrupts */
3988 amdgpu_irq_disable_all(adev);
3989 if (adev->mode_info.mode_config_initialized) {
3990 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
3991 drm_helper_force_disable_all(adev_to_drm(adev));
3993 drm_atomic_helper_shutdown(adev_to_drm(adev));
3995 amdgpu_fence_driver_hw_fini(adev);
3997 if (adev->mman.initialized)
3998 drain_workqueue(adev->mman.bdev.wq);
4000 if (adev->pm.sysfs_initialized)
4001 amdgpu_pm_sysfs_fini(adev);
4002 if (adev->ucode_sysfs_en)
4003 amdgpu_ucode_sysfs_fini(adev);
4004 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4005 amdgpu_fru_sysfs_fini(adev);
4007 /* disable ras feature must before hw fini */
4008 amdgpu_ras_pre_fini(adev);
4010 amdgpu_device_ip_fini_early(adev);
4012 amdgpu_irq_fini_hw(adev);
4014 if (adev->mman.initialized)
4015 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4017 amdgpu_gart_dummy_page_fini(adev);
4019 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4020 amdgpu_device_unmap_mmio(adev);
4024 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4029 amdgpu_fence_driver_sw_fini(adev);
4030 amdgpu_device_ip_fini(adev);
4031 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4032 adev->accel_working = false;
4033 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4035 amdgpu_reset_fini(adev);
4037 /* free i2c buses */
4038 if (!amdgpu_device_has_dc_support(adev))
4039 amdgpu_i2c_fini(adev);
4041 if (amdgpu_emu_mode != 1)
4042 amdgpu_atombios_fini(adev);
4047 px = amdgpu_device_supports_px(adev_to_drm(adev));
4049 if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
4050 apple_gmux_detect(NULL, NULL)))
4051 vga_switcheroo_unregister_client(adev->pdev);
4054 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4056 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4057 vga_client_unregister(adev->pdev);
4059 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4061 iounmap(adev->rmmio);
4063 amdgpu_doorbell_fini(adev);
4067 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4068 amdgpu_pmu_fini(adev);
4069 if (adev->mman.discovery_bin)
4070 amdgpu_discovery_fini(adev);
4072 amdgpu_reset_put_reset_domain(adev->reset_domain);
4073 adev->reset_domain = NULL;
4075 kfree(adev->pci_state);
4080 * amdgpu_device_evict_resources - evict device resources
4081 * @adev: amdgpu device object
4083 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4084 * of the vram memory type. Mainly used for evicting device resources
4088 static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4092 /* No need to evict vram on APUs for suspend to ram or s2idle */
4093 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4096 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4098 DRM_WARN("evicting device resources failed\n");
4106 * amdgpu_device_suspend - initiate device suspend
4108 * @dev: drm dev pointer
4109 * @fbcon : notify the fbdev of suspend
4111 * Puts the hw in the suspend state (all asics).
4112 * Returns 0 for success or an error on failure.
4113 * Called at driver suspend.
4115 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4117 struct amdgpu_device *adev = drm_to_adev(dev);
4120 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4123 adev->in_suspend = true;
4125 /* Evict the majority of BOs before grabbing the full access */
4126 r = amdgpu_device_evict_resources(adev);
4130 if (amdgpu_sriov_vf(adev)) {
4131 amdgpu_virt_fini_data_exchange(adev);
4132 r = amdgpu_virt_request_full_gpu(adev, false);
4137 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4138 DRM_WARN("smart shift update failed\n");
4141 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4143 cancel_delayed_work_sync(&adev->delayed_init_work);
4144 flush_delayed_work(&adev->gfx.gfx_off_delay_work);
4146 amdgpu_ras_suspend(adev);
4148 amdgpu_device_ip_suspend_phase1(adev);
4151 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4153 r = amdgpu_device_evict_resources(adev);
4157 amdgpu_fence_driver_hw_fini(adev);
4159 amdgpu_device_ip_suspend_phase2(adev);
4161 if (amdgpu_sriov_vf(adev))
4162 amdgpu_virt_release_full_gpu(adev, false);
4168 * amdgpu_device_resume - initiate device resume
4170 * @dev: drm dev pointer
4171 * @fbcon : notify the fbdev of resume
4173 * Bring the hw back to operating state (all asics).
4174 * Returns 0 for success or an error on failure.
4175 * Called at driver resume.
4177 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4179 struct amdgpu_device *adev = drm_to_adev(dev);
4182 if (amdgpu_sriov_vf(adev)) {
4183 r = amdgpu_virt_request_full_gpu(adev, true);
4188 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4192 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4195 if (amdgpu_device_need_post(adev)) {
4196 r = amdgpu_device_asic_init(adev);
4198 dev_err(adev->dev, "amdgpu asic init failed\n");
4201 r = amdgpu_device_ip_resume(adev);
4204 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4207 amdgpu_fence_driver_hw_init(adev);
4209 r = amdgpu_device_ip_late_init(adev);
4213 queue_delayed_work(system_wq, &adev->delayed_init_work,
4214 msecs_to_jiffies(AMDGPU_RESUME_MS));
4216 if (!adev->in_s0ix) {
4217 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4223 if (amdgpu_sriov_vf(adev)) {
4224 amdgpu_virt_init_data_exchange(adev);
4225 amdgpu_virt_release_full_gpu(adev, true);
4231 /* Make sure IB tests flushed */
4232 flush_delayed_work(&adev->delayed_init_work);
4235 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4237 amdgpu_ras_resume(adev);
4239 if (adev->mode_info.num_crtc) {
4241 * Most of the connector probing functions try to acquire runtime pm
4242 * refs to ensure that the GPU is powered on when connector polling is
4243 * performed. Since we're calling this from a runtime PM callback,
4244 * trying to acquire rpm refs will cause us to deadlock.
4246 * Since we're guaranteed to be holding the rpm lock, it's safe to
4247 * temporarily disable the rpm helpers so this doesn't deadlock us.
4250 dev->dev->power.disable_depth++;
4252 if (!adev->dc_enabled)
4253 drm_helper_hpd_irq_event(dev);
4255 drm_kms_helper_hotplug_event(dev);
4257 dev->dev->power.disable_depth--;
4260 adev->in_suspend = false;
4262 if (adev->enable_mes)
4263 amdgpu_mes_self_test(adev);
4265 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4266 DRM_WARN("smart shift update failed\n");
4272 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4274 * @adev: amdgpu_device pointer
4276 * The list of all the hardware IPs that make up the asic is walked and
4277 * the check_soft_reset callbacks are run. check_soft_reset determines
4278 * if the asic is still hung or not.
4279 * Returns true if any of the IPs are still in a hung state, false if not.
4281 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4284 bool asic_hang = false;
4286 if (amdgpu_sriov_vf(adev))
4289 if (amdgpu_asic_need_full_reset(adev))
4292 for (i = 0; i < adev->num_ip_blocks; i++) {
4293 if (!adev->ip_blocks[i].status.valid)
4295 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4296 adev->ip_blocks[i].status.hang =
4297 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4298 if (adev->ip_blocks[i].status.hang) {
4299 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4307 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4309 * @adev: amdgpu_device pointer
4311 * The list of all the hardware IPs that make up the asic is walked and the
4312 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4313 * handles any IP specific hardware or software state changes that are
4314 * necessary for a soft reset to succeed.
4315 * Returns 0 on success, negative error code on failure.
4317 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4321 for (i = 0; i < adev->num_ip_blocks; i++) {
4322 if (!adev->ip_blocks[i].status.valid)
4324 if (adev->ip_blocks[i].status.hang &&
4325 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4326 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4336 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4338 * @adev: amdgpu_device pointer
4340 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4341 * reset is necessary to recover.
4342 * Returns true if a full asic reset is required, false if not.
4344 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4348 if (amdgpu_asic_need_full_reset(adev))
4351 for (i = 0; i < adev->num_ip_blocks; i++) {
4352 if (!adev->ip_blocks[i].status.valid)
4354 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4355 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4356 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4357 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4358 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4359 if (adev->ip_blocks[i].status.hang) {
4360 dev_info(adev->dev, "Some block need full reset!\n");
4369 * amdgpu_device_ip_soft_reset - do a soft reset
4371 * @adev: amdgpu_device pointer
4373 * The list of all the hardware IPs that make up the asic is walked and the
4374 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4375 * IP specific hardware or software state changes that are necessary to soft
4377 * Returns 0 on success, negative error code on failure.
4379 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4383 for (i = 0; i < adev->num_ip_blocks; i++) {
4384 if (!adev->ip_blocks[i].status.valid)
4386 if (adev->ip_blocks[i].status.hang &&
4387 adev->ip_blocks[i].version->funcs->soft_reset) {
4388 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4398 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4400 * @adev: amdgpu_device pointer
4402 * The list of all the hardware IPs that make up the asic is walked and the
4403 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4404 * handles any IP specific hardware or software state changes that are
4405 * necessary after the IP has been soft reset.
4406 * Returns 0 on success, negative error code on failure.
4408 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4412 for (i = 0; i < adev->num_ip_blocks; i++) {
4413 if (!adev->ip_blocks[i].status.valid)
4415 if (adev->ip_blocks[i].status.hang &&
4416 adev->ip_blocks[i].version->funcs->post_soft_reset)
4417 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4426 * amdgpu_device_recover_vram - Recover some VRAM contents
4428 * @adev: amdgpu_device pointer
4430 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4431 * restore things like GPUVM page tables after a GPU reset where
4432 * the contents of VRAM might be lost.
4435 * 0 on success, negative error code on failure.
4437 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4439 struct dma_fence *fence = NULL, *next = NULL;
4440 struct amdgpu_bo *shadow;
4441 struct amdgpu_bo_vm *vmbo;
4444 if (amdgpu_sriov_runtime(adev))
4445 tmo = msecs_to_jiffies(8000);
4447 tmo = msecs_to_jiffies(100);
4449 dev_info(adev->dev, "recover vram bo from shadow start\n");
4450 mutex_lock(&adev->shadow_list_lock);
4451 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4452 /* If vm is compute context or adev is APU, shadow will be NULL */
4455 shadow = vmbo->shadow;
4457 /* No need to recover an evicted BO */
4458 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4459 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4460 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4463 r = amdgpu_bo_restore_shadow(shadow, &next);
4468 tmo = dma_fence_wait_timeout(fence, false, tmo);
4469 dma_fence_put(fence);
4474 } else if (tmo < 0) {
4482 mutex_unlock(&adev->shadow_list_lock);
4485 tmo = dma_fence_wait_timeout(fence, false, tmo);
4486 dma_fence_put(fence);
4488 if (r < 0 || tmo <= 0) {
4489 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4493 dev_info(adev->dev, "recover vram bo from shadow done\n");
4499 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4501 * @adev: amdgpu_device pointer
4502 * @from_hypervisor: request from hypervisor
4504 * do VF FLR and reinitialize Asic
4505 * return 0 means succeeded otherwise failed
4507 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4508 bool from_hypervisor)
4511 struct amdgpu_hive_info *hive = NULL;
4512 int retry_limit = 0;
4515 amdgpu_amdkfd_pre_reset(adev);
4517 if (from_hypervisor)
4518 r = amdgpu_virt_request_full_gpu(adev, true);
4520 r = amdgpu_virt_reset_gpu(adev);
4523 amdgpu_irq_gpu_reset_resume_helper(adev);
4525 /* some sw clean up VF needs to do before recover */
4526 amdgpu_virt_post_reset(adev);
4528 /* Resume IP prior to SMC */
4529 r = amdgpu_device_ip_reinit_early_sriov(adev);
4533 amdgpu_virt_init_data_exchange(adev);
4535 r = amdgpu_device_fw_loading(adev);
4539 /* now we are okay to resume SMC/CP/SDMA */
4540 r = amdgpu_device_ip_reinit_late_sriov(adev);
4544 hive = amdgpu_get_xgmi_hive(adev);
4545 /* Update PSP FW topology after reset */
4546 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
4547 r = amdgpu_xgmi_update_topology(hive, adev);
4550 amdgpu_put_xgmi_hive(hive);
4553 r = amdgpu_ib_ring_tests(adev);
4555 amdgpu_amdkfd_post_reset(adev);
4559 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4560 amdgpu_inc_vram_lost(adev);
4561 r = amdgpu_device_recover_vram(adev);
4563 amdgpu_virt_release_full_gpu(adev, true);
4565 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
4566 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
4570 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
4577 * amdgpu_device_has_job_running - check if there is any job in mirror list
4579 * @adev: amdgpu_device pointer
4581 * check if there is any job in mirror list
4583 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4586 struct drm_sched_job *job;
4588 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4589 struct amdgpu_ring *ring = adev->rings[i];
4591 if (!ring || !ring->sched.thread)
4594 spin_lock(&ring->sched.job_list_lock);
4595 job = list_first_entry_or_null(&ring->sched.pending_list,
4596 struct drm_sched_job, list);
4597 spin_unlock(&ring->sched.job_list_lock);
4605 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4607 * @adev: amdgpu_device pointer
4609 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4612 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4615 if (amdgpu_gpu_recovery == 0)
4618 /* Skip soft reset check in fatal error mode */
4619 if (!amdgpu_ras_is_poison_mode_supported(adev))
4622 if (amdgpu_sriov_vf(adev))
4625 if (amdgpu_gpu_recovery == -1) {
4626 switch (adev->asic_type) {
4627 #ifdef CONFIG_DRM_AMDGPU_SI
4634 #ifdef CONFIG_DRM_AMDGPU_CIK
4641 case CHIP_CYAN_SKILLFISH:
4651 dev_info(adev->dev, "GPU recovery disabled.\n");
4655 int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
4660 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
4662 dev_info(adev->dev, "GPU mode1 reset\n");
4665 pci_clear_master(adev->pdev);
4667 amdgpu_device_cache_pci_state(adev->pdev);
4669 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
4670 dev_info(adev->dev, "GPU smu mode1 reset\n");
4671 ret = amdgpu_dpm_mode1_reset(adev);
4673 dev_info(adev->dev, "GPU psp mode1 reset\n");
4674 ret = psp_gpu_reset(adev);
4678 goto mode1_reset_failed;
4680 amdgpu_device_load_pci_state(adev->pdev);
4681 ret = amdgpu_psp_wait_for_bootloader(adev);
4683 goto mode1_reset_failed;
4685 /* wait for asic to come out of reset */
4686 for (i = 0; i < adev->usec_timeout; i++) {
4687 u32 memsize = adev->nbio.funcs->get_memsize(adev);
4689 if (memsize != 0xffffffff)
4694 if (i >= adev->usec_timeout) {
4696 goto mode1_reset_failed;
4699 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
4704 dev_err(adev->dev, "GPU mode1 reset failed\n");
4708 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4709 struct amdgpu_reset_context *reset_context)
4712 struct amdgpu_job *job = NULL;
4713 bool need_full_reset =
4714 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4716 if (reset_context->reset_req_dev == adev)
4717 job = reset_context->job;
4719 if (amdgpu_sriov_vf(adev)) {
4720 /* stop the data exchange thread */
4721 amdgpu_virt_fini_data_exchange(adev);
4724 amdgpu_fence_driver_isr_toggle(adev, true);
4726 /* block all schedulers and reset given job's ring */
4727 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4728 struct amdgpu_ring *ring = adev->rings[i];
4730 if (!ring || !ring->sched.thread)
4733 /* Clear job fence from fence drv to avoid force_completion
4734 * leave NULL and vm flush fence in fence drv
4736 amdgpu_fence_driver_clear_job_fences(ring);
4738 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4739 amdgpu_fence_driver_force_completion(ring);
4742 amdgpu_fence_driver_isr_toggle(adev, false);
4745 drm_sched_increase_karma(&job->base);
4747 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
4748 /* If reset handler not implemented, continue; otherwise return */
4749 if (r == -EOPNOTSUPP)
4754 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4755 if (!amdgpu_sriov_vf(adev)) {
4757 if (!need_full_reset)
4758 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4760 if (!need_full_reset && amdgpu_gpu_recovery &&
4761 amdgpu_device_ip_check_soft_reset(adev)) {
4762 amdgpu_device_ip_pre_soft_reset(adev);
4763 r = amdgpu_device_ip_soft_reset(adev);
4764 amdgpu_device_ip_post_soft_reset(adev);
4765 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4766 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4767 need_full_reset = true;
4771 if (need_full_reset)
4772 r = amdgpu_device_ip_suspend(adev);
4773 if (need_full_reset)
4774 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4776 clear_bit(AMDGPU_NEED_FULL_RESET,
4777 &reset_context->flags);
4783 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
4787 lockdep_assert_held(&adev->reset_domain->sem);
4789 for (i = 0; i < adev->num_regs; i++) {
4790 adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]);
4791 trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i],
4792 adev->reset_dump_reg_value[i]);
4798 #ifdef CONFIG_DEV_COREDUMP
4799 static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset,
4800 size_t count, void *data, size_t datalen)
4802 struct drm_printer p;
4803 struct amdgpu_device *adev = data;
4804 struct drm_print_iterator iter;
4809 iter.start = offset;
4810 iter.remain = count;
4812 p = drm_coredump_printer(&iter);
4814 drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
4815 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
4816 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
4817 drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec);
4818 if (adev->reset_task_info.pid)
4819 drm_printf(&p, "process_name: %s PID: %d\n",
4820 adev->reset_task_info.process_name,
4821 adev->reset_task_info.pid);
4823 if (adev->reset_vram_lost)
4824 drm_printf(&p, "VRAM is lost due to GPU reset!\n");
4825 if (adev->num_regs) {
4826 drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n");
4828 for (i = 0; i < adev->num_regs; i++)
4829 drm_printf(&p, "0x%08x: 0x%08x\n",
4830 adev->reset_dump_reg_list[i],
4831 adev->reset_dump_reg_value[i]);
4834 return count - iter.remain;
4837 static void amdgpu_devcoredump_free(void *data)
4841 static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev)
4843 struct drm_device *dev = adev_to_drm(adev);
4845 ktime_get_ts64(&adev->reset_time);
4846 dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_NOWAIT,
4847 amdgpu_devcoredump_read, amdgpu_devcoredump_free);
4851 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
4852 struct amdgpu_reset_context *reset_context)
4854 struct amdgpu_device *tmp_adev = NULL;
4855 bool need_full_reset, skip_hw_reset, vram_lost = false;
4857 bool gpu_reset_for_dev_remove = 0;
4859 /* Try reset handler method first */
4860 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
4862 amdgpu_reset_reg_dumps(tmp_adev);
4864 reset_context->reset_device_list = device_list_handle;
4865 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
4866 /* If reset handler not implemented, continue; otherwise return */
4867 if (r == -EOPNOTSUPP)
4872 /* Reset handler not implemented, use the default method */
4874 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4875 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
4877 gpu_reset_for_dev_remove =
4878 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
4879 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4882 * ASIC reset has to be done on all XGMI hive nodes ASAP
4883 * to allow proper links negotiation in FW (within 1 sec)
4885 if (!skip_hw_reset && need_full_reset) {
4886 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4887 /* For XGMI run all resets in parallel to speed up the process */
4888 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4889 tmp_adev->gmc.xgmi.pending_reset = false;
4890 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4893 r = amdgpu_asic_reset(tmp_adev);
4896 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4897 r, adev_to_drm(tmp_adev)->unique);
4902 /* For XGMI wait for all resets to complete before proceed */
4904 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4905 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4906 flush_work(&tmp_adev->xgmi_reset_work);
4907 r = tmp_adev->asic_reset_res;
4915 if (!r && amdgpu_ras_intr_triggered()) {
4916 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4917 if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops &&
4918 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
4919 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev);
4922 amdgpu_ras_intr_cleared();
4925 /* Since the mode1 reset affects base ip blocks, the
4926 * phase1 ip blocks need to be resumed. Otherwise there
4927 * will be a BIOS signature error and the psp bootloader
4928 * can't load kdb on the next amdgpu install.
4930 if (gpu_reset_for_dev_remove) {
4931 list_for_each_entry(tmp_adev, device_list_handle, reset_list)
4932 amdgpu_device_ip_resume_phase1(tmp_adev);
4937 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4938 if (need_full_reset) {
4940 r = amdgpu_device_asic_init(tmp_adev);
4942 dev_warn(tmp_adev->dev, "asic atom init failed!");
4944 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4946 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4950 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4951 #ifdef CONFIG_DEV_COREDUMP
4952 tmp_adev->reset_vram_lost = vram_lost;
4953 memset(&tmp_adev->reset_task_info, 0,
4954 sizeof(tmp_adev->reset_task_info));
4955 if (reset_context->job && reset_context->job->vm)
4956 tmp_adev->reset_task_info =
4957 reset_context->job->vm->task_info;
4958 amdgpu_reset_capture_coredumpm(tmp_adev);
4961 DRM_INFO("VRAM is lost due to GPU reset!\n");
4962 amdgpu_inc_vram_lost(tmp_adev);
4965 r = amdgpu_device_fw_loading(tmp_adev);
4969 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4974 amdgpu_device_fill_reset_magic(tmp_adev);
4977 * Add this ASIC as tracked as reset was already
4978 * complete successfully.
4980 amdgpu_register_gpu_instance(tmp_adev);
4982 if (!reset_context->hive &&
4983 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4984 amdgpu_xgmi_add_device(tmp_adev);
4986 r = amdgpu_device_ip_late_init(tmp_adev);
4990 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
4993 * The GPU enters bad state once faulty pages
4994 * by ECC has reached the threshold, and ras
4995 * recovery is scheduled next. So add one check
4996 * here to break recovery if it indeed exceeds
4997 * bad page threshold, and remind user to
4998 * retire this GPU or setting one bigger
4999 * bad_page_threshold value to fix this once
5000 * probing driver again.
5002 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
5004 amdgpu_ras_resume(tmp_adev);
5010 /* Update PSP FW topology after reset */
5011 if (reset_context->hive &&
5012 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5013 r = amdgpu_xgmi_update_topology(
5014 reset_context->hive, tmp_adev);
5020 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5021 r = amdgpu_ib_ring_tests(tmp_adev);
5023 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5024 need_full_reset = true;
5031 r = amdgpu_device_recover_vram(tmp_adev);
5033 tmp_adev->asic_reset_res = r;
5037 if (need_full_reset)
5038 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5040 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5044 static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5047 switch (amdgpu_asic_reset_method(adev)) {
5048 case AMD_RESET_METHOD_MODE1:
5049 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5051 case AMD_RESET_METHOD_MODE2:
5052 adev->mp1_state = PP_MP1_STATE_RESET;
5055 adev->mp1_state = PP_MP1_STATE_NONE;
5060 static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5062 amdgpu_vf_error_trans_all(adev);
5063 adev->mp1_state = PP_MP1_STATE_NONE;
5066 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5068 struct pci_dev *p = NULL;
5070 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5071 adev->pdev->bus->number, 1);
5073 pm_runtime_enable(&(p->dev));
5074 pm_runtime_resume(&(p->dev));
5080 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5082 enum amd_reset_method reset_method;
5083 struct pci_dev *p = NULL;
5087 * For now, only BACO and mode1 reset are confirmed
5088 * to suffer the audio issue without proper suspended.
5090 reset_method = amdgpu_asic_reset_method(adev);
5091 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5092 (reset_method != AMD_RESET_METHOD_MODE1))
5095 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5096 adev->pdev->bus->number, 1);
5100 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5103 * If we cannot get the audio device autosuspend delay,
5104 * a fixed 4S interval will be used. Considering 3S is
5105 * the audio controller default autosuspend delay setting.
5106 * 4S used here is guaranteed to cover that.
5108 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5110 while (!pm_runtime_status_suspended(&(p->dev))) {
5111 if (!pm_runtime_suspend(&(p->dev)))
5114 if (expires < ktime_get_mono_fast_ns()) {
5115 dev_warn(adev->dev, "failed to suspend display audio\n");
5117 /* TODO: abort the succeeding gpu reset? */
5122 pm_runtime_disable(&(p->dev));
5128 static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5130 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5132 #if defined(CONFIG_DEBUG_FS)
5133 if (!amdgpu_sriov_vf(adev))
5134 cancel_work(&adev->reset_work);
5138 cancel_work(&adev->kfd.reset_work);
5140 if (amdgpu_sriov_vf(adev))
5141 cancel_work(&adev->virt.flr_work);
5143 if (con && adev->ras_enabled)
5144 cancel_work(&con->recovery_work);
5149 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5151 * @adev: amdgpu_device pointer
5152 * @job: which job trigger hang
5153 * @reset_context: amdgpu reset context pointer
5155 * Attempt to reset the GPU if it has hung (all asics).
5156 * Attempt to do soft-reset or full-reset and reinitialize Asic
5157 * Returns 0 for success or an error on failure.
5160 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5161 struct amdgpu_job *job,
5162 struct amdgpu_reset_context *reset_context)
5164 struct list_head device_list, *device_list_handle = NULL;
5165 bool job_signaled = false;
5166 struct amdgpu_hive_info *hive = NULL;
5167 struct amdgpu_device *tmp_adev = NULL;
5169 bool need_emergency_restart = false;
5170 bool audio_suspended = false;
5171 bool gpu_reset_for_dev_remove = false;
5173 gpu_reset_for_dev_remove =
5174 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5175 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5178 * Special case: RAS triggered and full reset isn't supported
5180 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5183 * Flush RAM to disk so that after reboot
5184 * the user can read log and see why the system rebooted.
5186 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
5187 DRM_WARN("Emergency reboot.");
5190 emergency_restart();
5193 dev_info(adev->dev, "GPU %s begin!\n",
5194 need_emergency_restart ? "jobs stop":"reset");
5196 if (!amdgpu_sriov_vf(adev))
5197 hive = amdgpu_get_xgmi_hive(adev);
5199 mutex_lock(&hive->hive_lock);
5201 reset_context->job = job;
5202 reset_context->hive = hive;
5204 * Build list of devices to reset.
5205 * In case we are in XGMI hive mode, resort the device list
5206 * to put adev in the 1st position.
5208 INIT_LIST_HEAD(&device_list);
5209 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5210 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5211 list_add_tail(&tmp_adev->reset_list, &device_list);
5212 if (gpu_reset_for_dev_remove && adev->shutdown)
5213 tmp_adev->shutdown = true;
5215 if (!list_is_first(&adev->reset_list, &device_list))
5216 list_rotate_to_front(&adev->reset_list, &device_list);
5217 device_list_handle = &device_list;
5219 list_add_tail(&adev->reset_list, &device_list);
5220 device_list_handle = &device_list;
5223 /* We need to lock reset domain only once both for XGMI and single device */
5224 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5226 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5228 /* block all schedulers and reset given job's ring */
5229 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5231 amdgpu_device_set_mp1_state(tmp_adev);
5234 * Try to put the audio codec into suspend state
5235 * before gpu reset started.
5237 * Due to the power domain of the graphics device
5238 * is shared with AZ power domain. Without this,
5239 * we may change the audio hardware from behind
5240 * the audio driver's back. That will trigger
5241 * some audio codec errors.
5243 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5244 audio_suspended = true;
5246 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5248 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5250 if (!amdgpu_sriov_vf(tmp_adev))
5251 amdgpu_amdkfd_pre_reset(tmp_adev);
5254 * Mark these ASICs to be reseted as untracked first
5255 * And add them back after reset completed
5257 amdgpu_unregister_gpu_instance(tmp_adev);
5259 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5261 /* disable ras on ALL IPs */
5262 if (!need_emergency_restart &&
5263 amdgpu_device_ip_need_full_reset(tmp_adev))
5264 amdgpu_ras_suspend(tmp_adev);
5266 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5267 struct amdgpu_ring *ring = tmp_adev->rings[i];
5269 if (!ring || !ring->sched.thread)
5272 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5274 if (need_emergency_restart)
5275 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5277 atomic_inc(&tmp_adev->gpu_reset_counter);
5280 if (need_emergency_restart)
5281 goto skip_sched_resume;
5284 * Must check guilty signal here since after this point all old
5285 * HW fences are force signaled.
5287 * job->base holds a reference to parent fence
5289 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5290 job_signaled = true;
5291 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5295 retry: /* Rest of adevs pre asic reset from XGMI hive. */
5296 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5297 if (gpu_reset_for_dev_remove) {
5298 /* Workaroud for ASICs need to disable SMC first */
5299 amdgpu_device_smu_fini_early(tmp_adev);
5301 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5302 /*TODO Should we stop ?*/
5304 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5305 r, adev_to_drm(tmp_adev)->unique);
5306 tmp_adev->asic_reset_res = r;
5310 * Drop all pending non scheduler resets. Scheduler resets
5311 * were already dropped during drm_sched_stop
5313 amdgpu_device_stop_pending_resets(tmp_adev);
5316 /* Actual ASIC resets if needed.*/
5317 /* Host driver will handle XGMI hive reset for SRIOV */
5318 if (amdgpu_sriov_vf(adev)) {
5319 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5321 adev->asic_reset_res = r;
5323 /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */
5324 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
5325 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3))
5326 amdgpu_ras_resume(adev);
5328 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5329 if (r && r == -EAGAIN)
5332 if (!r && gpu_reset_for_dev_remove)
5338 /* Post ASIC reset for all devs .*/
5339 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5341 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5342 struct amdgpu_ring *ring = tmp_adev->rings[i];
5344 if (!ring || !ring->sched.thread)
5347 drm_sched_start(&ring->sched, true);
5350 if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))
5351 amdgpu_mes_self_test(tmp_adev);
5353 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
5354 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5356 if (tmp_adev->asic_reset_res)
5357 r = tmp_adev->asic_reset_res;
5359 tmp_adev->asic_reset_res = 0;
5362 /* bad news, how to tell it to userspace ? */
5363 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5364 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5366 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5367 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5368 DRM_WARN("smart shift update failed\n");
5373 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5374 /* unlock kfd: SRIOV would do it separately */
5375 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5376 amdgpu_amdkfd_post_reset(tmp_adev);
5378 /* kfd_post_reset will do nothing if kfd device is not initialized,
5379 * need to bring up kfd here if it's not be initialized before
5381 if (!adev->kfd.init_complete)
5382 amdgpu_amdkfd_device_init(adev);
5384 if (audio_suspended)
5385 amdgpu_device_resume_display_audio(tmp_adev);
5387 amdgpu_device_unset_mp1_state(tmp_adev);
5389 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5393 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5395 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5398 mutex_unlock(&hive->hive_lock);
5399 amdgpu_put_xgmi_hive(hive);
5403 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5405 atomic_set(&adev->reset_domain->reset_res, r);
5410 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5412 * @adev: amdgpu_device pointer
5414 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5415 * and lanes) of the slot the device is in. Handles APUs and
5416 * virtualized environments where PCIE config space may not be available.
5418 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5420 struct pci_dev *pdev;
5421 enum pci_bus_speed speed_cap, platform_speed_cap;
5422 enum pcie_link_width platform_link_width;
5424 if (amdgpu_pcie_gen_cap)
5425 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5427 if (amdgpu_pcie_lane_cap)
5428 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5430 /* covers APUs as well */
5431 if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) {
5432 if (adev->pm.pcie_gen_mask == 0)
5433 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5434 if (adev->pm.pcie_mlw_mask == 0)
5435 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5439 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5442 pcie_bandwidth_available(adev->pdev, NULL,
5443 &platform_speed_cap, &platform_link_width);
5445 if (adev->pm.pcie_gen_mask == 0) {
5448 speed_cap = pcie_get_speed_cap(pdev);
5449 if (speed_cap == PCI_SPEED_UNKNOWN) {
5450 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5451 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5452 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5454 if (speed_cap == PCIE_SPEED_32_0GT)
5455 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5456 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5457 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5458 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5459 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5460 else if (speed_cap == PCIE_SPEED_16_0GT)
5461 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5462 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5463 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5464 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5465 else if (speed_cap == PCIE_SPEED_8_0GT)
5466 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5467 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5468 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5469 else if (speed_cap == PCIE_SPEED_5_0GT)
5470 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5471 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5473 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5476 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5477 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5478 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5480 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5481 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5482 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5483 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5484 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5485 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5486 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5487 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5488 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5489 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5490 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5491 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5492 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5493 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5494 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5495 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5496 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5497 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5499 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5503 if (adev->pm.pcie_mlw_mask == 0) {
5504 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5505 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5507 switch (platform_link_width) {
5509 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5510 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5511 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5512 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5513 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5514 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5515 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5518 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5519 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5520 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5521 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5522 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5523 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5526 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5527 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5528 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5529 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5530 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5533 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5534 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5535 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5536 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5539 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5540 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5541 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5544 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5545 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5548 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5558 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5560 * @adev: amdgpu_device pointer
5561 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5563 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5564 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5567 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5568 struct amdgpu_device *peer_adev)
5570 #ifdef CONFIG_HSA_AMD_P2P
5571 uint64_t address_mask = peer_adev->dev->dma_mask ?
5572 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5573 resource_size_t aper_limit =
5574 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5576 !adev->gmc.xgmi.connected_to_cpu &&
5577 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
5579 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
5580 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
5581 !(adev->gmc.aper_base & address_mask ||
5582 aper_limit & address_mask));
5588 int amdgpu_device_baco_enter(struct drm_device *dev)
5590 struct amdgpu_device *adev = drm_to_adev(dev);
5591 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5593 if (!amdgpu_device_supports_baco(dev))
5596 if (ras && adev->ras_enabled &&
5597 adev->nbio.funcs->enable_doorbell_interrupt)
5598 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5600 return amdgpu_dpm_baco_enter(adev);
5603 int amdgpu_device_baco_exit(struct drm_device *dev)
5605 struct amdgpu_device *adev = drm_to_adev(dev);
5606 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5609 if (!amdgpu_device_supports_baco(dev))
5612 ret = amdgpu_dpm_baco_exit(adev);
5616 if (ras && adev->ras_enabled &&
5617 adev->nbio.funcs->enable_doorbell_interrupt)
5618 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
5620 if (amdgpu_passthrough(adev) &&
5621 adev->nbio.funcs->clear_doorbell_interrupt)
5622 adev->nbio.funcs->clear_doorbell_interrupt(adev);
5628 * amdgpu_pci_error_detected - Called when a PCI error is detected.
5629 * @pdev: PCI device struct
5630 * @state: PCI channel state
5632 * Description: Called when a PCI error is detected.
5634 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
5636 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5638 struct drm_device *dev = pci_get_drvdata(pdev);
5639 struct amdgpu_device *adev = drm_to_adev(dev);
5642 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
5644 if (adev->gmc.xgmi.num_physical_nodes > 1) {
5645 DRM_WARN("No support for XGMI hive yet...");
5646 return PCI_ERS_RESULT_DISCONNECT;
5649 adev->pci_channel_state = state;
5652 case pci_channel_io_normal:
5653 return PCI_ERS_RESULT_CAN_RECOVER;
5654 /* Fatal error, prepare for slot reset */
5655 case pci_channel_io_frozen:
5657 * Locking adev->reset_domain->sem will prevent any external access
5658 * to GPU during PCI error recovery
5660 amdgpu_device_lock_reset_domain(adev->reset_domain);
5661 amdgpu_device_set_mp1_state(adev);
5664 * Block any work scheduling as we do for regular GPU reset
5665 * for the duration of the recovery
5667 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5668 struct amdgpu_ring *ring = adev->rings[i];
5670 if (!ring || !ring->sched.thread)
5673 drm_sched_stop(&ring->sched, NULL);
5675 atomic_inc(&adev->gpu_reset_counter);
5676 return PCI_ERS_RESULT_NEED_RESET;
5677 case pci_channel_io_perm_failure:
5678 /* Permanent error, prepare for device removal */
5679 return PCI_ERS_RESULT_DISCONNECT;
5682 return PCI_ERS_RESULT_NEED_RESET;
5686 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
5687 * @pdev: pointer to PCI device
5689 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
5692 DRM_INFO("PCI error: mmio enabled callback!!\n");
5694 /* TODO - dump whatever for debugging purposes */
5696 /* This called only if amdgpu_pci_error_detected returns
5697 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
5698 * works, no need to reset slot.
5701 return PCI_ERS_RESULT_RECOVERED;
5705 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5706 * @pdev: PCI device struct
5708 * Description: This routine is called by the pci error recovery
5709 * code after the PCI slot has been reset, just before we
5710 * should resume normal operations.
5712 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5714 struct drm_device *dev = pci_get_drvdata(pdev);
5715 struct amdgpu_device *adev = drm_to_adev(dev);
5717 struct amdgpu_reset_context reset_context;
5719 struct list_head device_list;
5721 DRM_INFO("PCI error: slot reset callback!!\n");
5723 memset(&reset_context, 0, sizeof(reset_context));
5725 INIT_LIST_HEAD(&device_list);
5726 list_add_tail(&adev->reset_list, &device_list);
5728 /* wait for asic to come out of reset */
5731 /* Restore PCI confspace */
5732 amdgpu_device_load_pci_state(pdev);
5734 /* confirm ASIC came out of reset */
5735 for (i = 0; i < adev->usec_timeout; i++) {
5736 memsize = amdgpu_asic_get_config_memsize(adev);
5738 if (memsize != 0xffffffff)
5742 if (memsize == 0xffffffff) {
5747 reset_context.method = AMD_RESET_METHOD_NONE;
5748 reset_context.reset_req_dev = adev;
5749 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
5750 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
5752 adev->no_hw_access = true;
5753 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
5754 adev->no_hw_access = false;
5758 r = amdgpu_do_asic_reset(&device_list, &reset_context);
5762 if (amdgpu_device_cache_pci_state(adev->pdev))
5763 pci_restore_state(adev->pdev);
5765 DRM_INFO("PCIe error recovery succeeded\n");
5767 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5768 amdgpu_device_unset_mp1_state(adev);
5769 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5772 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5776 * amdgpu_pci_resume() - resume normal ops after PCI reset
5777 * @pdev: pointer to PCI device
5779 * Called when the error recovery driver tells us that its
5780 * OK to resume normal operation.
5782 void amdgpu_pci_resume(struct pci_dev *pdev)
5784 struct drm_device *dev = pci_get_drvdata(pdev);
5785 struct amdgpu_device *adev = drm_to_adev(dev);
5789 DRM_INFO("PCI error: resume callback!!\n");
5791 /* Only continue execution for the case of pci_channel_io_frozen */
5792 if (adev->pci_channel_state != pci_channel_io_frozen)
5795 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5796 struct amdgpu_ring *ring = adev->rings[i];
5798 if (!ring || !ring->sched.thread)
5801 drm_sched_start(&ring->sched, true);
5804 amdgpu_device_unset_mp1_state(adev);
5805 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5808 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5810 struct drm_device *dev = pci_get_drvdata(pdev);
5811 struct amdgpu_device *adev = drm_to_adev(dev);
5814 r = pci_save_state(pdev);
5816 kfree(adev->pci_state);
5818 adev->pci_state = pci_store_saved_state(pdev);
5820 if (!adev->pci_state) {
5821 DRM_ERROR("Failed to store PCI saved state");
5825 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5832 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5834 struct drm_device *dev = pci_get_drvdata(pdev);
5835 struct amdgpu_device *adev = drm_to_adev(dev);
5838 if (!adev->pci_state)
5841 r = pci_load_saved_state(pdev, adev->pci_state);
5844 pci_restore_state(pdev);
5846 DRM_WARN("Failed to load PCI state, err:%d\n", r);
5853 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
5854 struct amdgpu_ring *ring)
5856 #ifdef CONFIG_X86_64
5857 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5860 if (adev->gmc.xgmi.connected_to_cpu)
5863 if (ring && ring->funcs->emit_hdp_flush)
5864 amdgpu_ring_emit_hdp_flush(ring);
5866 amdgpu_asic_flush_hdp(adev, ring);
5869 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
5870 struct amdgpu_ring *ring)
5872 #ifdef CONFIG_X86_64
5873 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5876 if (adev->gmc.xgmi.connected_to_cpu)
5879 amdgpu_asic_invalidate_hdp(adev, ring);
5882 int amdgpu_in_reset(struct amdgpu_device *adev)
5884 return atomic_read(&adev->reset_domain->in_gpu_reset);
5888 * amdgpu_device_halt() - bring hardware to some kind of halt state
5890 * @adev: amdgpu_device pointer
5892 * Bring hardware to some kind of halt state so that no one can touch it
5893 * any more. It will help to maintain error context when error occurred.
5894 * Compare to a simple hang, the system will keep stable at least for SSH
5895 * access. Then it should be trivial to inspect the hardware state and
5896 * see what's going on. Implemented as following:
5898 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
5899 * clears all CPU mappings to device, disallows remappings through page faults
5900 * 2. amdgpu_irq_disable_all() disables all interrupts
5901 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
5902 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
5903 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
5904 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
5905 * flush any in flight DMA operations
5907 void amdgpu_device_halt(struct amdgpu_device *adev)
5909 struct pci_dev *pdev = adev->pdev;
5910 struct drm_device *ddev = adev_to_drm(adev);
5912 amdgpu_xcp_dev_unplug(adev);
5913 drm_dev_unplug(ddev);
5915 amdgpu_irq_disable_all(adev);
5917 amdgpu_fence_driver_hw_fini(adev);
5919 adev->no_hw_access = true;
5921 amdgpu_device_unmap_mmio(adev);
5923 pci_disable_device(pdev);
5924 pci_wait_for_pending_transaction(pdev);
5927 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
5930 unsigned long flags, address, data;
5933 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5934 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5936 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5937 WREG32(address, reg * 4);
5938 (void)RREG32(address);
5940 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5944 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
5947 unsigned long flags, address, data;
5949 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5950 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5952 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5953 WREG32(address, reg * 4);
5954 (void)RREG32(address);
5957 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5961 * amdgpu_device_switch_gang - switch to a new gang
5962 * @adev: amdgpu_device pointer
5963 * @gang: the gang to switch to
5965 * Try to switch to a new gang.
5966 * Returns: NULL if we switched to the new gang or a reference to the current
5969 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
5970 struct dma_fence *gang)
5972 struct dma_fence *old = NULL;
5977 old = dma_fence_get_rcu_safe(&adev->gang_submit);
5983 if (!dma_fence_is_signaled(old))
5986 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
5993 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
5995 switch (adev->asic_type) {
5996 #ifdef CONFIG_DRM_AMDGPU_SI
6000 /* chips with no display hardware */
6002 #ifdef CONFIG_DRM_AMDGPU_SI
6008 #ifdef CONFIG_DRM_AMDGPU_CIK
6017 case CHIP_POLARIS10:
6018 case CHIP_POLARIS11:
6019 case CHIP_POLARIS12:
6023 /* chips with display hardware */
6027 if (!adev->ip_versions[DCE_HWIP][0] ||
6028 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6034 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
6035 uint32_t inst, uint32_t reg_addr, char reg_name[],
6036 uint32_t expected_value, uint32_t mask)
6040 uint32_t tmp_ = RREG32(reg_addr);
6041 uint32_t loop = adev->usec_timeout;
6043 while ((tmp_ & (mask)) != (expected_value)) {
6045 loop = adev->usec_timeout;
6049 tmp_ = RREG32(reg_addr);
6052 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",
6053 inst, reg_name, (uint32_t)expected_value,
6054 (uint32_t)(tmp_ & (mask)));