2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/amdgpu_drm.h>
37 #include <linux/vgaarb.h>
38 #include <linux/vga_switcheroo.h>
39 #include <linux/efi.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_i2c.h"
44 #include "amdgpu_atombios.h"
45 #include "amdgpu_atomfirmware.h"
47 #ifdef CONFIG_DRM_AMDGPU_SI
50 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #include "bif/bif_4_1_d.h"
57 #include <linux/pci.h>
58 #include <linux/firmware.h>
59 #include "amdgpu_vf_error.h"
61 #include "amdgpu_amdkfd.h"
62 #include "amdgpu_pm.h"
64 #include "amdgpu_xgmi.h"
65 #include "amdgpu_ras.h"
66 #include "amdgpu_pmu.h"
67 #include "amdgpu_fru_eeprom.h"
69 #include <linux/suspend.h>
70 #include <drm/task_barrier.h>
71 #include <linux/pm_runtime.h>
73 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
74 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
75 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
76 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
77 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
78 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
79 MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
80 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
81 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
82 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
83 MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
84 MODULE_FIRMWARE("amdgpu/green_sardine_gpu_info.bin");
86 #define AMDGPU_RESUME_MS 2000
88 const char *amdgpu_asic_name[] = {
125 * DOC: pcie_replay_count
127 * The amdgpu driver provides a sysfs API for reporting the total number
128 * of PCIe replays (NAKs)
129 * The file pcie_replay_count is used for this and returns the total
130 * number of replays as a sum of the NAKs generated and NAKs received
133 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
134 struct device_attribute *attr, char *buf)
136 struct drm_device *ddev = dev_get_drvdata(dev);
137 struct amdgpu_device *adev = drm_to_adev(ddev);
138 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
140 return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
143 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
144 amdgpu_device_get_pcie_replay_count, NULL);
146 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
151 * The amdgpu driver provides a sysfs API for reporting the product name
153 * The file serial_number is used for this and returns the product name
154 * as returned from the FRU.
155 * NOTE: This is only available for certain server cards
158 static ssize_t amdgpu_device_get_product_name(struct device *dev,
159 struct device_attribute *attr, char *buf)
161 struct drm_device *ddev = dev_get_drvdata(dev);
162 struct amdgpu_device *adev = drm_to_adev(ddev);
164 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name);
167 static DEVICE_ATTR(product_name, S_IRUGO,
168 amdgpu_device_get_product_name, NULL);
171 * DOC: product_number
173 * The amdgpu driver provides a sysfs API for reporting the part number
175 * The file serial_number is used for this and returns the part number
176 * as returned from the FRU.
177 * NOTE: This is only available for certain server cards
180 static ssize_t amdgpu_device_get_product_number(struct device *dev,
181 struct device_attribute *attr, char *buf)
183 struct drm_device *ddev = dev_get_drvdata(dev);
184 struct amdgpu_device *adev = drm_to_adev(ddev);
186 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number);
189 static DEVICE_ATTR(product_number, S_IRUGO,
190 amdgpu_device_get_product_number, NULL);
195 * The amdgpu driver provides a sysfs API for reporting the serial number
197 * The file serial_number is used for this and returns the serial number
198 * as returned from the FRU.
199 * NOTE: This is only available for certain server cards
202 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
203 struct device_attribute *attr, char *buf)
205 struct drm_device *ddev = dev_get_drvdata(dev);
206 struct amdgpu_device *adev = drm_to_adev(ddev);
208 return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial);
211 static DEVICE_ATTR(serial_number, S_IRUGO,
212 amdgpu_device_get_serial_number, NULL);
215 * amdgpu_device_supports_boco - Is the device a dGPU with HG/PX power control
217 * @dev: drm_device pointer
219 * Returns true if the device is a dGPU with HG/PX power control,
220 * otherwise return false.
222 bool amdgpu_device_supports_boco(struct drm_device *dev)
224 struct amdgpu_device *adev = drm_to_adev(dev);
226 if (adev->flags & AMD_IS_PX)
232 * amdgpu_device_supports_baco - Does the device support BACO
234 * @dev: drm_device pointer
236 * Returns true if the device supporte BACO,
237 * otherwise return false.
239 bool amdgpu_device_supports_baco(struct drm_device *dev)
241 struct amdgpu_device *adev = drm_to_adev(dev);
243 return amdgpu_asic_supports_baco(adev);
247 * VRAM access helper functions
251 * amdgpu_device_vram_access - read/write a buffer in vram
253 * @adev: amdgpu_device pointer
254 * @pos: offset of the buffer in vram
255 * @buf: virtual address of the buffer in system memory
256 * @size: read/write size, sizeof(@buf) must > @size
257 * @write: true - write to vram, otherwise - read from vram
259 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
260 uint32_t *buf, size_t size, bool write)
268 last = min(pos + size, adev->gmc.visible_vram_size);
270 void __iomem *addr = adev->mman.aper_base_kaddr + pos;
271 size_t count = last - pos;
274 memcpy_toio(addr, buf, count);
276 amdgpu_asic_flush_hdp(adev, NULL);
278 amdgpu_asic_invalidate_hdp(adev, NULL);
280 memcpy_fromio(buf, addr, count);
292 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
293 for (last = pos + size; pos < last; pos += 4) {
294 uint32_t tmp = pos >> 31;
296 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
298 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
302 WREG32_NO_KIQ(mmMM_DATA, *buf++);
304 *buf++ = RREG32_NO_KIQ(mmMM_DATA);
306 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
310 * register access helper functions.
313 * amdgpu_device_rreg - read a memory mapped IO or indirect register
315 * @adev: amdgpu_device pointer
316 * @reg: dword aligned register offset
317 * @acc_flags: access flags which require special behavior
319 * Returns the 32 bit value from the offset specified.
321 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
322 uint32_t reg, uint32_t acc_flags)
326 if (adev->in_pci_err_recovery)
329 if ((reg * 4) < adev->rmmio_size) {
330 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
331 amdgpu_sriov_runtime(adev) &&
332 down_read_trylock(&adev->reset_sem)) {
333 ret = amdgpu_kiq_rreg(adev, reg);
334 up_read(&adev->reset_sem);
336 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
339 ret = adev->pcie_rreg(adev, reg * 4);
342 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
348 * MMIO register read with bytes helper functions
349 * @offset:bytes offset from MMIO start
354 * amdgpu_mm_rreg8 - read a memory mapped IO register
356 * @adev: amdgpu_device pointer
357 * @offset: byte aligned register offset
359 * Returns the 8 bit value from the offset specified.
361 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
363 if (adev->in_pci_err_recovery)
366 if (offset < adev->rmmio_size)
367 return (readb(adev->rmmio + offset));
372 * MMIO register write with bytes helper functions
373 * @offset:bytes offset from MMIO start
374 * @value: the value want to be written to the register
378 * amdgpu_mm_wreg8 - read a memory mapped IO register
380 * @adev: amdgpu_device pointer
381 * @offset: byte aligned register offset
382 * @value: 8 bit value to write
384 * Writes the value specified to the offset specified.
386 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
388 if (adev->in_pci_err_recovery)
391 if (offset < adev->rmmio_size)
392 writeb(value, adev->rmmio + offset);
398 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
400 * @adev: amdgpu_device pointer
401 * @reg: dword aligned register offset
402 * @v: 32 bit value to write to the register
403 * @acc_flags: access flags which require special behavior
405 * Writes the value specified to the offset specified.
407 void amdgpu_device_wreg(struct amdgpu_device *adev,
408 uint32_t reg, uint32_t v,
411 if (adev->in_pci_err_recovery)
414 if ((reg * 4) < adev->rmmio_size) {
415 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
416 amdgpu_sriov_runtime(adev) &&
417 down_read_trylock(&adev->reset_sem)) {
418 amdgpu_kiq_wreg(adev, reg, v);
419 up_read(&adev->reset_sem);
421 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
424 adev->pcie_wreg(adev, reg * 4, v);
427 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
431 * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range
433 * this function is invoked only the debugfs register access
435 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
436 uint32_t reg, uint32_t v)
438 if (adev->in_pci_err_recovery)
441 if (amdgpu_sriov_fullaccess(adev) &&
442 adev->gfx.rlc.funcs &&
443 adev->gfx.rlc.funcs->is_rlcg_access_range) {
444 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
445 return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);
447 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
452 * amdgpu_io_rreg - read an IO register
454 * @adev: amdgpu_device pointer
455 * @reg: dword aligned register offset
457 * Returns the 32 bit value from the offset specified.
459 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
461 if (adev->in_pci_err_recovery)
464 if ((reg * 4) < adev->rio_mem_size)
465 return ioread32(adev->rio_mem + (reg * 4));
467 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
468 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
473 * amdgpu_io_wreg - write to an IO register
475 * @adev: amdgpu_device pointer
476 * @reg: dword aligned register offset
477 * @v: 32 bit value to write to the register
479 * Writes the value specified to the offset specified.
481 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
483 if (adev->in_pci_err_recovery)
486 if ((reg * 4) < adev->rio_mem_size)
487 iowrite32(v, adev->rio_mem + (reg * 4));
489 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
490 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
495 * amdgpu_mm_rdoorbell - read a doorbell dword
497 * @adev: amdgpu_device pointer
498 * @index: doorbell index
500 * Returns the value in the doorbell aperture at the
501 * requested doorbell index (CIK).
503 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
505 if (adev->in_pci_err_recovery)
508 if (index < adev->doorbell.num_doorbells) {
509 return readl(adev->doorbell.ptr + index);
511 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
517 * amdgpu_mm_wdoorbell - write a doorbell dword
519 * @adev: amdgpu_device pointer
520 * @index: doorbell index
523 * Writes @v to the doorbell aperture at the
524 * requested doorbell index (CIK).
526 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
528 if (adev->in_pci_err_recovery)
531 if (index < adev->doorbell.num_doorbells) {
532 writel(v, adev->doorbell.ptr + index);
534 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
539 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
541 * @adev: amdgpu_device pointer
542 * @index: doorbell index
544 * Returns the value in the doorbell aperture at the
545 * requested doorbell index (VEGA10+).
547 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
549 if (adev->in_pci_err_recovery)
552 if (index < adev->doorbell.num_doorbells) {
553 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
555 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
561 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
563 * @adev: amdgpu_device pointer
564 * @index: doorbell index
567 * Writes @v to the doorbell aperture at the
568 * requested doorbell index (VEGA10+).
570 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
572 if (adev->in_pci_err_recovery)
575 if (index < adev->doorbell.num_doorbells) {
576 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
578 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
583 * amdgpu_device_indirect_rreg - read an indirect register
585 * @adev: amdgpu_device pointer
586 * @pcie_index: mmio register offset
587 * @pcie_data: mmio register offset
588 * @reg_addr: indirect register address to read from
590 * Returns the value of indirect register @reg_addr
592 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
593 u32 pcie_index, u32 pcie_data,
598 void __iomem *pcie_index_offset;
599 void __iomem *pcie_data_offset;
601 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
602 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
603 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
605 writel(reg_addr, pcie_index_offset);
606 readl(pcie_index_offset);
607 r = readl(pcie_data_offset);
608 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
614 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
616 * @adev: amdgpu_device pointer
617 * @pcie_index: mmio register offset
618 * @pcie_data: mmio register offset
619 * @reg_addr: indirect register address to read from
621 * Returns the value of indirect register @reg_addr
623 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
624 u32 pcie_index, u32 pcie_data,
629 void __iomem *pcie_index_offset;
630 void __iomem *pcie_data_offset;
632 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
633 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
634 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
636 /* read low 32 bits */
637 writel(reg_addr, pcie_index_offset);
638 readl(pcie_index_offset);
639 r = readl(pcie_data_offset);
640 /* read high 32 bits */
641 writel(reg_addr + 4, pcie_index_offset);
642 readl(pcie_index_offset);
643 r |= ((u64)readl(pcie_data_offset) << 32);
644 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
650 * amdgpu_device_indirect_wreg - write an indirect register address
652 * @adev: amdgpu_device pointer
653 * @pcie_index: mmio register offset
654 * @pcie_data: mmio register offset
655 * @reg_addr: indirect register offset
656 * @reg_data: indirect register data
659 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
660 u32 pcie_index, u32 pcie_data,
661 u32 reg_addr, u32 reg_data)
664 void __iomem *pcie_index_offset;
665 void __iomem *pcie_data_offset;
667 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
668 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
669 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
671 writel(reg_addr, pcie_index_offset);
672 readl(pcie_index_offset);
673 writel(reg_data, pcie_data_offset);
674 readl(pcie_data_offset);
675 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
679 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
681 * @adev: amdgpu_device pointer
682 * @pcie_index: mmio register offset
683 * @pcie_data: mmio register offset
684 * @reg_addr: indirect register offset
685 * @reg_data: indirect register data
688 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
689 u32 pcie_index, u32 pcie_data,
690 u32 reg_addr, u64 reg_data)
693 void __iomem *pcie_index_offset;
694 void __iomem *pcie_data_offset;
696 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
697 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
698 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
700 /* write low 32 bits */
701 writel(reg_addr, pcie_index_offset);
702 readl(pcie_index_offset);
703 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
704 readl(pcie_data_offset);
705 /* write high 32 bits */
706 writel(reg_addr + 4, pcie_index_offset);
707 readl(pcie_index_offset);
708 writel((u32)(reg_data >> 32), pcie_data_offset);
709 readl(pcie_data_offset);
710 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
714 * amdgpu_invalid_rreg - dummy reg read function
716 * @adev: amdgpu_device pointer
717 * @reg: offset of register
719 * Dummy register read function. Used for register blocks
720 * that certain asics don't have (all asics).
721 * Returns the value in the register.
723 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
725 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
731 * amdgpu_invalid_wreg - dummy reg write function
733 * @adev: amdgpu_device pointer
734 * @reg: offset of register
735 * @v: value to write to the register
737 * Dummy register read function. Used for register blocks
738 * that certain asics don't have (all asics).
740 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
742 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
748 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
750 * @adev: amdgpu_device pointer
751 * @reg: offset of register
753 * Dummy register read function. Used for register blocks
754 * that certain asics don't have (all asics).
755 * Returns the value in the register.
757 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
759 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
765 * amdgpu_invalid_wreg64 - dummy reg write function
767 * @adev: amdgpu_device pointer
768 * @reg: offset of register
769 * @v: value to write to the register
771 * Dummy register read function. Used for register blocks
772 * that certain asics don't have (all asics).
774 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
776 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
782 * amdgpu_block_invalid_rreg - dummy reg read function
784 * @adev: amdgpu_device pointer
785 * @block: offset of instance
786 * @reg: offset of register
788 * Dummy register read function. Used for register blocks
789 * that certain asics don't have (all asics).
790 * Returns the value in the register.
792 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
793 uint32_t block, uint32_t reg)
795 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
802 * amdgpu_block_invalid_wreg - dummy reg write function
804 * @adev: amdgpu_device pointer
805 * @block: offset of instance
806 * @reg: offset of register
807 * @v: value to write to the register
809 * Dummy register read function. Used for register blocks
810 * that certain asics don't have (all asics).
812 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
814 uint32_t reg, uint32_t v)
816 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
822 * amdgpu_device_asic_init - Wrapper for atom asic_init
824 * @adev: amdgpu_device pointer
826 * Does any asic specific work and then calls atom asic init.
828 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
830 amdgpu_asic_pre_asic_init(adev);
832 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
836 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
838 * @adev: amdgpu_device pointer
840 * Allocates a scratch page of VRAM for use by various things in the
843 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
845 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
846 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
847 &adev->vram_scratch.robj,
848 &adev->vram_scratch.gpu_addr,
849 (void **)&adev->vram_scratch.ptr);
853 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
855 * @adev: amdgpu_device pointer
857 * Frees the VRAM scratch page.
859 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
861 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
865 * amdgpu_device_program_register_sequence - program an array of registers.
867 * @adev: amdgpu_device pointer
868 * @registers: pointer to the register array
869 * @array_size: size of the register array
871 * Programs an array or registers with and and or masks.
872 * This is a helper for setting golden registers.
874 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
875 const u32 *registers,
876 const u32 array_size)
878 u32 tmp, reg, and_mask, or_mask;
884 for (i = 0; i < array_size; i +=3) {
885 reg = registers[i + 0];
886 and_mask = registers[i + 1];
887 or_mask = registers[i + 2];
889 if (and_mask == 0xffffffff) {
894 if (adev->family >= AMDGPU_FAMILY_AI)
895 tmp |= (or_mask & and_mask);
904 * amdgpu_device_pci_config_reset - reset the GPU
906 * @adev: amdgpu_device pointer
908 * Resets the GPU using the pci config reset sequence.
909 * Only applicable to asics prior to vega10.
911 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
913 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
917 * GPU doorbell aperture helpers function.
920 * amdgpu_device_doorbell_init - Init doorbell driver information.
922 * @adev: amdgpu_device pointer
924 * Init doorbell driver information (CIK)
925 * Returns 0 on success, error on failure.
927 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
930 /* No doorbell on SI hardware generation */
931 if (adev->asic_type < CHIP_BONAIRE) {
932 adev->doorbell.base = 0;
933 adev->doorbell.size = 0;
934 adev->doorbell.num_doorbells = 0;
935 adev->doorbell.ptr = NULL;
939 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
942 amdgpu_asic_init_doorbell_index(adev);
944 /* doorbell bar mapping */
945 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
946 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
948 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
949 adev->doorbell_index.max_assignment+1);
950 if (adev->doorbell.num_doorbells == 0)
953 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
954 * paging queue doorbell use the second page. The
955 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
956 * doorbells are in the first page. So with paging queue enabled,
957 * the max num_doorbells should + 1 page (0x400 in dword)
959 if (adev->asic_type >= CHIP_VEGA10)
960 adev->doorbell.num_doorbells += 0x400;
962 adev->doorbell.ptr = ioremap(adev->doorbell.base,
963 adev->doorbell.num_doorbells *
965 if (adev->doorbell.ptr == NULL)
972 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
974 * @adev: amdgpu_device pointer
976 * Tear down doorbell driver information (CIK)
978 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
980 iounmap(adev->doorbell.ptr);
981 adev->doorbell.ptr = NULL;
987 * amdgpu_device_wb_*()
988 * Writeback is the method by which the GPU updates special pages in memory
989 * with the status of certain GPU events (fences, ring pointers,etc.).
993 * amdgpu_device_wb_fini - Disable Writeback and free memory
995 * @adev: amdgpu_device pointer
997 * Disables Writeback and frees the Writeback memory (all asics).
998 * Used at driver shutdown.
1000 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1002 if (adev->wb.wb_obj) {
1003 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1005 (void **)&adev->wb.wb);
1006 adev->wb.wb_obj = NULL;
1011 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
1013 * @adev: amdgpu_device pointer
1015 * Initializes writeback and allocates writeback memory (all asics).
1016 * Used at driver startup.
1017 * Returns 0 on success or an -error on failure.
1019 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1023 if (adev->wb.wb_obj == NULL) {
1024 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1025 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1026 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1027 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1028 (void **)&adev->wb.wb);
1030 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1034 adev->wb.num_wb = AMDGPU_MAX_WB;
1035 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1037 /* clear wb memory */
1038 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1045 * amdgpu_device_wb_get - Allocate a wb entry
1047 * @adev: amdgpu_device pointer
1050 * Allocate a wb slot for use by the driver (all asics).
1051 * Returns 0 on success or -EINVAL on failure.
1053 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1055 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1057 if (offset < adev->wb.num_wb) {
1058 __set_bit(offset, adev->wb.used);
1059 *wb = offset << 3; /* convert to dw offset */
1067 * amdgpu_device_wb_free - Free a wb entry
1069 * @adev: amdgpu_device pointer
1072 * Free a wb slot allocated for use by the driver (all asics)
1074 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1077 if (wb < adev->wb.num_wb)
1078 __clear_bit(wb, adev->wb.used);
1082 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1084 * @adev: amdgpu_device pointer
1086 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1087 * to fail, but if any of the BARs is not accessible after the size we abort
1088 * driver loading by returning -ENODEV.
1090 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1092 u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
1093 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
1094 struct pci_bus *root;
1095 struct resource *res;
1101 if (amdgpu_sriov_vf(adev))
1104 /* skip if the bios has already enabled large BAR */
1105 if (adev->gmc.real_vram_size &&
1106 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1109 /* Check if the root BUS has 64bit memory resources */
1110 root = adev->pdev->bus;
1111 while (root->parent)
1112 root = root->parent;
1114 pci_bus_for_each_resource(root, res, i) {
1115 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1116 res->start > 0x100000000ull)
1120 /* Trying to resize is pointless without a root hub window above 4GB */
1124 /* Disable memory decoding while we change the BAR addresses and size */
1125 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1126 pci_write_config_word(adev->pdev, PCI_COMMAND,
1127 cmd & ~PCI_COMMAND_MEMORY);
1129 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1130 amdgpu_device_doorbell_fini(adev);
1131 if (adev->asic_type >= CHIP_BONAIRE)
1132 pci_release_resource(adev->pdev, 2);
1134 pci_release_resource(adev->pdev, 0);
1136 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1138 DRM_INFO("Not enough PCI address space for a large BAR.");
1139 else if (r && r != -ENOTSUPP)
1140 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1142 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1144 /* When the doorbell or fb BAR isn't available we have no chance of
1147 r = amdgpu_device_doorbell_init(adev);
1148 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1151 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1157 * GPU helpers function.
1160 * amdgpu_device_need_post - check if the hw need post or not
1162 * @adev: amdgpu_device pointer
1164 * Check if the asic has been initialized (all asics) at driver startup
1165 * or post is needed if hw reset is performed.
1166 * Returns true if need or false if not.
1168 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1172 if (amdgpu_sriov_vf(adev))
1175 if (amdgpu_passthrough(adev)) {
1176 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1177 * some old smc fw still need driver do vPost otherwise gpu hang, while
1178 * those smc fw version above 22.15 doesn't have this flaw, so we force
1179 * vpost executed for smc version below 22.15
1181 if (adev->asic_type == CHIP_FIJI) {
1184 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1185 /* force vPost if error occured */
1189 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1190 if (fw_ver < 0x00160e00)
1195 if (adev->has_hw_reset) {
1196 adev->has_hw_reset = false;
1200 /* bios scratch used on CIK+ */
1201 if (adev->asic_type >= CHIP_BONAIRE)
1202 return amdgpu_atombios_scratch_need_asic_init(adev);
1204 /* check MEM_SIZE for older asics */
1205 reg = amdgpu_asic_get_config_memsize(adev);
1207 if ((reg != 0) && (reg != 0xffffffff))
1213 /* if we get transitioned to only one device, take VGA back */
1215 * amdgpu_device_vga_set_decode - enable/disable vga decode
1217 * @cookie: amdgpu_device pointer
1218 * @state: enable/disable vga decode
1220 * Enable/disable vga decode (all asics).
1221 * Returns VGA resource flags.
1223 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
1225 struct amdgpu_device *adev = cookie;
1226 amdgpu_asic_set_vga_state(adev, state);
1228 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1229 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1231 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1235 * amdgpu_device_check_block_size - validate the vm block size
1237 * @adev: amdgpu_device pointer
1239 * Validates the vm block size specified via module parameter.
1240 * The vm block size defines number of bits in page table versus page directory,
1241 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1242 * page table and the remaining bits are in the page directory.
1244 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1246 /* defines number of bits in page table versus page directory,
1247 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1248 * page table and the remaining bits are in the page directory */
1249 if (amdgpu_vm_block_size == -1)
1252 if (amdgpu_vm_block_size < 9) {
1253 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1254 amdgpu_vm_block_size);
1255 amdgpu_vm_block_size = -1;
1260 * amdgpu_device_check_vm_size - validate the vm size
1262 * @adev: amdgpu_device pointer
1264 * Validates the vm size in GB specified via module parameter.
1265 * The VM size is the size of the GPU virtual memory space in GB.
1267 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1269 /* no need to check the default value */
1270 if (amdgpu_vm_size == -1)
1273 if (amdgpu_vm_size < 1) {
1274 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1276 amdgpu_vm_size = -1;
1280 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1283 bool is_os_64 = (sizeof(void *) == 8);
1284 uint64_t total_memory;
1285 uint64_t dram_size_seven_GB = 0x1B8000000;
1286 uint64_t dram_size_three_GB = 0xB8000000;
1288 if (amdgpu_smu_memory_pool_size == 0)
1292 DRM_WARN("Not 64-bit OS, feature not supported\n");
1296 total_memory = (uint64_t)si.totalram * si.mem_unit;
1298 if ((amdgpu_smu_memory_pool_size == 1) ||
1299 (amdgpu_smu_memory_pool_size == 2)) {
1300 if (total_memory < dram_size_three_GB)
1302 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1303 (amdgpu_smu_memory_pool_size == 8)) {
1304 if (total_memory < dram_size_seven_GB)
1307 DRM_WARN("Smu memory pool size not supported\n");
1310 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1315 DRM_WARN("No enough system memory\n");
1317 adev->pm.smu_prv_buffer_size = 0;
1321 * amdgpu_device_check_arguments - validate module params
1323 * @adev: amdgpu_device pointer
1325 * Validates certain module parameters and updates
1326 * the associated values used by the driver (all asics).
1328 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1330 if (amdgpu_sched_jobs < 4) {
1331 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1333 amdgpu_sched_jobs = 4;
1334 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1335 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1337 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1340 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1341 /* gart size must be greater or equal to 32M */
1342 dev_warn(adev->dev, "gart size (%d) too small\n",
1344 amdgpu_gart_size = -1;
1347 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1348 /* gtt size must be greater or equal to 32M */
1349 dev_warn(adev->dev, "gtt size (%d) too small\n",
1351 amdgpu_gtt_size = -1;
1354 /* valid range is between 4 and 9 inclusive */
1355 if (amdgpu_vm_fragment_size != -1 &&
1356 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1357 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1358 amdgpu_vm_fragment_size = -1;
1361 if (amdgpu_sched_hw_submission < 2) {
1362 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1363 amdgpu_sched_hw_submission);
1364 amdgpu_sched_hw_submission = 2;
1365 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1366 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1367 amdgpu_sched_hw_submission);
1368 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1371 amdgpu_device_check_smu_prv_buffer_size(adev);
1373 amdgpu_device_check_vm_size(adev);
1375 amdgpu_device_check_block_size(adev);
1377 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1379 amdgpu_gmc_tmz_set(adev);
1381 amdgpu_gmc_noretry_set(adev);
1387 * amdgpu_switcheroo_set_state - set switcheroo state
1389 * @pdev: pci dev pointer
1390 * @state: vga_switcheroo state
1392 * Callback for the switcheroo driver. Suspends or resumes the
1393 * the asics before or after it is powered up using ACPI methods.
1395 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1396 enum vga_switcheroo_state state)
1398 struct drm_device *dev = pci_get_drvdata(pdev);
1401 if (amdgpu_device_supports_boco(dev) && state == VGA_SWITCHEROO_OFF)
1404 if (state == VGA_SWITCHEROO_ON) {
1405 pr_info("switched on\n");
1406 /* don't suspend or resume card normally */
1407 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1409 pci_set_power_state(dev->pdev, PCI_D0);
1410 amdgpu_device_load_pci_state(dev->pdev);
1411 r = pci_enable_device(dev->pdev);
1413 DRM_WARN("pci_enable_device failed (%d)\n", r);
1414 amdgpu_device_resume(dev, true);
1416 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1417 drm_kms_helper_poll_enable(dev);
1419 pr_info("switched off\n");
1420 drm_kms_helper_poll_disable(dev);
1421 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1422 amdgpu_device_suspend(dev, true);
1423 amdgpu_device_cache_pci_state(dev->pdev);
1424 /* Shut down the device */
1425 pci_disable_device(dev->pdev);
1426 pci_set_power_state(dev->pdev, PCI_D3cold);
1427 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1432 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1434 * @pdev: pci dev pointer
1436 * Callback for the switcheroo driver. Check of the switcheroo
1437 * state can be changed.
1438 * Returns true if the state can be changed, false if not.
1440 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1442 struct drm_device *dev = pci_get_drvdata(pdev);
1445 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1446 * locking inversion with the driver load path. And the access here is
1447 * completely racy anyway. So don't bother with locking for now.
1449 return atomic_read(&dev->open_count) == 0;
1452 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1453 .set_gpu_state = amdgpu_switcheroo_set_state,
1455 .can_switch = amdgpu_switcheroo_can_switch,
1459 * amdgpu_device_ip_set_clockgating_state - set the CG state
1461 * @dev: amdgpu_device pointer
1462 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1463 * @state: clockgating state (gate or ungate)
1465 * Sets the requested clockgating state for all instances of
1466 * the hardware IP specified.
1467 * Returns the error code from the last instance.
1469 int amdgpu_device_ip_set_clockgating_state(void *dev,
1470 enum amd_ip_block_type block_type,
1471 enum amd_clockgating_state state)
1473 struct amdgpu_device *adev = dev;
1476 for (i = 0; i < adev->num_ip_blocks; i++) {
1477 if (!adev->ip_blocks[i].status.valid)
1479 if (adev->ip_blocks[i].version->type != block_type)
1481 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1483 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1484 (void *)adev, state);
1486 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1487 adev->ip_blocks[i].version->funcs->name, r);
1493 * amdgpu_device_ip_set_powergating_state - set the PG state
1495 * @dev: amdgpu_device pointer
1496 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1497 * @state: powergating state (gate or ungate)
1499 * Sets the requested powergating state for all instances of
1500 * the hardware IP specified.
1501 * Returns the error code from the last instance.
1503 int amdgpu_device_ip_set_powergating_state(void *dev,
1504 enum amd_ip_block_type block_type,
1505 enum amd_powergating_state state)
1507 struct amdgpu_device *adev = dev;
1510 for (i = 0; i < adev->num_ip_blocks; i++) {
1511 if (!adev->ip_blocks[i].status.valid)
1513 if (adev->ip_blocks[i].version->type != block_type)
1515 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1517 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1518 (void *)adev, state);
1520 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1521 adev->ip_blocks[i].version->funcs->name, r);
1527 * amdgpu_device_ip_get_clockgating_state - get the CG state
1529 * @adev: amdgpu_device pointer
1530 * @flags: clockgating feature flags
1532 * Walks the list of IPs on the device and updates the clockgating
1533 * flags for each IP.
1534 * Updates @flags with the feature flags for each hardware IP where
1535 * clockgating is enabled.
1537 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1542 for (i = 0; i < adev->num_ip_blocks; i++) {
1543 if (!adev->ip_blocks[i].status.valid)
1545 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1546 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1551 * amdgpu_device_ip_wait_for_idle - wait for idle
1553 * @adev: amdgpu_device pointer
1554 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1556 * Waits for the request hardware IP to be idle.
1557 * Returns 0 for success or a negative error code on failure.
1559 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1560 enum amd_ip_block_type block_type)
1564 for (i = 0; i < adev->num_ip_blocks; i++) {
1565 if (!adev->ip_blocks[i].status.valid)
1567 if (adev->ip_blocks[i].version->type == block_type) {
1568 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1579 * amdgpu_device_ip_is_idle - is the hardware IP idle
1581 * @adev: amdgpu_device pointer
1582 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1584 * Check if the hardware IP is idle or not.
1585 * Returns true if it the IP is idle, false if not.
1587 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1588 enum amd_ip_block_type block_type)
1592 for (i = 0; i < adev->num_ip_blocks; i++) {
1593 if (!adev->ip_blocks[i].status.valid)
1595 if (adev->ip_blocks[i].version->type == block_type)
1596 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1603 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1605 * @adev: amdgpu_device pointer
1606 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1608 * Returns a pointer to the hardware IP block structure
1609 * if it exists for the asic, otherwise NULL.
1611 struct amdgpu_ip_block *
1612 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1613 enum amd_ip_block_type type)
1617 for (i = 0; i < adev->num_ip_blocks; i++)
1618 if (adev->ip_blocks[i].version->type == type)
1619 return &adev->ip_blocks[i];
1625 * amdgpu_device_ip_block_version_cmp
1627 * @adev: amdgpu_device pointer
1628 * @type: enum amd_ip_block_type
1629 * @major: major version
1630 * @minor: minor version
1632 * return 0 if equal or greater
1633 * return 1 if smaller or the ip_block doesn't exist
1635 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1636 enum amd_ip_block_type type,
1637 u32 major, u32 minor)
1639 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1641 if (ip_block && ((ip_block->version->major > major) ||
1642 ((ip_block->version->major == major) &&
1643 (ip_block->version->minor >= minor))))
1650 * amdgpu_device_ip_block_add
1652 * @adev: amdgpu_device pointer
1653 * @ip_block_version: pointer to the IP to add
1655 * Adds the IP block driver information to the collection of IPs
1658 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1659 const struct amdgpu_ip_block_version *ip_block_version)
1661 if (!ip_block_version)
1664 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1665 ip_block_version->funcs->name);
1667 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1673 * amdgpu_device_enable_virtual_display - enable virtual display feature
1675 * @adev: amdgpu_device pointer
1677 * Enabled the virtual display feature if the user has enabled it via
1678 * the module parameter virtual_display. This feature provides a virtual
1679 * display hardware on headless boards or in virtualized environments.
1680 * This function parses and validates the configuration string specified by
1681 * the user and configues the virtual display configuration (number of
1682 * virtual connectors, crtcs, etc.) specified.
1684 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1686 adev->enable_virtual_display = false;
1688 if (amdgpu_virtual_display) {
1689 struct drm_device *ddev = adev_to_drm(adev);
1690 const char *pci_address_name = pci_name(ddev->pdev);
1691 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1693 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1694 pciaddstr_tmp = pciaddstr;
1695 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1696 pciaddname = strsep(&pciaddname_tmp, ",");
1697 if (!strcmp("all", pciaddname)
1698 || !strcmp(pci_address_name, pciaddname)) {
1702 adev->enable_virtual_display = true;
1705 res = kstrtol(pciaddname_tmp, 10,
1713 adev->mode_info.num_crtc = num_crtc;
1715 adev->mode_info.num_crtc = 1;
1721 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1722 amdgpu_virtual_display, pci_address_name,
1723 adev->enable_virtual_display, adev->mode_info.num_crtc);
1730 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1732 * @adev: amdgpu_device pointer
1734 * Parses the asic configuration parameters specified in the gpu info
1735 * firmware and makes them availale to the driver for use in configuring
1737 * Returns 0 on success, -EINVAL on failure.
1739 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1741 const char *chip_name;
1744 const struct gpu_info_firmware_header_v1_0 *hdr;
1746 adev->firmware.gpu_info_fw = NULL;
1748 if (adev->mman.discovery_bin) {
1749 amdgpu_discovery_get_gfx_info(adev);
1752 * FIXME: The bounding box is still needed by Navi12, so
1753 * temporarily read it from gpu_info firmware. Should be droped
1754 * when DAL no longer needs it.
1756 if (adev->asic_type != CHIP_NAVI12)
1760 switch (adev->asic_type) {
1761 #ifdef CONFIG_DRM_AMDGPU_SI
1768 #ifdef CONFIG_DRM_AMDGPU_CIK
1778 case CHIP_POLARIS10:
1779 case CHIP_POLARIS11:
1780 case CHIP_POLARIS12:
1785 case CHIP_SIENNA_CICHLID:
1786 case CHIP_NAVY_FLOUNDER:
1787 case CHIP_DIMGREY_CAVEFISH:
1791 chip_name = "vega10";
1794 chip_name = "vega12";
1797 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1798 chip_name = "raven2";
1799 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1800 chip_name = "picasso";
1802 chip_name = "raven";
1805 chip_name = "arcturus";
1808 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1809 chip_name = "renoir";
1811 chip_name = "green_sardine";
1814 chip_name = "navi10";
1817 chip_name = "navi14";
1820 chip_name = "navi12";
1823 chip_name = "vangogh";
1827 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1828 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1831 "Failed to load gpu_info firmware \"%s\"\n",
1835 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1838 "Failed to validate gpu_info firmware \"%s\"\n",
1843 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1844 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1846 switch (hdr->version_major) {
1849 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1850 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1851 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1854 * Should be droped when DAL no longer needs it.
1856 if (adev->asic_type == CHIP_NAVI12)
1857 goto parse_soc_bounding_box;
1859 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1860 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1861 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1862 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1863 adev->gfx.config.max_texture_channel_caches =
1864 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1865 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1866 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1867 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1868 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1869 adev->gfx.config.double_offchip_lds_buf =
1870 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1871 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1872 adev->gfx.cu_info.max_waves_per_simd =
1873 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1874 adev->gfx.cu_info.max_scratch_slots_per_cu =
1875 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1876 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1877 if (hdr->version_minor >= 1) {
1878 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1879 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1880 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1881 adev->gfx.config.num_sc_per_sh =
1882 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1883 adev->gfx.config.num_packer_per_sc =
1884 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1887 parse_soc_bounding_box:
1889 * soc bounding box info is not integrated in disocovery table,
1890 * we always need to parse it from gpu info firmware if needed.
1892 if (hdr->version_minor == 2) {
1893 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1894 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1895 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1896 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1902 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1911 * amdgpu_device_ip_early_init - run early init for hardware IPs
1913 * @adev: amdgpu_device pointer
1915 * Early initialization pass for hardware IPs. The hardware IPs that make
1916 * up each asic are discovered each IP's early_init callback is run. This
1917 * is the first stage in initializing the asic.
1918 * Returns 0 on success, negative error code on failure.
1920 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1924 amdgpu_device_enable_virtual_display(adev);
1926 if (amdgpu_sriov_vf(adev)) {
1927 r = amdgpu_virt_request_full_gpu(adev, true);
1932 switch (adev->asic_type) {
1933 #ifdef CONFIG_DRM_AMDGPU_SI
1939 adev->family = AMDGPU_FAMILY_SI;
1940 r = si_set_ip_blocks(adev);
1945 #ifdef CONFIG_DRM_AMDGPU_CIK
1951 if (adev->flags & AMD_IS_APU)
1952 adev->family = AMDGPU_FAMILY_KV;
1954 adev->family = AMDGPU_FAMILY_CI;
1956 r = cik_set_ip_blocks(adev);
1964 case CHIP_POLARIS10:
1965 case CHIP_POLARIS11:
1966 case CHIP_POLARIS12:
1970 if (adev->flags & AMD_IS_APU)
1971 adev->family = AMDGPU_FAMILY_CZ;
1973 adev->family = AMDGPU_FAMILY_VI;
1975 r = vi_set_ip_blocks(adev);
1985 if (adev->flags & AMD_IS_APU)
1986 adev->family = AMDGPU_FAMILY_RV;
1988 adev->family = AMDGPU_FAMILY_AI;
1990 r = soc15_set_ip_blocks(adev);
1997 case CHIP_SIENNA_CICHLID:
1998 case CHIP_NAVY_FLOUNDER:
1999 case CHIP_DIMGREY_CAVEFISH:
2001 if (adev->asic_type == CHIP_VANGOGH)
2002 adev->family = AMDGPU_FAMILY_VGH;
2004 adev->family = AMDGPU_FAMILY_NV;
2006 r = nv_set_ip_blocks(adev);
2011 /* FIXME: not supported yet */
2015 amdgpu_amdkfd_device_probe(adev);
2017 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2018 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2019 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2021 for (i = 0; i < adev->num_ip_blocks; i++) {
2022 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2023 DRM_ERROR("disabled ip block: %d <%s>\n",
2024 i, adev->ip_blocks[i].version->funcs->name);
2025 adev->ip_blocks[i].status.valid = false;
2027 if (adev->ip_blocks[i].version->funcs->early_init) {
2028 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2030 adev->ip_blocks[i].status.valid = false;
2032 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2033 adev->ip_blocks[i].version->funcs->name, r);
2036 adev->ip_blocks[i].status.valid = true;
2039 adev->ip_blocks[i].status.valid = true;
2042 /* get the vbios after the asic_funcs are set up */
2043 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2044 r = amdgpu_device_parse_gpu_info_fw(adev);
2049 if (!amdgpu_get_bios(adev))
2052 r = amdgpu_atombios_init(adev);
2054 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2055 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2061 adev->cg_flags &= amdgpu_cg_mask;
2062 adev->pg_flags &= amdgpu_pg_mask;
2067 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2071 for (i = 0; i < adev->num_ip_blocks; i++) {
2072 if (!adev->ip_blocks[i].status.sw)
2074 if (adev->ip_blocks[i].status.hw)
2076 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2077 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2078 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2079 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2081 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2082 adev->ip_blocks[i].version->funcs->name, r);
2085 adev->ip_blocks[i].status.hw = true;
2092 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2096 for (i = 0; i < adev->num_ip_blocks; i++) {
2097 if (!adev->ip_blocks[i].status.sw)
2099 if (adev->ip_blocks[i].status.hw)
2101 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2103 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2104 adev->ip_blocks[i].version->funcs->name, r);
2107 adev->ip_blocks[i].status.hw = true;
2113 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2117 uint32_t smu_version;
2119 if (adev->asic_type >= CHIP_VEGA10) {
2120 for (i = 0; i < adev->num_ip_blocks; i++) {
2121 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2124 /* no need to do the fw loading again if already done*/
2125 if (adev->ip_blocks[i].status.hw == true)
2128 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2129 r = adev->ip_blocks[i].version->funcs->resume(adev);
2131 DRM_ERROR("resume of IP block <%s> failed %d\n",
2132 adev->ip_blocks[i].version->funcs->name, r);
2136 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2138 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2139 adev->ip_blocks[i].version->funcs->name, r);
2144 adev->ip_blocks[i].status.hw = true;
2149 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2150 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2156 * amdgpu_device_ip_init - run init for hardware IPs
2158 * @adev: amdgpu_device pointer
2160 * Main initialization pass for hardware IPs. The list of all the hardware
2161 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2162 * are run. sw_init initializes the software state associated with each IP
2163 * and hw_init initializes the hardware associated with each IP.
2164 * Returns 0 on success, negative error code on failure.
2166 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2170 r = amdgpu_ras_init(adev);
2174 for (i = 0; i < adev->num_ip_blocks; i++) {
2175 if (!adev->ip_blocks[i].status.valid)
2177 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2179 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2180 adev->ip_blocks[i].version->funcs->name, r);
2183 adev->ip_blocks[i].status.sw = true;
2185 /* need to do gmc hw init early so we can allocate gpu mem */
2186 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2187 r = amdgpu_device_vram_scratch_init(adev);
2189 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
2192 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2194 DRM_ERROR("hw_init %d failed %d\n", i, r);
2197 r = amdgpu_device_wb_init(adev);
2199 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2202 adev->ip_blocks[i].status.hw = true;
2204 /* right after GMC hw init, we create CSA */
2205 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
2206 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2207 AMDGPU_GEM_DOMAIN_VRAM,
2210 DRM_ERROR("allocate CSA failed %d\n", r);
2217 if (amdgpu_sriov_vf(adev))
2218 amdgpu_virt_init_data_exchange(adev);
2220 r = amdgpu_ib_pool_init(adev);
2222 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2223 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2227 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2231 r = amdgpu_device_ip_hw_init_phase1(adev);
2235 r = amdgpu_device_fw_loading(adev);
2239 r = amdgpu_device_ip_hw_init_phase2(adev);
2244 * retired pages will be loaded from eeprom and reserved here,
2245 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2246 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2247 * for I2C communication which only true at this point.
2249 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2250 * failure from bad gpu situation and stop amdgpu init process
2251 * accordingly. For other failed cases, it will still release all
2252 * the resource and print error message, rather than returning one
2253 * negative value to upper level.
2255 * Note: theoretically, this should be called before all vram allocations
2256 * to protect retired page from abusing
2258 r = amdgpu_ras_recovery_init(adev);
2262 if (adev->gmc.xgmi.num_physical_nodes > 1)
2263 amdgpu_xgmi_add_device(adev);
2264 amdgpu_amdkfd_device_init(adev);
2266 amdgpu_fru_get_product_info(adev);
2269 if (amdgpu_sriov_vf(adev))
2270 amdgpu_virt_release_full_gpu(adev, true);
2276 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2278 * @adev: amdgpu_device pointer
2280 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2281 * this function before a GPU reset. If the value is retained after a
2282 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2284 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2286 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2290 * amdgpu_device_check_vram_lost - check if vram is valid
2292 * @adev: amdgpu_device pointer
2294 * Checks the reset magic value written to the gart pointer in VRAM.
2295 * The driver calls this after a GPU reset to see if the contents of
2296 * VRAM is lost or now.
2297 * returns true if vram is lost, false if not.
2299 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2301 if (memcmp(adev->gart.ptr, adev->reset_magic,
2302 AMDGPU_RESET_MAGIC_NUM))
2305 if (!amdgpu_in_reset(adev))
2309 * For all ASICs with baco/mode1 reset, the VRAM is
2310 * always assumed to be lost.
2312 switch (amdgpu_asic_reset_method(adev)) {
2313 case AMD_RESET_METHOD_BACO:
2314 case AMD_RESET_METHOD_MODE1:
2322 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2324 * @adev: amdgpu_device pointer
2325 * @state: clockgating state (gate or ungate)
2327 * The list of all the hardware IPs that make up the asic is walked and the
2328 * set_clockgating_state callbacks are run.
2329 * Late initialization pass enabling clockgating for hardware IPs.
2330 * Fini or suspend, pass disabling clockgating for hardware IPs.
2331 * Returns 0 on success, negative error code on failure.
2334 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2335 enum amd_clockgating_state state)
2339 if (amdgpu_emu_mode == 1)
2342 for (j = 0; j < adev->num_ip_blocks; j++) {
2343 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2344 if (!adev->ip_blocks[i].status.late_initialized)
2346 /* skip CG for VCE/UVD, it's handled specially */
2347 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2348 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2349 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2350 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2351 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2352 /* enable clockgating to save power */
2353 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2356 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2357 adev->ip_blocks[i].version->funcs->name, r);
2366 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
2370 if (amdgpu_emu_mode == 1)
2373 for (j = 0; j < adev->num_ip_blocks; j++) {
2374 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2375 if (!adev->ip_blocks[i].status.late_initialized)
2377 /* skip CG for VCE/UVD, it's handled specially */
2378 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2379 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2380 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2381 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2382 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2383 /* enable powergating to save power */
2384 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2387 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2388 adev->ip_blocks[i].version->funcs->name, r);
2396 static int amdgpu_device_enable_mgpu_fan_boost(void)
2398 struct amdgpu_gpu_instance *gpu_ins;
2399 struct amdgpu_device *adev;
2402 mutex_lock(&mgpu_info.mutex);
2405 * MGPU fan boost feature should be enabled
2406 * only when there are two or more dGPUs in
2409 if (mgpu_info.num_dgpu < 2)
2412 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2413 gpu_ins = &(mgpu_info.gpu_ins[i]);
2414 adev = gpu_ins->adev;
2415 if (!(adev->flags & AMD_IS_APU) &&
2416 !gpu_ins->mgpu_fan_enabled) {
2417 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2421 gpu_ins->mgpu_fan_enabled = 1;
2426 mutex_unlock(&mgpu_info.mutex);
2432 * amdgpu_device_ip_late_init - run late init for hardware IPs
2434 * @adev: amdgpu_device pointer
2436 * Late initialization pass for hardware IPs. The list of all the hardware
2437 * IPs that make up the asic is walked and the late_init callbacks are run.
2438 * late_init covers any special initialization that an IP requires
2439 * after all of the have been initialized or something that needs to happen
2440 * late in the init process.
2441 * Returns 0 on success, negative error code on failure.
2443 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2445 struct amdgpu_gpu_instance *gpu_instance;
2448 for (i = 0; i < adev->num_ip_blocks; i++) {
2449 if (!adev->ip_blocks[i].status.hw)
2451 if (adev->ip_blocks[i].version->funcs->late_init) {
2452 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2454 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2455 adev->ip_blocks[i].version->funcs->name, r);
2459 adev->ip_blocks[i].status.late_initialized = true;
2462 amdgpu_ras_set_error_query_ready(adev, true);
2464 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2465 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2467 amdgpu_device_fill_reset_magic(adev);
2469 r = amdgpu_device_enable_mgpu_fan_boost();
2471 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2474 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2475 mutex_lock(&mgpu_info.mutex);
2478 * Reset device p-state to low as this was booted with high.
2480 * This should be performed only after all devices from the same
2481 * hive get initialized.
2483 * However, it's unknown how many device in the hive in advance.
2484 * As this is counted one by one during devices initializations.
2486 * So, we wait for all XGMI interlinked devices initialized.
2487 * This may bring some delays as those devices may come from
2488 * different hives. But that should be OK.
2490 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2491 for (i = 0; i < mgpu_info.num_gpu; i++) {
2492 gpu_instance = &(mgpu_info.gpu_ins[i]);
2493 if (gpu_instance->adev->flags & AMD_IS_APU)
2496 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2497 AMDGPU_XGMI_PSTATE_MIN);
2499 DRM_ERROR("pstate setting failed (%d).\n", r);
2505 mutex_unlock(&mgpu_info.mutex);
2512 * amdgpu_device_ip_fini - run fini for hardware IPs
2514 * @adev: amdgpu_device pointer
2516 * Main teardown pass for hardware IPs. The list of all the hardware
2517 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2518 * are run. hw_fini tears down the hardware associated with each IP
2519 * and sw_fini tears down any software state associated with each IP.
2520 * Returns 0 on success, negative error code on failure.
2522 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2526 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2527 amdgpu_virt_release_ras_err_handler_data(adev);
2529 amdgpu_ras_pre_fini(adev);
2531 if (adev->gmc.xgmi.num_physical_nodes > 1)
2532 amdgpu_xgmi_remove_device(adev);
2534 amdgpu_amdkfd_device_fini(adev);
2536 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2537 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2539 /* need to disable SMC first */
2540 for (i = 0; i < adev->num_ip_blocks; i++) {
2541 if (!adev->ip_blocks[i].status.hw)
2543 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2544 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2545 /* XXX handle errors */
2547 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2548 adev->ip_blocks[i].version->funcs->name, r);
2550 adev->ip_blocks[i].status.hw = false;
2555 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2556 if (!adev->ip_blocks[i].status.hw)
2559 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2560 /* XXX handle errors */
2562 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2563 adev->ip_blocks[i].version->funcs->name, r);
2566 adev->ip_blocks[i].status.hw = false;
2570 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2571 if (!adev->ip_blocks[i].status.sw)
2574 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2575 amdgpu_ucode_free_bo(adev);
2576 amdgpu_free_static_csa(&adev->virt.csa_obj);
2577 amdgpu_device_wb_fini(adev);
2578 amdgpu_device_vram_scratch_fini(adev);
2579 amdgpu_ib_pool_fini(adev);
2582 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2583 /* XXX handle errors */
2585 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2586 adev->ip_blocks[i].version->funcs->name, r);
2588 adev->ip_blocks[i].status.sw = false;
2589 adev->ip_blocks[i].status.valid = false;
2592 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2593 if (!adev->ip_blocks[i].status.late_initialized)
2595 if (adev->ip_blocks[i].version->funcs->late_fini)
2596 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2597 adev->ip_blocks[i].status.late_initialized = false;
2600 amdgpu_ras_fini(adev);
2602 if (amdgpu_sriov_vf(adev))
2603 if (amdgpu_virt_release_full_gpu(adev, false))
2604 DRM_ERROR("failed to release exclusive mode on fini\n");
2610 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2612 * @work: work_struct.
2614 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2616 struct amdgpu_device *adev =
2617 container_of(work, struct amdgpu_device, delayed_init_work.work);
2620 r = amdgpu_ib_ring_tests(adev);
2622 DRM_ERROR("ib ring test failed (%d).\n", r);
2625 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2627 struct amdgpu_device *adev =
2628 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2630 mutex_lock(&adev->gfx.gfx_off_mutex);
2631 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2632 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2633 adev->gfx.gfx_off_state = true;
2635 mutex_unlock(&adev->gfx.gfx_off_mutex);
2639 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2641 * @adev: amdgpu_device pointer
2643 * Main suspend function for hardware IPs. The list of all the hardware
2644 * IPs that make up the asic is walked, clockgating is disabled and the
2645 * suspend callbacks are run. suspend puts the hardware and software state
2646 * in each IP into a state suitable for suspend.
2647 * Returns 0 on success, negative error code on failure.
2649 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2653 if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev)) {
2654 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2655 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2658 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2659 if (!adev->ip_blocks[i].status.valid)
2662 /* displays are handled separately */
2663 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2666 /* XXX handle errors */
2667 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2668 /* XXX handle errors */
2670 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2671 adev->ip_blocks[i].version->funcs->name, r);
2675 adev->ip_blocks[i].status.hw = false;
2682 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2684 * @adev: amdgpu_device pointer
2686 * Main suspend function for hardware IPs. The list of all the hardware
2687 * IPs that make up the asic is walked, clockgating is disabled and the
2688 * suspend callbacks are run. suspend puts the hardware and software state
2689 * in each IP into a state suitable for suspend.
2690 * Returns 0 on success, negative error code on failure.
2692 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2696 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2697 if (!adev->ip_blocks[i].status.valid)
2699 /* displays are handled in phase1 */
2700 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2702 /* PSP lost connection when err_event_athub occurs */
2703 if (amdgpu_ras_intr_triggered() &&
2704 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2705 adev->ip_blocks[i].status.hw = false;
2708 /* XXX handle errors */
2709 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2710 /* XXX handle errors */
2712 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2713 adev->ip_blocks[i].version->funcs->name, r);
2715 adev->ip_blocks[i].status.hw = false;
2716 /* handle putting the SMC in the appropriate state */
2717 if(!amdgpu_sriov_vf(adev)){
2718 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2719 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
2721 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2722 adev->mp1_state, r);
2727 adev->ip_blocks[i].status.hw = false;
2734 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2736 * @adev: amdgpu_device pointer
2738 * Main suspend function for hardware IPs. The list of all the hardware
2739 * IPs that make up the asic is walked, clockgating is disabled and the
2740 * suspend callbacks are run. suspend puts the hardware and software state
2741 * in each IP into a state suitable for suspend.
2742 * Returns 0 on success, negative error code on failure.
2744 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2748 if (amdgpu_sriov_vf(adev))
2749 amdgpu_virt_request_full_gpu(adev, false);
2751 r = amdgpu_device_ip_suspend_phase1(adev);
2754 r = amdgpu_device_ip_suspend_phase2(adev);
2756 if (amdgpu_sriov_vf(adev))
2757 amdgpu_virt_release_full_gpu(adev, false);
2762 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2766 static enum amd_ip_block_type ip_order[] = {
2767 AMD_IP_BLOCK_TYPE_GMC,
2768 AMD_IP_BLOCK_TYPE_COMMON,
2769 AMD_IP_BLOCK_TYPE_PSP,
2770 AMD_IP_BLOCK_TYPE_IH,
2773 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2775 struct amdgpu_ip_block *block;
2777 block = &adev->ip_blocks[i];
2778 block->status.hw = false;
2780 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
2782 if (block->version->type != ip_order[j] ||
2783 !block->status.valid)
2786 r = block->version->funcs->hw_init(adev);
2787 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2790 block->status.hw = true;
2797 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2801 static enum amd_ip_block_type ip_order[] = {
2802 AMD_IP_BLOCK_TYPE_SMC,
2803 AMD_IP_BLOCK_TYPE_DCE,
2804 AMD_IP_BLOCK_TYPE_GFX,
2805 AMD_IP_BLOCK_TYPE_SDMA,
2806 AMD_IP_BLOCK_TYPE_UVD,
2807 AMD_IP_BLOCK_TYPE_VCE,
2808 AMD_IP_BLOCK_TYPE_VCN
2811 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2813 struct amdgpu_ip_block *block;
2815 for (j = 0; j < adev->num_ip_blocks; j++) {
2816 block = &adev->ip_blocks[j];
2818 if (block->version->type != ip_order[i] ||
2819 !block->status.valid ||
2823 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
2824 r = block->version->funcs->resume(adev);
2826 r = block->version->funcs->hw_init(adev);
2828 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2831 block->status.hw = true;
2839 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2841 * @adev: amdgpu_device pointer
2843 * First resume function for hardware IPs. The list of all the hardware
2844 * IPs that make up the asic is walked and the resume callbacks are run for
2845 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2846 * after a suspend and updates the software state as necessary. This
2847 * function is also used for restoring the GPU after a GPU reset.
2848 * Returns 0 on success, negative error code on failure.
2850 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2854 for (i = 0; i < adev->num_ip_blocks; i++) {
2855 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2857 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2858 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2859 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2861 r = adev->ip_blocks[i].version->funcs->resume(adev);
2863 DRM_ERROR("resume of IP block <%s> failed %d\n",
2864 adev->ip_blocks[i].version->funcs->name, r);
2867 adev->ip_blocks[i].status.hw = true;
2875 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2877 * @adev: amdgpu_device pointer
2879 * First resume function for hardware IPs. The list of all the hardware
2880 * IPs that make up the asic is walked and the resume callbacks are run for
2881 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2882 * functional state after a suspend and updates the software state as
2883 * necessary. This function is also used for restoring the GPU after a GPU
2885 * Returns 0 on success, negative error code on failure.
2887 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2891 for (i = 0; i < adev->num_ip_blocks; i++) {
2892 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2894 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2895 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2896 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2897 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2899 r = adev->ip_blocks[i].version->funcs->resume(adev);
2901 DRM_ERROR("resume of IP block <%s> failed %d\n",
2902 adev->ip_blocks[i].version->funcs->name, r);
2905 adev->ip_blocks[i].status.hw = true;
2912 * amdgpu_device_ip_resume - run resume for hardware IPs
2914 * @adev: amdgpu_device pointer
2916 * Main resume function for hardware IPs. The hardware IPs
2917 * are split into two resume functions because they are
2918 * are also used in in recovering from a GPU reset and some additional
2919 * steps need to be take between them. In this case (S3/S4) they are
2921 * Returns 0 on success, negative error code on failure.
2923 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2927 r = amdgpu_device_ip_resume_phase1(adev);
2931 r = amdgpu_device_fw_loading(adev);
2935 r = amdgpu_device_ip_resume_phase2(adev);
2941 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2943 * @adev: amdgpu_device pointer
2945 * Query the VBIOS data tables to determine if the board supports SR-IOV.
2947 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2949 if (amdgpu_sriov_vf(adev)) {
2950 if (adev->is_atom_fw) {
2951 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2952 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2954 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2955 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2958 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2959 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2964 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2966 * @asic_type: AMD asic type
2968 * Check if there is DC (new modesetting infrastructre) support for an asic.
2969 * returns true if DC has support, false if not.
2971 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2973 switch (asic_type) {
2974 #if defined(CONFIG_DRM_AMD_DC)
2975 #if defined(CONFIG_DRM_AMD_DC_SI)
2986 * We have systems in the wild with these ASICs that require
2987 * LVDS and VGA support which is not supported with DC.
2989 * Fallback to the non-DC driver here by default so as not to
2990 * cause regressions.
2992 return amdgpu_dc > 0;
2996 case CHIP_POLARIS10:
2997 case CHIP_POLARIS11:
2998 case CHIP_POLARIS12:
3005 #if defined(CONFIG_DRM_AMD_DC_DCN)
3011 case CHIP_SIENNA_CICHLID:
3012 case CHIP_NAVY_FLOUNDER:
3013 case CHIP_DIMGREY_CAVEFISH:
3016 return amdgpu_dc != 0;
3020 DRM_INFO("Display Core has been requested via kernel parameter "
3021 "but isn't supported by ASIC, ignoring\n");
3027 * amdgpu_device_has_dc_support - check if dc is supported
3029 * @adev: amdgpu_device pointer
3031 * Returns true for supported, false for not supported
3033 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3035 if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display)
3038 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3042 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3044 struct amdgpu_device *adev =
3045 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3046 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3048 /* It's a bug to not have a hive within this function */
3053 * Use task barrier to synchronize all xgmi reset works across the
3054 * hive. task_barrier_enter and task_barrier_exit will block
3055 * until all the threads running the xgmi reset works reach
3056 * those points. task_barrier_full will do both blocks.
3058 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3060 task_barrier_enter(&hive->tb);
3061 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3063 if (adev->asic_reset_res)
3066 task_barrier_exit(&hive->tb);
3067 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3069 if (adev->asic_reset_res)
3072 if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
3073 adev->mmhub.funcs->reset_ras_error_count(adev);
3076 task_barrier_full(&hive->tb);
3077 adev->asic_reset_res = amdgpu_asic_reset(adev);
3081 if (adev->asic_reset_res)
3082 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3083 adev->asic_reset_res, adev_to_drm(adev)->unique);
3084 amdgpu_put_xgmi_hive(hive);
3087 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3089 char *input = amdgpu_lockup_timeout;
3090 char *timeout_setting = NULL;
3096 * By default timeout for non compute jobs is 10000.
3097 * And there is no timeout enforced on compute jobs.
3098 * In SR-IOV or passthrough mode, timeout for compute
3099 * jobs are 60000 by default.
3101 adev->gfx_timeout = msecs_to_jiffies(10000);
3102 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3103 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3104 adev->compute_timeout = msecs_to_jiffies(60000);
3106 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
3108 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3109 while ((timeout_setting = strsep(&input, ",")) &&
3110 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3111 ret = kstrtol(timeout_setting, 0, &timeout);
3118 } else if (timeout < 0) {
3119 timeout = MAX_SCHEDULE_TIMEOUT;
3121 timeout = msecs_to_jiffies(timeout);
3126 adev->gfx_timeout = timeout;
3129 adev->compute_timeout = timeout;
3132 adev->sdma_timeout = timeout;
3135 adev->video_timeout = timeout;
3142 * There is only one value specified and
3143 * it should apply to all non-compute jobs.
3146 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3147 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3148 adev->compute_timeout = adev->gfx_timeout;
3155 static const struct attribute *amdgpu_dev_attributes[] = {
3156 &dev_attr_product_name.attr,
3157 &dev_attr_product_number.attr,
3158 &dev_attr_serial_number.attr,
3159 &dev_attr_pcie_replay_count.attr,
3165 * amdgpu_device_init - initialize the driver
3167 * @adev: amdgpu_device pointer
3168 * @flags: driver flags
3170 * Initializes the driver info and hw (all asics).
3171 * Returns 0 for success or an error on failure.
3172 * Called at driver startup.
3174 int amdgpu_device_init(struct amdgpu_device *adev,
3177 struct drm_device *ddev = adev_to_drm(adev);
3178 struct pci_dev *pdev = adev->pdev;
3183 adev->shutdown = false;
3184 adev->flags = flags;
3186 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3187 adev->asic_type = amdgpu_force_asic_type;
3189 adev->asic_type = flags & AMD_ASIC_MASK;
3191 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3192 if (amdgpu_emu_mode == 1)
3193 adev->usec_timeout *= 10;
3194 adev->gmc.gart_size = 512 * 1024 * 1024;
3195 adev->accel_working = false;
3196 adev->num_rings = 0;
3197 adev->mman.buffer_funcs = NULL;
3198 adev->mman.buffer_funcs_ring = NULL;
3199 adev->vm_manager.vm_pte_funcs = NULL;
3200 adev->vm_manager.vm_pte_num_scheds = 0;
3201 adev->gmc.gmc_funcs = NULL;
3202 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3203 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3205 adev->smc_rreg = &amdgpu_invalid_rreg;
3206 adev->smc_wreg = &amdgpu_invalid_wreg;
3207 adev->pcie_rreg = &amdgpu_invalid_rreg;
3208 adev->pcie_wreg = &amdgpu_invalid_wreg;
3209 adev->pciep_rreg = &amdgpu_invalid_rreg;
3210 adev->pciep_wreg = &amdgpu_invalid_wreg;
3211 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3212 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3213 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3214 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3215 adev->didt_rreg = &amdgpu_invalid_rreg;
3216 adev->didt_wreg = &amdgpu_invalid_wreg;
3217 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3218 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3219 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3220 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3222 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3223 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3224 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3226 /* mutex initialization are all done here so we
3227 * can recall function without having locking issues */
3228 atomic_set(&adev->irq.ih.lock, 0);
3229 mutex_init(&adev->firmware.mutex);
3230 mutex_init(&adev->pm.mutex);
3231 mutex_init(&adev->gfx.gpu_clock_mutex);
3232 mutex_init(&adev->srbm_mutex);
3233 mutex_init(&adev->gfx.pipe_reserve_mutex);
3234 mutex_init(&adev->gfx.gfx_off_mutex);
3235 mutex_init(&adev->grbm_idx_mutex);
3236 mutex_init(&adev->mn_lock);
3237 mutex_init(&adev->virt.vf_errors.lock);
3238 hash_init(adev->mn_hash);
3239 atomic_set(&adev->in_gpu_reset, 0);
3240 init_rwsem(&adev->reset_sem);
3241 mutex_init(&adev->psp.mutex);
3242 mutex_init(&adev->notifier_lock);
3244 r = amdgpu_device_check_arguments(adev);
3248 spin_lock_init(&adev->mmio_idx_lock);
3249 spin_lock_init(&adev->smc_idx_lock);
3250 spin_lock_init(&adev->pcie_idx_lock);
3251 spin_lock_init(&adev->uvd_ctx_idx_lock);
3252 spin_lock_init(&adev->didt_idx_lock);
3253 spin_lock_init(&adev->gc_cac_idx_lock);
3254 spin_lock_init(&adev->se_cac_idx_lock);
3255 spin_lock_init(&adev->audio_endpt_idx_lock);
3256 spin_lock_init(&adev->mm_stats.lock);
3258 INIT_LIST_HEAD(&adev->shadow_list);
3259 mutex_init(&adev->shadow_list_lock);
3261 INIT_DELAYED_WORK(&adev->delayed_init_work,
3262 amdgpu_device_delayed_init_work_handler);
3263 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3264 amdgpu_device_delay_enable_gfx_off);
3266 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3268 adev->gfx.gfx_off_req_count = 1;
3269 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3271 atomic_set(&adev->throttling_logging_enabled, 1);
3273 * If throttling continues, logging will be performed every minute
3274 * to avoid log flooding. "-1" is subtracted since the thermal
3275 * throttling interrupt comes every second. Thus, the total logging
3276 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3277 * for throttling interrupt) = 60 seconds.
3279 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3280 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3282 /* Registers mapping */
3283 /* TODO: block userspace mapping of io register */
3284 if (adev->asic_type >= CHIP_BONAIRE) {
3285 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3286 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3288 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3289 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3292 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3293 if (adev->rmmio == NULL) {
3296 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3297 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3299 /* io port mapping */
3300 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3301 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
3302 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
3303 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
3307 if (adev->rio_mem == NULL)
3308 DRM_INFO("PCI I/O BAR is not found.\n");
3310 /* enable PCIE atomic ops */
3311 r = pci_enable_atomic_ops_to_root(adev->pdev,
3312 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3313 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3315 adev->have_atomics_support = false;
3316 DRM_INFO("PCIE atomic ops is not supported\n");
3318 adev->have_atomics_support = true;
3321 amdgpu_device_get_pcie_info(adev);
3324 DRM_INFO("MCBP is enabled\n");
3326 if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
3327 adev->enable_mes = true;
3329 /* detect hw virtualization here */
3330 amdgpu_detect_virtualization(adev);
3332 r = amdgpu_device_get_job_timeout_settings(adev);
3334 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3338 /* early init functions */
3339 r = amdgpu_device_ip_early_init(adev);
3343 /* doorbell bar mapping and doorbell index init*/
3344 amdgpu_device_doorbell_init(adev);
3346 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3347 /* this will fail for cards that aren't VGA class devices, just
3349 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3350 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
3352 if (amdgpu_device_supports_boco(ddev))
3354 if (amdgpu_has_atpx() &&
3355 (amdgpu_is_atpx_hybrid() ||
3356 amdgpu_has_atpx_dgpu_power_cntl()) &&
3357 !pci_is_thunderbolt_attached(adev->pdev))
3358 vga_switcheroo_register_client(adev->pdev,
3359 &amdgpu_switcheroo_ops, boco);
3361 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3363 if (amdgpu_emu_mode == 1) {
3364 /* post the asic on emulation mode */
3365 emu_soc_asic_init(adev);
3366 goto fence_driver_init;
3369 /* detect if we are with an SRIOV vbios */
3370 amdgpu_device_detect_sriov_bios(adev);
3372 /* check if we need to reset the asic
3373 * E.g., driver was not cleanly unloaded previously, etc.
3375 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3376 r = amdgpu_asic_reset(adev);
3378 dev_err(adev->dev, "asic reset on init failed\n");
3383 pci_enable_pcie_error_reporting(adev->ddev.pdev);
3385 /* Post card if necessary */
3386 if (amdgpu_device_need_post(adev)) {
3388 dev_err(adev->dev, "no vBIOS found\n");
3392 DRM_INFO("GPU posting now...\n");
3393 r = amdgpu_device_asic_init(adev);
3395 dev_err(adev->dev, "gpu post error!\n");
3400 if (adev->is_atom_fw) {
3401 /* Initialize clocks */
3402 r = amdgpu_atomfirmware_get_clock_info(adev);
3404 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3405 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3409 /* Initialize clocks */
3410 r = amdgpu_atombios_get_clock_info(adev);
3412 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3413 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3416 /* init i2c buses */
3417 if (!amdgpu_device_has_dc_support(adev))
3418 amdgpu_atombios_i2c_init(adev);
3423 r = amdgpu_fence_driver_init(adev);
3425 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
3426 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3430 /* init the mode config */
3431 drm_mode_config_init(adev_to_drm(adev));
3433 r = amdgpu_device_ip_init(adev);
3435 /* failed in exclusive mode due to timeout */
3436 if (amdgpu_sriov_vf(adev) &&
3437 !amdgpu_sriov_runtime(adev) &&
3438 amdgpu_virt_mmio_blocked(adev) &&
3439 !amdgpu_virt_wait_reset(adev)) {
3440 dev_err(adev->dev, "VF exclusive mode timeout\n");
3441 /* Don't send request since VF is inactive. */
3442 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3443 adev->virt.ops = NULL;
3447 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3448 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3453 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3454 adev->gfx.config.max_shader_engines,
3455 adev->gfx.config.max_sh_per_se,
3456 adev->gfx.config.max_cu_per_sh,
3457 adev->gfx.cu_info.number);
3459 adev->accel_working = true;
3461 amdgpu_vm_check_compute_bug(adev);
3463 /* Initialize the buffer migration limit. */
3464 if (amdgpu_moverate >= 0)
3465 max_MBps = amdgpu_moverate;
3467 max_MBps = 8; /* Allow 8 MB/s. */
3468 /* Get a log2 for easy divisions. */
3469 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3471 amdgpu_fbdev_init(adev);
3473 r = amdgpu_pm_sysfs_init(adev);
3475 adev->pm_sysfs_en = false;
3476 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3478 adev->pm_sysfs_en = true;
3480 r = amdgpu_ucode_sysfs_init(adev);
3482 adev->ucode_sysfs_en = false;
3483 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3485 adev->ucode_sysfs_en = true;
3487 if ((amdgpu_testing & 1)) {
3488 if (adev->accel_working)
3489 amdgpu_test_moves(adev);
3491 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
3493 if (amdgpu_benchmarking) {
3494 if (adev->accel_working)
3495 amdgpu_benchmark(adev, amdgpu_benchmarking);
3497 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
3501 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3502 * Otherwise the mgpu fan boost feature will be skipped due to the
3503 * gpu instance is counted less.
3505 amdgpu_register_gpu_instance(adev);
3507 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3508 * explicit gating rather than handling it automatically.
3510 r = amdgpu_device_ip_late_init(adev);
3512 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3513 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3518 amdgpu_ras_resume(adev);
3520 queue_delayed_work(system_wq, &adev->delayed_init_work,
3521 msecs_to_jiffies(AMDGPU_RESUME_MS));
3523 if (amdgpu_sriov_vf(adev))
3524 flush_delayed_work(&adev->delayed_init_work);
3526 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3528 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3530 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3531 r = amdgpu_pmu_init(adev);
3533 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3535 /* Have stored pci confspace at hand for restore in sudden PCI error */
3536 if (amdgpu_device_cache_pci_state(adev->pdev))
3537 pci_restore_state(pdev);
3542 amdgpu_vf_error_trans_all(adev);
3544 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3547 iounmap(adev->rmmio);
3554 * amdgpu_device_fini - tear down the driver
3556 * @adev: amdgpu_device pointer
3558 * Tear down the driver info (all asics).
3559 * Called at driver shutdown.
3561 void amdgpu_device_fini(struct amdgpu_device *adev)
3563 dev_info(adev->dev, "amdgpu: finishing device.\n");
3564 flush_delayed_work(&adev->delayed_init_work);
3565 adev->shutdown = true;
3567 kfree(adev->pci_state);
3569 /* make sure IB test finished before entering exclusive mode
3570 * to avoid preemption on IB test
3572 if (amdgpu_sriov_vf(adev)) {
3573 amdgpu_virt_request_full_gpu(adev, false);
3574 amdgpu_virt_fini_data_exchange(adev);
3577 /* disable all interrupts */
3578 amdgpu_irq_disable_all(adev);
3579 if (adev->mode_info.mode_config_initialized){
3580 if (!amdgpu_device_has_dc_support(adev))
3581 drm_helper_force_disable_all(adev_to_drm(adev));
3583 drm_atomic_helper_shutdown(adev_to_drm(adev));
3585 amdgpu_fence_driver_fini(adev);
3586 if (adev->pm_sysfs_en)
3587 amdgpu_pm_sysfs_fini(adev);
3588 amdgpu_fbdev_fini(adev);
3589 amdgpu_device_ip_fini(adev);
3590 release_firmware(adev->firmware.gpu_info_fw);
3591 adev->firmware.gpu_info_fw = NULL;
3592 adev->accel_working = false;
3593 /* free i2c buses */
3594 if (!amdgpu_device_has_dc_support(adev))
3595 amdgpu_i2c_fini(adev);
3597 if (amdgpu_emu_mode != 1)
3598 amdgpu_atombios_fini(adev);
3602 if (amdgpu_has_atpx() &&
3603 (amdgpu_is_atpx_hybrid() ||
3604 amdgpu_has_atpx_dgpu_power_cntl()) &&
3605 !pci_is_thunderbolt_attached(adev->pdev))
3606 vga_switcheroo_unregister_client(adev->pdev);
3607 if (amdgpu_device_supports_boco(adev_to_drm(adev)))
3608 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3609 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3610 vga_client_register(adev->pdev, NULL, NULL, NULL);
3612 pci_iounmap(adev->pdev, adev->rio_mem);
3613 adev->rio_mem = NULL;
3614 iounmap(adev->rmmio);
3616 amdgpu_device_doorbell_fini(adev);
3618 if (adev->ucode_sysfs_en)
3619 amdgpu_ucode_sysfs_fini(adev);
3621 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
3622 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3623 amdgpu_pmu_fini(adev);
3624 if (adev->mman.discovery_bin)
3625 amdgpu_discovery_fini(adev);
3633 * amdgpu_device_suspend - initiate device suspend
3635 * @dev: drm dev pointer
3636 * @fbcon : notify the fbdev of suspend
3638 * Puts the hw in the suspend state (all asics).
3639 * Returns 0 for success or an error on failure.
3640 * Called at driver suspend.
3642 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
3644 struct amdgpu_device *adev;
3645 struct drm_crtc *crtc;
3646 struct drm_connector *connector;
3647 struct drm_connector_list_iter iter;
3650 adev = drm_to_adev(dev);
3652 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3655 adev->in_suspend = true;
3656 drm_kms_helper_poll_disable(dev);
3659 amdgpu_fbdev_set_suspend(adev, 1);
3661 cancel_delayed_work_sync(&adev->delayed_init_work);
3663 if (!amdgpu_device_has_dc_support(adev)) {
3664 /* turn off display hw */
3665 drm_modeset_lock_all(dev);
3666 drm_connector_list_iter_begin(dev, &iter);
3667 drm_for_each_connector_iter(connector, &iter)
3668 drm_helper_connector_dpms(connector,
3670 drm_connector_list_iter_end(&iter);
3671 drm_modeset_unlock_all(dev);
3672 /* unpin the front buffers and cursors */
3673 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3674 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3675 struct drm_framebuffer *fb = crtc->primary->fb;
3676 struct amdgpu_bo *robj;
3678 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3679 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3680 r = amdgpu_bo_reserve(aobj, true);
3682 amdgpu_bo_unpin(aobj);
3683 amdgpu_bo_unreserve(aobj);
3687 if (fb == NULL || fb->obj[0] == NULL) {
3690 robj = gem_to_amdgpu_bo(fb->obj[0]);
3691 /* don't unpin kernel fb objects */
3692 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
3693 r = amdgpu_bo_reserve(robj, true);
3695 amdgpu_bo_unpin(robj);
3696 amdgpu_bo_unreserve(robj);
3702 amdgpu_ras_suspend(adev);
3704 r = amdgpu_device_ip_suspend_phase1(adev);
3706 amdgpu_amdkfd_suspend(adev, !fbcon);
3708 /* evict vram memory */
3709 amdgpu_bo_evict_vram(adev);
3711 amdgpu_fence_driver_suspend(adev);
3713 if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev))
3714 r = amdgpu_device_ip_suspend_phase2(adev);
3716 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
3717 /* evict remaining vram memory
3718 * This second call to evict vram is to evict the gart page table
3721 amdgpu_bo_evict_vram(adev);
3727 * amdgpu_device_resume - initiate device resume
3729 * @dev: drm dev pointer
3730 * @fbcon : notify the fbdev of resume
3732 * Bring the hw back to operating state (all asics).
3733 * Returns 0 for success or an error on failure.
3734 * Called at driver resume.
3736 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
3738 struct drm_connector *connector;
3739 struct drm_connector_list_iter iter;
3740 struct amdgpu_device *adev = drm_to_adev(dev);
3741 struct drm_crtc *crtc;
3744 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3747 if (amdgpu_acpi_is_s0ix_supported())
3748 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
3751 if (amdgpu_device_need_post(adev)) {
3752 r = amdgpu_device_asic_init(adev);
3754 dev_err(adev->dev, "amdgpu asic init failed\n");
3757 r = amdgpu_device_ip_resume(adev);
3759 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
3762 amdgpu_fence_driver_resume(adev);
3765 r = amdgpu_device_ip_late_init(adev);
3769 queue_delayed_work(system_wq, &adev->delayed_init_work,
3770 msecs_to_jiffies(AMDGPU_RESUME_MS));
3772 if (!amdgpu_device_has_dc_support(adev)) {
3774 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3775 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3777 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3778 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3779 r = amdgpu_bo_reserve(aobj, true);
3781 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3783 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
3784 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3785 amdgpu_bo_unreserve(aobj);
3790 r = amdgpu_amdkfd_resume(adev, !fbcon);
3794 /* Make sure IB tests flushed */
3795 flush_delayed_work(&adev->delayed_init_work);
3797 /* blat the mode back in */
3799 if (!amdgpu_device_has_dc_support(adev)) {
3801 drm_helper_resume_force_mode(dev);
3803 /* turn on display hw */
3804 drm_modeset_lock_all(dev);
3806 drm_connector_list_iter_begin(dev, &iter);
3807 drm_for_each_connector_iter(connector, &iter)
3808 drm_helper_connector_dpms(connector,
3810 drm_connector_list_iter_end(&iter);
3812 drm_modeset_unlock_all(dev);
3814 amdgpu_fbdev_set_suspend(adev, 0);
3817 drm_kms_helper_poll_enable(dev);
3819 amdgpu_ras_resume(adev);
3822 * Most of the connector probing functions try to acquire runtime pm
3823 * refs to ensure that the GPU is powered on when connector polling is
3824 * performed. Since we're calling this from a runtime PM callback,
3825 * trying to acquire rpm refs will cause us to deadlock.
3827 * Since we're guaranteed to be holding the rpm lock, it's safe to
3828 * temporarily disable the rpm helpers so this doesn't deadlock us.
3831 dev->dev->power.disable_depth++;
3833 if (!amdgpu_device_has_dc_support(adev))
3834 drm_helper_hpd_irq_event(dev);
3836 drm_kms_helper_hotplug_event(dev);
3838 dev->dev->power.disable_depth--;
3840 adev->in_suspend = false;
3846 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3848 * @adev: amdgpu_device pointer
3850 * The list of all the hardware IPs that make up the asic is walked and
3851 * the check_soft_reset callbacks are run. check_soft_reset determines
3852 * if the asic is still hung or not.
3853 * Returns true if any of the IPs are still in a hung state, false if not.
3855 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3858 bool asic_hang = false;
3860 if (amdgpu_sriov_vf(adev))
3863 if (amdgpu_asic_need_full_reset(adev))
3866 for (i = 0; i < adev->num_ip_blocks; i++) {
3867 if (!adev->ip_blocks[i].status.valid)
3869 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3870 adev->ip_blocks[i].status.hang =
3871 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3872 if (adev->ip_blocks[i].status.hang) {
3873 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3881 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3883 * @adev: amdgpu_device pointer
3885 * The list of all the hardware IPs that make up the asic is walked and the
3886 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3887 * handles any IP specific hardware or software state changes that are
3888 * necessary for a soft reset to succeed.
3889 * Returns 0 on success, negative error code on failure.
3891 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3895 for (i = 0; i < adev->num_ip_blocks; i++) {
3896 if (!adev->ip_blocks[i].status.valid)
3898 if (adev->ip_blocks[i].status.hang &&
3899 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3900 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3910 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3912 * @adev: amdgpu_device pointer
3914 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
3915 * reset is necessary to recover.
3916 * Returns true if a full asic reset is required, false if not.
3918 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3922 if (amdgpu_asic_need_full_reset(adev))
3925 for (i = 0; i < adev->num_ip_blocks; i++) {
3926 if (!adev->ip_blocks[i].status.valid)
3928 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3929 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3930 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3931 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3932 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3933 if (adev->ip_blocks[i].status.hang) {
3934 dev_info(adev->dev, "Some block need full reset!\n");
3943 * amdgpu_device_ip_soft_reset - do a soft reset
3945 * @adev: amdgpu_device pointer
3947 * The list of all the hardware IPs that make up the asic is walked and the
3948 * soft_reset callbacks are run if the block is hung. soft_reset handles any
3949 * IP specific hardware or software state changes that are necessary to soft
3951 * Returns 0 on success, negative error code on failure.
3953 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3957 for (i = 0; i < adev->num_ip_blocks; i++) {
3958 if (!adev->ip_blocks[i].status.valid)
3960 if (adev->ip_blocks[i].status.hang &&
3961 adev->ip_blocks[i].version->funcs->soft_reset) {
3962 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3972 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3974 * @adev: amdgpu_device pointer
3976 * The list of all the hardware IPs that make up the asic is walked and the
3977 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
3978 * handles any IP specific hardware or software state changes that are
3979 * necessary after the IP has been soft reset.
3980 * Returns 0 on success, negative error code on failure.
3982 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3986 for (i = 0; i < adev->num_ip_blocks; i++) {
3987 if (!adev->ip_blocks[i].status.valid)
3989 if (adev->ip_blocks[i].status.hang &&
3990 adev->ip_blocks[i].version->funcs->post_soft_reset)
3991 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4000 * amdgpu_device_recover_vram - Recover some VRAM contents
4002 * @adev: amdgpu_device pointer
4004 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4005 * restore things like GPUVM page tables after a GPU reset where
4006 * the contents of VRAM might be lost.
4009 * 0 on success, negative error code on failure.
4011 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4013 struct dma_fence *fence = NULL, *next = NULL;
4014 struct amdgpu_bo *shadow;
4017 if (amdgpu_sriov_runtime(adev))
4018 tmo = msecs_to_jiffies(8000);
4020 tmo = msecs_to_jiffies(100);
4022 dev_info(adev->dev, "recover vram bo from shadow start\n");
4023 mutex_lock(&adev->shadow_list_lock);
4024 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
4026 /* No need to recover an evicted BO */
4027 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
4028 shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
4029 shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
4032 r = amdgpu_bo_restore_shadow(shadow, &next);
4037 tmo = dma_fence_wait_timeout(fence, false, tmo);
4038 dma_fence_put(fence);
4043 } else if (tmo < 0) {
4051 mutex_unlock(&adev->shadow_list_lock);
4054 tmo = dma_fence_wait_timeout(fence, false, tmo);
4055 dma_fence_put(fence);
4057 if (r < 0 || tmo <= 0) {
4058 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4062 dev_info(adev->dev, "recover vram bo from shadow done\n");
4068 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4070 * @adev: amdgpu_device pointer
4071 * @from_hypervisor: request from hypervisor
4073 * do VF FLR and reinitialize Asic
4074 * return 0 means succeeded otherwise failed
4076 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4077 bool from_hypervisor)
4081 if (from_hypervisor)
4082 r = amdgpu_virt_request_full_gpu(adev, true);
4084 r = amdgpu_virt_reset_gpu(adev);
4088 amdgpu_amdkfd_pre_reset(adev);
4090 /* Resume IP prior to SMC */
4091 r = amdgpu_device_ip_reinit_early_sriov(adev);
4095 amdgpu_virt_init_data_exchange(adev);
4096 /* we need recover gart prior to run SMC/CP/SDMA resume */
4097 amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
4099 r = amdgpu_device_fw_loading(adev);
4103 /* now we are okay to resume SMC/CP/SDMA */
4104 r = amdgpu_device_ip_reinit_late_sriov(adev);
4108 amdgpu_irq_gpu_reset_resume_helper(adev);
4109 r = amdgpu_ib_ring_tests(adev);
4110 amdgpu_amdkfd_post_reset(adev);
4113 amdgpu_virt_release_full_gpu(adev, true);
4114 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4115 amdgpu_inc_vram_lost(adev);
4116 r = amdgpu_device_recover_vram(adev);
4123 * amdgpu_device_has_job_running - check if there is any job in mirror list
4125 * @adev: amdgpu_device pointer
4127 * check if there is any job in mirror list
4129 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4132 struct drm_sched_job *job;
4134 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4135 struct amdgpu_ring *ring = adev->rings[i];
4137 if (!ring || !ring->sched.thread)
4140 spin_lock(&ring->sched.job_list_lock);
4141 job = list_first_entry_or_null(&ring->sched.ring_mirror_list,
4142 struct drm_sched_job, node);
4143 spin_unlock(&ring->sched.job_list_lock);
4151 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4153 * @adev: amdgpu_device pointer
4155 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4158 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4160 if (!amdgpu_device_ip_check_soft_reset(adev)) {
4161 dev_info(adev->dev, "Timeout, but no hardware hang detected.\n");
4165 if (amdgpu_gpu_recovery == 0)
4168 if (amdgpu_sriov_vf(adev))
4171 if (amdgpu_gpu_recovery == -1) {
4172 switch (adev->asic_type) {
4178 case CHIP_POLARIS10:
4179 case CHIP_POLARIS11:
4180 case CHIP_POLARIS12:
4191 case CHIP_SIENNA_CICHLID:
4201 dev_info(adev->dev, "GPU recovery disabled.\n");
4206 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4207 struct amdgpu_job *job,
4208 bool *need_full_reset_arg)
4211 bool need_full_reset = *need_full_reset_arg;
4213 amdgpu_debugfs_wait_dump(adev);
4215 if (amdgpu_sriov_vf(adev)) {
4216 /* stop the data exchange thread */
4217 amdgpu_virt_fini_data_exchange(adev);
4220 /* block all schedulers and reset given job's ring */
4221 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4222 struct amdgpu_ring *ring = adev->rings[i];
4224 if (!ring || !ring->sched.thread)
4227 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4228 amdgpu_fence_driver_force_completion(ring);
4232 drm_sched_increase_karma(&job->base);
4234 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4235 if (!amdgpu_sriov_vf(adev)) {
4237 if (!need_full_reset)
4238 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4240 if (!need_full_reset) {
4241 amdgpu_device_ip_pre_soft_reset(adev);
4242 r = amdgpu_device_ip_soft_reset(adev);
4243 amdgpu_device_ip_post_soft_reset(adev);
4244 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4245 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4246 need_full_reset = true;
4250 if (need_full_reset)
4251 r = amdgpu_device_ip_suspend(adev);
4253 *need_full_reset_arg = need_full_reset;
4259 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
4260 struct list_head *device_list_handle,
4261 bool *need_full_reset_arg,
4264 struct amdgpu_device *tmp_adev = NULL;
4265 bool need_full_reset = *need_full_reset_arg, vram_lost = false;
4269 * ASIC reset has to be done on all HGMI hive nodes ASAP
4270 * to allow proper links negotiation in FW (within 1 sec)
4272 if (!skip_hw_reset && need_full_reset) {
4273 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4274 /* For XGMI run all resets in parallel to speed up the process */
4275 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4276 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4279 r = amdgpu_asic_reset(tmp_adev);
4282 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4283 r, adev_to_drm(tmp_adev)->unique);
4288 /* For XGMI wait for all resets to complete before proceed */
4290 list_for_each_entry(tmp_adev, device_list_handle,
4292 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4293 flush_work(&tmp_adev->xgmi_reset_work);
4294 r = tmp_adev->asic_reset_res;
4302 if (!r && amdgpu_ras_intr_triggered()) {
4303 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4304 if (tmp_adev->mmhub.funcs &&
4305 tmp_adev->mmhub.funcs->reset_ras_error_count)
4306 tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev);
4309 amdgpu_ras_intr_cleared();
4312 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4313 if (need_full_reset) {
4315 if (amdgpu_device_asic_init(tmp_adev))
4316 dev_warn(tmp_adev->dev, "asic atom init failed!");
4319 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4320 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4324 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4326 DRM_INFO("VRAM is lost due to GPU reset!\n");
4327 amdgpu_inc_vram_lost(tmp_adev);
4330 r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT));
4334 r = amdgpu_device_fw_loading(tmp_adev);
4338 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4343 amdgpu_device_fill_reset_magic(tmp_adev);
4346 * Add this ASIC as tracked as reset was already
4347 * complete successfully.
4349 amdgpu_register_gpu_instance(tmp_adev);
4351 r = amdgpu_device_ip_late_init(tmp_adev);
4355 amdgpu_fbdev_set_suspend(tmp_adev, 0);
4358 * The GPU enters bad state once faulty pages
4359 * by ECC has reached the threshold, and ras
4360 * recovery is scheduled next. So add one check
4361 * here to break recovery if it indeed exceeds
4362 * bad page threshold, and remind user to
4363 * retire this GPU or setting one bigger
4364 * bad_page_threshold value to fix this once
4365 * probing driver again.
4367 if (!amdgpu_ras_check_err_threshold(tmp_adev)) {
4369 amdgpu_ras_resume(tmp_adev);
4375 /* Update PSP FW topology after reset */
4376 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4377 r = amdgpu_xgmi_update_topology(hive, tmp_adev);
4383 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
4384 r = amdgpu_ib_ring_tests(tmp_adev);
4386 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
4387 r = amdgpu_device_ip_suspend(tmp_adev);
4388 need_full_reset = true;
4395 r = amdgpu_device_recover_vram(tmp_adev);
4397 tmp_adev->asic_reset_res = r;
4401 *need_full_reset_arg = need_full_reset;
4405 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev,
4406 struct amdgpu_hive_info *hive)
4408 if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)
4412 down_write_nest_lock(&adev->reset_sem, &hive->hive_lock);
4414 down_write(&adev->reset_sem);
4417 atomic_inc(&adev->gpu_reset_counter);
4418 switch (amdgpu_asic_reset_method(adev)) {
4419 case AMD_RESET_METHOD_MODE1:
4420 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
4422 case AMD_RESET_METHOD_MODE2:
4423 adev->mp1_state = PP_MP1_STATE_RESET;
4426 adev->mp1_state = PP_MP1_STATE_NONE;
4433 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
4435 amdgpu_vf_error_trans_all(adev);
4436 adev->mp1_state = PP_MP1_STATE_NONE;
4437 atomic_set(&adev->in_gpu_reset, 0);
4438 up_write(&adev->reset_sem);
4441 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
4443 struct pci_dev *p = NULL;
4445 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4446 adev->pdev->bus->number, 1);
4448 pm_runtime_enable(&(p->dev));
4449 pm_runtime_resume(&(p->dev));
4453 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
4455 enum amd_reset_method reset_method;
4456 struct pci_dev *p = NULL;
4460 * For now, only BACO and mode1 reset are confirmed
4461 * to suffer the audio issue without proper suspended.
4463 reset_method = amdgpu_asic_reset_method(adev);
4464 if ((reset_method != AMD_RESET_METHOD_BACO) &&
4465 (reset_method != AMD_RESET_METHOD_MODE1))
4468 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4469 adev->pdev->bus->number, 1);
4473 expires = pm_runtime_autosuspend_expiration(&(p->dev));
4476 * If we cannot get the audio device autosuspend delay,
4477 * a fixed 4S interval will be used. Considering 3S is
4478 * the audio controller default autosuspend delay setting.
4479 * 4S used here is guaranteed to cover that.
4481 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
4483 while (!pm_runtime_status_suspended(&(p->dev))) {
4484 if (!pm_runtime_suspend(&(p->dev)))
4487 if (expires < ktime_get_mono_fast_ns()) {
4488 dev_warn(adev->dev, "failed to suspend display audio\n");
4489 /* TODO: abort the succeeding gpu reset? */
4494 pm_runtime_disable(&(p->dev));
4500 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
4502 * @adev: amdgpu_device pointer
4503 * @job: which job trigger hang
4505 * Attempt to reset the GPU if it has hung (all asics).
4506 * Attempt to do soft-reset or full-reset and reinitialize Asic
4507 * Returns 0 for success or an error on failure.
4510 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
4511 struct amdgpu_job *job)
4513 struct list_head device_list, *device_list_handle = NULL;
4514 bool need_full_reset = false;
4515 bool job_signaled = false;
4516 struct amdgpu_hive_info *hive = NULL;
4517 struct amdgpu_device *tmp_adev = NULL;
4519 bool need_emergency_restart = false;
4520 bool audio_suspended = false;
4523 * Special case: RAS triggered and full reset isn't supported
4525 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
4528 * Flush RAM to disk so that after reboot
4529 * the user can read log and see why the system rebooted.
4531 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
4532 DRM_WARN("Emergency reboot.");
4535 emergency_restart();
4538 dev_info(adev->dev, "GPU %s begin!\n",
4539 need_emergency_restart ? "jobs stop":"reset");
4542 * Here we trylock to avoid chain of resets executing from
4543 * either trigger by jobs on different adevs in XGMI hive or jobs on
4544 * different schedulers for same device while this TO handler is running.
4545 * We always reset all schedulers for device and all devices for XGMI
4546 * hive so that should take care of them too.
4548 hive = amdgpu_get_xgmi_hive(adev);
4550 if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) {
4551 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
4552 job ? job->base.id : -1, hive->hive_id);
4553 amdgpu_put_xgmi_hive(hive);
4556 mutex_lock(&hive->hive_lock);
4560 * Build list of devices to reset.
4561 * In case we are in XGMI hive mode, resort the device list
4562 * to put adev in the 1st position.
4564 INIT_LIST_HEAD(&device_list);
4565 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4568 if (!list_is_first(&adev->gmc.xgmi.head, &hive->device_list))
4569 list_rotate_to_front(&adev->gmc.xgmi.head, &hive->device_list);
4570 device_list_handle = &hive->device_list;
4572 list_add_tail(&adev->gmc.xgmi.head, &device_list);
4573 device_list_handle = &device_list;
4576 /* block all schedulers and reset given job's ring */
4577 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4578 if (!amdgpu_device_lock_adev(tmp_adev, hive)) {
4579 dev_info(tmp_adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress",
4580 job ? job->base.id : -1);
4586 * Try to put the audio codec into suspend state
4587 * before gpu reset started.
4589 * Due to the power domain of the graphics device
4590 * is shared with AZ power domain. Without this,
4591 * we may change the audio hardware from behind
4592 * the audio driver's back. That will trigger
4593 * some audio codec errors.
4595 if (!amdgpu_device_suspend_display_audio(tmp_adev))
4596 audio_suspended = true;
4598 amdgpu_ras_set_error_query_ready(tmp_adev, false);
4600 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
4602 if (!amdgpu_sriov_vf(tmp_adev))
4603 amdgpu_amdkfd_pre_reset(tmp_adev);
4606 * Mark these ASICs to be reseted as untracked first
4607 * And add them back after reset completed
4609 amdgpu_unregister_gpu_instance(tmp_adev);
4611 amdgpu_fbdev_set_suspend(tmp_adev, 1);
4613 /* disable ras on ALL IPs */
4614 if (!need_emergency_restart &&
4615 amdgpu_device_ip_need_full_reset(tmp_adev))
4616 amdgpu_ras_suspend(tmp_adev);
4618 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4619 struct amdgpu_ring *ring = tmp_adev->rings[i];
4621 if (!ring || !ring->sched.thread)
4624 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
4626 if (need_emergency_restart)
4627 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
4631 if (need_emergency_restart)
4632 goto skip_sched_resume;
4635 * Must check guilty signal here since after this point all old
4636 * HW fences are force signaled.
4638 * job->base holds a reference to parent fence
4640 if (job && job->base.s_fence->parent &&
4641 dma_fence_is_signaled(job->base.s_fence->parent)) {
4642 job_signaled = true;
4643 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
4647 retry: /* Rest of adevs pre asic reset from XGMI hive. */
4648 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4649 r = amdgpu_device_pre_asic_reset(tmp_adev,
4650 (tmp_adev == adev) ? job : NULL,
4652 /*TODO Should we stop ?*/
4654 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
4655 r, adev_to_drm(tmp_adev)->unique);
4656 tmp_adev->asic_reset_res = r;
4660 /* Actual ASIC resets if needed.*/
4661 /* TODO Implement XGMI hive reset logic for SRIOV */
4662 if (amdgpu_sriov_vf(adev)) {
4663 r = amdgpu_device_reset_sriov(adev, job ? false : true);
4665 adev->asic_reset_res = r;
4667 r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset, false);
4668 if (r && r == -EAGAIN)
4674 /* Post ASIC reset for all devs .*/
4675 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4677 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4678 struct amdgpu_ring *ring = tmp_adev->rings[i];
4680 if (!ring || !ring->sched.thread)
4683 /* No point to resubmit jobs if we didn't HW reset*/
4684 if (!tmp_adev->asic_reset_res && !job_signaled)
4685 drm_sched_resubmit_jobs(&ring->sched);
4687 drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
4690 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
4691 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
4694 tmp_adev->asic_reset_res = 0;
4697 /* bad news, how to tell it to userspace ? */
4698 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
4699 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
4701 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
4706 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4707 /*unlock kfd: SRIOV would do it separately */
4708 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
4709 amdgpu_amdkfd_post_reset(tmp_adev);
4710 if (audio_suspended)
4711 amdgpu_device_resume_display_audio(tmp_adev);
4712 amdgpu_device_unlock_adev(tmp_adev);
4717 atomic_set(&hive->in_reset, 0);
4718 mutex_unlock(&hive->hive_lock);
4719 amdgpu_put_xgmi_hive(hive);
4723 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
4728 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
4730 * @adev: amdgpu_device pointer
4732 * Fetchs and stores in the driver the PCIE capabilities (gen speed
4733 * and lanes) of the slot the device is in. Handles APUs and
4734 * virtualized environments where PCIE config space may not be available.
4736 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
4738 struct pci_dev *pdev;
4739 enum pci_bus_speed speed_cap, platform_speed_cap;
4740 enum pcie_link_width platform_link_width;
4742 if (amdgpu_pcie_gen_cap)
4743 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
4745 if (amdgpu_pcie_lane_cap)
4746 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
4748 /* covers APUs as well */
4749 if (pci_is_root_bus(adev->pdev->bus)) {
4750 if (adev->pm.pcie_gen_mask == 0)
4751 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
4752 if (adev->pm.pcie_mlw_mask == 0)
4753 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4757 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
4760 pcie_bandwidth_available(adev->pdev, NULL,
4761 &platform_speed_cap, &platform_link_width);
4763 if (adev->pm.pcie_gen_mask == 0) {
4766 speed_cap = pcie_get_speed_cap(pdev);
4767 if (speed_cap == PCI_SPEED_UNKNOWN) {
4768 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4769 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4770 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4772 if (speed_cap == PCIE_SPEED_16_0GT)
4773 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4774 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4775 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4776 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
4777 else if (speed_cap == PCIE_SPEED_8_0GT)
4778 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4779 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4780 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4781 else if (speed_cap == PCIE_SPEED_5_0GT)
4782 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4783 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
4785 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
4788 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
4789 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4790 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4792 if (platform_speed_cap == PCIE_SPEED_16_0GT)
4793 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4794 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4795 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4796 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
4797 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
4798 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4799 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4800 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
4801 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
4802 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4803 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4805 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
4809 if (adev->pm.pcie_mlw_mask == 0) {
4810 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
4811 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
4813 switch (platform_link_width) {
4815 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
4816 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4817 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4818 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4819 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4820 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4821 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4824 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4825 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4826 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4827 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4828 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4829 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4832 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4833 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4834 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4835 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4836 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4839 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4840 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4841 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4842 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4845 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4846 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4847 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4850 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4851 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4854 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
4863 int amdgpu_device_baco_enter(struct drm_device *dev)
4865 struct amdgpu_device *adev = drm_to_adev(dev);
4866 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4868 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
4871 if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
4872 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
4874 return amdgpu_dpm_baco_enter(adev);
4877 int amdgpu_device_baco_exit(struct drm_device *dev)
4879 struct amdgpu_device *adev = drm_to_adev(dev);
4880 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4883 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
4886 ret = amdgpu_dpm_baco_exit(adev);
4890 if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
4891 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
4896 static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev)
4900 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4901 struct amdgpu_ring *ring = adev->rings[i];
4903 if (!ring || !ring->sched.thread)
4906 cancel_delayed_work_sync(&ring->sched.work_tdr);
4911 * amdgpu_pci_error_detected - Called when a PCI error is detected.
4912 * @pdev: PCI device struct
4913 * @state: PCI channel state
4915 * Description: Called when a PCI error is detected.
4917 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
4919 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4921 struct drm_device *dev = pci_get_drvdata(pdev);
4922 struct amdgpu_device *adev = drm_to_adev(dev);
4925 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
4927 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4928 DRM_WARN("No support for XGMI hive yet...");
4929 return PCI_ERS_RESULT_DISCONNECT;
4933 case pci_channel_io_normal:
4934 return PCI_ERS_RESULT_CAN_RECOVER;
4935 /* Fatal error, prepare for slot reset */
4936 case pci_channel_io_frozen:
4938 * Cancel and wait for all TDRs in progress if failing to
4939 * set adev->in_gpu_reset in amdgpu_device_lock_adev
4941 * Locking adev->reset_sem will prevent any external access
4942 * to GPU during PCI error recovery
4944 while (!amdgpu_device_lock_adev(adev, NULL))
4945 amdgpu_cancel_all_tdr(adev);
4948 * Block any work scheduling as we do for regular GPU reset
4949 * for the duration of the recovery
4951 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4952 struct amdgpu_ring *ring = adev->rings[i];
4954 if (!ring || !ring->sched.thread)
4957 drm_sched_stop(&ring->sched, NULL);
4959 return PCI_ERS_RESULT_NEED_RESET;
4960 case pci_channel_io_perm_failure:
4961 /* Permanent error, prepare for device removal */
4962 return PCI_ERS_RESULT_DISCONNECT;
4965 return PCI_ERS_RESULT_NEED_RESET;
4969 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
4970 * @pdev: pointer to PCI device
4972 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
4975 DRM_INFO("PCI error: mmio enabled callback!!\n");
4977 /* TODO - dump whatever for debugging purposes */
4979 /* This called only if amdgpu_pci_error_detected returns
4980 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
4981 * works, no need to reset slot.
4984 return PCI_ERS_RESULT_RECOVERED;
4988 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
4989 * @pdev: PCI device struct
4991 * Description: This routine is called by the pci error recovery
4992 * code after the PCI slot has been reset, just before we
4993 * should resume normal operations.
4995 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
4997 struct drm_device *dev = pci_get_drvdata(pdev);
4998 struct amdgpu_device *adev = drm_to_adev(dev);
5000 bool need_full_reset = true;
5002 struct list_head device_list;
5004 DRM_INFO("PCI error: slot reset callback!!\n");
5006 INIT_LIST_HEAD(&device_list);
5007 list_add_tail(&adev->gmc.xgmi.head, &device_list);
5009 /* wait for asic to come out of reset */
5012 /* Restore PCI confspace */
5013 amdgpu_device_load_pci_state(pdev);
5015 /* confirm ASIC came out of reset */
5016 for (i = 0; i < adev->usec_timeout; i++) {
5017 memsize = amdgpu_asic_get_config_memsize(adev);
5019 if (memsize != 0xffffffff)
5023 if (memsize == 0xffffffff) {
5028 adev->in_pci_err_recovery = true;
5029 r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset);
5030 adev->in_pci_err_recovery = false;
5034 r = amdgpu_do_asic_reset(NULL, &device_list, &need_full_reset, true);
5038 if (amdgpu_device_cache_pci_state(adev->pdev))
5039 pci_restore_state(adev->pdev);
5041 DRM_INFO("PCIe error recovery succeeded\n");
5043 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5044 amdgpu_device_unlock_adev(adev);
5047 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5051 * amdgpu_pci_resume() - resume normal ops after PCI reset
5052 * @pdev: pointer to PCI device
5054 * Called when the error recovery driver tells us that its
5055 * OK to resume normal operation. Use completion to allow
5056 * halted scsi ops to resume.
5058 void amdgpu_pci_resume(struct pci_dev *pdev)
5060 struct drm_device *dev = pci_get_drvdata(pdev);
5061 struct amdgpu_device *adev = drm_to_adev(dev);
5065 DRM_INFO("PCI error: resume callback!!\n");
5067 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5068 struct amdgpu_ring *ring = adev->rings[i];
5070 if (!ring || !ring->sched.thread)
5074 drm_sched_resubmit_jobs(&ring->sched);
5075 drm_sched_start(&ring->sched, true);
5078 amdgpu_device_unlock_adev(adev);
5081 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5083 struct drm_device *dev = pci_get_drvdata(pdev);
5084 struct amdgpu_device *adev = drm_to_adev(dev);
5087 r = pci_save_state(pdev);
5089 kfree(adev->pci_state);
5091 adev->pci_state = pci_store_saved_state(pdev);
5093 if (!adev->pci_state) {
5094 DRM_ERROR("Failed to store PCI saved state");
5098 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5105 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5107 struct drm_device *dev = pci_get_drvdata(pdev);
5108 struct amdgpu_device *adev = drm_to_adev(dev);
5111 if (!adev->pci_state)
5114 r = pci_load_saved_state(pdev, adev->pci_state);
5117 pci_restore_state(pdev);
5119 DRM_WARN("Failed to load PCI state, err:%d\n", r);