2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
33 #include <linux/iommu.h>
34 #include <linux/pci.h>
35 #include <linux/pci-p2pdma.h>
36 #include <linux/apple-gmux.h>
38 #include <drm/drm_aperture.h>
39 #include <drm/drm_atomic_helper.h>
40 #include <drm/drm_crtc_helper.h>
41 #include <drm/drm_fb_helper.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/amdgpu_drm.h>
44 #include <linux/device.h>
45 #include <linux/vgaarb.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/efi.h>
49 #include "amdgpu_trace.h"
50 #include "amdgpu_i2c.h"
52 #include "amdgpu_atombios.h"
53 #include "amdgpu_atomfirmware.h"
55 #ifdef CONFIG_DRM_AMDGPU_SI
58 #ifdef CONFIG_DRM_AMDGPU_CIK
64 #include "bif/bif_4_1_d.h"
65 #include <linux/firmware.h>
66 #include "amdgpu_vf_error.h"
68 #include "amdgpu_amdkfd.h"
69 #include "amdgpu_pm.h"
71 #include "amdgpu_xgmi.h"
72 #include "amdgpu_ras.h"
73 #include "amdgpu_pmu.h"
74 #include "amdgpu_fru_eeprom.h"
75 #include "amdgpu_reset.h"
76 #include "amdgpu_virt.h"
78 #include <linux/suspend.h>
79 #include <drm/task_barrier.h>
80 #include <linux/pm_runtime.h>
82 #include <drm/drm_drv.h>
84 #if IS_ENABLED(CONFIG_X86)
85 #include <asm/intel-family.h>
88 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
89 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
90 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
91 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
92 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
93 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
94 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
96 #define AMDGPU_RESUME_MS 2000
97 #define AMDGPU_MAX_RETRY_LIMIT 2
98 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
100 static const struct drm_driver amdgpu_kms_driver;
102 const char *amdgpu_asic_name[] = {
144 * DOC: pcie_replay_count
146 * The amdgpu driver provides a sysfs API for reporting the total number
147 * of PCIe replays (NAKs)
148 * The file pcie_replay_count is used for this and returns the total
149 * number of replays as a sum of the NAKs generated and NAKs received
152 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
153 struct device_attribute *attr, char *buf)
155 struct drm_device *ddev = dev_get_drvdata(dev);
156 struct amdgpu_device *adev = drm_to_adev(ddev);
157 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
159 return sysfs_emit(buf, "%llu\n", cnt);
162 static DEVICE_ATTR(pcie_replay_count, 0444,
163 amdgpu_device_get_pcie_replay_count, NULL);
168 * The amdgpu driver provides a sysfs API for giving board related information.
169 * It provides the form factor information in the format
173 * Possible form factor values
175 * - "cem" - PCIE CEM card
176 * - "oam" - Open Compute Accelerator Module
177 * - "unknown" - Not known
181 static ssize_t amdgpu_device_get_board_info(struct device *dev,
182 struct device_attribute *attr,
185 struct drm_device *ddev = dev_get_drvdata(dev);
186 struct amdgpu_device *adev = drm_to_adev(ddev);
187 enum amdgpu_pkg_type pkg_type = AMDGPU_PKG_TYPE_CEM;
190 if (adev->smuio.funcs && adev->smuio.funcs->get_pkg_type)
191 pkg_type = adev->smuio.funcs->get_pkg_type(adev);
194 case AMDGPU_PKG_TYPE_CEM:
197 case AMDGPU_PKG_TYPE_OAM:
205 return sysfs_emit(buf, "%s : %s\n", "type", pkg);
208 static DEVICE_ATTR(board_info, 0444, amdgpu_device_get_board_info, NULL);
210 static struct attribute *amdgpu_board_attrs[] = {
211 &dev_attr_board_info.attr,
215 static umode_t amdgpu_board_attrs_is_visible(struct kobject *kobj,
216 struct attribute *attr, int n)
218 struct device *dev = kobj_to_dev(kobj);
219 struct drm_device *ddev = dev_get_drvdata(dev);
220 struct amdgpu_device *adev = drm_to_adev(ddev);
222 if (adev->flags & AMD_IS_APU)
228 static const struct attribute_group amdgpu_board_attrs_group = {
229 .attrs = amdgpu_board_attrs,
230 .is_visible = amdgpu_board_attrs_is_visible
233 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
237 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
239 * @dev: drm_device pointer
241 * Returns true if the device is a dGPU with ATPX power control,
242 * otherwise return false.
244 bool amdgpu_device_supports_px(struct drm_device *dev)
246 struct amdgpu_device *adev = drm_to_adev(dev);
248 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
254 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
256 * @dev: drm_device pointer
258 * Returns true if the device is a dGPU with ACPI power control,
259 * otherwise return false.
261 bool amdgpu_device_supports_boco(struct drm_device *dev)
263 struct amdgpu_device *adev = drm_to_adev(dev);
266 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
272 * amdgpu_device_supports_baco - Does the device support BACO
274 * @dev: drm_device pointer
276 * Returns true if the device supporte BACO,
277 * otherwise return false.
279 bool amdgpu_device_supports_baco(struct drm_device *dev)
281 struct amdgpu_device *adev = drm_to_adev(dev);
283 return amdgpu_asic_supports_baco(adev);
287 * amdgpu_device_supports_smart_shift - Is the device dGPU with
288 * smart shift support
290 * @dev: drm_device pointer
292 * Returns true if the device is a dGPU with Smart Shift support,
293 * otherwise returns false.
295 bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
297 return (amdgpu_device_supports_boco(dev) &&
298 amdgpu_acpi_is_power_shift_control_supported());
302 * VRAM access helper functions
306 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
308 * @adev: amdgpu_device pointer
309 * @pos: offset of the buffer in vram
310 * @buf: virtual address of the buffer in system memory
311 * @size: read/write size, sizeof(@buf) must > @size
312 * @write: true - write to vram, otherwise - read from vram
314 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
315 void *buf, size_t size, bool write)
318 uint32_t hi = ~0, tmp = 0;
319 uint32_t *data = buf;
323 if (!drm_dev_enter(adev_to_drm(adev), &idx))
326 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
328 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
329 for (last = pos + size; pos < last; pos += 4) {
332 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
334 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
338 WREG32_NO_KIQ(mmMM_DATA, *data++);
340 *data++ = RREG32_NO_KIQ(mmMM_DATA);
343 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
348 * amdgpu_device_aper_access - access vram by vram aperature
350 * @adev: amdgpu_device pointer
351 * @pos: offset of the buffer in vram
352 * @buf: virtual address of the buffer in system memory
353 * @size: read/write size, sizeof(@buf) must > @size
354 * @write: true - write to vram, otherwise - read from vram
356 * The return value means how many bytes have been transferred.
358 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
359 void *buf, size_t size, bool write)
366 if (!adev->mman.aper_base_kaddr)
369 last = min(pos + size, adev->gmc.visible_vram_size);
371 addr = adev->mman.aper_base_kaddr + pos;
375 memcpy_toio(addr, buf, count);
376 /* Make sure HDP write cache flush happens without any reordering
377 * after the system memory contents are sent over PCIe device
380 amdgpu_device_flush_hdp(adev, NULL);
382 amdgpu_device_invalidate_hdp(adev, NULL);
383 /* Make sure HDP read cache is invalidated before issuing a read
387 memcpy_fromio(buf, addr, count);
399 * amdgpu_device_vram_access - read/write a buffer in vram
401 * @adev: amdgpu_device pointer
402 * @pos: offset of the buffer in vram
403 * @buf: virtual address of the buffer in system memory
404 * @size: read/write size, sizeof(@buf) must > @size
405 * @write: true - write to vram, otherwise - read from vram
407 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
408 void *buf, size_t size, bool write)
412 /* try to using vram apreature to access vram first */
413 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
416 /* using MM to access rest vram */
419 amdgpu_device_mm_access(adev, pos, buf, size, write);
424 * register access helper functions.
427 /* Check if hw access should be skipped because of hotplug or device error */
428 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
430 if (adev->no_hw_access)
433 #ifdef CONFIG_LOCKDEP
435 * This is a bit complicated to understand, so worth a comment. What we assert
436 * here is that the GPU reset is not running on another thread in parallel.
438 * For this we trylock the read side of the reset semaphore, if that succeeds
439 * we know that the reset is not running in paralell.
441 * If the trylock fails we assert that we are either already holding the read
442 * side of the lock or are the reset thread itself and hold the write side of
446 if (down_read_trylock(&adev->reset_domain->sem))
447 up_read(&adev->reset_domain->sem);
449 lockdep_assert_held(&adev->reset_domain->sem);
456 * amdgpu_device_rreg - read a memory mapped IO or indirect register
458 * @adev: amdgpu_device pointer
459 * @reg: dword aligned register offset
460 * @acc_flags: access flags which require special behavior
462 * Returns the 32 bit value from the offset specified.
464 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
465 uint32_t reg, uint32_t acc_flags)
469 if (amdgpu_device_skip_hw_access(adev))
472 if ((reg * 4) < adev->rmmio_size) {
473 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
474 amdgpu_sriov_runtime(adev) &&
475 down_read_trylock(&adev->reset_domain->sem)) {
476 ret = amdgpu_kiq_rreg(adev, reg, 0);
477 up_read(&adev->reset_domain->sem);
479 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
482 ret = adev->pcie_rreg(adev, reg * 4);
485 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
491 * MMIO register read with bytes helper functions
492 * @offset:bytes offset from MMIO start
496 * amdgpu_mm_rreg8 - read a memory mapped IO register
498 * @adev: amdgpu_device pointer
499 * @offset: byte aligned register offset
501 * Returns the 8 bit value from the offset specified.
503 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
505 if (amdgpu_device_skip_hw_access(adev))
508 if (offset < adev->rmmio_size)
509 return (readb(adev->rmmio + offset));
515 * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC
517 * @adev: amdgpu_device pointer
518 * @reg: dword aligned register offset
519 * @acc_flags: access flags which require special behavior
520 * @xcc_id: xcc accelerated compute core id
522 * Returns the 32 bit value from the offset specified.
524 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
525 uint32_t reg, uint32_t acc_flags,
528 uint32_t ret, rlcg_flag;
530 if (amdgpu_device_skip_hw_access(adev))
533 if ((reg * 4) < adev->rmmio_size) {
534 if (amdgpu_sriov_vf(adev) &&
535 !amdgpu_sriov_runtime(adev) &&
536 adev->gfx.rlc.rlcg_reg_access_supported &&
537 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
540 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, xcc_id);
541 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
542 amdgpu_sriov_runtime(adev) &&
543 down_read_trylock(&adev->reset_domain->sem)) {
544 ret = amdgpu_kiq_rreg(adev, reg, xcc_id);
545 up_read(&adev->reset_domain->sem);
547 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
550 ret = adev->pcie_rreg(adev, reg * 4);
557 * MMIO register write with bytes helper functions
558 * @offset:bytes offset from MMIO start
559 * @value: the value want to be written to the register
563 * amdgpu_mm_wreg8 - read a memory mapped IO register
565 * @adev: amdgpu_device pointer
566 * @offset: byte aligned register offset
567 * @value: 8 bit value to write
569 * Writes the value specified to the offset specified.
571 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
573 if (amdgpu_device_skip_hw_access(adev))
576 if (offset < adev->rmmio_size)
577 writeb(value, adev->rmmio + offset);
583 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
585 * @adev: amdgpu_device pointer
586 * @reg: dword aligned register offset
587 * @v: 32 bit value to write to the register
588 * @acc_flags: access flags which require special behavior
590 * Writes the value specified to the offset specified.
592 void amdgpu_device_wreg(struct amdgpu_device *adev,
593 uint32_t reg, uint32_t v,
596 if (amdgpu_device_skip_hw_access(adev))
599 if ((reg * 4) < adev->rmmio_size) {
600 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
601 amdgpu_sriov_runtime(adev) &&
602 down_read_trylock(&adev->reset_domain->sem)) {
603 amdgpu_kiq_wreg(adev, reg, v, 0);
604 up_read(&adev->reset_domain->sem);
606 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
609 adev->pcie_wreg(adev, reg * 4, v);
612 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
616 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
618 * @adev: amdgpu_device pointer
619 * @reg: mmio/rlc register
621 * @xcc_id: xcc accelerated compute core id
623 * this function is invoked only for the debugfs register access
625 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
626 uint32_t reg, uint32_t v,
629 if (amdgpu_device_skip_hw_access(adev))
632 if (amdgpu_sriov_fullaccess(adev) &&
633 adev->gfx.rlc.funcs &&
634 adev->gfx.rlc.funcs->is_rlcg_access_range) {
635 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
636 return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
637 } else if ((reg * 4) >= adev->rmmio_size) {
638 adev->pcie_wreg(adev, reg * 4, v);
640 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
645 * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC
647 * @adev: amdgpu_device pointer
648 * @reg: dword aligned register offset
649 * @v: 32 bit value to write to the register
650 * @acc_flags: access flags which require special behavior
651 * @xcc_id: xcc accelerated compute core id
653 * Writes the value specified to the offset specified.
655 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
656 uint32_t reg, uint32_t v,
657 uint32_t acc_flags, uint32_t xcc_id)
661 if (amdgpu_device_skip_hw_access(adev))
664 if ((reg * 4) < adev->rmmio_size) {
665 if (amdgpu_sriov_vf(adev) &&
666 !amdgpu_sriov_runtime(adev) &&
667 adev->gfx.rlc.rlcg_reg_access_supported &&
668 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
671 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, xcc_id);
672 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
673 amdgpu_sriov_runtime(adev) &&
674 down_read_trylock(&adev->reset_domain->sem)) {
675 amdgpu_kiq_wreg(adev, reg, v, xcc_id);
676 up_read(&adev->reset_domain->sem);
678 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
681 adev->pcie_wreg(adev, reg * 4, v);
686 * amdgpu_device_indirect_rreg - read an indirect register
688 * @adev: amdgpu_device pointer
689 * @reg_addr: indirect register address to read from
691 * Returns the value of indirect register @reg_addr
693 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
696 unsigned long flags, pcie_index, pcie_data;
697 void __iomem *pcie_index_offset;
698 void __iomem *pcie_data_offset;
701 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
702 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
704 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
705 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
706 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
708 writel(reg_addr, pcie_index_offset);
709 readl(pcie_index_offset);
710 r = readl(pcie_data_offset);
711 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
716 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
719 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
721 void __iomem *pcie_index_offset;
722 void __iomem *pcie_index_hi_offset;
723 void __iomem *pcie_data_offset;
725 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
726 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
727 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
728 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
732 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
733 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
734 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
735 if (pcie_index_hi != 0)
736 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
739 writel(reg_addr, pcie_index_offset);
740 readl(pcie_index_offset);
741 if (pcie_index_hi != 0) {
742 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
743 readl(pcie_index_hi_offset);
745 r = readl(pcie_data_offset);
747 /* clear the high bits */
748 if (pcie_index_hi != 0) {
749 writel(0, pcie_index_hi_offset);
750 readl(pcie_index_hi_offset);
753 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
759 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
761 * @adev: amdgpu_device pointer
762 * @reg_addr: indirect register address to read from
764 * Returns the value of indirect register @reg_addr
766 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
769 unsigned long flags, pcie_index, pcie_data;
770 void __iomem *pcie_index_offset;
771 void __iomem *pcie_data_offset;
774 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
775 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
777 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
778 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
779 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
781 /* read low 32 bits */
782 writel(reg_addr, pcie_index_offset);
783 readl(pcie_index_offset);
784 r = readl(pcie_data_offset);
785 /* read high 32 bits */
786 writel(reg_addr + 4, pcie_index_offset);
787 readl(pcie_index_offset);
788 r |= ((u64)readl(pcie_data_offset) << 32);
789 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
794 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
797 unsigned long flags, pcie_index, pcie_data;
798 unsigned long pcie_index_hi = 0;
799 void __iomem *pcie_index_offset;
800 void __iomem *pcie_index_hi_offset;
801 void __iomem *pcie_data_offset;
804 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
805 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
806 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
807 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
809 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
810 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
811 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
812 if (pcie_index_hi != 0)
813 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
816 /* read low 32 bits */
817 writel(reg_addr, pcie_index_offset);
818 readl(pcie_index_offset);
819 if (pcie_index_hi != 0) {
820 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
821 readl(pcie_index_hi_offset);
823 r = readl(pcie_data_offset);
824 /* read high 32 bits */
825 writel(reg_addr + 4, pcie_index_offset);
826 readl(pcie_index_offset);
827 if (pcie_index_hi != 0) {
828 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
829 readl(pcie_index_hi_offset);
831 r |= ((u64)readl(pcie_data_offset) << 32);
833 /* clear the high bits */
834 if (pcie_index_hi != 0) {
835 writel(0, pcie_index_hi_offset);
836 readl(pcie_index_hi_offset);
839 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
845 * amdgpu_device_indirect_wreg - write an indirect register address
847 * @adev: amdgpu_device pointer
848 * @reg_addr: indirect register offset
849 * @reg_data: indirect register data
852 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
853 u32 reg_addr, u32 reg_data)
855 unsigned long flags, pcie_index, pcie_data;
856 void __iomem *pcie_index_offset;
857 void __iomem *pcie_data_offset;
859 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
860 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
862 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
863 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
864 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
866 writel(reg_addr, pcie_index_offset);
867 readl(pcie_index_offset);
868 writel(reg_data, pcie_data_offset);
869 readl(pcie_data_offset);
870 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
873 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
874 u64 reg_addr, u32 reg_data)
876 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
877 void __iomem *pcie_index_offset;
878 void __iomem *pcie_index_hi_offset;
879 void __iomem *pcie_data_offset;
881 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
882 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
883 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
884 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
888 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
889 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
890 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
891 if (pcie_index_hi != 0)
892 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
895 writel(reg_addr, pcie_index_offset);
896 readl(pcie_index_offset);
897 if (pcie_index_hi != 0) {
898 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
899 readl(pcie_index_hi_offset);
901 writel(reg_data, pcie_data_offset);
902 readl(pcie_data_offset);
904 /* clear the high bits */
905 if (pcie_index_hi != 0) {
906 writel(0, pcie_index_hi_offset);
907 readl(pcie_index_hi_offset);
910 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
914 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
916 * @adev: amdgpu_device pointer
917 * @reg_addr: indirect register offset
918 * @reg_data: indirect register data
921 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
922 u32 reg_addr, u64 reg_data)
924 unsigned long flags, pcie_index, pcie_data;
925 void __iomem *pcie_index_offset;
926 void __iomem *pcie_data_offset;
928 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
929 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
931 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
932 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
933 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
935 /* write low 32 bits */
936 writel(reg_addr, pcie_index_offset);
937 readl(pcie_index_offset);
938 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
939 readl(pcie_data_offset);
940 /* write high 32 bits */
941 writel(reg_addr + 4, pcie_index_offset);
942 readl(pcie_index_offset);
943 writel((u32)(reg_data >> 32), pcie_data_offset);
944 readl(pcie_data_offset);
945 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
948 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
949 u64 reg_addr, u64 reg_data)
951 unsigned long flags, pcie_index, pcie_data;
952 unsigned long pcie_index_hi = 0;
953 void __iomem *pcie_index_offset;
954 void __iomem *pcie_index_hi_offset;
955 void __iomem *pcie_data_offset;
957 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
958 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
959 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
960 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
962 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
963 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
964 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
965 if (pcie_index_hi != 0)
966 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
969 /* write low 32 bits */
970 writel(reg_addr, pcie_index_offset);
971 readl(pcie_index_offset);
972 if (pcie_index_hi != 0) {
973 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
974 readl(pcie_index_hi_offset);
976 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
977 readl(pcie_data_offset);
978 /* write high 32 bits */
979 writel(reg_addr + 4, pcie_index_offset);
980 readl(pcie_index_offset);
981 if (pcie_index_hi != 0) {
982 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
983 readl(pcie_index_hi_offset);
985 writel((u32)(reg_data >> 32), pcie_data_offset);
986 readl(pcie_data_offset);
988 /* clear the high bits */
989 if (pcie_index_hi != 0) {
990 writel(0, pcie_index_hi_offset);
991 readl(pcie_index_hi_offset);
994 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
998 * amdgpu_device_get_rev_id - query device rev_id
1000 * @adev: amdgpu_device pointer
1002 * Return device rev_id
1004 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)
1006 return adev->nbio.funcs->get_rev_id(adev);
1010 * amdgpu_invalid_rreg - dummy reg read function
1012 * @adev: amdgpu_device pointer
1013 * @reg: offset of register
1015 * Dummy register read function. Used for register blocks
1016 * that certain asics don't have (all asics).
1017 * Returns the value in the register.
1019 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
1021 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
1026 static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
1028 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1034 * amdgpu_invalid_wreg - dummy reg write function
1036 * @adev: amdgpu_device pointer
1037 * @reg: offset of register
1038 * @v: value to write to the register
1040 * Dummy register read function. Used for register blocks
1041 * that certain asics don't have (all asics).
1043 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
1045 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
1050 static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
1052 DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",
1058 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
1060 * @adev: amdgpu_device pointer
1061 * @reg: offset of register
1063 * Dummy register read function. Used for register blocks
1064 * that certain asics don't have (all asics).
1065 * Returns the value in the register.
1067 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
1069 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
1074 static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)
1076 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1082 * amdgpu_invalid_wreg64 - dummy reg write function
1084 * @adev: amdgpu_device pointer
1085 * @reg: offset of register
1086 * @v: value to write to the register
1088 * Dummy register read function. Used for register blocks
1089 * that certain asics don't have (all asics).
1091 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
1093 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
1098 static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)
1100 DRM_ERROR("Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",
1106 * amdgpu_block_invalid_rreg - dummy reg read function
1108 * @adev: amdgpu_device pointer
1109 * @block: offset of instance
1110 * @reg: offset of register
1112 * Dummy register read function. Used for register blocks
1113 * that certain asics don't have (all asics).
1114 * Returns the value in the register.
1116 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
1117 uint32_t block, uint32_t reg)
1119 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
1126 * amdgpu_block_invalid_wreg - dummy reg write function
1128 * @adev: amdgpu_device pointer
1129 * @block: offset of instance
1130 * @reg: offset of register
1131 * @v: value to write to the register
1133 * Dummy register read function. Used for register blocks
1134 * that certain asics don't have (all asics).
1136 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
1138 uint32_t reg, uint32_t v)
1140 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
1146 * amdgpu_device_asic_init - Wrapper for atom asic_init
1148 * @adev: amdgpu_device pointer
1150 * Does any asic specific work and then calls atom asic init.
1152 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
1156 amdgpu_asic_pre_asic_init(adev);
1158 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1159 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) {
1160 amdgpu_psp_wait_for_bootloader(adev);
1161 ret = amdgpu_atomfirmware_asic_init(adev, true);
1162 /* TODO: check the return val and stop device initialization if boot fails */
1163 amdgpu_psp_query_boot_status(adev);
1166 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
1173 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
1175 * @adev: amdgpu_device pointer
1177 * Allocates a scratch page of VRAM for use by various things in the
1180 static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
1182 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
1183 AMDGPU_GEM_DOMAIN_VRAM |
1184 AMDGPU_GEM_DOMAIN_GTT,
1185 &adev->mem_scratch.robj,
1186 &adev->mem_scratch.gpu_addr,
1187 (void **)&adev->mem_scratch.ptr);
1191 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
1193 * @adev: amdgpu_device pointer
1195 * Frees the VRAM scratch page.
1197 static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
1199 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
1203 * amdgpu_device_program_register_sequence - program an array of registers.
1205 * @adev: amdgpu_device pointer
1206 * @registers: pointer to the register array
1207 * @array_size: size of the register array
1209 * Programs an array or registers with and or masks.
1210 * This is a helper for setting golden registers.
1212 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1213 const u32 *registers,
1214 const u32 array_size)
1216 u32 tmp, reg, and_mask, or_mask;
1222 for (i = 0; i < array_size; i += 3) {
1223 reg = registers[i + 0];
1224 and_mask = registers[i + 1];
1225 or_mask = registers[i + 2];
1227 if (and_mask == 0xffffffff) {
1232 if (adev->family >= AMDGPU_FAMILY_AI)
1233 tmp |= (or_mask & and_mask);
1242 * amdgpu_device_pci_config_reset - reset the GPU
1244 * @adev: amdgpu_device pointer
1246 * Resets the GPU using the pci config reset sequence.
1247 * Only applicable to asics prior to vega10.
1249 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1251 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1255 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1257 * @adev: amdgpu_device pointer
1259 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1261 int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1263 return pci_reset_function(adev->pdev);
1267 * amdgpu_device_wb_*()
1268 * Writeback is the method by which the GPU updates special pages in memory
1269 * with the status of certain GPU events (fences, ring pointers,etc.).
1273 * amdgpu_device_wb_fini - Disable Writeback and free memory
1275 * @adev: amdgpu_device pointer
1277 * Disables Writeback and frees the Writeback memory (all asics).
1278 * Used at driver shutdown.
1280 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1282 if (adev->wb.wb_obj) {
1283 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1285 (void **)&adev->wb.wb);
1286 adev->wb.wb_obj = NULL;
1291 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1293 * @adev: amdgpu_device pointer
1295 * Initializes writeback and allocates writeback memory (all asics).
1296 * Used at driver startup.
1297 * Returns 0 on success or an -error on failure.
1299 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1303 if (adev->wb.wb_obj == NULL) {
1304 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1305 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1306 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1307 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1308 (void **)&adev->wb.wb);
1310 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1314 adev->wb.num_wb = AMDGPU_MAX_WB;
1315 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1317 /* clear wb memory */
1318 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1325 * amdgpu_device_wb_get - Allocate a wb entry
1327 * @adev: amdgpu_device pointer
1330 * Allocate a wb slot for use by the driver (all asics).
1331 * Returns 0 on success or -EINVAL on failure.
1333 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1335 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1337 if (offset < adev->wb.num_wb) {
1338 __set_bit(offset, adev->wb.used);
1339 *wb = offset << 3; /* convert to dw offset */
1347 * amdgpu_device_wb_free - Free a wb entry
1349 * @adev: amdgpu_device pointer
1352 * Free a wb slot allocated for use by the driver (all asics)
1354 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1357 if (wb < adev->wb.num_wb)
1358 __clear_bit(wb, adev->wb.used);
1362 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1364 * @adev: amdgpu_device pointer
1366 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1367 * to fail, but if any of the BARs is not accessible after the size we abort
1368 * driver loading by returning -ENODEV.
1370 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1372 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1373 struct pci_bus *root;
1374 struct resource *res;
1379 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
1383 if (amdgpu_sriov_vf(adev))
1386 /* skip if the bios has already enabled large BAR */
1387 if (adev->gmc.real_vram_size &&
1388 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1391 /* Check if the root BUS has 64bit memory resources */
1392 root = adev->pdev->bus;
1393 while (root->parent)
1394 root = root->parent;
1396 pci_bus_for_each_resource(root, res, i) {
1397 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1398 res->start > 0x100000000ull)
1402 /* Trying to resize is pointless without a root hub window above 4GB */
1406 /* Limit the BAR size to what is available */
1407 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1410 /* Disable memory decoding while we change the BAR addresses and size */
1411 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1412 pci_write_config_word(adev->pdev, PCI_COMMAND,
1413 cmd & ~PCI_COMMAND_MEMORY);
1415 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1416 amdgpu_doorbell_fini(adev);
1417 if (adev->asic_type >= CHIP_BONAIRE)
1418 pci_release_resource(adev->pdev, 2);
1420 pci_release_resource(adev->pdev, 0);
1422 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1424 DRM_INFO("Not enough PCI address space for a large BAR.");
1425 else if (r && r != -ENOTSUPP)
1426 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1428 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1430 /* When the doorbell or fb BAR isn't available we have no chance of
1433 r = amdgpu_doorbell_init(adev);
1434 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1437 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1442 static bool amdgpu_device_read_bios(struct amdgpu_device *adev)
1444 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
1451 * GPU helpers function.
1454 * amdgpu_device_need_post - check if the hw need post or not
1456 * @adev: amdgpu_device pointer
1458 * Check if the asic has been initialized (all asics) at driver startup
1459 * or post is needed if hw reset is performed.
1460 * Returns true if need or false if not.
1462 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1466 if (amdgpu_sriov_vf(adev))
1469 if (!amdgpu_device_read_bios(adev))
1472 if (amdgpu_passthrough(adev)) {
1473 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1474 * some old smc fw still need driver do vPost otherwise gpu hang, while
1475 * those smc fw version above 22.15 doesn't have this flaw, so we force
1476 * vpost executed for smc version below 22.15
1478 if (adev->asic_type == CHIP_FIJI) {
1482 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1483 /* force vPost if error occured */
1487 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1488 if (fw_ver < 0x00160e00)
1493 /* Don't post if we need to reset whole hive on init */
1494 if (adev->gmc.xgmi.pending_reset)
1497 if (adev->has_hw_reset) {
1498 adev->has_hw_reset = false;
1502 /* bios scratch used on CIK+ */
1503 if (adev->asic_type >= CHIP_BONAIRE)
1504 return amdgpu_atombios_scratch_need_asic_init(adev);
1506 /* check MEM_SIZE for older asics */
1507 reg = amdgpu_asic_get_config_memsize(adev);
1509 if ((reg != 0) && (reg != 0xffffffff))
1516 * Check whether seamless boot is supported.
1518 * So far we only support seamless boot on DCE 3.0 or later.
1519 * If users report that it works on older ASICS as well, we may
1522 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)
1524 switch (amdgpu_seamless) {
1532 DRM_ERROR("Invalid value for amdgpu.seamless: %d\n",
1537 if (!(adev->flags & AMD_IS_APU))
1540 if (adev->mman.keep_stolen_vga_memory)
1543 return adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0);
1547 * Intel hosts such as Rocket Lake, Alder Lake, Raptor Lake and Sapphire Rapids
1548 * don't support dynamic speed switching. Until we have confirmation from Intel
1549 * that a specific host supports it, it's safer that we keep it disabled for all.
1551 * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
1552 * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
1554 static bool amdgpu_device_pcie_dynamic_switching_supported(void)
1556 #if IS_ENABLED(CONFIG_X86)
1557 struct cpuinfo_x86 *c = &cpu_data(0);
1559 if (c->x86_vendor == X86_VENDOR_INTEL)
1566 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1568 * @adev: amdgpu_device pointer
1570 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1571 * be set for this device.
1573 * Returns true if it should be used or false if not.
1575 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1577 switch (amdgpu_aspm) {
1587 if (adev->flags & AMD_IS_APU)
1589 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK))
1591 return pcie_aspm_enabled(adev->pdev);
1594 /* if we get transitioned to only one device, take VGA back */
1596 * amdgpu_device_vga_set_decode - enable/disable vga decode
1598 * @pdev: PCI device pointer
1599 * @state: enable/disable vga decode
1601 * Enable/disable vga decode (all asics).
1602 * Returns VGA resource flags.
1604 static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1607 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1609 amdgpu_asic_set_vga_state(adev, state);
1611 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1612 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1614 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1618 * amdgpu_device_check_block_size - validate the vm block size
1620 * @adev: amdgpu_device pointer
1622 * Validates the vm block size specified via module parameter.
1623 * The vm block size defines number of bits in page table versus page directory,
1624 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1625 * page table and the remaining bits are in the page directory.
1627 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1629 /* defines number of bits in page table versus page directory,
1630 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1631 * page table and the remaining bits are in the page directory
1633 if (amdgpu_vm_block_size == -1)
1636 if (amdgpu_vm_block_size < 9) {
1637 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1638 amdgpu_vm_block_size);
1639 amdgpu_vm_block_size = -1;
1644 * amdgpu_device_check_vm_size - validate the vm size
1646 * @adev: amdgpu_device pointer
1648 * Validates the vm size in GB specified via module parameter.
1649 * The VM size is the size of the GPU virtual memory space in GB.
1651 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1653 /* no need to check the default value */
1654 if (amdgpu_vm_size == -1)
1657 if (amdgpu_vm_size < 1) {
1658 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1660 amdgpu_vm_size = -1;
1664 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1667 bool is_os_64 = (sizeof(void *) == 8);
1668 uint64_t total_memory;
1669 uint64_t dram_size_seven_GB = 0x1B8000000;
1670 uint64_t dram_size_three_GB = 0xB8000000;
1672 if (amdgpu_smu_memory_pool_size == 0)
1676 DRM_WARN("Not 64-bit OS, feature not supported\n");
1680 total_memory = (uint64_t)si.totalram * si.mem_unit;
1682 if ((amdgpu_smu_memory_pool_size == 1) ||
1683 (amdgpu_smu_memory_pool_size == 2)) {
1684 if (total_memory < dram_size_three_GB)
1686 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1687 (amdgpu_smu_memory_pool_size == 8)) {
1688 if (total_memory < dram_size_seven_GB)
1691 DRM_WARN("Smu memory pool size not supported\n");
1694 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1699 DRM_WARN("No enough system memory\n");
1701 adev->pm.smu_prv_buffer_size = 0;
1704 static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1706 if (!(adev->flags & AMD_IS_APU) ||
1707 adev->asic_type < CHIP_RAVEN)
1710 switch (adev->asic_type) {
1712 if (adev->pdev->device == 0x15dd)
1713 adev->apu_flags |= AMD_APU_IS_RAVEN;
1714 if (adev->pdev->device == 0x15d8)
1715 adev->apu_flags |= AMD_APU_IS_PICASSO;
1718 if ((adev->pdev->device == 0x1636) ||
1719 (adev->pdev->device == 0x164c))
1720 adev->apu_flags |= AMD_APU_IS_RENOIR;
1722 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1725 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1727 case CHIP_YELLOW_CARP:
1729 case CHIP_CYAN_SKILLFISH:
1730 if ((adev->pdev->device == 0x13FE) ||
1731 (adev->pdev->device == 0x143F))
1732 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1742 * amdgpu_device_check_arguments - validate module params
1744 * @adev: amdgpu_device pointer
1746 * Validates certain module parameters and updates
1747 * the associated values used by the driver (all asics).
1749 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1751 if (amdgpu_sched_jobs < 4) {
1752 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1754 amdgpu_sched_jobs = 4;
1755 } else if (!is_power_of_2(amdgpu_sched_jobs)) {
1756 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1758 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1761 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1762 /* gart size must be greater or equal to 32M */
1763 dev_warn(adev->dev, "gart size (%d) too small\n",
1765 amdgpu_gart_size = -1;
1768 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1769 /* gtt size must be greater or equal to 32M */
1770 dev_warn(adev->dev, "gtt size (%d) too small\n",
1772 amdgpu_gtt_size = -1;
1775 /* valid range is between 4 and 9 inclusive */
1776 if (amdgpu_vm_fragment_size != -1 &&
1777 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1778 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1779 amdgpu_vm_fragment_size = -1;
1782 if (amdgpu_sched_hw_submission < 2) {
1783 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1784 amdgpu_sched_hw_submission);
1785 amdgpu_sched_hw_submission = 2;
1786 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1787 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1788 amdgpu_sched_hw_submission);
1789 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1792 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1793 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1794 amdgpu_reset_method = -1;
1797 amdgpu_device_check_smu_prv_buffer_size(adev);
1799 amdgpu_device_check_vm_size(adev);
1801 amdgpu_device_check_block_size(adev);
1803 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1809 * amdgpu_switcheroo_set_state - set switcheroo state
1811 * @pdev: pci dev pointer
1812 * @state: vga_switcheroo state
1814 * Callback for the switcheroo driver. Suspends or resumes
1815 * the asics before or after it is powered up using ACPI methods.
1817 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1818 enum vga_switcheroo_state state)
1820 struct drm_device *dev = pci_get_drvdata(pdev);
1823 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1826 if (state == VGA_SWITCHEROO_ON) {
1827 pr_info("switched on\n");
1828 /* don't suspend or resume card normally */
1829 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1831 pci_set_power_state(pdev, PCI_D0);
1832 amdgpu_device_load_pci_state(pdev);
1833 r = pci_enable_device(pdev);
1835 DRM_WARN("pci_enable_device failed (%d)\n", r);
1836 amdgpu_device_resume(dev, true);
1838 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1840 pr_info("switched off\n");
1841 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1842 amdgpu_device_prepare(dev);
1843 amdgpu_device_suspend(dev, true);
1844 amdgpu_device_cache_pci_state(pdev);
1845 /* Shut down the device */
1846 pci_disable_device(pdev);
1847 pci_set_power_state(pdev, PCI_D3cold);
1848 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1853 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1855 * @pdev: pci dev pointer
1857 * Callback for the switcheroo driver. Check of the switcheroo
1858 * state can be changed.
1859 * Returns true if the state can be changed, false if not.
1861 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1863 struct drm_device *dev = pci_get_drvdata(pdev);
1866 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1867 * locking inversion with the driver load path. And the access here is
1868 * completely racy anyway. So don't bother with locking for now.
1870 return atomic_read(&dev->open_count) == 0;
1873 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1874 .set_gpu_state = amdgpu_switcheroo_set_state,
1876 .can_switch = amdgpu_switcheroo_can_switch,
1880 * amdgpu_device_ip_set_clockgating_state - set the CG state
1882 * @dev: amdgpu_device pointer
1883 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1884 * @state: clockgating state (gate or ungate)
1886 * Sets the requested clockgating state for all instances of
1887 * the hardware IP specified.
1888 * Returns the error code from the last instance.
1890 int amdgpu_device_ip_set_clockgating_state(void *dev,
1891 enum amd_ip_block_type block_type,
1892 enum amd_clockgating_state state)
1894 struct amdgpu_device *adev = dev;
1897 for (i = 0; i < adev->num_ip_blocks; i++) {
1898 if (!adev->ip_blocks[i].status.valid)
1900 if (adev->ip_blocks[i].version->type != block_type)
1902 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1904 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1905 (void *)adev, state);
1907 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1908 adev->ip_blocks[i].version->funcs->name, r);
1914 * amdgpu_device_ip_set_powergating_state - set the PG state
1916 * @dev: amdgpu_device pointer
1917 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1918 * @state: powergating state (gate or ungate)
1920 * Sets the requested powergating state for all instances of
1921 * the hardware IP specified.
1922 * Returns the error code from the last instance.
1924 int amdgpu_device_ip_set_powergating_state(void *dev,
1925 enum amd_ip_block_type block_type,
1926 enum amd_powergating_state state)
1928 struct amdgpu_device *adev = dev;
1931 for (i = 0; i < adev->num_ip_blocks; i++) {
1932 if (!adev->ip_blocks[i].status.valid)
1934 if (adev->ip_blocks[i].version->type != block_type)
1936 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1938 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1939 (void *)adev, state);
1941 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1942 adev->ip_blocks[i].version->funcs->name, r);
1948 * amdgpu_device_ip_get_clockgating_state - get the CG state
1950 * @adev: amdgpu_device pointer
1951 * @flags: clockgating feature flags
1953 * Walks the list of IPs on the device and updates the clockgating
1954 * flags for each IP.
1955 * Updates @flags with the feature flags for each hardware IP where
1956 * clockgating is enabled.
1958 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1963 for (i = 0; i < adev->num_ip_blocks; i++) {
1964 if (!adev->ip_blocks[i].status.valid)
1966 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1967 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1972 * amdgpu_device_ip_wait_for_idle - wait for idle
1974 * @adev: amdgpu_device pointer
1975 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1977 * Waits for the request hardware IP to be idle.
1978 * Returns 0 for success or a negative error code on failure.
1980 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1981 enum amd_ip_block_type block_type)
1985 for (i = 0; i < adev->num_ip_blocks; i++) {
1986 if (!adev->ip_blocks[i].status.valid)
1988 if (adev->ip_blocks[i].version->type == block_type) {
1989 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
2000 * amdgpu_device_ip_is_idle - is the hardware IP idle
2002 * @adev: amdgpu_device pointer
2003 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2005 * Check if the hardware IP is idle or not.
2006 * Returns true if it the IP is idle, false if not.
2008 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
2009 enum amd_ip_block_type block_type)
2013 for (i = 0; i < adev->num_ip_blocks; i++) {
2014 if (!adev->ip_blocks[i].status.valid)
2016 if (adev->ip_blocks[i].version->type == block_type)
2017 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
2024 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
2026 * @adev: amdgpu_device pointer
2027 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
2029 * Returns a pointer to the hardware IP block structure
2030 * if it exists for the asic, otherwise NULL.
2032 struct amdgpu_ip_block *
2033 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
2034 enum amd_ip_block_type type)
2038 for (i = 0; i < adev->num_ip_blocks; i++)
2039 if (adev->ip_blocks[i].version->type == type)
2040 return &adev->ip_blocks[i];
2046 * amdgpu_device_ip_block_version_cmp
2048 * @adev: amdgpu_device pointer
2049 * @type: enum amd_ip_block_type
2050 * @major: major version
2051 * @minor: minor version
2053 * return 0 if equal or greater
2054 * return 1 if smaller or the ip_block doesn't exist
2056 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
2057 enum amd_ip_block_type type,
2058 u32 major, u32 minor)
2060 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
2062 if (ip_block && ((ip_block->version->major > major) ||
2063 ((ip_block->version->major == major) &&
2064 (ip_block->version->minor >= minor))))
2071 * amdgpu_device_ip_block_add
2073 * @adev: amdgpu_device pointer
2074 * @ip_block_version: pointer to the IP to add
2076 * Adds the IP block driver information to the collection of IPs
2079 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
2080 const struct amdgpu_ip_block_version *ip_block_version)
2082 if (!ip_block_version)
2085 switch (ip_block_version->type) {
2086 case AMD_IP_BLOCK_TYPE_VCN:
2087 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
2090 case AMD_IP_BLOCK_TYPE_JPEG:
2091 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
2098 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
2099 ip_block_version->funcs->name);
2101 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
2107 * amdgpu_device_enable_virtual_display - enable virtual display feature
2109 * @adev: amdgpu_device pointer
2111 * Enabled the virtual display feature if the user has enabled it via
2112 * the module parameter virtual_display. This feature provides a virtual
2113 * display hardware on headless boards or in virtualized environments.
2114 * This function parses and validates the configuration string specified by
2115 * the user and configues the virtual display configuration (number of
2116 * virtual connectors, crtcs, etc.) specified.
2118 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
2120 adev->enable_virtual_display = false;
2122 if (amdgpu_virtual_display) {
2123 const char *pci_address_name = pci_name(adev->pdev);
2124 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
2126 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
2127 pciaddstr_tmp = pciaddstr;
2128 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
2129 pciaddname = strsep(&pciaddname_tmp, ",");
2130 if (!strcmp("all", pciaddname)
2131 || !strcmp(pci_address_name, pciaddname)) {
2135 adev->enable_virtual_display = true;
2138 res = kstrtol(pciaddname_tmp, 10,
2146 adev->mode_info.num_crtc = num_crtc;
2148 adev->mode_info.num_crtc = 1;
2154 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
2155 amdgpu_virtual_display, pci_address_name,
2156 adev->enable_virtual_display, adev->mode_info.num_crtc);
2162 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
2164 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
2165 adev->mode_info.num_crtc = 1;
2166 adev->enable_virtual_display = true;
2167 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
2168 adev->enable_virtual_display, adev->mode_info.num_crtc);
2173 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
2175 * @adev: amdgpu_device pointer
2177 * Parses the asic configuration parameters specified in the gpu info
2178 * firmware and makes them availale to the driver for use in configuring
2180 * Returns 0 on success, -EINVAL on failure.
2182 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
2184 const char *chip_name;
2187 const struct gpu_info_firmware_header_v1_0 *hdr;
2189 adev->firmware.gpu_info_fw = NULL;
2191 if (adev->mman.discovery_bin) {
2193 * FIXME: The bounding box is still needed by Navi12, so
2194 * temporarily read it from gpu_info firmware. Should be dropped
2195 * when DAL no longer needs it.
2197 if (adev->asic_type != CHIP_NAVI12)
2201 switch (adev->asic_type) {
2205 chip_name = "vega10";
2208 chip_name = "vega12";
2211 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
2212 chip_name = "raven2";
2213 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
2214 chip_name = "picasso";
2216 chip_name = "raven";
2219 chip_name = "arcturus";
2222 chip_name = "navi12";
2226 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
2227 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name);
2230 "Failed to get gpu_info firmware \"%s\"\n",
2235 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2236 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2238 switch (hdr->version_major) {
2241 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2242 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2243 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2246 * Should be droped when DAL no longer needs it.
2248 if (adev->asic_type == CHIP_NAVI12)
2249 goto parse_soc_bounding_box;
2251 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2252 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2253 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2254 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2255 adev->gfx.config.max_texture_channel_caches =
2256 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2257 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2258 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2259 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2260 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2261 adev->gfx.config.double_offchip_lds_buf =
2262 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2263 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2264 adev->gfx.cu_info.max_waves_per_simd =
2265 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2266 adev->gfx.cu_info.max_scratch_slots_per_cu =
2267 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2268 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2269 if (hdr->version_minor >= 1) {
2270 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2271 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2272 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2273 adev->gfx.config.num_sc_per_sh =
2274 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2275 adev->gfx.config.num_packer_per_sc =
2276 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2279 parse_soc_bounding_box:
2281 * soc bounding box info is not integrated in disocovery table,
2282 * we always need to parse it from gpu info firmware if needed.
2284 if (hdr->version_minor == 2) {
2285 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2286 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2287 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2288 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2294 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2303 * amdgpu_device_ip_early_init - run early init for hardware IPs
2305 * @adev: amdgpu_device pointer
2307 * Early initialization pass for hardware IPs. The hardware IPs that make
2308 * up each asic are discovered each IP's early_init callback is run. This
2309 * is the first stage in initializing the asic.
2310 * Returns 0 on success, negative error code on failure.
2312 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2314 struct pci_dev *parent;
2318 amdgpu_device_enable_virtual_display(adev);
2320 if (amdgpu_sriov_vf(adev)) {
2321 r = amdgpu_virt_request_full_gpu(adev, true);
2326 switch (adev->asic_type) {
2327 #ifdef CONFIG_DRM_AMDGPU_SI
2333 adev->family = AMDGPU_FAMILY_SI;
2334 r = si_set_ip_blocks(adev);
2339 #ifdef CONFIG_DRM_AMDGPU_CIK
2345 if (adev->flags & AMD_IS_APU)
2346 adev->family = AMDGPU_FAMILY_KV;
2348 adev->family = AMDGPU_FAMILY_CI;
2350 r = cik_set_ip_blocks(adev);
2358 case CHIP_POLARIS10:
2359 case CHIP_POLARIS11:
2360 case CHIP_POLARIS12:
2364 if (adev->flags & AMD_IS_APU)
2365 adev->family = AMDGPU_FAMILY_CZ;
2367 adev->family = AMDGPU_FAMILY_VI;
2369 r = vi_set_ip_blocks(adev);
2374 r = amdgpu_discovery_set_ip_blocks(adev);
2380 if (amdgpu_has_atpx() &&
2381 (amdgpu_is_atpx_hybrid() ||
2382 amdgpu_has_atpx_dgpu_power_cntl()) &&
2383 ((adev->flags & AMD_IS_APU) == 0) &&
2384 !dev_is_removable(&adev->pdev->dev))
2385 adev->flags |= AMD_IS_PX;
2387 if (!(adev->flags & AMD_IS_APU)) {
2388 parent = pcie_find_root_port(adev->pdev);
2389 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2393 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2394 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2395 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2396 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2397 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2398 if (!amdgpu_device_pcie_dynamic_switching_supported())
2399 adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;
2402 for (i = 0; i < adev->num_ip_blocks; i++) {
2403 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2404 DRM_WARN("disabled ip block: %d <%s>\n",
2405 i, adev->ip_blocks[i].version->funcs->name);
2406 adev->ip_blocks[i].status.valid = false;
2408 if (adev->ip_blocks[i].version->funcs->early_init) {
2409 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2411 adev->ip_blocks[i].status.valid = false;
2413 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2414 adev->ip_blocks[i].version->funcs->name, r);
2417 adev->ip_blocks[i].status.valid = true;
2420 adev->ip_blocks[i].status.valid = true;
2423 /* get the vbios after the asic_funcs are set up */
2424 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2425 r = amdgpu_device_parse_gpu_info_fw(adev);
2430 if (amdgpu_device_read_bios(adev)) {
2431 if (!amdgpu_get_bios(adev))
2434 r = amdgpu_atombios_init(adev);
2436 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2437 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2442 /*get pf2vf msg info at it's earliest time*/
2443 if (amdgpu_sriov_vf(adev))
2444 amdgpu_virt_init_data_exchange(adev);
2451 amdgpu_amdkfd_device_probe(adev);
2452 adev->cg_flags &= amdgpu_cg_mask;
2453 adev->pg_flags &= amdgpu_pg_mask;
2458 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2462 for (i = 0; i < adev->num_ip_blocks; i++) {
2463 if (!adev->ip_blocks[i].status.sw)
2465 if (adev->ip_blocks[i].status.hw)
2467 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2468 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2469 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2470 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2472 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2473 adev->ip_blocks[i].version->funcs->name, r);
2476 adev->ip_blocks[i].status.hw = true;
2483 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2487 for (i = 0; i < adev->num_ip_blocks; i++) {
2488 if (!adev->ip_blocks[i].status.sw)
2490 if (adev->ip_blocks[i].status.hw)
2492 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2494 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2495 adev->ip_blocks[i].version->funcs->name, r);
2498 adev->ip_blocks[i].status.hw = true;
2504 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2508 uint32_t smu_version;
2510 if (adev->asic_type >= CHIP_VEGA10) {
2511 for (i = 0; i < adev->num_ip_blocks; i++) {
2512 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2515 if (!adev->ip_blocks[i].status.sw)
2518 /* no need to do the fw loading again if already done*/
2519 if (adev->ip_blocks[i].status.hw == true)
2522 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2523 r = adev->ip_blocks[i].version->funcs->resume(adev);
2525 DRM_ERROR("resume of IP block <%s> failed %d\n",
2526 adev->ip_blocks[i].version->funcs->name, r);
2530 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2532 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2533 adev->ip_blocks[i].version->funcs->name, r);
2538 adev->ip_blocks[i].status.hw = true;
2543 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2544 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2549 static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2554 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2555 struct amdgpu_ring *ring = adev->rings[i];
2557 /* No need to setup the GPU scheduler for rings that don't need it */
2558 if (!ring || ring->no_scheduler)
2561 switch (ring->funcs->type) {
2562 case AMDGPU_RING_TYPE_GFX:
2563 timeout = adev->gfx_timeout;
2565 case AMDGPU_RING_TYPE_COMPUTE:
2566 timeout = adev->compute_timeout;
2568 case AMDGPU_RING_TYPE_SDMA:
2569 timeout = adev->sdma_timeout;
2572 timeout = adev->video_timeout;
2576 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
2577 DRM_SCHED_PRIORITY_COUNT,
2578 ring->num_hw_submission, 0,
2579 timeout, adev->reset_domain->wq,
2580 ring->sched_score, ring->name,
2583 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2587 r = amdgpu_uvd_entity_init(adev, ring);
2589 DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n",
2593 r = amdgpu_vce_entity_init(adev, ring);
2595 DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n",
2601 amdgpu_xcp_update_partition_sched_list(adev);
2608 * amdgpu_device_ip_init - run init for hardware IPs
2610 * @adev: amdgpu_device pointer
2612 * Main initialization pass for hardware IPs. The list of all the hardware
2613 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2614 * are run. sw_init initializes the software state associated with each IP
2615 * and hw_init initializes the hardware associated with each IP.
2616 * Returns 0 on success, negative error code on failure.
2618 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2622 r = amdgpu_ras_init(adev);
2626 for (i = 0; i < adev->num_ip_blocks; i++) {
2627 if (!adev->ip_blocks[i].status.valid)
2629 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2631 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2632 adev->ip_blocks[i].version->funcs->name, r);
2635 adev->ip_blocks[i].status.sw = true;
2637 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2638 /* need to do common hw init early so everything is set up for gmc */
2639 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2641 DRM_ERROR("hw_init %d failed %d\n", i, r);
2644 adev->ip_blocks[i].status.hw = true;
2645 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2646 /* need to do gmc hw init early so we can allocate gpu mem */
2647 /* Try to reserve bad pages early */
2648 if (amdgpu_sriov_vf(adev))
2649 amdgpu_virt_exchange_data(adev);
2651 r = amdgpu_device_mem_scratch_init(adev);
2653 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2656 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2658 DRM_ERROR("hw_init %d failed %d\n", i, r);
2661 r = amdgpu_device_wb_init(adev);
2663 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2666 adev->ip_blocks[i].status.hw = true;
2668 /* right after GMC hw init, we create CSA */
2669 if (adev->gfx.mcbp) {
2670 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2671 AMDGPU_GEM_DOMAIN_VRAM |
2672 AMDGPU_GEM_DOMAIN_GTT,
2675 DRM_ERROR("allocate CSA failed %d\n", r);
2682 if (amdgpu_sriov_vf(adev))
2683 amdgpu_virt_init_data_exchange(adev);
2685 r = amdgpu_ib_pool_init(adev);
2687 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2688 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2692 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2696 r = amdgpu_device_ip_hw_init_phase1(adev);
2700 r = amdgpu_device_fw_loading(adev);
2704 r = amdgpu_device_ip_hw_init_phase2(adev);
2709 * retired pages will be loaded from eeprom and reserved here,
2710 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2711 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2712 * for I2C communication which only true at this point.
2714 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2715 * failure from bad gpu situation and stop amdgpu init process
2716 * accordingly. For other failed cases, it will still release all
2717 * the resource and print error message, rather than returning one
2718 * negative value to upper level.
2720 * Note: theoretically, this should be called before all vram allocations
2721 * to protect retired page from abusing
2723 r = amdgpu_ras_recovery_init(adev);
2728 * In case of XGMI grab extra reference for reset domain for this device
2730 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2731 if (amdgpu_xgmi_add_device(adev) == 0) {
2732 if (!amdgpu_sriov_vf(adev)) {
2733 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2735 if (WARN_ON(!hive)) {
2740 if (!hive->reset_domain ||
2741 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2743 amdgpu_put_xgmi_hive(hive);
2747 /* Drop the early temporary reset domain we created for device */
2748 amdgpu_reset_put_reset_domain(adev->reset_domain);
2749 adev->reset_domain = hive->reset_domain;
2750 amdgpu_put_xgmi_hive(hive);
2755 r = amdgpu_device_init_schedulers(adev);
2759 if (adev->mman.buffer_funcs_ring->sched.ready)
2760 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2762 /* Don't init kfd if whole hive need to be reset during init */
2763 if (!adev->gmc.xgmi.pending_reset) {
2764 kgd2kfd_init_zone_device(adev);
2765 amdgpu_amdkfd_device_init(adev);
2768 amdgpu_fru_get_product_info(adev);
2776 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2778 * @adev: amdgpu_device pointer
2780 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2781 * this function before a GPU reset. If the value is retained after a
2782 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2784 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2786 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2790 * amdgpu_device_check_vram_lost - check if vram is valid
2792 * @adev: amdgpu_device pointer
2794 * Checks the reset magic value written to the gart pointer in VRAM.
2795 * The driver calls this after a GPU reset to see if the contents of
2796 * VRAM is lost or now.
2797 * returns true if vram is lost, false if not.
2799 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2801 if (memcmp(adev->gart.ptr, adev->reset_magic,
2802 AMDGPU_RESET_MAGIC_NUM))
2805 if (!amdgpu_in_reset(adev))
2809 * For all ASICs with baco/mode1 reset, the VRAM is
2810 * always assumed to be lost.
2812 switch (amdgpu_asic_reset_method(adev)) {
2813 case AMD_RESET_METHOD_BACO:
2814 case AMD_RESET_METHOD_MODE1:
2822 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2824 * @adev: amdgpu_device pointer
2825 * @state: clockgating state (gate or ungate)
2827 * The list of all the hardware IPs that make up the asic is walked and the
2828 * set_clockgating_state callbacks are run.
2829 * Late initialization pass enabling clockgating for hardware IPs.
2830 * Fini or suspend, pass disabling clockgating for hardware IPs.
2831 * Returns 0 on success, negative error code on failure.
2834 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2835 enum amd_clockgating_state state)
2839 if (amdgpu_emu_mode == 1)
2842 for (j = 0; j < adev->num_ip_blocks; j++) {
2843 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2844 if (!adev->ip_blocks[i].status.late_initialized)
2846 /* skip CG for GFX, SDMA on S0ix */
2847 if (adev->in_s0ix &&
2848 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2849 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2851 /* skip CG for VCE/UVD, it's handled specially */
2852 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2853 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2854 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2855 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2856 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2857 /* enable clockgating to save power */
2858 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2861 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2862 adev->ip_blocks[i].version->funcs->name, r);
2871 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2872 enum amd_powergating_state state)
2876 if (amdgpu_emu_mode == 1)
2879 for (j = 0; j < adev->num_ip_blocks; j++) {
2880 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2881 if (!adev->ip_blocks[i].status.late_initialized)
2883 /* skip PG for GFX, SDMA on S0ix */
2884 if (adev->in_s0ix &&
2885 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2886 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2888 /* skip CG for VCE/UVD, it's handled specially */
2889 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2890 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2891 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2892 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2893 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2894 /* enable powergating to save power */
2895 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2898 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2899 adev->ip_blocks[i].version->funcs->name, r);
2907 static int amdgpu_device_enable_mgpu_fan_boost(void)
2909 struct amdgpu_gpu_instance *gpu_ins;
2910 struct amdgpu_device *adev;
2913 mutex_lock(&mgpu_info.mutex);
2916 * MGPU fan boost feature should be enabled
2917 * only when there are two or more dGPUs in
2920 if (mgpu_info.num_dgpu < 2)
2923 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2924 gpu_ins = &(mgpu_info.gpu_ins[i]);
2925 adev = gpu_ins->adev;
2926 if (!(adev->flags & AMD_IS_APU) &&
2927 !gpu_ins->mgpu_fan_enabled) {
2928 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2932 gpu_ins->mgpu_fan_enabled = 1;
2937 mutex_unlock(&mgpu_info.mutex);
2943 * amdgpu_device_ip_late_init - run late init for hardware IPs
2945 * @adev: amdgpu_device pointer
2947 * Late initialization pass for hardware IPs. The list of all the hardware
2948 * IPs that make up the asic is walked and the late_init callbacks are run.
2949 * late_init covers any special initialization that an IP requires
2950 * after all of the have been initialized or something that needs to happen
2951 * late in the init process.
2952 * Returns 0 on success, negative error code on failure.
2954 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2956 struct amdgpu_gpu_instance *gpu_instance;
2959 for (i = 0; i < adev->num_ip_blocks; i++) {
2960 if (!adev->ip_blocks[i].status.hw)
2962 if (adev->ip_blocks[i].version->funcs->late_init) {
2963 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2965 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2966 adev->ip_blocks[i].version->funcs->name, r);
2970 adev->ip_blocks[i].status.late_initialized = true;
2973 r = amdgpu_ras_late_init(adev);
2975 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
2979 amdgpu_ras_set_error_query_ready(adev, true);
2981 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2982 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2984 amdgpu_device_fill_reset_magic(adev);
2986 r = amdgpu_device_enable_mgpu_fan_boost();
2988 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2990 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
2991 if (amdgpu_passthrough(adev) &&
2992 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
2993 adev->asic_type == CHIP_ALDEBARAN))
2994 amdgpu_dpm_handle_passthrough_sbr(adev, true);
2996 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2997 mutex_lock(&mgpu_info.mutex);
3000 * Reset device p-state to low as this was booted with high.
3002 * This should be performed only after all devices from the same
3003 * hive get initialized.
3005 * However, it's unknown how many device in the hive in advance.
3006 * As this is counted one by one during devices initializations.
3008 * So, we wait for all XGMI interlinked devices initialized.
3009 * This may bring some delays as those devices may come from
3010 * different hives. But that should be OK.
3012 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
3013 for (i = 0; i < mgpu_info.num_gpu; i++) {
3014 gpu_instance = &(mgpu_info.gpu_ins[i]);
3015 if (gpu_instance->adev->flags & AMD_IS_APU)
3018 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
3019 AMDGPU_XGMI_PSTATE_MIN);
3021 DRM_ERROR("pstate setting failed (%d).\n", r);
3027 mutex_unlock(&mgpu_info.mutex);
3034 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
3036 * @adev: amdgpu_device pointer
3038 * For ASICs need to disable SMC first
3040 static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
3044 if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0))
3047 for (i = 0; i < adev->num_ip_blocks; i++) {
3048 if (!adev->ip_blocks[i].status.hw)
3050 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3051 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
3052 /* XXX handle errors */
3054 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3055 adev->ip_blocks[i].version->funcs->name, r);
3057 adev->ip_blocks[i].status.hw = false;
3063 static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
3067 for (i = 0; i < adev->num_ip_blocks; i++) {
3068 if (!adev->ip_blocks[i].version->funcs->early_fini)
3071 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
3073 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
3074 adev->ip_blocks[i].version->funcs->name, r);
3078 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3079 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3081 amdgpu_amdkfd_suspend(adev, false);
3083 /* Workaroud for ASICs need to disable SMC first */
3084 amdgpu_device_smu_fini_early(adev);
3086 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3087 if (!adev->ip_blocks[i].status.hw)
3090 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
3091 /* XXX handle errors */
3093 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3094 adev->ip_blocks[i].version->funcs->name, r);
3097 adev->ip_blocks[i].status.hw = false;
3100 if (amdgpu_sriov_vf(adev)) {
3101 if (amdgpu_virt_release_full_gpu(adev, false))
3102 DRM_ERROR("failed to release exclusive mode on fini\n");
3109 * amdgpu_device_ip_fini - run fini for hardware IPs
3111 * @adev: amdgpu_device pointer
3113 * Main teardown pass for hardware IPs. The list of all the hardware
3114 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
3115 * are run. hw_fini tears down the hardware associated with each IP
3116 * and sw_fini tears down any software state associated with each IP.
3117 * Returns 0 on success, negative error code on failure.
3119 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
3123 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
3124 amdgpu_virt_release_ras_err_handler_data(adev);
3126 if (adev->gmc.xgmi.num_physical_nodes > 1)
3127 amdgpu_xgmi_remove_device(adev);
3129 amdgpu_amdkfd_device_fini_sw(adev);
3131 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3132 if (!adev->ip_blocks[i].status.sw)
3135 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
3136 amdgpu_ucode_free_bo(adev);
3137 amdgpu_free_static_csa(&adev->virt.csa_obj);
3138 amdgpu_device_wb_fini(adev);
3139 amdgpu_device_mem_scratch_fini(adev);
3140 amdgpu_ib_pool_fini(adev);
3143 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
3144 /* XXX handle errors */
3146 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
3147 adev->ip_blocks[i].version->funcs->name, r);
3149 adev->ip_blocks[i].status.sw = false;
3150 adev->ip_blocks[i].status.valid = false;
3153 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3154 if (!adev->ip_blocks[i].status.late_initialized)
3156 if (adev->ip_blocks[i].version->funcs->late_fini)
3157 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
3158 adev->ip_blocks[i].status.late_initialized = false;
3161 amdgpu_ras_fini(adev);
3167 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
3169 * @work: work_struct.
3171 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
3173 struct amdgpu_device *adev =
3174 container_of(work, struct amdgpu_device, delayed_init_work.work);
3177 r = amdgpu_ib_ring_tests(adev);
3179 DRM_ERROR("ib ring test failed (%d).\n", r);
3182 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
3184 struct amdgpu_device *adev =
3185 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
3187 WARN_ON_ONCE(adev->gfx.gfx_off_state);
3188 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
3190 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
3191 adev->gfx.gfx_off_state = true;
3195 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
3197 * @adev: amdgpu_device pointer
3199 * Main suspend function for hardware IPs. The list of all the hardware
3200 * IPs that make up the asic is walked, clockgating is disabled and the
3201 * suspend callbacks are run. suspend puts the hardware and software state
3202 * in each IP into a state suitable for suspend.
3203 * Returns 0 on success, negative error code on failure.
3205 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
3209 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3210 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3213 * Per PMFW team's suggestion, driver needs to handle gfxoff
3214 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
3215 * scenario. Add the missing df cstate disablement here.
3217 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
3218 dev_warn(adev->dev, "Failed to disallow df cstate");
3220 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3221 if (!adev->ip_blocks[i].status.valid)
3224 /* displays are handled separately */
3225 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
3228 /* XXX handle errors */
3229 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3230 /* XXX handle errors */
3232 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3233 adev->ip_blocks[i].version->funcs->name, r);
3237 adev->ip_blocks[i].status.hw = false;
3244 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
3246 * @adev: amdgpu_device pointer
3248 * Main suspend function for hardware IPs. The list of all the hardware
3249 * IPs that make up the asic is walked, clockgating is disabled and the
3250 * suspend callbacks are run. suspend puts the hardware and software state
3251 * in each IP into a state suitable for suspend.
3252 * Returns 0 on success, negative error code on failure.
3254 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
3259 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
3261 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3262 if (!adev->ip_blocks[i].status.valid)
3264 /* displays are handled in phase1 */
3265 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3267 /* PSP lost connection when err_event_athub occurs */
3268 if (amdgpu_ras_intr_triggered() &&
3269 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3270 adev->ip_blocks[i].status.hw = false;
3274 /* skip unnecessary suspend if we do not initialize them yet */
3275 if (adev->gmc.xgmi.pending_reset &&
3276 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3277 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
3278 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3279 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
3280 adev->ip_blocks[i].status.hw = false;
3284 /* skip suspend of gfx/mes and psp for S0ix
3285 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3286 * like at runtime. PSP is also part of the always on hardware
3287 * so no need to suspend it.
3289 if (adev->in_s0ix &&
3290 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3291 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3292 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3295 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
3296 if (adev->in_s0ix &&
3297 (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >=
3298 IP_VERSION(5, 0, 0)) &&
3299 (adev->ip_blocks[i].version->type ==
3300 AMD_IP_BLOCK_TYPE_SDMA))
3303 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
3304 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
3305 * from this location and RLC Autoload automatically also gets loaded
3306 * from here based on PMFW -> PSP message during re-init sequence.
3307 * Therefore, the psp suspend & resume should be skipped to avoid destroy
3308 * the TMR and reload FWs again for IMU enabled APU ASICs.
3310 if (amdgpu_in_reset(adev) &&
3311 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3312 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3315 /* XXX handle errors */
3316 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3317 /* XXX handle errors */
3319 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3320 adev->ip_blocks[i].version->funcs->name, r);
3322 adev->ip_blocks[i].status.hw = false;
3323 /* handle putting the SMC in the appropriate state */
3324 if (!amdgpu_sriov_vf(adev)) {
3325 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3326 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3328 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3329 adev->mp1_state, r);
3340 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3342 * @adev: amdgpu_device pointer
3344 * Main suspend function for hardware IPs. The list of all the hardware
3345 * IPs that make up the asic is walked, clockgating is disabled and the
3346 * suspend callbacks are run. suspend puts the hardware and software state
3347 * in each IP into a state suitable for suspend.
3348 * Returns 0 on success, negative error code on failure.
3350 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3354 if (amdgpu_sriov_vf(adev)) {
3355 amdgpu_virt_fini_data_exchange(adev);
3356 amdgpu_virt_request_full_gpu(adev, false);
3359 amdgpu_ttm_set_buffer_funcs_status(adev, false);
3361 r = amdgpu_device_ip_suspend_phase1(adev);
3364 r = amdgpu_device_ip_suspend_phase2(adev);
3366 if (amdgpu_sriov_vf(adev))
3367 amdgpu_virt_release_full_gpu(adev, false);
3372 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3376 static enum amd_ip_block_type ip_order[] = {
3377 AMD_IP_BLOCK_TYPE_COMMON,
3378 AMD_IP_BLOCK_TYPE_GMC,
3379 AMD_IP_BLOCK_TYPE_PSP,
3380 AMD_IP_BLOCK_TYPE_IH,
3383 for (i = 0; i < adev->num_ip_blocks; i++) {
3385 struct amdgpu_ip_block *block;
3387 block = &adev->ip_blocks[i];
3388 block->status.hw = false;
3390 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3392 if (block->version->type != ip_order[j] ||
3393 !block->status.valid)
3396 r = block->version->funcs->hw_init(adev);
3397 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3400 block->status.hw = true;
3407 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3411 static enum amd_ip_block_type ip_order[] = {
3412 AMD_IP_BLOCK_TYPE_SMC,
3413 AMD_IP_BLOCK_TYPE_DCE,
3414 AMD_IP_BLOCK_TYPE_GFX,
3415 AMD_IP_BLOCK_TYPE_SDMA,
3416 AMD_IP_BLOCK_TYPE_MES,
3417 AMD_IP_BLOCK_TYPE_UVD,
3418 AMD_IP_BLOCK_TYPE_VCE,
3419 AMD_IP_BLOCK_TYPE_VCN,
3420 AMD_IP_BLOCK_TYPE_JPEG
3423 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3425 struct amdgpu_ip_block *block;
3427 for (j = 0; j < adev->num_ip_blocks; j++) {
3428 block = &adev->ip_blocks[j];
3430 if (block->version->type != ip_order[i] ||
3431 !block->status.valid ||
3435 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3436 r = block->version->funcs->resume(adev);
3438 r = block->version->funcs->hw_init(adev);
3440 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3443 block->status.hw = true;
3451 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3453 * @adev: amdgpu_device pointer
3455 * First resume function for hardware IPs. The list of all the hardware
3456 * IPs that make up the asic is walked and the resume callbacks are run for
3457 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3458 * after a suspend and updates the software state as necessary. This
3459 * function is also used for restoring the GPU after a GPU reset.
3460 * Returns 0 on success, negative error code on failure.
3462 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3466 for (i = 0; i < adev->num_ip_blocks; i++) {
3467 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3469 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3470 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3471 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3472 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3474 r = adev->ip_blocks[i].version->funcs->resume(adev);
3476 DRM_ERROR("resume of IP block <%s> failed %d\n",
3477 adev->ip_blocks[i].version->funcs->name, r);
3480 adev->ip_blocks[i].status.hw = true;
3488 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3490 * @adev: amdgpu_device pointer
3492 * First resume function for hardware IPs. The list of all the hardware
3493 * IPs that make up the asic is walked and the resume callbacks are run for
3494 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3495 * functional state after a suspend and updates the software state as
3496 * necessary. This function is also used for restoring the GPU after a GPU
3498 * Returns 0 on success, negative error code on failure.
3500 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3504 for (i = 0; i < adev->num_ip_blocks; i++) {
3505 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3507 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3508 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3509 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3510 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3512 r = adev->ip_blocks[i].version->funcs->resume(adev);
3514 DRM_ERROR("resume of IP block <%s> failed %d\n",
3515 adev->ip_blocks[i].version->funcs->name, r);
3518 adev->ip_blocks[i].status.hw = true;
3525 * amdgpu_device_ip_resume - run resume for hardware IPs
3527 * @adev: amdgpu_device pointer
3529 * Main resume function for hardware IPs. The hardware IPs
3530 * are split into two resume functions because they are
3531 * also used in recovering from a GPU reset and some additional
3532 * steps need to be take between them. In this case (S3/S4) they are
3534 * Returns 0 on success, negative error code on failure.
3536 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3540 r = amdgpu_device_ip_resume_phase1(adev);
3544 r = amdgpu_device_fw_loading(adev);
3548 r = amdgpu_device_ip_resume_phase2(adev);
3550 if (adev->mman.buffer_funcs_ring->sched.ready)
3551 amdgpu_ttm_set_buffer_funcs_status(adev, true);
3557 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3559 * @adev: amdgpu_device pointer
3561 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3563 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3565 if (amdgpu_sriov_vf(adev)) {
3566 if (adev->is_atom_fw) {
3567 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3568 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3570 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3571 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3574 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3575 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3580 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3582 * @asic_type: AMD asic type
3584 * Check if there is DC (new modesetting infrastructre) support for an asic.
3585 * returns true if DC has support, false if not.
3587 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3589 switch (asic_type) {
3590 #ifdef CONFIG_DRM_AMDGPU_SI
3594 /* chips with no display hardware */
3596 #if defined(CONFIG_DRM_AMD_DC)
3602 * We have systems in the wild with these ASICs that require
3603 * LVDS and VGA support which is not supported with DC.
3605 * Fallback to the non-DC driver here by default so as not to
3606 * cause regressions.
3608 #if defined(CONFIG_DRM_AMD_DC_SI)
3609 return amdgpu_dc > 0;
3618 * We have systems in the wild with these ASICs that require
3619 * VGA support which is not supported with DC.
3621 * Fallback to the non-DC driver here by default so as not to
3622 * cause regressions.
3624 return amdgpu_dc > 0;
3626 return amdgpu_dc != 0;
3630 DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");
3637 * amdgpu_device_has_dc_support - check if dc is supported
3639 * @adev: amdgpu_device pointer
3641 * Returns true for supported, false for not supported
3643 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3645 if (adev->enable_virtual_display ||
3646 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3649 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3652 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3654 struct amdgpu_device *adev =
3655 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3656 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3658 /* It's a bug to not have a hive within this function */
3663 * Use task barrier to synchronize all xgmi reset works across the
3664 * hive. task_barrier_enter and task_barrier_exit will block
3665 * until all the threads running the xgmi reset works reach
3666 * those points. task_barrier_full will do both blocks.
3668 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3670 task_barrier_enter(&hive->tb);
3671 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3673 if (adev->asic_reset_res)
3676 task_barrier_exit(&hive->tb);
3677 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3679 if (adev->asic_reset_res)
3682 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
3685 task_barrier_full(&hive->tb);
3686 adev->asic_reset_res = amdgpu_asic_reset(adev);
3690 if (adev->asic_reset_res)
3691 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3692 adev->asic_reset_res, adev_to_drm(adev)->unique);
3693 amdgpu_put_xgmi_hive(hive);
3696 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3698 char *input = amdgpu_lockup_timeout;
3699 char *timeout_setting = NULL;
3705 * By default timeout for non compute jobs is 10000
3706 * and 60000 for compute jobs.
3707 * In SR-IOV or passthrough mode, timeout for compute
3708 * jobs are 60000 by default.
3710 adev->gfx_timeout = msecs_to_jiffies(10000);
3711 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3712 if (amdgpu_sriov_vf(adev))
3713 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3714 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3716 adev->compute_timeout = msecs_to_jiffies(60000);
3718 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3719 while ((timeout_setting = strsep(&input, ",")) &&
3720 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3721 ret = kstrtol(timeout_setting, 0, &timeout);
3728 } else if (timeout < 0) {
3729 timeout = MAX_SCHEDULE_TIMEOUT;
3730 dev_warn(adev->dev, "lockup timeout disabled");
3731 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3733 timeout = msecs_to_jiffies(timeout);
3738 adev->gfx_timeout = timeout;
3741 adev->compute_timeout = timeout;
3744 adev->sdma_timeout = timeout;
3747 adev->video_timeout = timeout;
3754 * There is only one value specified and
3755 * it should apply to all non-compute jobs.
3758 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3759 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3760 adev->compute_timeout = adev->gfx_timeout;
3768 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3770 * @adev: amdgpu_device pointer
3772 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3774 static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3776 struct iommu_domain *domain;
3778 domain = iommu_get_domain_for_dev(adev->dev);
3779 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3780 adev->ram_is_direct_mapped = true;
3783 static const struct attribute *amdgpu_dev_attributes[] = {
3784 &dev_attr_pcie_replay_count.attr,
3788 static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
3790 if (amdgpu_mcbp == 1)
3791 adev->gfx.mcbp = true;
3792 else if (amdgpu_mcbp == 0)
3793 adev->gfx.mcbp = false;
3795 if (amdgpu_sriov_vf(adev))
3796 adev->gfx.mcbp = true;
3799 DRM_INFO("MCBP is enabled\n");
3803 * amdgpu_device_init - initialize the driver
3805 * @adev: amdgpu_device pointer
3806 * @flags: driver flags
3808 * Initializes the driver info and hw (all asics).
3809 * Returns 0 for success or an error on failure.
3810 * Called at driver startup.
3812 int amdgpu_device_init(struct amdgpu_device *adev,
3815 struct drm_device *ddev = adev_to_drm(adev);
3816 struct pci_dev *pdev = adev->pdev;
3822 adev->shutdown = false;
3823 adev->flags = flags;
3825 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3826 adev->asic_type = amdgpu_force_asic_type;
3828 adev->asic_type = flags & AMD_ASIC_MASK;
3830 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3831 if (amdgpu_emu_mode == 1)
3832 adev->usec_timeout *= 10;
3833 adev->gmc.gart_size = 512 * 1024 * 1024;
3834 adev->accel_working = false;
3835 adev->num_rings = 0;
3836 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3837 adev->mman.buffer_funcs = NULL;
3838 adev->mman.buffer_funcs_ring = NULL;
3839 adev->vm_manager.vm_pte_funcs = NULL;
3840 adev->vm_manager.vm_pte_num_scheds = 0;
3841 adev->gmc.gmc_funcs = NULL;
3842 adev->harvest_ip_mask = 0x0;
3843 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3844 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3846 adev->smc_rreg = &amdgpu_invalid_rreg;
3847 adev->smc_wreg = &amdgpu_invalid_wreg;
3848 adev->pcie_rreg = &amdgpu_invalid_rreg;
3849 adev->pcie_wreg = &amdgpu_invalid_wreg;
3850 adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext;
3851 adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext;
3852 adev->pciep_rreg = &amdgpu_invalid_rreg;
3853 adev->pciep_wreg = &amdgpu_invalid_wreg;
3854 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3855 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3856 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext;
3857 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext;
3858 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3859 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3860 adev->didt_rreg = &amdgpu_invalid_rreg;
3861 adev->didt_wreg = &amdgpu_invalid_wreg;
3862 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3863 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3864 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3865 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3867 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3868 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3869 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3871 /* mutex initialization are all done here so we
3872 * can recall function without having locking issues
3874 mutex_init(&adev->firmware.mutex);
3875 mutex_init(&adev->pm.mutex);
3876 mutex_init(&adev->gfx.gpu_clock_mutex);
3877 mutex_init(&adev->srbm_mutex);
3878 mutex_init(&adev->gfx.pipe_reserve_mutex);
3879 mutex_init(&adev->gfx.gfx_off_mutex);
3880 mutex_init(&adev->gfx.partition_mutex);
3881 mutex_init(&adev->grbm_idx_mutex);
3882 mutex_init(&adev->mn_lock);
3883 mutex_init(&adev->virt.vf_errors.lock);
3884 hash_init(adev->mn_hash);
3885 mutex_init(&adev->psp.mutex);
3886 mutex_init(&adev->notifier_lock);
3887 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3888 mutex_init(&adev->benchmark_mutex);
3890 amdgpu_device_init_apu_flags(adev);
3892 r = amdgpu_device_check_arguments(adev);
3896 spin_lock_init(&adev->mmio_idx_lock);
3897 spin_lock_init(&adev->smc_idx_lock);
3898 spin_lock_init(&adev->pcie_idx_lock);
3899 spin_lock_init(&adev->uvd_ctx_idx_lock);
3900 spin_lock_init(&adev->didt_idx_lock);
3901 spin_lock_init(&adev->gc_cac_idx_lock);
3902 spin_lock_init(&adev->se_cac_idx_lock);
3903 spin_lock_init(&adev->audio_endpt_idx_lock);
3904 spin_lock_init(&adev->mm_stats.lock);
3906 INIT_LIST_HEAD(&adev->shadow_list);
3907 mutex_init(&adev->shadow_list_lock);
3909 INIT_LIST_HEAD(&adev->reset_list);
3911 INIT_LIST_HEAD(&adev->ras_list);
3913 INIT_LIST_HEAD(&adev->pm.od_kobj_list);
3915 INIT_DELAYED_WORK(&adev->delayed_init_work,
3916 amdgpu_device_delayed_init_work_handler);
3917 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3918 amdgpu_device_delay_enable_gfx_off);
3920 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3922 adev->gfx.gfx_off_req_count = 1;
3923 adev->gfx.gfx_off_residency = 0;
3924 adev->gfx.gfx_off_entrycount = 0;
3925 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3927 atomic_set(&adev->throttling_logging_enabled, 1);
3929 * If throttling continues, logging will be performed every minute
3930 * to avoid log flooding. "-1" is subtracted since the thermal
3931 * throttling interrupt comes every second. Thus, the total logging
3932 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3933 * for throttling interrupt) = 60 seconds.
3935 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3936 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3938 /* Registers mapping */
3939 /* TODO: block userspace mapping of io register */
3940 if (adev->asic_type >= CHIP_BONAIRE) {
3941 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3942 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3944 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3945 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3948 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
3949 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
3951 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3955 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3956 DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size);
3959 * Reset domain needs to be present early, before XGMI hive discovered
3960 * (if any) and intitialized to use reset sem and in_gpu reset flag
3961 * early on during init and before calling to RREG32.
3963 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
3964 if (!adev->reset_domain)
3967 /* detect hw virtualization here */
3968 amdgpu_detect_virtualization(adev);
3970 amdgpu_device_get_pcie_info(adev);
3972 r = amdgpu_device_get_job_timeout_settings(adev);
3974 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3978 /* early init functions */
3979 r = amdgpu_device_ip_early_init(adev);
3983 amdgpu_device_set_mcbp(adev);
3985 /* Get rid of things like offb */
3986 r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
3990 /* Enable TMZ based on IP_VERSION */
3991 amdgpu_gmc_tmz_set(adev);
3993 amdgpu_gmc_noretry_set(adev);
3994 /* Need to get xgmi info early to decide the reset behavior*/
3995 if (adev->gmc.xgmi.supported) {
3996 r = adev->gfxhub.funcs->get_xgmi_info(adev);
4001 /* enable PCIE atomic ops */
4002 if (amdgpu_sriov_vf(adev)) {
4003 if (adev->virt.fw_reserve.p_pf2vf)
4004 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
4005 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
4006 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4007 /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
4008 * internal path natively support atomics, set have_atomics_support to true.
4010 } else if ((adev->flags & AMD_IS_APU) &&
4011 (amdgpu_ip_version(adev, GC_HWIP, 0) >
4012 IP_VERSION(9, 0, 0))) {
4013 adev->have_atomics_support = true;
4015 adev->have_atomics_support =
4016 !pci_enable_atomic_ops_to_root(adev->pdev,
4017 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
4018 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4021 if (!adev->have_atomics_support)
4022 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
4024 /* doorbell bar mapping and doorbell index init*/
4025 amdgpu_doorbell_init(adev);
4027 if (amdgpu_emu_mode == 1) {
4028 /* post the asic on emulation mode */
4029 emu_soc_asic_init(adev);
4030 goto fence_driver_init;
4033 amdgpu_reset_init(adev);
4035 /* detect if we are with an SRIOV vbios */
4037 amdgpu_device_detect_sriov_bios(adev);
4039 /* check if we need to reset the asic
4040 * E.g., driver was not cleanly unloaded previously, etc.
4042 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
4043 if (adev->gmc.xgmi.num_physical_nodes) {
4044 dev_info(adev->dev, "Pending hive reset.\n");
4045 adev->gmc.xgmi.pending_reset = true;
4046 /* Only need to init necessary block for SMU to handle the reset */
4047 for (i = 0; i < adev->num_ip_blocks; i++) {
4048 if (!adev->ip_blocks[i].status.valid)
4050 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
4051 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
4052 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
4053 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
4054 DRM_DEBUG("IP %s disabled for hw_init.\n",
4055 adev->ip_blocks[i].version->funcs->name);
4056 adev->ip_blocks[i].status.hw = true;
4060 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
4061 case IP_VERSION(13, 0, 0):
4062 case IP_VERSION(13, 0, 7):
4063 case IP_VERSION(13, 0, 10):
4064 r = psp_gpu_reset(adev);
4067 tmp = amdgpu_reset_method;
4068 /* It should do a default reset when loading or reloading the driver,
4069 * regardless of the module parameter reset_method.
4071 amdgpu_reset_method = AMD_RESET_METHOD_NONE;
4072 r = amdgpu_asic_reset(adev);
4073 amdgpu_reset_method = tmp;
4078 dev_err(adev->dev, "asic reset on init failed\n");
4084 /* Post card if necessary */
4085 if (amdgpu_device_need_post(adev)) {
4087 dev_err(adev->dev, "no vBIOS found\n");
4091 DRM_INFO("GPU posting now...\n");
4092 r = amdgpu_device_asic_init(adev);
4094 dev_err(adev->dev, "gpu post error!\n");
4100 if (adev->is_atom_fw) {
4101 /* Initialize clocks */
4102 r = amdgpu_atomfirmware_get_clock_info(adev);
4104 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
4105 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4109 /* Initialize clocks */
4110 r = amdgpu_atombios_get_clock_info(adev);
4112 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
4113 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4116 /* init i2c buses */
4117 if (!amdgpu_device_has_dc_support(adev))
4118 amdgpu_atombios_i2c_init(adev);
4124 r = amdgpu_fence_driver_sw_init(adev);
4126 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
4127 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
4131 /* init the mode config */
4132 drm_mode_config_init(adev_to_drm(adev));
4134 r = amdgpu_device_ip_init(adev);
4136 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
4137 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
4138 goto release_ras_con;
4141 amdgpu_fence_driver_hw_init(adev);
4144 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
4145 adev->gfx.config.max_shader_engines,
4146 adev->gfx.config.max_sh_per_se,
4147 adev->gfx.config.max_cu_per_sh,
4148 adev->gfx.cu_info.number);
4150 adev->accel_working = true;
4152 amdgpu_vm_check_compute_bug(adev);
4154 /* Initialize the buffer migration limit. */
4155 if (amdgpu_moverate >= 0)
4156 max_MBps = amdgpu_moverate;
4158 max_MBps = 8; /* Allow 8 MB/s. */
4159 /* Get a log2 for easy divisions. */
4160 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
4163 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
4164 * Otherwise the mgpu fan boost feature will be skipped due to the
4165 * gpu instance is counted less.
4167 amdgpu_register_gpu_instance(adev);
4169 /* enable clockgating, etc. after ib tests, etc. since some blocks require
4170 * explicit gating rather than handling it automatically.
4172 if (!adev->gmc.xgmi.pending_reset) {
4173 r = amdgpu_device_ip_late_init(adev);
4175 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
4176 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
4177 goto release_ras_con;
4180 amdgpu_ras_resume(adev);
4181 queue_delayed_work(system_wq, &adev->delayed_init_work,
4182 msecs_to_jiffies(AMDGPU_RESUME_MS));
4185 if (amdgpu_sriov_vf(adev)) {
4186 amdgpu_virt_release_full_gpu(adev, true);
4187 flush_delayed_work(&adev->delayed_init_work);
4191 * Place those sysfs registering after `late_init`. As some of those
4192 * operations performed in `late_init` might affect the sysfs
4193 * interfaces creating.
4195 r = amdgpu_atombios_sysfs_init(adev);
4197 drm_err(&adev->ddev,
4198 "registering atombios sysfs failed (%d).\n", r);
4200 r = amdgpu_pm_sysfs_init(adev);
4202 DRM_ERROR("registering pm sysfs failed (%d).\n", r);
4204 r = amdgpu_ucode_sysfs_init(adev);
4206 adev->ucode_sysfs_en = false;
4207 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
4209 adev->ucode_sysfs_en = true;
4211 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
4213 dev_err(adev->dev, "Could not create amdgpu device attr\n");
4215 r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group);
4218 "Could not create amdgpu board attributes\n");
4220 amdgpu_fru_sysfs_init(adev);
4222 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4223 r = amdgpu_pmu_init(adev);
4225 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
4227 /* Have stored pci confspace at hand for restore in sudden PCI error */
4228 if (amdgpu_device_cache_pci_state(adev->pdev))
4229 pci_restore_state(pdev);
4231 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
4232 /* this will fail for cards that aren't VGA class devices, just
4235 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4236 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
4238 px = amdgpu_device_supports_px(ddev);
4240 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4241 apple_gmux_detect(NULL, NULL)))
4242 vga_switcheroo_register_client(adev->pdev,
4243 &amdgpu_switcheroo_ops, px);
4246 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
4248 if (adev->gmc.xgmi.pending_reset)
4249 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
4250 msecs_to_jiffies(AMDGPU_RESUME_MS));
4252 amdgpu_device_check_iommu_direct_map(adev);
4257 if (amdgpu_sriov_vf(adev))
4258 amdgpu_virt_release_full_gpu(adev, true);
4260 /* failed in exclusive mode due to timeout */
4261 if (amdgpu_sriov_vf(adev) &&
4262 !amdgpu_sriov_runtime(adev) &&
4263 amdgpu_virt_mmio_blocked(adev) &&
4264 !amdgpu_virt_wait_reset(adev)) {
4265 dev_err(adev->dev, "VF exclusive mode timeout\n");
4266 /* Don't send request since VF is inactive. */
4267 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
4268 adev->virt.ops = NULL;
4271 amdgpu_release_ras_context(adev);
4274 amdgpu_vf_error_trans_all(adev);
4279 static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
4282 /* Clear all CPU mappings pointing to this device */
4283 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
4285 /* Unmap all mapped bars - Doorbell, registers and VRAM */
4286 amdgpu_doorbell_fini(adev);
4288 iounmap(adev->rmmio);
4290 if (adev->mman.aper_base_kaddr)
4291 iounmap(adev->mman.aper_base_kaddr);
4292 adev->mman.aper_base_kaddr = NULL;
4294 /* Memory manager related */
4295 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
4296 arch_phys_wc_del(adev->gmc.vram_mtrr);
4297 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
4302 * amdgpu_device_fini_hw - tear down the driver
4304 * @adev: amdgpu_device pointer
4306 * Tear down the driver info (all asics).
4307 * Called at driver shutdown.
4309 void amdgpu_device_fini_hw(struct amdgpu_device *adev)
4311 dev_info(adev->dev, "amdgpu: finishing device.\n");
4312 flush_delayed_work(&adev->delayed_init_work);
4313 adev->shutdown = true;
4315 /* make sure IB test finished before entering exclusive mode
4316 * to avoid preemption on IB test
4318 if (amdgpu_sriov_vf(adev)) {
4319 amdgpu_virt_request_full_gpu(adev, false);
4320 amdgpu_virt_fini_data_exchange(adev);
4323 /* disable all interrupts */
4324 amdgpu_irq_disable_all(adev);
4325 if (adev->mode_info.mode_config_initialized) {
4326 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
4327 drm_helper_force_disable_all(adev_to_drm(adev));
4329 drm_atomic_helper_shutdown(adev_to_drm(adev));
4331 amdgpu_fence_driver_hw_fini(adev);
4333 if (adev->mman.initialized)
4334 drain_workqueue(adev->mman.bdev.wq);
4336 if (adev->pm.sysfs_initialized)
4337 amdgpu_pm_sysfs_fini(adev);
4338 if (adev->ucode_sysfs_en)
4339 amdgpu_ucode_sysfs_fini(adev);
4340 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4341 amdgpu_fru_sysfs_fini(adev);
4343 /* disable ras feature must before hw fini */
4344 amdgpu_ras_pre_fini(adev);
4346 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4348 amdgpu_device_ip_fini_early(adev);
4350 amdgpu_irq_fini_hw(adev);
4352 if (adev->mman.initialized)
4353 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4355 amdgpu_gart_dummy_page_fini(adev);
4357 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4358 amdgpu_device_unmap_mmio(adev);
4362 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4367 amdgpu_fence_driver_sw_fini(adev);
4368 amdgpu_device_ip_fini(adev);
4369 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4370 adev->accel_working = false;
4371 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4373 amdgpu_reset_fini(adev);
4375 /* free i2c buses */
4376 if (!amdgpu_device_has_dc_support(adev))
4377 amdgpu_i2c_fini(adev);
4379 if (amdgpu_emu_mode != 1)
4380 amdgpu_atombios_fini(adev);
4385 kfree(adev->fru_info);
4386 adev->fru_info = NULL;
4388 px = amdgpu_device_supports_px(adev_to_drm(adev));
4390 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4391 apple_gmux_detect(NULL, NULL)))
4392 vga_switcheroo_unregister_client(adev->pdev);
4395 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4397 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4398 vga_client_unregister(adev->pdev);
4400 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4402 iounmap(adev->rmmio);
4404 amdgpu_doorbell_fini(adev);
4408 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4409 amdgpu_pmu_fini(adev);
4410 if (adev->mman.discovery_bin)
4411 amdgpu_discovery_fini(adev);
4413 amdgpu_reset_put_reset_domain(adev->reset_domain);
4414 adev->reset_domain = NULL;
4416 kfree(adev->pci_state);
4421 * amdgpu_device_evict_resources - evict device resources
4422 * @adev: amdgpu device object
4424 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4425 * of the vram memory type. Mainly used for evicting device resources
4429 static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4433 /* No need to evict vram on APUs for suspend to ram or s2idle */
4434 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4437 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4439 DRM_WARN("evicting device resources failed\n");
4447 * amdgpu_device_prepare - prepare for device suspend
4449 * @dev: drm dev pointer
4451 * Prepare to put the hw in the suspend state (all asics).
4452 * Returns 0 for success or an error on failure.
4453 * Called at driver suspend.
4455 int amdgpu_device_prepare(struct drm_device *dev)
4457 struct amdgpu_device *adev = drm_to_adev(dev);
4460 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4463 /* Evict the majority of BOs before starting suspend sequence */
4464 r = amdgpu_device_evict_resources(adev);
4468 for (i = 0; i < adev->num_ip_blocks; i++) {
4469 if (!adev->ip_blocks[i].status.valid)
4471 if (!adev->ip_blocks[i].version->funcs->prepare_suspend)
4473 r = adev->ip_blocks[i].version->funcs->prepare_suspend((void *)adev);
4482 * amdgpu_device_suspend - initiate device suspend
4484 * @dev: drm dev pointer
4485 * @fbcon : notify the fbdev of suspend
4487 * Puts the hw in the suspend state (all asics).
4488 * Returns 0 for success or an error on failure.
4489 * Called at driver suspend.
4491 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4493 struct amdgpu_device *adev = drm_to_adev(dev);
4496 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4499 adev->in_suspend = true;
4501 if (amdgpu_sriov_vf(adev)) {
4502 amdgpu_virt_fini_data_exchange(adev);
4503 r = amdgpu_virt_request_full_gpu(adev, false);
4508 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4509 DRM_WARN("smart shift update failed\n");
4512 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4514 cancel_delayed_work_sync(&adev->delayed_init_work);
4515 flush_delayed_work(&adev->gfx.gfx_off_delay_work);
4517 amdgpu_ras_suspend(adev);
4519 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4521 amdgpu_device_ip_suspend_phase1(adev);
4524 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4526 r = amdgpu_device_evict_resources(adev);
4530 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4532 amdgpu_fence_driver_hw_fini(adev);
4534 amdgpu_device_ip_suspend_phase2(adev);
4536 if (amdgpu_sriov_vf(adev))
4537 amdgpu_virt_release_full_gpu(adev, false);
4539 r = amdgpu_dpm_notify_rlc_state(adev, false);
4547 * amdgpu_device_resume - initiate device resume
4549 * @dev: drm dev pointer
4550 * @fbcon : notify the fbdev of resume
4552 * Bring the hw back to operating state (all asics).
4553 * Returns 0 for success or an error on failure.
4554 * Called at driver resume.
4556 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4558 struct amdgpu_device *adev = drm_to_adev(dev);
4561 if (amdgpu_sriov_vf(adev)) {
4562 r = amdgpu_virt_request_full_gpu(adev, true);
4567 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4571 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4574 if (amdgpu_device_need_post(adev)) {
4575 r = amdgpu_device_asic_init(adev);
4577 dev_err(adev->dev, "amdgpu asic init failed\n");
4580 r = amdgpu_device_ip_resume(adev);
4583 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4586 amdgpu_fence_driver_hw_init(adev);
4588 if (!adev->in_s0ix) {
4589 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4594 r = amdgpu_device_ip_late_init(adev);
4598 queue_delayed_work(system_wq, &adev->delayed_init_work,
4599 msecs_to_jiffies(AMDGPU_RESUME_MS));
4601 if (amdgpu_sriov_vf(adev)) {
4602 amdgpu_virt_init_data_exchange(adev);
4603 amdgpu_virt_release_full_gpu(adev, true);
4609 /* Make sure IB tests flushed */
4610 flush_delayed_work(&adev->delayed_init_work);
4613 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4615 amdgpu_ras_resume(adev);
4617 if (adev->mode_info.num_crtc) {
4619 * Most of the connector probing functions try to acquire runtime pm
4620 * refs to ensure that the GPU is powered on when connector polling is
4621 * performed. Since we're calling this from a runtime PM callback,
4622 * trying to acquire rpm refs will cause us to deadlock.
4624 * Since we're guaranteed to be holding the rpm lock, it's safe to
4625 * temporarily disable the rpm helpers so this doesn't deadlock us.
4628 dev->dev->power.disable_depth++;
4630 if (!adev->dc_enabled)
4631 drm_helper_hpd_irq_event(dev);
4633 drm_kms_helper_hotplug_event(dev);
4635 dev->dev->power.disable_depth--;
4638 adev->in_suspend = false;
4640 if (adev->enable_mes)
4641 amdgpu_mes_self_test(adev);
4643 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4644 DRM_WARN("smart shift update failed\n");
4650 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4652 * @adev: amdgpu_device pointer
4654 * The list of all the hardware IPs that make up the asic is walked and
4655 * the check_soft_reset callbacks are run. check_soft_reset determines
4656 * if the asic is still hung or not.
4657 * Returns true if any of the IPs are still in a hung state, false if not.
4659 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4662 bool asic_hang = false;
4664 if (amdgpu_sriov_vf(adev))
4667 if (amdgpu_asic_need_full_reset(adev))
4670 for (i = 0; i < adev->num_ip_blocks; i++) {
4671 if (!adev->ip_blocks[i].status.valid)
4673 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4674 adev->ip_blocks[i].status.hang =
4675 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4676 if (adev->ip_blocks[i].status.hang) {
4677 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4685 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4687 * @adev: amdgpu_device pointer
4689 * The list of all the hardware IPs that make up the asic is walked and the
4690 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4691 * handles any IP specific hardware or software state changes that are
4692 * necessary for a soft reset to succeed.
4693 * Returns 0 on success, negative error code on failure.
4695 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4699 for (i = 0; i < adev->num_ip_blocks; i++) {
4700 if (!adev->ip_blocks[i].status.valid)
4702 if (adev->ip_blocks[i].status.hang &&
4703 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4704 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4714 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4716 * @adev: amdgpu_device pointer
4718 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4719 * reset is necessary to recover.
4720 * Returns true if a full asic reset is required, false if not.
4722 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4726 if (amdgpu_asic_need_full_reset(adev))
4729 for (i = 0; i < adev->num_ip_blocks; i++) {
4730 if (!adev->ip_blocks[i].status.valid)
4732 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4733 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4734 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4735 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4736 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4737 if (adev->ip_blocks[i].status.hang) {
4738 dev_info(adev->dev, "Some block need full reset!\n");
4747 * amdgpu_device_ip_soft_reset - do a soft reset
4749 * @adev: amdgpu_device pointer
4751 * The list of all the hardware IPs that make up the asic is walked and the
4752 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4753 * IP specific hardware or software state changes that are necessary to soft
4755 * Returns 0 on success, negative error code on failure.
4757 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4761 for (i = 0; i < adev->num_ip_blocks; i++) {
4762 if (!adev->ip_blocks[i].status.valid)
4764 if (adev->ip_blocks[i].status.hang &&
4765 adev->ip_blocks[i].version->funcs->soft_reset) {
4766 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4776 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4778 * @adev: amdgpu_device pointer
4780 * The list of all the hardware IPs that make up the asic is walked and the
4781 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4782 * handles any IP specific hardware or software state changes that are
4783 * necessary after the IP has been soft reset.
4784 * Returns 0 on success, negative error code on failure.
4786 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4790 for (i = 0; i < adev->num_ip_blocks; i++) {
4791 if (!adev->ip_blocks[i].status.valid)
4793 if (adev->ip_blocks[i].status.hang &&
4794 adev->ip_blocks[i].version->funcs->post_soft_reset)
4795 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4804 * amdgpu_device_recover_vram - Recover some VRAM contents
4806 * @adev: amdgpu_device pointer
4808 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4809 * restore things like GPUVM page tables after a GPU reset where
4810 * the contents of VRAM might be lost.
4813 * 0 on success, negative error code on failure.
4815 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4817 struct dma_fence *fence = NULL, *next = NULL;
4818 struct amdgpu_bo *shadow;
4819 struct amdgpu_bo_vm *vmbo;
4822 if (amdgpu_sriov_runtime(adev))
4823 tmo = msecs_to_jiffies(8000);
4825 tmo = msecs_to_jiffies(100);
4827 dev_info(adev->dev, "recover vram bo from shadow start\n");
4828 mutex_lock(&adev->shadow_list_lock);
4829 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4830 /* If vm is compute context or adev is APU, shadow will be NULL */
4833 shadow = vmbo->shadow;
4835 /* No need to recover an evicted BO */
4836 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4837 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4838 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4841 r = amdgpu_bo_restore_shadow(shadow, &next);
4846 tmo = dma_fence_wait_timeout(fence, false, tmo);
4847 dma_fence_put(fence);
4852 } else if (tmo < 0) {
4860 mutex_unlock(&adev->shadow_list_lock);
4863 tmo = dma_fence_wait_timeout(fence, false, tmo);
4864 dma_fence_put(fence);
4866 if (r < 0 || tmo <= 0) {
4867 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4871 dev_info(adev->dev, "recover vram bo from shadow done\n");
4877 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4879 * @adev: amdgpu_device pointer
4880 * @from_hypervisor: request from hypervisor
4882 * do VF FLR and reinitialize Asic
4883 * return 0 means succeeded otherwise failed
4885 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4886 bool from_hypervisor)
4889 struct amdgpu_hive_info *hive = NULL;
4890 int retry_limit = 0;
4893 amdgpu_amdkfd_pre_reset(adev);
4895 if (from_hypervisor)
4896 r = amdgpu_virt_request_full_gpu(adev, true);
4898 r = amdgpu_virt_reset_gpu(adev);
4901 amdgpu_irq_gpu_reset_resume_helper(adev);
4903 /* some sw clean up VF needs to do before recover */
4904 amdgpu_virt_post_reset(adev);
4906 /* Resume IP prior to SMC */
4907 r = amdgpu_device_ip_reinit_early_sriov(adev);
4911 amdgpu_virt_init_data_exchange(adev);
4913 r = amdgpu_device_fw_loading(adev);
4917 /* now we are okay to resume SMC/CP/SDMA */
4918 r = amdgpu_device_ip_reinit_late_sriov(adev);
4922 hive = amdgpu_get_xgmi_hive(adev);
4923 /* Update PSP FW topology after reset */
4924 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
4925 r = amdgpu_xgmi_update_topology(hive, adev);
4928 amdgpu_put_xgmi_hive(hive);
4931 r = amdgpu_ib_ring_tests(adev);
4933 amdgpu_amdkfd_post_reset(adev);
4937 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4938 amdgpu_inc_vram_lost(adev);
4939 r = amdgpu_device_recover_vram(adev);
4941 amdgpu_virt_release_full_gpu(adev, true);
4943 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
4944 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
4948 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
4955 * amdgpu_device_has_job_running - check if there is any job in mirror list
4957 * @adev: amdgpu_device pointer
4959 * check if there is any job in mirror list
4961 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4964 struct drm_sched_job *job;
4966 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4967 struct amdgpu_ring *ring = adev->rings[i];
4969 if (!ring || !ring->sched.thread)
4972 spin_lock(&ring->sched.job_list_lock);
4973 job = list_first_entry_or_null(&ring->sched.pending_list,
4974 struct drm_sched_job, list);
4975 spin_unlock(&ring->sched.job_list_lock);
4983 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4985 * @adev: amdgpu_device pointer
4987 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4990 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4993 if (amdgpu_gpu_recovery == 0)
4996 /* Skip soft reset check in fatal error mode */
4997 if (!amdgpu_ras_is_poison_mode_supported(adev))
5000 if (amdgpu_sriov_vf(adev))
5003 if (amdgpu_gpu_recovery == -1) {
5004 switch (adev->asic_type) {
5005 #ifdef CONFIG_DRM_AMDGPU_SI
5012 #ifdef CONFIG_DRM_AMDGPU_CIK
5019 case CHIP_CYAN_SKILLFISH:
5029 dev_info(adev->dev, "GPU recovery disabled.\n");
5033 int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
5038 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
5040 dev_info(adev->dev, "GPU mode1 reset\n");
5043 pci_clear_master(adev->pdev);
5045 amdgpu_device_cache_pci_state(adev->pdev);
5047 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
5048 dev_info(adev->dev, "GPU smu mode1 reset\n");
5049 ret = amdgpu_dpm_mode1_reset(adev);
5051 dev_info(adev->dev, "GPU psp mode1 reset\n");
5052 ret = psp_gpu_reset(adev);
5056 goto mode1_reset_failed;
5058 amdgpu_device_load_pci_state(adev->pdev);
5059 ret = amdgpu_psp_wait_for_bootloader(adev);
5061 goto mode1_reset_failed;
5063 /* wait for asic to come out of reset */
5064 for (i = 0; i < adev->usec_timeout; i++) {
5065 u32 memsize = adev->nbio.funcs->get_memsize(adev);
5067 if (memsize != 0xffffffff)
5072 if (i >= adev->usec_timeout) {
5074 goto mode1_reset_failed;
5077 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
5082 dev_err(adev->dev, "GPU mode1 reset failed\n");
5086 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
5087 struct amdgpu_reset_context *reset_context)
5090 struct amdgpu_job *job = NULL;
5091 bool need_full_reset =
5092 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5094 if (reset_context->reset_req_dev == adev)
5095 job = reset_context->job;
5097 if (amdgpu_sriov_vf(adev)) {
5098 /* stop the data exchange thread */
5099 amdgpu_virt_fini_data_exchange(adev);
5102 amdgpu_fence_driver_isr_toggle(adev, true);
5104 /* block all schedulers and reset given job's ring */
5105 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5106 struct amdgpu_ring *ring = adev->rings[i];
5108 if (!ring || !ring->sched.thread)
5111 /* Clear job fence from fence drv to avoid force_completion
5112 * leave NULL and vm flush fence in fence drv
5114 amdgpu_fence_driver_clear_job_fences(ring);
5116 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
5117 amdgpu_fence_driver_force_completion(ring);
5120 amdgpu_fence_driver_isr_toggle(adev, false);
5123 drm_sched_increase_karma(&job->base);
5125 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
5126 /* If reset handler not implemented, continue; otherwise return */
5127 if (r == -EOPNOTSUPP)
5132 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
5133 if (!amdgpu_sriov_vf(adev)) {
5135 if (!need_full_reset)
5136 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
5138 if (!need_full_reset && amdgpu_gpu_recovery &&
5139 amdgpu_device_ip_check_soft_reset(adev)) {
5140 amdgpu_device_ip_pre_soft_reset(adev);
5141 r = amdgpu_device_ip_soft_reset(adev);
5142 amdgpu_device_ip_post_soft_reset(adev);
5143 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
5144 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
5145 need_full_reset = true;
5149 if (need_full_reset)
5150 r = amdgpu_device_ip_suspend(adev);
5151 if (need_full_reset)
5152 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5154 clear_bit(AMDGPU_NEED_FULL_RESET,
5155 &reset_context->flags);
5161 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
5165 lockdep_assert_held(&adev->reset_domain->sem);
5167 for (i = 0; i < adev->reset_info.num_regs; i++) {
5168 adev->reset_info.reset_dump_reg_value[i] =
5169 RREG32(adev->reset_info.reset_dump_reg_list[i]);
5171 trace_amdgpu_reset_reg_dumps(adev->reset_info.reset_dump_reg_list[i],
5172 adev->reset_info.reset_dump_reg_value[i]);
5178 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
5179 struct amdgpu_reset_context *reset_context)
5181 struct amdgpu_device *tmp_adev = NULL;
5182 bool need_full_reset, skip_hw_reset, vram_lost = false;
5184 bool gpu_reset_for_dev_remove = 0;
5186 /* Try reset handler method first */
5187 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5189 amdgpu_reset_reg_dumps(tmp_adev);
5191 reset_context->reset_device_list = device_list_handle;
5192 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
5193 /* If reset handler not implemented, continue; otherwise return */
5194 if (r == -EOPNOTSUPP)
5199 /* Reset handler not implemented, use the default method */
5201 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5202 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
5204 gpu_reset_for_dev_remove =
5205 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5206 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5209 * ASIC reset has to be done on all XGMI hive nodes ASAP
5210 * to allow proper links negotiation in FW (within 1 sec)
5212 if (!skip_hw_reset && need_full_reset) {
5213 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5214 /* For XGMI run all resets in parallel to speed up the process */
5215 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5216 tmp_adev->gmc.xgmi.pending_reset = false;
5217 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
5220 r = amdgpu_asic_reset(tmp_adev);
5223 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
5224 r, adev_to_drm(tmp_adev)->unique);
5229 /* For XGMI wait for all resets to complete before proceed */
5231 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5232 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5233 flush_work(&tmp_adev->xgmi_reset_work);
5234 r = tmp_adev->asic_reset_res;
5242 if (!r && amdgpu_ras_intr_triggered()) {
5243 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5244 amdgpu_ras_reset_error_count(tmp_adev, AMDGPU_RAS_BLOCK__MMHUB);
5247 amdgpu_ras_intr_cleared();
5250 /* Since the mode1 reset affects base ip blocks, the
5251 * phase1 ip blocks need to be resumed. Otherwise there
5252 * will be a BIOS signature error and the psp bootloader
5253 * can't load kdb on the next amdgpu install.
5255 if (gpu_reset_for_dev_remove) {
5256 list_for_each_entry(tmp_adev, device_list_handle, reset_list)
5257 amdgpu_device_ip_resume_phase1(tmp_adev);
5262 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5263 if (need_full_reset) {
5265 r = amdgpu_device_asic_init(tmp_adev);
5267 dev_warn(tmp_adev->dev, "asic atom init failed!");
5269 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
5271 r = amdgpu_device_ip_resume_phase1(tmp_adev);
5275 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
5277 amdgpu_coredump(tmp_adev, vram_lost, reset_context);
5280 DRM_INFO("VRAM is lost due to GPU reset!\n");
5281 amdgpu_inc_vram_lost(tmp_adev);
5284 r = amdgpu_device_fw_loading(tmp_adev);
5288 r = amdgpu_xcp_restore_partition_mode(
5293 r = amdgpu_device_ip_resume_phase2(tmp_adev);
5297 if (tmp_adev->mman.buffer_funcs_ring->sched.ready)
5298 amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);
5301 amdgpu_device_fill_reset_magic(tmp_adev);
5304 * Add this ASIC as tracked as reset was already
5305 * complete successfully.
5307 amdgpu_register_gpu_instance(tmp_adev);
5309 if (!reset_context->hive &&
5310 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5311 amdgpu_xgmi_add_device(tmp_adev);
5313 r = amdgpu_device_ip_late_init(tmp_adev);
5317 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
5320 * The GPU enters bad state once faulty pages
5321 * by ECC has reached the threshold, and ras
5322 * recovery is scheduled next. So add one check
5323 * here to break recovery if it indeed exceeds
5324 * bad page threshold, and remind user to
5325 * retire this GPU or setting one bigger
5326 * bad_page_threshold value to fix this once
5327 * probing driver again.
5329 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
5331 amdgpu_ras_resume(tmp_adev);
5337 /* Update PSP FW topology after reset */
5338 if (reset_context->hive &&
5339 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5340 r = amdgpu_xgmi_update_topology(
5341 reset_context->hive, tmp_adev);
5347 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5348 r = amdgpu_ib_ring_tests(tmp_adev);
5350 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5351 need_full_reset = true;
5358 r = amdgpu_device_recover_vram(tmp_adev);
5360 tmp_adev->asic_reset_res = r;
5364 if (need_full_reset)
5365 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5367 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5371 static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5374 switch (amdgpu_asic_reset_method(adev)) {
5375 case AMD_RESET_METHOD_MODE1:
5376 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5378 case AMD_RESET_METHOD_MODE2:
5379 adev->mp1_state = PP_MP1_STATE_RESET;
5382 adev->mp1_state = PP_MP1_STATE_NONE;
5387 static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5389 amdgpu_vf_error_trans_all(adev);
5390 adev->mp1_state = PP_MP1_STATE_NONE;
5393 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5395 struct pci_dev *p = NULL;
5397 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5398 adev->pdev->bus->number, 1);
5400 pm_runtime_enable(&(p->dev));
5401 pm_runtime_resume(&(p->dev));
5407 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5409 enum amd_reset_method reset_method;
5410 struct pci_dev *p = NULL;
5414 * For now, only BACO and mode1 reset are confirmed
5415 * to suffer the audio issue without proper suspended.
5417 reset_method = amdgpu_asic_reset_method(adev);
5418 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5419 (reset_method != AMD_RESET_METHOD_MODE1))
5422 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5423 adev->pdev->bus->number, 1);
5427 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5430 * If we cannot get the audio device autosuspend delay,
5431 * a fixed 4S interval will be used. Considering 3S is
5432 * the audio controller default autosuspend delay setting.
5433 * 4S used here is guaranteed to cover that.
5435 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5437 while (!pm_runtime_status_suspended(&(p->dev))) {
5438 if (!pm_runtime_suspend(&(p->dev)))
5441 if (expires < ktime_get_mono_fast_ns()) {
5442 dev_warn(adev->dev, "failed to suspend display audio\n");
5444 /* TODO: abort the succeeding gpu reset? */
5449 pm_runtime_disable(&(p->dev));
5455 static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5457 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5459 #if defined(CONFIG_DEBUG_FS)
5460 if (!amdgpu_sriov_vf(adev))
5461 cancel_work(&adev->reset_work);
5465 cancel_work(&adev->kfd.reset_work);
5467 if (amdgpu_sriov_vf(adev))
5468 cancel_work(&adev->virt.flr_work);
5470 if (con && adev->ras_enabled)
5471 cancel_work(&con->recovery_work);
5476 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5478 * @adev: amdgpu_device pointer
5479 * @job: which job trigger hang
5480 * @reset_context: amdgpu reset context pointer
5482 * Attempt to reset the GPU if it has hung (all asics).
5483 * Attempt to do soft-reset or full-reset and reinitialize Asic
5484 * Returns 0 for success or an error on failure.
5487 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5488 struct amdgpu_job *job,
5489 struct amdgpu_reset_context *reset_context)
5491 struct list_head device_list, *device_list_handle = NULL;
5492 bool job_signaled = false;
5493 struct amdgpu_hive_info *hive = NULL;
5494 struct amdgpu_device *tmp_adev = NULL;
5496 bool need_emergency_restart = false;
5497 bool audio_suspended = false;
5498 bool gpu_reset_for_dev_remove = false;
5500 gpu_reset_for_dev_remove =
5501 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5502 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5505 * Special case: RAS triggered and full reset isn't supported
5507 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5510 * Flush RAM to disk so that after reboot
5511 * the user can read log and see why the system rebooted.
5513 if (need_emergency_restart && amdgpu_ras_get_context(adev) &&
5514 amdgpu_ras_get_context(adev)->reboot) {
5515 DRM_WARN("Emergency reboot.");
5518 emergency_restart();
5521 dev_info(adev->dev, "GPU %s begin!\n",
5522 need_emergency_restart ? "jobs stop":"reset");
5524 if (!amdgpu_sriov_vf(adev))
5525 hive = amdgpu_get_xgmi_hive(adev);
5527 mutex_lock(&hive->hive_lock);
5529 reset_context->job = job;
5530 reset_context->hive = hive;
5532 * Build list of devices to reset.
5533 * In case we are in XGMI hive mode, resort the device list
5534 * to put adev in the 1st position.
5536 INIT_LIST_HEAD(&device_list);
5537 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5538 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5539 list_add_tail(&tmp_adev->reset_list, &device_list);
5540 if (gpu_reset_for_dev_remove && adev->shutdown)
5541 tmp_adev->shutdown = true;
5543 if (!list_is_first(&adev->reset_list, &device_list))
5544 list_rotate_to_front(&adev->reset_list, &device_list);
5545 device_list_handle = &device_list;
5547 list_add_tail(&adev->reset_list, &device_list);
5548 device_list_handle = &device_list;
5551 /* We need to lock reset domain only once both for XGMI and single device */
5552 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5554 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5556 /* block all schedulers and reset given job's ring */
5557 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5559 amdgpu_device_set_mp1_state(tmp_adev);
5562 * Try to put the audio codec into suspend state
5563 * before gpu reset started.
5565 * Due to the power domain of the graphics device
5566 * is shared with AZ power domain. Without this,
5567 * we may change the audio hardware from behind
5568 * the audio driver's back. That will trigger
5569 * some audio codec errors.
5571 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5572 audio_suspended = true;
5574 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5576 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5578 if (!amdgpu_sriov_vf(tmp_adev))
5579 amdgpu_amdkfd_pre_reset(tmp_adev);
5582 * Mark these ASICs to be reseted as untracked first
5583 * And add them back after reset completed
5585 amdgpu_unregister_gpu_instance(tmp_adev);
5587 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5589 /* disable ras on ALL IPs */
5590 if (!need_emergency_restart &&
5591 amdgpu_device_ip_need_full_reset(tmp_adev))
5592 amdgpu_ras_suspend(tmp_adev);
5594 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5595 struct amdgpu_ring *ring = tmp_adev->rings[i];
5597 if (!ring || !ring->sched.thread)
5600 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5602 if (need_emergency_restart)
5603 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5605 atomic_inc(&tmp_adev->gpu_reset_counter);
5608 if (need_emergency_restart)
5609 goto skip_sched_resume;
5612 * Must check guilty signal here since after this point all old
5613 * HW fences are force signaled.
5615 * job->base holds a reference to parent fence
5617 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5618 job_signaled = true;
5619 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5623 retry: /* Rest of adevs pre asic reset from XGMI hive. */
5624 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5625 if (gpu_reset_for_dev_remove) {
5626 /* Workaroud for ASICs need to disable SMC first */
5627 amdgpu_device_smu_fini_early(tmp_adev);
5629 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5630 /*TODO Should we stop ?*/
5632 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5633 r, adev_to_drm(tmp_adev)->unique);
5634 tmp_adev->asic_reset_res = r;
5638 * Drop all pending non scheduler resets. Scheduler resets
5639 * were already dropped during drm_sched_stop
5641 amdgpu_device_stop_pending_resets(tmp_adev);
5644 /* Actual ASIC resets if needed.*/
5645 /* Host driver will handle XGMI hive reset for SRIOV */
5646 if (amdgpu_sriov_vf(adev)) {
5647 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5649 adev->asic_reset_res = r;
5651 /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */
5652 if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5653 IP_VERSION(9, 4, 2) ||
5654 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))
5655 amdgpu_ras_resume(adev);
5657 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5658 if (r && r == -EAGAIN)
5661 if (!r && gpu_reset_for_dev_remove)
5667 /* Post ASIC reset for all devs .*/
5668 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5670 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5671 struct amdgpu_ring *ring = tmp_adev->rings[i];
5673 if (!ring || !ring->sched.thread)
5676 drm_sched_start(&ring->sched, true);
5679 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
5680 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5682 if (tmp_adev->asic_reset_res)
5683 r = tmp_adev->asic_reset_res;
5685 tmp_adev->asic_reset_res = 0;
5688 /* bad news, how to tell it to userspace ? */
5689 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5690 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5692 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5693 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5694 DRM_WARN("smart shift update failed\n");
5699 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5700 /* unlock kfd: SRIOV would do it separately */
5701 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5702 amdgpu_amdkfd_post_reset(tmp_adev);
5704 /* kfd_post_reset will do nothing if kfd device is not initialized,
5705 * need to bring up kfd here if it's not be initialized before
5707 if (!adev->kfd.init_complete)
5708 amdgpu_amdkfd_device_init(adev);
5710 if (audio_suspended)
5711 amdgpu_device_resume_display_audio(tmp_adev);
5713 amdgpu_device_unset_mp1_state(tmp_adev);
5715 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5719 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5721 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5724 mutex_unlock(&hive->hive_lock);
5725 amdgpu_put_xgmi_hive(hive);
5729 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5731 atomic_set(&adev->reset_domain->reset_res, r);
5736 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5738 * @adev: amdgpu_device pointer
5740 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5741 * and lanes) of the slot the device is in. Handles APUs and
5742 * virtualized environments where PCIE config space may not be available.
5744 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5746 struct pci_dev *pdev;
5747 enum pci_bus_speed speed_cap, platform_speed_cap;
5748 enum pcie_link_width platform_link_width;
5750 if (amdgpu_pcie_gen_cap)
5751 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5753 if (amdgpu_pcie_lane_cap)
5754 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5756 /* covers APUs as well */
5757 if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) {
5758 if (adev->pm.pcie_gen_mask == 0)
5759 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5760 if (adev->pm.pcie_mlw_mask == 0)
5761 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5765 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5768 pcie_bandwidth_available(adev->pdev, NULL,
5769 &platform_speed_cap, &platform_link_width);
5771 if (adev->pm.pcie_gen_mask == 0) {
5774 speed_cap = pcie_get_speed_cap(pdev);
5775 if (speed_cap == PCI_SPEED_UNKNOWN) {
5776 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5777 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5778 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5780 if (speed_cap == PCIE_SPEED_32_0GT)
5781 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5782 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5783 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5784 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5785 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5786 else if (speed_cap == PCIE_SPEED_16_0GT)
5787 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5788 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5789 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5790 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5791 else if (speed_cap == PCIE_SPEED_8_0GT)
5792 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5793 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5794 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5795 else if (speed_cap == PCIE_SPEED_5_0GT)
5796 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5797 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5799 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5802 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5803 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5804 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5806 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5807 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5808 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5809 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5810 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5811 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5812 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5813 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5814 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5815 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5816 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5817 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5818 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5819 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5820 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5821 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5822 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5823 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5825 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5829 if (adev->pm.pcie_mlw_mask == 0) {
5830 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5831 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5833 switch (platform_link_width) {
5835 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5836 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5837 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5838 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5839 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5840 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5841 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5844 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5845 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5846 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5847 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5848 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5849 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5852 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5853 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5854 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5855 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5856 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5859 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5860 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5861 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5862 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5865 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5866 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5867 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5870 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5871 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5874 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5884 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5886 * @adev: amdgpu_device pointer
5887 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5889 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5890 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5893 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5894 struct amdgpu_device *peer_adev)
5896 #ifdef CONFIG_HSA_AMD_P2P
5897 uint64_t address_mask = peer_adev->dev->dma_mask ?
5898 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5899 resource_size_t aper_limit =
5900 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5902 !adev->gmc.xgmi.connected_to_cpu &&
5903 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
5905 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
5906 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
5907 !(adev->gmc.aper_base & address_mask ||
5908 aper_limit & address_mask));
5914 int amdgpu_device_baco_enter(struct drm_device *dev)
5916 struct amdgpu_device *adev = drm_to_adev(dev);
5917 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5919 if (!amdgpu_device_supports_baco(dev))
5922 if (ras && adev->ras_enabled &&
5923 adev->nbio.funcs->enable_doorbell_interrupt)
5924 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5926 return amdgpu_dpm_baco_enter(adev);
5929 int amdgpu_device_baco_exit(struct drm_device *dev)
5931 struct amdgpu_device *adev = drm_to_adev(dev);
5932 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5935 if (!amdgpu_device_supports_baco(dev))
5938 ret = amdgpu_dpm_baco_exit(adev);
5942 if (ras && adev->ras_enabled &&
5943 adev->nbio.funcs->enable_doorbell_interrupt)
5944 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
5946 if (amdgpu_passthrough(adev) &&
5947 adev->nbio.funcs->clear_doorbell_interrupt)
5948 adev->nbio.funcs->clear_doorbell_interrupt(adev);
5954 * amdgpu_pci_error_detected - Called when a PCI error is detected.
5955 * @pdev: PCI device struct
5956 * @state: PCI channel state
5958 * Description: Called when a PCI error is detected.
5960 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
5962 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5964 struct drm_device *dev = pci_get_drvdata(pdev);
5965 struct amdgpu_device *adev = drm_to_adev(dev);
5968 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
5970 if (adev->gmc.xgmi.num_physical_nodes > 1) {
5971 DRM_WARN("No support for XGMI hive yet...");
5972 return PCI_ERS_RESULT_DISCONNECT;
5975 adev->pci_channel_state = state;
5978 case pci_channel_io_normal:
5979 return PCI_ERS_RESULT_CAN_RECOVER;
5980 /* Fatal error, prepare for slot reset */
5981 case pci_channel_io_frozen:
5983 * Locking adev->reset_domain->sem will prevent any external access
5984 * to GPU during PCI error recovery
5986 amdgpu_device_lock_reset_domain(adev->reset_domain);
5987 amdgpu_device_set_mp1_state(adev);
5990 * Block any work scheduling as we do for regular GPU reset
5991 * for the duration of the recovery
5993 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5994 struct amdgpu_ring *ring = adev->rings[i];
5996 if (!ring || !ring->sched.thread)
5999 drm_sched_stop(&ring->sched, NULL);
6001 atomic_inc(&adev->gpu_reset_counter);
6002 return PCI_ERS_RESULT_NEED_RESET;
6003 case pci_channel_io_perm_failure:
6004 /* Permanent error, prepare for device removal */
6005 return PCI_ERS_RESULT_DISCONNECT;
6008 return PCI_ERS_RESULT_NEED_RESET;
6012 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
6013 * @pdev: pointer to PCI device
6015 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
6018 DRM_INFO("PCI error: mmio enabled callback!!\n");
6020 /* TODO - dump whatever for debugging purposes */
6022 /* This called only if amdgpu_pci_error_detected returns
6023 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
6024 * works, no need to reset slot.
6027 return PCI_ERS_RESULT_RECOVERED;
6031 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
6032 * @pdev: PCI device struct
6034 * Description: This routine is called by the pci error recovery
6035 * code after the PCI slot has been reset, just before we
6036 * should resume normal operations.
6038 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
6040 struct drm_device *dev = pci_get_drvdata(pdev);
6041 struct amdgpu_device *adev = drm_to_adev(dev);
6043 struct amdgpu_reset_context reset_context;
6045 struct list_head device_list;
6047 DRM_INFO("PCI error: slot reset callback!!\n");
6049 memset(&reset_context, 0, sizeof(reset_context));
6051 INIT_LIST_HEAD(&device_list);
6052 list_add_tail(&adev->reset_list, &device_list);
6054 /* wait for asic to come out of reset */
6057 /* Restore PCI confspace */
6058 amdgpu_device_load_pci_state(pdev);
6060 /* confirm ASIC came out of reset */
6061 for (i = 0; i < adev->usec_timeout; i++) {
6062 memsize = amdgpu_asic_get_config_memsize(adev);
6064 if (memsize != 0xffffffff)
6068 if (memsize == 0xffffffff) {
6073 reset_context.method = AMD_RESET_METHOD_NONE;
6074 reset_context.reset_req_dev = adev;
6075 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
6076 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
6078 adev->no_hw_access = true;
6079 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
6080 adev->no_hw_access = false;
6084 r = amdgpu_do_asic_reset(&device_list, &reset_context);
6088 if (amdgpu_device_cache_pci_state(adev->pdev))
6089 pci_restore_state(adev->pdev);
6091 DRM_INFO("PCIe error recovery succeeded\n");
6093 DRM_ERROR("PCIe error recovery failed, err:%d", r);
6094 amdgpu_device_unset_mp1_state(adev);
6095 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6098 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
6102 * amdgpu_pci_resume() - resume normal ops after PCI reset
6103 * @pdev: pointer to PCI device
6105 * Called when the error recovery driver tells us that its
6106 * OK to resume normal operation.
6108 void amdgpu_pci_resume(struct pci_dev *pdev)
6110 struct drm_device *dev = pci_get_drvdata(pdev);
6111 struct amdgpu_device *adev = drm_to_adev(dev);
6115 DRM_INFO("PCI error: resume callback!!\n");
6117 /* Only continue execution for the case of pci_channel_io_frozen */
6118 if (adev->pci_channel_state != pci_channel_io_frozen)
6121 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6122 struct amdgpu_ring *ring = adev->rings[i];
6124 if (!ring || !ring->sched.thread)
6127 drm_sched_start(&ring->sched, true);
6130 amdgpu_device_unset_mp1_state(adev);
6131 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6134 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
6136 struct drm_device *dev = pci_get_drvdata(pdev);
6137 struct amdgpu_device *adev = drm_to_adev(dev);
6140 r = pci_save_state(pdev);
6142 kfree(adev->pci_state);
6144 adev->pci_state = pci_store_saved_state(pdev);
6146 if (!adev->pci_state) {
6147 DRM_ERROR("Failed to store PCI saved state");
6151 DRM_WARN("Failed to save PCI state, err:%d\n", r);
6158 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
6160 struct drm_device *dev = pci_get_drvdata(pdev);
6161 struct amdgpu_device *adev = drm_to_adev(dev);
6164 if (!adev->pci_state)
6167 r = pci_load_saved_state(pdev, adev->pci_state);
6170 pci_restore_state(pdev);
6172 DRM_WARN("Failed to load PCI state, err:%d\n", r);
6179 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
6180 struct amdgpu_ring *ring)
6182 #ifdef CONFIG_X86_64
6183 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6186 if (adev->gmc.xgmi.connected_to_cpu)
6189 if (ring && ring->funcs->emit_hdp_flush)
6190 amdgpu_ring_emit_hdp_flush(ring);
6192 amdgpu_asic_flush_hdp(adev, ring);
6195 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
6196 struct amdgpu_ring *ring)
6198 #ifdef CONFIG_X86_64
6199 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6202 if (adev->gmc.xgmi.connected_to_cpu)
6205 amdgpu_asic_invalidate_hdp(adev, ring);
6208 int amdgpu_in_reset(struct amdgpu_device *adev)
6210 return atomic_read(&adev->reset_domain->in_gpu_reset);
6214 * amdgpu_device_halt() - bring hardware to some kind of halt state
6216 * @adev: amdgpu_device pointer
6218 * Bring hardware to some kind of halt state so that no one can touch it
6219 * any more. It will help to maintain error context when error occurred.
6220 * Compare to a simple hang, the system will keep stable at least for SSH
6221 * access. Then it should be trivial to inspect the hardware state and
6222 * see what's going on. Implemented as following:
6224 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
6225 * clears all CPU mappings to device, disallows remappings through page faults
6226 * 2. amdgpu_irq_disable_all() disables all interrupts
6227 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
6228 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
6229 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
6230 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
6231 * flush any in flight DMA operations
6233 void amdgpu_device_halt(struct amdgpu_device *adev)
6235 struct pci_dev *pdev = adev->pdev;
6236 struct drm_device *ddev = adev_to_drm(adev);
6238 amdgpu_xcp_dev_unplug(adev);
6239 drm_dev_unplug(ddev);
6241 amdgpu_irq_disable_all(adev);
6243 amdgpu_fence_driver_hw_fini(adev);
6245 adev->no_hw_access = true;
6247 amdgpu_device_unmap_mmio(adev);
6249 pci_disable_device(pdev);
6250 pci_wait_for_pending_transaction(pdev);
6253 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
6256 unsigned long flags, address, data;
6259 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6260 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6262 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6263 WREG32(address, reg * 4);
6264 (void)RREG32(address);
6266 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6270 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
6273 unsigned long flags, address, data;
6275 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6276 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6278 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6279 WREG32(address, reg * 4);
6280 (void)RREG32(address);
6283 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6287 * amdgpu_device_switch_gang - switch to a new gang
6288 * @adev: amdgpu_device pointer
6289 * @gang: the gang to switch to
6291 * Try to switch to a new gang.
6292 * Returns: NULL if we switched to the new gang or a reference to the current
6295 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
6296 struct dma_fence *gang)
6298 struct dma_fence *old = NULL;
6303 old = dma_fence_get_rcu_safe(&adev->gang_submit);
6309 if (!dma_fence_is_signaled(old))
6312 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
6319 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
6321 switch (adev->asic_type) {
6322 #ifdef CONFIG_DRM_AMDGPU_SI
6326 /* chips with no display hardware */
6328 #ifdef CONFIG_DRM_AMDGPU_SI
6334 #ifdef CONFIG_DRM_AMDGPU_CIK
6343 case CHIP_POLARIS10:
6344 case CHIP_POLARIS11:
6345 case CHIP_POLARIS12:
6349 /* chips with display hardware */
6353 if (!amdgpu_ip_version(adev, DCE_HWIP, 0) ||
6354 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6360 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
6361 uint32_t inst, uint32_t reg_addr, char reg_name[],
6362 uint32_t expected_value, uint32_t mask)
6366 uint32_t tmp_ = RREG32(reg_addr);
6367 uint32_t loop = adev->usec_timeout;
6369 while ((tmp_ & (mask)) != (expected_value)) {
6371 loop = adev->usec_timeout;
6375 tmp_ = RREG32(reg_addr);
6378 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",
6379 inst, reg_name, (uint32_t)expected_value,
6380 (uint32_t)(tmp_ & (mask)));