2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/console.h>
31 #include <linux/slab.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/amdgpu_drm.h>
36 #include <linux/vgaarb.h>
37 #include <linux/vga_switcheroo.h>
38 #include <linux/efi.h>
40 #include "amdgpu_trace.h"
41 #include "amdgpu_i2c.h"
43 #include "amdgpu_atombios.h"
44 #include "amdgpu_atomfirmware.h"
46 #ifdef CONFIG_DRM_AMDGPU_SI
49 #ifdef CONFIG_DRM_AMDGPU_CIK
54 #include "bif/bif_4_1_d.h"
55 #include <linux/pci.h>
56 #include <linux/firmware.h>
57 #include "amdgpu_vf_error.h"
59 #include "amdgpu_amdkfd.h"
60 #include "amdgpu_pm.h"
62 #include "amdgpu_xgmi.h"
64 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
65 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
66 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
67 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
68 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
70 #define AMDGPU_RESUME_MS 2000
72 static const char *amdgpu_asic_name[] = {
99 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
102 * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
104 * @dev: drm_device pointer
106 * Returns true if the device is a dGPU with HG/PX power control,
107 * otherwise return false.
109 bool amdgpu_device_is_px(struct drm_device *dev)
111 struct amdgpu_device *adev = dev->dev_private;
113 if (adev->flags & AMD_IS_PX)
119 * MMIO register access helper functions.
122 * amdgpu_mm_rreg - read a memory mapped IO register
124 * @adev: amdgpu_device pointer
125 * @reg: dword aligned register offset
126 * @acc_flags: access flags which require special behavior
128 * Returns the 32 bit value from the offset specified.
130 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
135 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
136 return amdgpu_virt_kiq_rreg(adev, reg);
138 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
139 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
143 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
144 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
145 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
146 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
148 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
153 * MMIO register read with bytes helper functions
154 * @offset:bytes offset from MMIO start
159 * amdgpu_mm_rreg8 - read a memory mapped IO register
161 * @adev: amdgpu_device pointer
162 * @offset: byte aligned register offset
164 * Returns the 8 bit value from the offset specified.
166 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
167 if (offset < adev->rmmio_size)
168 return (readb(adev->rmmio + offset));
173 * MMIO register write with bytes helper functions
174 * @offset:bytes offset from MMIO start
175 * @value: the value want to be written to the register
179 * amdgpu_mm_wreg8 - read a memory mapped IO register
181 * @adev: amdgpu_device pointer
182 * @offset: byte aligned register offset
183 * @value: 8 bit value to write
185 * Writes the value specified to the offset specified.
187 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
188 if (offset < adev->rmmio_size)
189 writeb(value, adev->rmmio + offset);
195 * amdgpu_mm_wreg - write to a memory mapped IO register
197 * @adev: amdgpu_device pointer
198 * @reg: dword aligned register offset
199 * @v: 32 bit value to write to the register
200 * @acc_flags: access flags which require special behavior
202 * Writes the value specified to the offset specified.
204 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
207 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
209 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
210 adev->last_mm_index = v;
213 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
214 return amdgpu_virt_kiq_wreg(adev, reg, v);
216 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
217 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
221 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
222 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
223 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
224 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
227 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
233 * amdgpu_io_rreg - read an IO register
235 * @adev: amdgpu_device pointer
236 * @reg: dword aligned register offset
238 * Returns the 32 bit value from the offset specified.
240 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
242 if ((reg * 4) < adev->rio_mem_size)
243 return ioread32(adev->rio_mem + (reg * 4));
245 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
246 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
251 * amdgpu_io_wreg - write to an IO register
253 * @adev: amdgpu_device pointer
254 * @reg: dword aligned register offset
255 * @v: 32 bit value to write to the register
257 * Writes the value specified to the offset specified.
259 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
261 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
262 adev->last_mm_index = v;
265 if ((reg * 4) < adev->rio_mem_size)
266 iowrite32(v, adev->rio_mem + (reg * 4));
268 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
269 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
272 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
278 * amdgpu_mm_rdoorbell - read a doorbell dword
280 * @adev: amdgpu_device pointer
281 * @index: doorbell index
283 * Returns the value in the doorbell aperture at the
284 * requested doorbell index (CIK).
286 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
288 if (index < adev->doorbell.num_doorbells) {
289 return readl(adev->doorbell.ptr + index);
291 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
297 * amdgpu_mm_wdoorbell - write a doorbell dword
299 * @adev: amdgpu_device pointer
300 * @index: doorbell index
303 * Writes @v to the doorbell aperture at the
304 * requested doorbell index (CIK).
306 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
308 if (index < adev->doorbell.num_doorbells) {
309 writel(v, adev->doorbell.ptr + index);
311 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
316 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
318 * @adev: amdgpu_device pointer
319 * @index: doorbell index
321 * Returns the value in the doorbell aperture at the
322 * requested doorbell index (VEGA10+).
324 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
326 if (index < adev->doorbell.num_doorbells) {
327 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
329 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
335 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
337 * @adev: amdgpu_device pointer
338 * @index: doorbell index
341 * Writes @v to the doorbell aperture at the
342 * requested doorbell index (VEGA10+).
344 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
346 if (index < adev->doorbell.num_doorbells) {
347 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
349 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
354 * amdgpu_invalid_rreg - dummy reg read function
356 * @adev: amdgpu device pointer
357 * @reg: offset of register
359 * Dummy register read function. Used for register blocks
360 * that certain asics don't have (all asics).
361 * Returns the value in the register.
363 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
365 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
371 * amdgpu_invalid_wreg - dummy reg write function
373 * @adev: amdgpu device pointer
374 * @reg: offset of register
375 * @v: value to write to the register
377 * Dummy register read function. Used for register blocks
378 * that certain asics don't have (all asics).
380 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
382 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
388 * amdgpu_block_invalid_rreg - dummy reg read function
390 * @adev: amdgpu device pointer
391 * @block: offset of instance
392 * @reg: offset of register
394 * Dummy register read function. Used for register blocks
395 * that certain asics don't have (all asics).
396 * Returns the value in the register.
398 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
399 uint32_t block, uint32_t reg)
401 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
408 * amdgpu_block_invalid_wreg - dummy reg write function
410 * @adev: amdgpu device pointer
411 * @block: offset of instance
412 * @reg: offset of register
413 * @v: value to write to the register
415 * Dummy register read function. Used for register blocks
416 * that certain asics don't have (all asics).
418 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
420 uint32_t reg, uint32_t v)
422 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
428 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
430 * @adev: amdgpu device pointer
432 * Allocates a scratch page of VRAM for use by various things in the
435 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
437 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
438 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
439 &adev->vram_scratch.robj,
440 &adev->vram_scratch.gpu_addr,
441 (void **)&adev->vram_scratch.ptr);
445 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
447 * @adev: amdgpu device pointer
449 * Frees the VRAM scratch page.
451 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
453 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
457 * amdgpu_device_program_register_sequence - program an array of registers.
459 * @adev: amdgpu_device pointer
460 * @registers: pointer to the register array
461 * @array_size: size of the register array
463 * Programs an array or registers with and and or masks.
464 * This is a helper for setting golden registers.
466 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
467 const u32 *registers,
468 const u32 array_size)
470 u32 tmp, reg, and_mask, or_mask;
476 for (i = 0; i < array_size; i +=3) {
477 reg = registers[i + 0];
478 and_mask = registers[i + 1];
479 or_mask = registers[i + 2];
481 if (and_mask == 0xffffffff) {
493 * amdgpu_device_pci_config_reset - reset the GPU
495 * @adev: amdgpu_device pointer
497 * Resets the GPU using the pci config reset sequence.
498 * Only applicable to asics prior to vega10.
500 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
502 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
506 * GPU doorbell aperture helpers function.
509 * amdgpu_device_doorbell_init - Init doorbell driver information.
511 * @adev: amdgpu_device pointer
513 * Init doorbell driver information (CIK)
514 * Returns 0 on success, error on failure.
516 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
519 /* No doorbell on SI hardware generation */
520 if (adev->asic_type < CHIP_BONAIRE) {
521 adev->doorbell.base = 0;
522 adev->doorbell.size = 0;
523 adev->doorbell.num_doorbells = 0;
524 adev->doorbell.ptr = NULL;
528 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
531 amdgpu_asic_init_doorbell_index(adev);
533 /* doorbell bar mapping */
534 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
535 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
537 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
538 adev->doorbell_index.max_assignment+1);
539 if (adev->doorbell.num_doorbells == 0)
542 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
543 * paging queue doorbell use the second page. The
544 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
545 * doorbells are in the first page. So with paging queue enabled,
546 * the max num_doorbells should + 1 page (0x400 in dword)
548 if (adev->asic_type >= CHIP_VEGA10)
549 adev->doorbell.num_doorbells += 0x400;
551 adev->doorbell.ptr = ioremap(adev->doorbell.base,
552 adev->doorbell.num_doorbells *
554 if (adev->doorbell.ptr == NULL)
561 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
563 * @adev: amdgpu_device pointer
565 * Tear down doorbell driver information (CIK)
567 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
569 iounmap(adev->doorbell.ptr);
570 adev->doorbell.ptr = NULL;
576 * amdgpu_device_wb_*()
577 * Writeback is the method by which the GPU updates special pages in memory
578 * with the status of certain GPU events (fences, ring pointers,etc.).
582 * amdgpu_device_wb_fini - Disable Writeback and free memory
584 * @adev: amdgpu_device pointer
586 * Disables Writeback and frees the Writeback memory (all asics).
587 * Used at driver shutdown.
589 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
591 if (adev->wb.wb_obj) {
592 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
594 (void **)&adev->wb.wb);
595 adev->wb.wb_obj = NULL;
600 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
602 * @adev: amdgpu_device pointer
604 * Initializes writeback and allocates writeback memory (all asics).
605 * Used at driver startup.
606 * Returns 0 on success or an -error on failure.
608 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
612 if (adev->wb.wb_obj == NULL) {
613 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
614 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
615 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
616 &adev->wb.wb_obj, &adev->wb.gpu_addr,
617 (void **)&adev->wb.wb);
619 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
623 adev->wb.num_wb = AMDGPU_MAX_WB;
624 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
626 /* clear wb memory */
627 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
634 * amdgpu_device_wb_get - Allocate a wb entry
636 * @adev: amdgpu_device pointer
639 * Allocate a wb slot for use by the driver (all asics).
640 * Returns 0 on success or -EINVAL on failure.
642 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
644 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
646 if (offset < adev->wb.num_wb) {
647 __set_bit(offset, adev->wb.used);
648 *wb = offset << 3; /* convert to dw offset */
656 * amdgpu_device_wb_free - Free a wb entry
658 * @adev: amdgpu_device pointer
661 * Free a wb slot allocated for use by the driver (all asics)
663 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
666 if (wb < adev->wb.num_wb)
667 __clear_bit(wb, adev->wb.used);
671 * amdgpu_device_resize_fb_bar - try to resize FB BAR
673 * @adev: amdgpu_device pointer
675 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
676 * to fail, but if any of the BARs is not accessible after the size we abort
677 * driver loading by returning -ENODEV.
679 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
681 u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
682 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
683 struct pci_bus *root;
684 struct resource *res;
690 if (amdgpu_sriov_vf(adev))
693 /* Check if the root BUS has 64bit memory resources */
694 root = adev->pdev->bus;
698 pci_bus_for_each_resource(root, res, i) {
699 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
700 res->start > 0x100000000ull)
704 /* Trying to resize is pointless without a root hub window above 4GB */
708 /* Disable memory decoding while we change the BAR addresses and size */
709 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
710 pci_write_config_word(adev->pdev, PCI_COMMAND,
711 cmd & ~PCI_COMMAND_MEMORY);
713 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
714 amdgpu_device_doorbell_fini(adev);
715 if (adev->asic_type >= CHIP_BONAIRE)
716 pci_release_resource(adev->pdev, 2);
718 pci_release_resource(adev->pdev, 0);
720 r = pci_resize_resource(adev->pdev, 0, rbar_size);
722 DRM_INFO("Not enough PCI address space for a large BAR.");
723 else if (r && r != -ENOTSUPP)
724 DRM_ERROR("Problem resizing BAR0 (%d).", r);
726 pci_assign_unassigned_bus_resources(adev->pdev->bus);
728 /* When the doorbell or fb BAR isn't available we have no chance of
731 r = amdgpu_device_doorbell_init(adev);
732 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
735 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
741 * GPU helpers function.
744 * amdgpu_device_need_post - check if the hw need post or not
746 * @adev: amdgpu_device pointer
748 * Check if the asic has been initialized (all asics) at driver startup
749 * or post is needed if hw reset is performed.
750 * Returns true if need or false if not.
752 bool amdgpu_device_need_post(struct amdgpu_device *adev)
756 if (amdgpu_sriov_vf(adev))
759 if (amdgpu_passthrough(adev)) {
760 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
761 * some old smc fw still need driver do vPost otherwise gpu hang, while
762 * those smc fw version above 22.15 doesn't have this flaw, so we force
763 * vpost executed for smc version below 22.15
765 if (adev->asic_type == CHIP_FIJI) {
768 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
769 /* force vPost if error occured */
773 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
774 if (fw_ver < 0x00160e00)
779 if (adev->has_hw_reset) {
780 adev->has_hw_reset = false;
784 /* bios scratch used on CIK+ */
785 if (adev->asic_type >= CHIP_BONAIRE)
786 return amdgpu_atombios_scratch_need_asic_init(adev);
788 /* check MEM_SIZE for older asics */
789 reg = amdgpu_asic_get_config_memsize(adev);
791 if ((reg != 0) && (reg != 0xffffffff))
797 /* if we get transitioned to only one device, take VGA back */
799 * amdgpu_device_vga_set_decode - enable/disable vga decode
801 * @cookie: amdgpu_device pointer
802 * @state: enable/disable vga decode
804 * Enable/disable vga decode (all asics).
805 * Returns VGA resource flags.
807 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
809 struct amdgpu_device *adev = cookie;
810 amdgpu_asic_set_vga_state(adev, state);
812 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
813 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
815 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
819 * amdgpu_device_check_block_size - validate the vm block size
821 * @adev: amdgpu_device pointer
823 * Validates the vm block size specified via module parameter.
824 * The vm block size defines number of bits in page table versus page directory,
825 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
826 * page table and the remaining bits are in the page directory.
828 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
830 /* defines number of bits in page table versus page directory,
831 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
832 * page table and the remaining bits are in the page directory */
833 if (amdgpu_vm_block_size == -1)
836 if (amdgpu_vm_block_size < 9) {
837 dev_warn(adev->dev, "VM page table size (%d) too small\n",
838 amdgpu_vm_block_size);
839 amdgpu_vm_block_size = -1;
844 * amdgpu_device_check_vm_size - validate the vm size
846 * @adev: amdgpu_device pointer
848 * Validates the vm size in GB specified via module parameter.
849 * The VM size is the size of the GPU virtual memory space in GB.
851 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
853 /* no need to check the default value */
854 if (amdgpu_vm_size == -1)
857 if (amdgpu_vm_size < 1) {
858 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
864 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
867 bool is_os_64 = (sizeof(void *) == 8) ? true : false;
868 uint64_t total_memory;
869 uint64_t dram_size_seven_GB = 0x1B8000000;
870 uint64_t dram_size_three_GB = 0xB8000000;
872 if (amdgpu_smu_memory_pool_size == 0)
876 DRM_WARN("Not 64-bit OS, feature not supported\n");
880 total_memory = (uint64_t)si.totalram * si.mem_unit;
882 if ((amdgpu_smu_memory_pool_size == 1) ||
883 (amdgpu_smu_memory_pool_size == 2)) {
884 if (total_memory < dram_size_three_GB)
886 } else if ((amdgpu_smu_memory_pool_size == 4) ||
887 (amdgpu_smu_memory_pool_size == 8)) {
888 if (total_memory < dram_size_seven_GB)
891 DRM_WARN("Smu memory pool size not supported\n");
894 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
899 DRM_WARN("No enough system memory\n");
901 adev->pm.smu_prv_buffer_size = 0;
905 * amdgpu_device_check_arguments - validate module params
907 * @adev: amdgpu_device pointer
909 * Validates certain module parameters and updates
910 * the associated values used by the driver (all asics).
912 static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
914 if (amdgpu_sched_jobs < 4) {
915 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
917 amdgpu_sched_jobs = 4;
918 } else if (!is_power_of_2(amdgpu_sched_jobs)){
919 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
921 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
924 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
925 /* gart size must be greater or equal to 32M */
926 dev_warn(adev->dev, "gart size (%d) too small\n",
928 amdgpu_gart_size = -1;
931 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
932 /* gtt size must be greater or equal to 32M */
933 dev_warn(adev->dev, "gtt size (%d) too small\n",
935 amdgpu_gtt_size = -1;
938 /* valid range is between 4 and 9 inclusive */
939 if (amdgpu_vm_fragment_size != -1 &&
940 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
941 dev_warn(adev->dev, "valid range is between 4 and 9\n");
942 amdgpu_vm_fragment_size = -1;
945 amdgpu_device_check_smu_prv_buffer_size(adev);
947 amdgpu_device_check_vm_size(adev);
949 amdgpu_device_check_block_size(adev);
951 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
952 !is_power_of_2(amdgpu_vram_page_split))) {
953 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
954 amdgpu_vram_page_split);
955 amdgpu_vram_page_split = 1024;
958 if (amdgpu_lockup_timeout == 0) {
959 dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
960 amdgpu_lockup_timeout = 10000;
963 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
967 * amdgpu_switcheroo_set_state - set switcheroo state
969 * @pdev: pci dev pointer
970 * @state: vga_switcheroo state
972 * Callback for the switcheroo driver. Suspends or resumes the
973 * the asics before or after it is powered up using ACPI methods.
975 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
977 struct drm_device *dev = pci_get_drvdata(pdev);
979 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
982 if (state == VGA_SWITCHEROO_ON) {
983 pr_info("amdgpu: switched on\n");
984 /* don't suspend or resume card normally */
985 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
987 amdgpu_device_resume(dev, true, true);
989 dev->switch_power_state = DRM_SWITCH_POWER_ON;
990 drm_kms_helper_poll_enable(dev);
992 pr_info("amdgpu: switched off\n");
993 drm_kms_helper_poll_disable(dev);
994 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
995 amdgpu_device_suspend(dev, true, true);
996 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1001 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1003 * @pdev: pci dev pointer
1005 * Callback for the switcheroo driver. Check of the switcheroo
1006 * state can be changed.
1007 * Returns true if the state can be changed, false if not.
1009 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1011 struct drm_device *dev = pci_get_drvdata(pdev);
1014 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1015 * locking inversion with the driver load path. And the access here is
1016 * completely racy anyway. So don't bother with locking for now.
1018 return dev->open_count == 0;
1021 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1022 .set_gpu_state = amdgpu_switcheroo_set_state,
1024 .can_switch = amdgpu_switcheroo_can_switch,
1028 * amdgpu_device_ip_set_clockgating_state - set the CG state
1030 * @dev: amdgpu_device pointer
1031 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1032 * @state: clockgating state (gate or ungate)
1034 * Sets the requested clockgating state for all instances of
1035 * the hardware IP specified.
1036 * Returns the error code from the last instance.
1038 int amdgpu_device_ip_set_clockgating_state(void *dev,
1039 enum amd_ip_block_type block_type,
1040 enum amd_clockgating_state state)
1042 struct amdgpu_device *adev = dev;
1045 for (i = 0; i < adev->num_ip_blocks; i++) {
1046 if (!adev->ip_blocks[i].status.valid)
1048 if (adev->ip_blocks[i].version->type != block_type)
1050 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1052 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1053 (void *)adev, state);
1055 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1056 adev->ip_blocks[i].version->funcs->name, r);
1062 * amdgpu_device_ip_set_powergating_state - set the PG state
1064 * @dev: amdgpu_device pointer
1065 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1066 * @state: powergating state (gate or ungate)
1068 * Sets the requested powergating state for all instances of
1069 * the hardware IP specified.
1070 * Returns the error code from the last instance.
1072 int amdgpu_device_ip_set_powergating_state(void *dev,
1073 enum amd_ip_block_type block_type,
1074 enum amd_powergating_state state)
1076 struct amdgpu_device *adev = dev;
1079 for (i = 0; i < adev->num_ip_blocks; i++) {
1080 if (!adev->ip_blocks[i].status.valid)
1082 if (adev->ip_blocks[i].version->type != block_type)
1084 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1086 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1087 (void *)adev, state);
1089 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1090 adev->ip_blocks[i].version->funcs->name, r);
1096 * amdgpu_device_ip_get_clockgating_state - get the CG state
1098 * @adev: amdgpu_device pointer
1099 * @flags: clockgating feature flags
1101 * Walks the list of IPs on the device and updates the clockgating
1102 * flags for each IP.
1103 * Updates @flags with the feature flags for each hardware IP where
1104 * clockgating is enabled.
1106 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1111 for (i = 0; i < adev->num_ip_blocks; i++) {
1112 if (!adev->ip_blocks[i].status.valid)
1114 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1115 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1120 * amdgpu_device_ip_wait_for_idle - wait for idle
1122 * @adev: amdgpu_device pointer
1123 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1125 * Waits for the request hardware IP to be idle.
1126 * Returns 0 for success or a negative error code on failure.
1128 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1129 enum amd_ip_block_type block_type)
1133 for (i = 0; i < adev->num_ip_blocks; i++) {
1134 if (!adev->ip_blocks[i].status.valid)
1136 if (adev->ip_blocks[i].version->type == block_type) {
1137 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1148 * amdgpu_device_ip_is_idle - is the hardware IP idle
1150 * @adev: amdgpu_device pointer
1151 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1153 * Check if the hardware IP is idle or not.
1154 * Returns true if it the IP is idle, false if not.
1156 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1157 enum amd_ip_block_type block_type)
1161 for (i = 0; i < adev->num_ip_blocks; i++) {
1162 if (!adev->ip_blocks[i].status.valid)
1164 if (adev->ip_blocks[i].version->type == block_type)
1165 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1172 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1174 * @adev: amdgpu_device pointer
1175 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1177 * Returns a pointer to the hardware IP block structure
1178 * if it exists for the asic, otherwise NULL.
1180 struct amdgpu_ip_block *
1181 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1182 enum amd_ip_block_type type)
1186 for (i = 0; i < adev->num_ip_blocks; i++)
1187 if (adev->ip_blocks[i].version->type == type)
1188 return &adev->ip_blocks[i];
1194 * amdgpu_device_ip_block_version_cmp
1196 * @adev: amdgpu_device pointer
1197 * @type: enum amd_ip_block_type
1198 * @major: major version
1199 * @minor: minor version
1201 * return 0 if equal or greater
1202 * return 1 if smaller or the ip_block doesn't exist
1204 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1205 enum amd_ip_block_type type,
1206 u32 major, u32 minor)
1208 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1210 if (ip_block && ((ip_block->version->major > major) ||
1211 ((ip_block->version->major == major) &&
1212 (ip_block->version->minor >= minor))))
1219 * amdgpu_device_ip_block_add
1221 * @adev: amdgpu_device pointer
1222 * @ip_block_version: pointer to the IP to add
1224 * Adds the IP block driver information to the collection of IPs
1227 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1228 const struct amdgpu_ip_block_version *ip_block_version)
1230 if (!ip_block_version)
1233 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1234 ip_block_version->funcs->name);
1236 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1242 * amdgpu_device_enable_virtual_display - enable virtual display feature
1244 * @adev: amdgpu_device pointer
1246 * Enabled the virtual display feature if the user has enabled it via
1247 * the module parameter virtual_display. This feature provides a virtual
1248 * display hardware on headless boards or in virtualized environments.
1249 * This function parses and validates the configuration string specified by
1250 * the user and configues the virtual display configuration (number of
1251 * virtual connectors, crtcs, etc.) specified.
1253 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1255 adev->enable_virtual_display = false;
1257 if (amdgpu_virtual_display) {
1258 struct drm_device *ddev = adev->ddev;
1259 const char *pci_address_name = pci_name(ddev->pdev);
1260 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1262 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1263 pciaddstr_tmp = pciaddstr;
1264 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1265 pciaddname = strsep(&pciaddname_tmp, ",");
1266 if (!strcmp("all", pciaddname)
1267 || !strcmp(pci_address_name, pciaddname)) {
1271 adev->enable_virtual_display = true;
1274 res = kstrtol(pciaddname_tmp, 10,
1282 adev->mode_info.num_crtc = num_crtc;
1284 adev->mode_info.num_crtc = 1;
1290 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1291 amdgpu_virtual_display, pci_address_name,
1292 adev->enable_virtual_display, adev->mode_info.num_crtc);
1299 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1301 * @adev: amdgpu_device pointer
1303 * Parses the asic configuration parameters specified in the gpu info
1304 * firmware and makes them availale to the driver for use in configuring
1306 * Returns 0 on success, -EINVAL on failure.
1308 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1310 const char *chip_name;
1313 const struct gpu_info_firmware_header_v1_0 *hdr;
1315 adev->firmware.gpu_info_fw = NULL;
1317 switch (adev->asic_type) {
1321 case CHIP_POLARIS10:
1322 case CHIP_POLARIS11:
1323 case CHIP_POLARIS12:
1327 #ifdef CONFIG_DRM_AMDGPU_SI
1334 #ifdef CONFIG_DRM_AMDGPU_CIK
1345 chip_name = "vega10";
1348 chip_name = "vega12";
1351 if (adev->rev_id >= 8)
1352 chip_name = "raven2";
1353 else if (adev->pdev->device == 0x15d8)
1354 chip_name = "picasso";
1356 chip_name = "raven";
1360 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1361 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1364 "Failed to load gpu_info firmware \"%s\"\n",
1368 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1371 "Failed to validate gpu_info firmware \"%s\"\n",
1376 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1377 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1379 switch (hdr->version_major) {
1382 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1383 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1384 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1386 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1387 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1388 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1389 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1390 adev->gfx.config.max_texture_channel_caches =
1391 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1392 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1393 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1394 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1395 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1396 adev->gfx.config.double_offchip_lds_buf =
1397 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1398 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1399 adev->gfx.cu_info.max_waves_per_simd =
1400 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1401 adev->gfx.cu_info.max_scratch_slots_per_cu =
1402 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1403 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1408 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1417 * amdgpu_device_ip_early_init - run early init for hardware IPs
1419 * @adev: amdgpu_device pointer
1421 * Early initialization pass for hardware IPs. The hardware IPs that make
1422 * up each asic are discovered each IP's early_init callback is run. This
1423 * is the first stage in initializing the asic.
1424 * Returns 0 on success, negative error code on failure.
1426 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1430 amdgpu_device_enable_virtual_display(adev);
1432 switch (adev->asic_type) {
1436 case CHIP_POLARIS10:
1437 case CHIP_POLARIS11:
1438 case CHIP_POLARIS12:
1442 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1443 adev->family = AMDGPU_FAMILY_CZ;
1445 adev->family = AMDGPU_FAMILY_VI;
1447 r = vi_set_ip_blocks(adev);
1451 #ifdef CONFIG_DRM_AMDGPU_SI
1457 adev->family = AMDGPU_FAMILY_SI;
1458 r = si_set_ip_blocks(adev);
1463 #ifdef CONFIG_DRM_AMDGPU_CIK
1469 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1470 adev->family = AMDGPU_FAMILY_CI;
1472 adev->family = AMDGPU_FAMILY_KV;
1474 r = cik_set_ip_blocks(adev);
1483 if (adev->asic_type == CHIP_RAVEN)
1484 adev->family = AMDGPU_FAMILY_RV;
1486 adev->family = AMDGPU_FAMILY_AI;
1488 r = soc15_set_ip_blocks(adev);
1493 /* FIXME: not supported yet */
1497 r = amdgpu_device_parse_gpu_info_fw(adev);
1501 amdgpu_amdkfd_device_probe(adev);
1503 if (amdgpu_sriov_vf(adev)) {
1504 r = amdgpu_virt_request_full_gpu(adev, true);
1509 adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
1511 for (i = 0; i < adev->num_ip_blocks; i++) {
1512 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1513 DRM_ERROR("disabled ip block: %d <%s>\n",
1514 i, adev->ip_blocks[i].version->funcs->name);
1515 adev->ip_blocks[i].status.valid = false;
1517 if (adev->ip_blocks[i].version->funcs->early_init) {
1518 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1520 adev->ip_blocks[i].status.valid = false;
1522 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1523 adev->ip_blocks[i].version->funcs->name, r);
1526 adev->ip_blocks[i].status.valid = true;
1529 adev->ip_blocks[i].status.valid = true;
1534 adev->cg_flags &= amdgpu_cg_mask;
1535 adev->pg_flags &= amdgpu_pg_mask;
1540 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1544 for (i = 0; i < adev->num_ip_blocks; i++) {
1545 if (!adev->ip_blocks[i].status.sw)
1547 if (adev->ip_blocks[i].status.hw)
1549 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1550 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1551 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1553 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1554 adev->ip_blocks[i].version->funcs->name, r);
1557 adev->ip_blocks[i].status.hw = true;
1564 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1568 for (i = 0; i < adev->num_ip_blocks; i++) {
1569 if (!adev->ip_blocks[i].status.sw)
1571 if (adev->ip_blocks[i].status.hw)
1573 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1575 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1576 adev->ip_blocks[i].version->funcs->name, r);
1579 adev->ip_blocks[i].status.hw = true;
1585 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1590 if (adev->asic_type >= CHIP_VEGA10) {
1591 for (i = 0; i < adev->num_ip_blocks; i++) {
1592 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
1593 if (adev->in_gpu_reset || adev->in_suspend) {
1594 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
1595 break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
1596 r = adev->ip_blocks[i].version->funcs->resume(adev);
1598 DRM_ERROR("resume of IP block <%s> failed %d\n",
1599 adev->ip_blocks[i].version->funcs->name, r);
1603 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1605 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1606 adev->ip_blocks[i].version->funcs->name, r);
1610 adev->ip_blocks[i].status.hw = true;
1615 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
1616 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
1618 pr_err("firmware loading failed\n");
1627 * amdgpu_device_ip_init - run init for hardware IPs
1629 * @adev: amdgpu_device pointer
1631 * Main initialization pass for hardware IPs. The list of all the hardware
1632 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1633 * are run. sw_init initializes the software state associated with each IP
1634 * and hw_init initializes the hardware associated with each IP.
1635 * Returns 0 on success, negative error code on failure.
1637 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1641 for (i = 0; i < adev->num_ip_blocks; i++) {
1642 if (!adev->ip_blocks[i].status.valid)
1644 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1646 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1647 adev->ip_blocks[i].version->funcs->name, r);
1650 adev->ip_blocks[i].status.sw = true;
1652 /* need to do gmc hw init early so we can allocate gpu mem */
1653 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1654 r = amdgpu_device_vram_scratch_init(adev);
1656 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1659 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1661 DRM_ERROR("hw_init %d failed %d\n", i, r);
1664 r = amdgpu_device_wb_init(adev);
1666 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1669 adev->ip_blocks[i].status.hw = true;
1671 /* right after GMC hw init, we create CSA */
1672 if (amdgpu_sriov_vf(adev)) {
1673 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1674 AMDGPU_GEM_DOMAIN_VRAM,
1677 DRM_ERROR("allocate CSA failed %d\n", r);
1684 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1688 r = amdgpu_device_ip_hw_init_phase1(adev);
1692 r = amdgpu_device_fw_loading(adev);
1696 r = amdgpu_device_ip_hw_init_phase2(adev);
1700 if (adev->gmc.xgmi.num_physical_nodes > 1)
1701 amdgpu_xgmi_add_device(adev);
1702 amdgpu_amdkfd_device_init(adev);
1704 if (amdgpu_sriov_vf(adev))
1705 amdgpu_virt_release_full_gpu(adev, true);
1711 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1713 * @adev: amdgpu_device pointer
1715 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
1716 * this function before a GPU reset. If the value is retained after a
1717 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
1719 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1721 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1725 * amdgpu_device_check_vram_lost - check if vram is valid
1727 * @adev: amdgpu_device pointer
1729 * Checks the reset magic value written to the gart pointer in VRAM.
1730 * The driver calls this after a GPU reset to see if the contents of
1731 * VRAM is lost or now.
1732 * returns true if vram is lost, false if not.
1734 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1736 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1737 AMDGPU_RESET_MAGIC_NUM);
1741 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1743 * @adev: amdgpu_device pointer
1745 * The list of all the hardware IPs that make up the asic is walked and the
1746 * set_clockgating_state callbacks are run.
1747 * Late initialization pass enabling clockgating for hardware IPs.
1748 * Fini or suspend, pass disabling clockgating for hardware IPs.
1749 * Returns 0 on success, negative error code on failure.
1752 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1753 enum amd_clockgating_state state)
1757 if (amdgpu_emu_mode == 1)
1760 for (j = 0; j < adev->num_ip_blocks; j++) {
1761 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1762 if (!adev->ip_blocks[i].status.late_initialized)
1764 /* skip CG for VCE/UVD, it's handled specially */
1765 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1766 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1767 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1768 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1769 /* enable clockgating to save power */
1770 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1773 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1774 adev->ip_blocks[i].version->funcs->name, r);
1783 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1787 if (amdgpu_emu_mode == 1)
1790 for (j = 0; j < adev->num_ip_blocks; j++) {
1791 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1792 if (!adev->ip_blocks[i].status.late_initialized)
1794 /* skip CG for VCE/UVD, it's handled specially */
1795 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1796 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1797 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1798 adev->ip_blocks[i].version->funcs->set_powergating_state) {
1799 /* enable powergating to save power */
1800 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1803 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1804 adev->ip_blocks[i].version->funcs->name, r);
1813 * amdgpu_device_ip_late_init - run late init for hardware IPs
1815 * @adev: amdgpu_device pointer
1817 * Late initialization pass for hardware IPs. The list of all the hardware
1818 * IPs that make up the asic is walked and the late_init callbacks are run.
1819 * late_init covers any special initialization that an IP requires
1820 * after all of the have been initialized or something that needs to happen
1821 * late in the init process.
1822 * Returns 0 on success, negative error code on failure.
1824 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1828 for (i = 0; i < adev->num_ip_blocks; i++) {
1829 if (!adev->ip_blocks[i].status.hw)
1831 if (adev->ip_blocks[i].version->funcs->late_init) {
1832 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1834 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1835 adev->ip_blocks[i].version->funcs->name, r);
1839 adev->ip_blocks[i].status.late_initialized = true;
1842 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
1843 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
1845 queue_delayed_work(system_wq, &adev->late_init_work,
1846 msecs_to_jiffies(AMDGPU_RESUME_MS));
1848 amdgpu_device_fill_reset_magic(adev);
1854 * amdgpu_device_ip_fini - run fini for hardware IPs
1856 * @adev: amdgpu_device pointer
1858 * Main teardown pass for hardware IPs. The list of all the hardware
1859 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
1860 * are run. hw_fini tears down the hardware associated with each IP
1861 * and sw_fini tears down any software state associated with each IP.
1862 * Returns 0 on success, negative error code on failure.
1864 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1868 if (adev->gmc.xgmi.num_physical_nodes > 1)
1869 amdgpu_xgmi_remove_device(adev);
1871 amdgpu_amdkfd_device_fini(adev);
1873 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1874 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
1876 /* need to disable SMC first */
1877 for (i = 0; i < adev->num_ip_blocks; i++) {
1878 if (!adev->ip_blocks[i].status.hw)
1880 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1881 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1882 /* XXX handle errors */
1884 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1885 adev->ip_blocks[i].version->funcs->name, r);
1887 adev->ip_blocks[i].status.hw = false;
1892 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1893 if (!adev->ip_blocks[i].status.hw)
1896 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1897 /* XXX handle errors */
1899 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1900 adev->ip_blocks[i].version->funcs->name, r);
1903 adev->ip_blocks[i].status.hw = false;
1907 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1908 if (!adev->ip_blocks[i].status.sw)
1911 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1912 amdgpu_ucode_free_bo(adev);
1913 amdgpu_free_static_csa(&adev->virt.csa_obj);
1914 amdgpu_device_wb_fini(adev);
1915 amdgpu_device_vram_scratch_fini(adev);
1918 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1919 /* XXX handle errors */
1921 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1922 adev->ip_blocks[i].version->funcs->name, r);
1924 adev->ip_blocks[i].status.sw = false;
1925 adev->ip_blocks[i].status.valid = false;
1928 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1929 if (!adev->ip_blocks[i].status.late_initialized)
1931 if (adev->ip_blocks[i].version->funcs->late_fini)
1932 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1933 adev->ip_blocks[i].status.late_initialized = false;
1936 if (amdgpu_sriov_vf(adev))
1937 if (amdgpu_virt_release_full_gpu(adev, false))
1938 DRM_ERROR("failed to release exclusive mode on fini\n");
1943 static int amdgpu_device_enable_mgpu_fan_boost(void)
1945 struct amdgpu_gpu_instance *gpu_ins;
1946 struct amdgpu_device *adev;
1949 mutex_lock(&mgpu_info.mutex);
1952 * MGPU fan boost feature should be enabled
1953 * only when there are two or more dGPUs in
1956 if (mgpu_info.num_dgpu < 2)
1959 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1960 gpu_ins = &(mgpu_info.gpu_ins[i]);
1961 adev = gpu_ins->adev;
1962 if (!(adev->flags & AMD_IS_APU) &&
1963 !gpu_ins->mgpu_fan_enabled &&
1964 adev->powerplay.pp_funcs &&
1965 adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
1966 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
1970 gpu_ins->mgpu_fan_enabled = 1;
1975 mutex_unlock(&mgpu_info.mutex);
1981 * amdgpu_device_ip_late_init_func_handler - work handler for ib test
1983 * @work: work_struct.
1985 static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
1987 struct amdgpu_device *adev =
1988 container_of(work, struct amdgpu_device, late_init_work.work);
1991 r = amdgpu_ib_ring_tests(adev);
1993 DRM_ERROR("ib ring test failed (%d).\n", r);
1995 r = amdgpu_device_enable_mgpu_fan_boost();
1997 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2000 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2002 struct amdgpu_device *adev =
2003 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2005 mutex_lock(&adev->gfx.gfx_off_mutex);
2006 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2007 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2008 adev->gfx.gfx_off_state = true;
2010 mutex_unlock(&adev->gfx.gfx_off_mutex);
2014 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2016 * @adev: amdgpu_device pointer
2018 * Main suspend function for hardware IPs. The list of all the hardware
2019 * IPs that make up the asic is walked, clockgating is disabled and the
2020 * suspend callbacks are run. suspend puts the hardware and software state
2021 * in each IP into a state suitable for suspend.
2022 * Returns 0 on success, negative error code on failure.
2024 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2028 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2029 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2031 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2032 if (!adev->ip_blocks[i].status.valid)
2034 /* displays are handled separately */
2035 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2036 /* XXX handle errors */
2037 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2038 /* XXX handle errors */
2040 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2041 adev->ip_blocks[i].version->funcs->name, r);
2050 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2052 * @adev: amdgpu_device pointer
2054 * Main suspend function for hardware IPs. The list of all the hardware
2055 * IPs that make up the asic is walked, clockgating is disabled and the
2056 * suspend callbacks are run. suspend puts the hardware and software state
2057 * in each IP into a state suitable for suspend.
2058 * Returns 0 on success, negative error code on failure.
2060 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2064 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2065 if (!adev->ip_blocks[i].status.valid)
2067 /* displays are handled in phase1 */
2068 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2070 /* XXX handle errors */
2071 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2072 /* XXX handle errors */
2074 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2075 adev->ip_blocks[i].version->funcs->name, r);
2083 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2085 * @adev: amdgpu_device pointer
2087 * Main suspend function for hardware IPs. The list of all the hardware
2088 * IPs that make up the asic is walked, clockgating is disabled and the
2089 * suspend callbacks are run. suspend puts the hardware and software state
2090 * in each IP into a state suitable for suspend.
2091 * Returns 0 on success, negative error code on failure.
2093 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2097 if (amdgpu_sriov_vf(adev))
2098 amdgpu_virt_request_full_gpu(adev, false);
2100 r = amdgpu_device_ip_suspend_phase1(adev);
2103 r = amdgpu_device_ip_suspend_phase2(adev);
2105 if (amdgpu_sriov_vf(adev))
2106 amdgpu_virt_release_full_gpu(adev, false);
2111 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2115 static enum amd_ip_block_type ip_order[] = {
2116 AMD_IP_BLOCK_TYPE_GMC,
2117 AMD_IP_BLOCK_TYPE_COMMON,
2118 AMD_IP_BLOCK_TYPE_PSP,
2119 AMD_IP_BLOCK_TYPE_IH,
2122 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2124 struct amdgpu_ip_block *block;
2126 for (j = 0; j < adev->num_ip_blocks; j++) {
2127 block = &adev->ip_blocks[j];
2129 if (block->version->type != ip_order[i] ||
2130 !block->status.valid)
2133 r = block->version->funcs->hw_init(adev);
2134 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2143 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2147 static enum amd_ip_block_type ip_order[] = {
2148 AMD_IP_BLOCK_TYPE_SMC,
2149 AMD_IP_BLOCK_TYPE_DCE,
2150 AMD_IP_BLOCK_TYPE_GFX,
2151 AMD_IP_BLOCK_TYPE_SDMA,
2152 AMD_IP_BLOCK_TYPE_UVD,
2153 AMD_IP_BLOCK_TYPE_VCE
2156 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2158 struct amdgpu_ip_block *block;
2160 for (j = 0; j < adev->num_ip_blocks; j++) {
2161 block = &adev->ip_blocks[j];
2163 if (block->version->type != ip_order[i] ||
2164 !block->status.valid)
2167 r = block->version->funcs->hw_init(adev);
2168 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2178 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2180 * @adev: amdgpu_device pointer
2182 * First resume function for hardware IPs. The list of all the hardware
2183 * IPs that make up the asic is walked and the resume callbacks are run for
2184 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2185 * after a suspend and updates the software state as necessary. This
2186 * function is also used for restoring the GPU after a GPU reset.
2187 * Returns 0 on success, negative error code on failure.
2189 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2193 for (i = 0; i < adev->num_ip_blocks; i++) {
2194 if (!adev->ip_blocks[i].status.valid)
2196 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2197 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2198 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2199 r = adev->ip_blocks[i].version->funcs->resume(adev);
2201 DRM_ERROR("resume of IP block <%s> failed %d\n",
2202 adev->ip_blocks[i].version->funcs->name, r);
2212 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2214 * @adev: amdgpu_device pointer
2216 * First resume function for hardware IPs. The list of all the hardware
2217 * IPs that make up the asic is walked and the resume callbacks are run for
2218 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2219 * functional state after a suspend and updates the software state as
2220 * necessary. This function is also used for restoring the GPU after a GPU
2222 * Returns 0 on success, negative error code on failure.
2224 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2228 for (i = 0; i < adev->num_ip_blocks; i++) {
2229 if (!adev->ip_blocks[i].status.valid)
2231 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2232 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2233 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2234 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2236 r = adev->ip_blocks[i].version->funcs->resume(adev);
2238 DRM_ERROR("resume of IP block <%s> failed %d\n",
2239 adev->ip_blocks[i].version->funcs->name, r);
2248 * amdgpu_device_ip_resume - run resume for hardware IPs
2250 * @adev: amdgpu_device pointer
2252 * Main resume function for hardware IPs. The hardware IPs
2253 * are split into two resume functions because they are
2254 * are also used in in recovering from a GPU reset and some additional
2255 * steps need to be take between them. In this case (S3/S4) they are
2257 * Returns 0 on success, negative error code on failure.
2259 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2263 r = amdgpu_device_ip_resume_phase1(adev);
2267 r = amdgpu_device_fw_loading(adev);
2271 r = amdgpu_device_ip_resume_phase2(adev);
2277 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2279 * @adev: amdgpu_device pointer
2281 * Query the VBIOS data tables to determine if the board supports SR-IOV.
2283 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2285 if (amdgpu_sriov_vf(adev)) {
2286 if (adev->is_atom_fw) {
2287 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2288 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2290 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2291 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2294 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2295 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2300 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2302 * @asic_type: AMD asic type
2304 * Check if there is DC (new modesetting infrastructre) support for an asic.
2305 * returns true if DC has support, false if not.
2307 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2309 switch (asic_type) {
2310 #if defined(CONFIG_DRM_AMD_DC)
2316 * We have systems in the wild with these ASICs that require
2317 * LVDS and VGA support which is not supported with DC.
2319 * Fallback to the non-DC driver here by default so as not to
2320 * cause regressions.
2322 return amdgpu_dc > 0;
2326 case CHIP_POLARIS10:
2327 case CHIP_POLARIS11:
2328 case CHIP_POLARIS12:
2335 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2338 return amdgpu_dc != 0;
2346 * amdgpu_device_has_dc_support - check if dc is supported
2348 * @adev: amdgpu_device_pointer
2350 * Returns true for supported, false for not supported
2352 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2354 if (amdgpu_sriov_vf(adev))
2357 return amdgpu_device_asic_has_dc_support(adev->asic_type);
2361 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2363 struct amdgpu_device *adev =
2364 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2366 adev->asic_reset_res = amdgpu_asic_reset(adev);
2367 if (adev->asic_reset_res)
2368 DRM_WARN("ASIC reset failed with err r, %d for drm dev, %s",
2369 adev->asic_reset_res, adev->ddev->unique);
2374 * amdgpu_device_init - initialize the driver
2376 * @adev: amdgpu_device pointer
2377 * @ddev: drm dev pointer
2378 * @pdev: pci dev pointer
2379 * @flags: driver flags
2381 * Initializes the driver info and hw (all asics).
2382 * Returns 0 for success or an error on failure.
2383 * Called at driver startup.
2385 int amdgpu_device_init(struct amdgpu_device *adev,
2386 struct drm_device *ddev,
2387 struct pci_dev *pdev,
2391 bool runtime = false;
2394 adev->shutdown = false;
2395 adev->dev = &pdev->dev;
2398 adev->flags = flags;
2399 adev->asic_type = flags & AMD_ASIC_MASK;
2400 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2401 if (amdgpu_emu_mode == 1)
2402 adev->usec_timeout *= 2;
2403 adev->gmc.gart_size = 512 * 1024 * 1024;
2404 adev->accel_working = false;
2405 adev->num_rings = 0;
2406 adev->mman.buffer_funcs = NULL;
2407 adev->mman.buffer_funcs_ring = NULL;
2408 adev->vm_manager.vm_pte_funcs = NULL;
2409 adev->vm_manager.vm_pte_num_rqs = 0;
2410 adev->gmc.gmc_funcs = NULL;
2411 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2412 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2414 adev->smc_rreg = &amdgpu_invalid_rreg;
2415 adev->smc_wreg = &amdgpu_invalid_wreg;
2416 adev->pcie_rreg = &amdgpu_invalid_rreg;
2417 adev->pcie_wreg = &amdgpu_invalid_wreg;
2418 adev->pciep_rreg = &amdgpu_invalid_rreg;
2419 adev->pciep_wreg = &amdgpu_invalid_wreg;
2420 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2421 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2422 adev->didt_rreg = &amdgpu_invalid_rreg;
2423 adev->didt_wreg = &amdgpu_invalid_wreg;
2424 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2425 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2426 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2427 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2429 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2430 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2431 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2433 /* mutex initialization are all done here so we
2434 * can recall function without having locking issues */
2435 atomic_set(&adev->irq.ih.lock, 0);
2436 mutex_init(&adev->firmware.mutex);
2437 mutex_init(&adev->pm.mutex);
2438 mutex_init(&adev->gfx.gpu_clock_mutex);
2439 mutex_init(&adev->srbm_mutex);
2440 mutex_init(&adev->gfx.pipe_reserve_mutex);
2441 mutex_init(&adev->gfx.gfx_off_mutex);
2442 mutex_init(&adev->grbm_idx_mutex);
2443 mutex_init(&adev->mn_lock);
2444 mutex_init(&adev->virt.vf_errors.lock);
2445 hash_init(adev->mn_hash);
2446 mutex_init(&adev->lock_reset);
2448 amdgpu_device_check_arguments(adev);
2450 spin_lock_init(&adev->mmio_idx_lock);
2451 spin_lock_init(&adev->smc_idx_lock);
2452 spin_lock_init(&adev->pcie_idx_lock);
2453 spin_lock_init(&adev->uvd_ctx_idx_lock);
2454 spin_lock_init(&adev->didt_idx_lock);
2455 spin_lock_init(&adev->gc_cac_idx_lock);
2456 spin_lock_init(&adev->se_cac_idx_lock);
2457 spin_lock_init(&adev->audio_endpt_idx_lock);
2458 spin_lock_init(&adev->mm_stats.lock);
2460 INIT_LIST_HEAD(&adev->shadow_list);
2461 mutex_init(&adev->shadow_list_lock);
2463 INIT_LIST_HEAD(&adev->ring_lru_list);
2464 spin_lock_init(&adev->ring_lru_list_lock);
2466 INIT_DELAYED_WORK(&adev->late_init_work,
2467 amdgpu_device_ip_late_init_func_handler);
2468 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2469 amdgpu_device_delay_enable_gfx_off);
2471 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2473 adev->gfx.gfx_off_req_count = 1;
2474 adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2476 /* Registers mapping */
2477 /* TODO: block userspace mapping of io register */
2478 if (adev->asic_type >= CHIP_BONAIRE) {
2479 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2480 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2482 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2483 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2486 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2487 if (adev->rmmio == NULL) {
2490 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2491 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2493 /* io port mapping */
2494 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2495 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2496 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2497 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2501 if (adev->rio_mem == NULL)
2502 DRM_INFO("PCI I/O BAR is not found.\n");
2504 amdgpu_device_get_pcie_info(adev);
2506 /* early init functions */
2507 r = amdgpu_device_ip_early_init(adev);
2511 /* doorbell bar mapping and doorbell index init*/
2512 amdgpu_device_doorbell_init(adev);
2514 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2515 /* this will fail for cards that aren't VGA class devices, just
2517 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2519 if (amdgpu_device_is_px(ddev))
2521 if (!pci_is_thunderbolt_attached(adev->pdev))
2522 vga_switcheroo_register_client(adev->pdev,
2523 &amdgpu_switcheroo_ops, runtime);
2525 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2527 if (amdgpu_emu_mode == 1) {
2528 /* post the asic on emulation mode */
2529 emu_soc_asic_init(adev);
2530 goto fence_driver_init;
2534 if (!amdgpu_get_bios(adev)) {
2539 r = amdgpu_atombios_init(adev);
2541 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2542 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2546 /* detect if we are with an SRIOV vbios */
2547 amdgpu_device_detect_sriov_bios(adev);
2549 /* Post card if necessary */
2550 if (amdgpu_device_need_post(adev)) {
2552 dev_err(adev->dev, "no vBIOS found\n");
2556 DRM_INFO("GPU posting now...\n");
2557 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2559 dev_err(adev->dev, "gpu post error!\n");
2564 if (adev->is_atom_fw) {
2565 /* Initialize clocks */
2566 r = amdgpu_atomfirmware_get_clock_info(adev);
2568 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2569 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2573 /* Initialize clocks */
2574 r = amdgpu_atombios_get_clock_info(adev);
2576 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2577 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2580 /* init i2c buses */
2581 if (!amdgpu_device_has_dc_support(adev))
2582 amdgpu_atombios_i2c_init(adev);
2587 r = amdgpu_fence_driver_init(adev);
2589 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2590 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2594 /* init the mode config */
2595 drm_mode_config_init(adev->ddev);
2597 r = amdgpu_device_ip_init(adev);
2599 /* failed in exclusive mode due to timeout */
2600 if (amdgpu_sriov_vf(adev) &&
2601 !amdgpu_sriov_runtime(adev) &&
2602 amdgpu_virt_mmio_blocked(adev) &&
2603 !amdgpu_virt_wait_reset(adev)) {
2604 dev_err(adev->dev, "VF exclusive mode timeout\n");
2605 /* Don't send request since VF is inactive. */
2606 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2607 adev->virt.ops = NULL;
2611 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2612 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2616 adev->accel_working = true;
2618 amdgpu_vm_check_compute_bug(adev);
2620 /* Initialize the buffer migration limit. */
2621 if (amdgpu_moverate >= 0)
2622 max_MBps = amdgpu_moverate;
2624 max_MBps = 8; /* Allow 8 MB/s. */
2625 /* Get a log2 for easy divisions. */
2626 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2628 r = amdgpu_ib_pool_init(adev);
2630 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2631 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2635 if (amdgpu_sriov_vf(adev))
2636 amdgpu_virt_init_data_exchange(adev);
2638 amdgpu_fbdev_init(adev);
2640 r = amdgpu_pm_sysfs_init(adev);
2642 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2644 r = amdgpu_debugfs_gem_init(adev);
2646 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2648 r = amdgpu_debugfs_regs_init(adev);
2650 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2652 r = amdgpu_debugfs_firmware_init(adev);
2654 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2656 r = amdgpu_debugfs_init(adev);
2658 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2660 if ((amdgpu_testing & 1)) {
2661 if (adev->accel_working)
2662 amdgpu_test_moves(adev);
2664 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2666 if (amdgpu_benchmarking) {
2667 if (adev->accel_working)
2668 amdgpu_benchmark(adev, amdgpu_benchmarking);
2670 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2673 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2674 * explicit gating rather than handling it automatically.
2676 r = amdgpu_device_ip_late_init(adev);
2678 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2679 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2686 amdgpu_vf_error_trans_all(adev);
2688 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2694 * amdgpu_device_fini - tear down the driver
2696 * @adev: amdgpu_device pointer
2698 * Tear down the driver info (all asics).
2699 * Called at driver shutdown.
2701 void amdgpu_device_fini(struct amdgpu_device *adev)
2705 DRM_INFO("amdgpu: finishing device.\n");
2706 adev->shutdown = true;
2707 /* disable all interrupts */
2708 amdgpu_irq_disable_all(adev);
2709 if (adev->mode_info.mode_config_initialized){
2710 if (!amdgpu_device_has_dc_support(adev))
2711 drm_crtc_force_disable_all(adev->ddev);
2713 drm_atomic_helper_shutdown(adev->ddev);
2715 amdgpu_ib_pool_fini(adev);
2716 amdgpu_fence_driver_fini(adev);
2717 amdgpu_pm_sysfs_fini(adev);
2718 amdgpu_fbdev_fini(adev);
2719 r = amdgpu_device_ip_fini(adev);
2720 if (adev->firmware.gpu_info_fw) {
2721 release_firmware(adev->firmware.gpu_info_fw);
2722 adev->firmware.gpu_info_fw = NULL;
2724 adev->accel_working = false;
2725 cancel_delayed_work_sync(&adev->late_init_work);
2726 /* free i2c buses */
2727 if (!amdgpu_device_has_dc_support(adev))
2728 amdgpu_i2c_fini(adev);
2730 if (amdgpu_emu_mode != 1)
2731 amdgpu_atombios_fini(adev);
2735 if (!pci_is_thunderbolt_attached(adev->pdev))
2736 vga_switcheroo_unregister_client(adev->pdev);
2737 if (adev->flags & AMD_IS_PX)
2738 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2739 vga_client_register(adev->pdev, NULL, NULL, NULL);
2741 pci_iounmap(adev->pdev, adev->rio_mem);
2742 adev->rio_mem = NULL;
2743 iounmap(adev->rmmio);
2745 amdgpu_device_doorbell_fini(adev);
2746 amdgpu_debugfs_regs_cleanup(adev);
2754 * amdgpu_device_suspend - initiate device suspend
2756 * @dev: drm dev pointer
2757 * @suspend: suspend state
2758 * @fbcon : notify the fbdev of suspend
2760 * Puts the hw in the suspend state (all asics).
2761 * Returns 0 for success or an error on failure.
2762 * Called at driver suspend.
2764 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2766 struct amdgpu_device *adev;
2767 struct drm_crtc *crtc;
2768 struct drm_connector *connector;
2771 if (dev == NULL || dev->dev_private == NULL) {
2775 adev = dev->dev_private;
2777 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2780 adev->in_suspend = true;
2781 drm_kms_helper_poll_disable(dev);
2784 amdgpu_fbdev_set_suspend(adev, 1);
2786 cancel_delayed_work_sync(&adev->late_init_work);
2788 if (!amdgpu_device_has_dc_support(adev)) {
2789 /* turn off display hw */
2790 drm_modeset_lock_all(dev);
2791 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2792 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2794 drm_modeset_unlock_all(dev);
2795 /* unpin the front buffers and cursors */
2796 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2797 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2798 struct drm_framebuffer *fb = crtc->primary->fb;
2799 struct amdgpu_bo *robj;
2801 if (amdgpu_crtc->cursor_bo) {
2802 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2803 r = amdgpu_bo_reserve(aobj, true);
2805 amdgpu_bo_unpin(aobj);
2806 amdgpu_bo_unreserve(aobj);
2810 if (fb == NULL || fb->obj[0] == NULL) {
2813 robj = gem_to_amdgpu_bo(fb->obj[0]);
2814 /* don't unpin kernel fb objects */
2815 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2816 r = amdgpu_bo_reserve(robj, true);
2818 amdgpu_bo_unpin(robj);
2819 amdgpu_bo_unreserve(robj);
2825 amdgpu_amdkfd_suspend(adev);
2827 r = amdgpu_device_ip_suspend_phase1(adev);
2829 /* evict vram memory */
2830 amdgpu_bo_evict_vram(adev);
2832 amdgpu_fence_driver_suspend(adev);
2834 r = amdgpu_device_ip_suspend_phase2(adev);
2836 /* evict remaining vram memory
2837 * This second call to evict vram is to evict the gart page table
2840 amdgpu_bo_evict_vram(adev);
2842 pci_save_state(dev->pdev);
2844 /* Shut down the device */
2845 pci_disable_device(dev->pdev);
2846 pci_set_power_state(dev->pdev, PCI_D3hot);
2848 r = amdgpu_asic_reset(adev);
2850 DRM_ERROR("amdgpu asic reset failed\n");
2857 * amdgpu_device_resume - initiate device resume
2859 * @dev: drm dev pointer
2860 * @resume: resume state
2861 * @fbcon : notify the fbdev of resume
2863 * Bring the hw back to operating state (all asics).
2864 * Returns 0 for success or an error on failure.
2865 * Called at driver resume.
2867 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2869 struct drm_connector *connector;
2870 struct amdgpu_device *adev = dev->dev_private;
2871 struct drm_crtc *crtc;
2874 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2878 pci_set_power_state(dev->pdev, PCI_D0);
2879 pci_restore_state(dev->pdev);
2880 r = pci_enable_device(dev->pdev);
2886 if (amdgpu_device_need_post(adev)) {
2887 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2889 DRM_ERROR("amdgpu asic init failed\n");
2892 r = amdgpu_device_ip_resume(adev);
2894 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2897 amdgpu_fence_driver_resume(adev);
2900 r = amdgpu_device_ip_late_init(adev);
2904 if (!amdgpu_device_has_dc_support(adev)) {
2906 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2907 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2909 if (amdgpu_crtc->cursor_bo) {
2910 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2911 r = amdgpu_bo_reserve(aobj, true);
2913 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2915 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2916 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2917 amdgpu_bo_unreserve(aobj);
2922 r = amdgpu_amdkfd_resume(adev);
2926 /* Make sure IB tests flushed */
2927 flush_delayed_work(&adev->late_init_work);
2929 /* blat the mode back in */
2931 if (!amdgpu_device_has_dc_support(adev)) {
2933 drm_helper_resume_force_mode(dev);
2935 /* turn on display hw */
2936 drm_modeset_lock_all(dev);
2937 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2938 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2940 drm_modeset_unlock_all(dev);
2942 amdgpu_fbdev_set_suspend(adev, 0);
2945 drm_kms_helper_poll_enable(dev);
2948 * Most of the connector probing functions try to acquire runtime pm
2949 * refs to ensure that the GPU is powered on when connector polling is
2950 * performed. Since we're calling this from a runtime PM callback,
2951 * trying to acquire rpm refs will cause us to deadlock.
2953 * Since we're guaranteed to be holding the rpm lock, it's safe to
2954 * temporarily disable the rpm helpers so this doesn't deadlock us.
2957 dev->dev->power.disable_depth++;
2959 if (!amdgpu_device_has_dc_support(adev))
2960 drm_helper_hpd_irq_event(dev);
2962 drm_kms_helper_hotplug_event(dev);
2964 dev->dev->power.disable_depth--;
2966 adev->in_suspend = false;
2972 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
2974 * @adev: amdgpu_device pointer
2976 * The list of all the hardware IPs that make up the asic is walked and
2977 * the check_soft_reset callbacks are run. check_soft_reset determines
2978 * if the asic is still hung or not.
2979 * Returns true if any of the IPs are still in a hung state, false if not.
2981 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
2984 bool asic_hang = false;
2986 if (amdgpu_sriov_vf(adev))
2989 if (amdgpu_asic_need_full_reset(adev))
2992 for (i = 0; i < adev->num_ip_blocks; i++) {
2993 if (!adev->ip_blocks[i].status.valid)
2995 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2996 adev->ip_blocks[i].status.hang =
2997 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2998 if (adev->ip_blocks[i].status.hang) {
2999 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3007 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3009 * @adev: amdgpu_device pointer
3011 * The list of all the hardware IPs that make up the asic is walked and the
3012 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3013 * handles any IP specific hardware or software state changes that are
3014 * necessary for a soft reset to succeed.
3015 * Returns 0 on success, negative error code on failure.
3017 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3021 for (i = 0; i < adev->num_ip_blocks; i++) {
3022 if (!adev->ip_blocks[i].status.valid)
3024 if (adev->ip_blocks[i].status.hang &&
3025 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3026 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3036 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3038 * @adev: amdgpu_device pointer
3040 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
3041 * reset is necessary to recover.
3042 * Returns true if a full asic reset is required, false if not.
3044 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3048 if (amdgpu_asic_need_full_reset(adev))
3051 for (i = 0; i < adev->num_ip_blocks; i++) {
3052 if (!adev->ip_blocks[i].status.valid)
3054 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3055 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3056 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3057 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3058 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3059 if (adev->ip_blocks[i].status.hang) {
3060 DRM_INFO("Some block need full reset!\n");
3069 * amdgpu_device_ip_soft_reset - do a soft reset
3071 * @adev: amdgpu_device pointer
3073 * The list of all the hardware IPs that make up the asic is walked and the
3074 * soft_reset callbacks are run if the block is hung. soft_reset handles any
3075 * IP specific hardware or software state changes that are necessary to soft
3077 * Returns 0 on success, negative error code on failure.
3079 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3083 for (i = 0; i < adev->num_ip_blocks; i++) {
3084 if (!adev->ip_blocks[i].status.valid)
3086 if (adev->ip_blocks[i].status.hang &&
3087 adev->ip_blocks[i].version->funcs->soft_reset) {
3088 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3098 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3100 * @adev: amdgpu_device pointer
3102 * The list of all the hardware IPs that make up the asic is walked and the
3103 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
3104 * handles any IP specific hardware or software state changes that are
3105 * necessary after the IP has been soft reset.
3106 * Returns 0 on success, negative error code on failure.
3108 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3112 for (i = 0; i < adev->num_ip_blocks; i++) {
3113 if (!adev->ip_blocks[i].status.valid)
3115 if (adev->ip_blocks[i].status.hang &&
3116 adev->ip_blocks[i].version->funcs->post_soft_reset)
3117 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3126 * amdgpu_device_recover_vram - Recover some VRAM contents
3128 * @adev: amdgpu_device pointer
3130 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
3131 * restore things like GPUVM page tables after a GPU reset where
3132 * the contents of VRAM might be lost.
3135 * 0 on success, negative error code on failure.
3137 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3139 struct dma_fence *fence = NULL, *next = NULL;
3140 struct amdgpu_bo *shadow;
3143 if (amdgpu_sriov_runtime(adev))
3144 tmo = msecs_to_jiffies(8000);
3146 tmo = msecs_to_jiffies(100);
3148 DRM_INFO("recover vram bo from shadow start\n");
3149 mutex_lock(&adev->shadow_list_lock);
3150 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3152 /* No need to recover an evicted BO */
3153 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3154 shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3157 r = amdgpu_bo_restore_shadow(shadow, &next);
3162 r = dma_fence_wait_timeout(fence, false, tmo);
3163 dma_fence_put(fence);
3171 mutex_unlock(&adev->shadow_list_lock);
3174 tmo = dma_fence_wait_timeout(fence, false, tmo);
3175 dma_fence_put(fence);
3177 if (r <= 0 || tmo <= 0) {
3178 DRM_ERROR("recover vram bo from shadow failed\n");
3182 DRM_INFO("recover vram bo from shadow done\n");
3188 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3190 * @adev: amdgpu device pointer
3191 * @from_hypervisor: request from hypervisor
3193 * do VF FLR and reinitialize Asic
3194 * return 0 means succeeded otherwise failed
3196 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3197 bool from_hypervisor)
3201 if (from_hypervisor)
3202 r = amdgpu_virt_request_full_gpu(adev, true);
3204 r = amdgpu_virt_reset_gpu(adev);
3208 /* Resume IP prior to SMC */
3209 r = amdgpu_device_ip_reinit_early_sriov(adev);
3213 /* we need recover gart prior to run SMC/CP/SDMA resume */
3214 amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3216 r = amdgpu_device_fw_loading(adev);
3220 /* now we are okay to resume SMC/CP/SDMA */
3221 r = amdgpu_device_ip_reinit_late_sriov(adev);
3225 amdgpu_irq_gpu_reset_resume_helper(adev);
3226 r = amdgpu_ib_ring_tests(adev);
3229 amdgpu_virt_release_full_gpu(adev, true);
3230 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3231 atomic_inc(&adev->vram_lost_counter);
3232 r = amdgpu_device_recover_vram(adev);
3239 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3241 * @adev: amdgpu device pointer
3243 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3246 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3248 if (!amdgpu_device_ip_check_soft_reset(adev)) {
3249 DRM_INFO("Timeout, but no hardware hang detected.\n");
3253 if (amdgpu_gpu_recovery == 0)
3256 if (amdgpu_sriov_vf(adev))
3259 if (amdgpu_gpu_recovery == -1) {
3260 switch (adev->asic_type) {
3266 case CHIP_POLARIS10:
3267 case CHIP_POLARIS11:
3268 case CHIP_POLARIS12:
3282 DRM_INFO("GPU recovery disabled.\n");
3287 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3288 struct amdgpu_job *job,
3289 bool *need_full_reset_arg)
3292 bool need_full_reset = *need_full_reset_arg;
3294 /* block all schedulers and reset given job's ring */
3295 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3296 struct amdgpu_ring *ring = adev->rings[i];
3298 if (!ring || !ring->sched.thread)
3301 kthread_park(ring->sched.thread);
3303 if (job && job->base.sched != &ring->sched)
3306 drm_sched_hw_job_reset(&ring->sched, job ? &job->base : NULL);
3308 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3309 amdgpu_fence_driver_force_completion(ring);
3314 if (!amdgpu_sriov_vf(adev)) {
3316 if (!need_full_reset)
3317 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3319 if (!need_full_reset) {
3320 amdgpu_device_ip_pre_soft_reset(adev);
3321 r = amdgpu_device_ip_soft_reset(adev);
3322 amdgpu_device_ip_post_soft_reset(adev);
3323 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3324 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3325 need_full_reset = true;
3329 if (need_full_reset)
3330 r = amdgpu_device_ip_suspend(adev);
3332 *need_full_reset_arg = need_full_reset;
3338 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3339 struct list_head *device_list_handle,
3340 bool *need_full_reset_arg)
3342 struct amdgpu_device *tmp_adev = NULL;
3343 bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3347 * ASIC reset has to be done on all HGMI hive nodes ASAP
3348 * to allow proper links negotiation in FW (within 1 sec)
3350 if (need_full_reset) {
3351 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3352 /* For XGMI run all resets in parallel to speed up the process */
3353 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3354 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3357 r = amdgpu_asic_reset(tmp_adev);
3360 DRM_ERROR("ASIC reset failed with err r, %d for drm dev, %s",
3361 r, tmp_adev->ddev->unique);
3366 /* For XGMI wait for all PSP resets to complete before proceed */
3368 list_for_each_entry(tmp_adev, device_list_handle,
3370 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3371 flush_work(&tmp_adev->xgmi_reset_work);
3372 r = tmp_adev->asic_reset_res;
3381 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3382 if (need_full_reset) {
3384 if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3385 DRM_WARN("asic atom init failed!");
3388 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3389 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3393 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3395 DRM_ERROR("VRAM is lost!\n");
3396 atomic_inc(&tmp_adev->vram_lost_counter);
3399 r = amdgpu_gtt_mgr_recover(
3400 &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3404 r = amdgpu_device_fw_loading(tmp_adev);
3408 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3413 amdgpu_device_fill_reset_magic(tmp_adev);
3415 /* Update PSP FW topology after reset */
3416 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3417 r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3424 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3425 r = amdgpu_ib_ring_tests(tmp_adev);
3427 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3428 r = amdgpu_device_ip_suspend(tmp_adev);
3429 need_full_reset = true;
3436 r = amdgpu_device_recover_vram(tmp_adev);
3438 tmp_adev->asic_reset_res = r;
3442 *need_full_reset_arg = need_full_reset;
3446 static void amdgpu_device_post_asic_reset(struct amdgpu_device *adev,
3447 struct amdgpu_job *job)
3451 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3452 struct amdgpu_ring *ring = adev->rings[i];
3454 if (!ring || !ring->sched.thread)
3457 /* only need recovery sched of the given job's ring
3458 * or all rings (in the case @job is NULL)
3459 * after above amdgpu_reset accomplished
3461 if ((!job || job->base.sched == &ring->sched) && !adev->asic_reset_res)
3462 drm_sched_job_recovery(&ring->sched);
3464 kthread_unpark(ring->sched.thread);
3467 if (!amdgpu_device_has_dc_support(adev)) {
3468 drm_helper_resume_force_mode(adev->ddev);
3471 adev->asic_reset_res = 0;
3474 static void amdgpu_device_lock_adev(struct amdgpu_device *adev)
3476 mutex_lock(&adev->lock_reset);
3477 atomic_inc(&adev->gpu_reset_counter);
3478 adev->in_gpu_reset = 1;
3480 amdgpu_amdkfd_pre_reset(adev);
3483 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3486 amdgpu_amdkfd_post_reset(adev);
3487 amdgpu_vf_error_trans_all(adev);
3488 adev->in_gpu_reset = 0;
3489 mutex_unlock(&adev->lock_reset);
3494 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3496 * @adev: amdgpu device pointer
3497 * @job: which job trigger hang
3499 * Attempt to reset the GPU if it has hung (all asics).
3500 * Attempt to do soft-reset or full-reset and reinitialize Asic
3501 * Returns 0 for success or an error on failure.
3504 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3505 struct amdgpu_job *job)
3508 struct amdgpu_hive_info *hive = NULL;
3509 bool need_full_reset = false;
3510 struct amdgpu_device *tmp_adev = NULL;
3511 struct list_head device_list, *device_list_handle = NULL;
3513 INIT_LIST_HEAD(&device_list);
3515 dev_info(adev->dev, "GPU reset begin!\n");
3518 * In case of XGMI hive disallow concurrent resets to be triggered
3519 * by different nodes. No point also since the one node already executing
3520 * reset will also reset all the other nodes in the hive.
3522 hive = amdgpu_get_xgmi_hive(adev);
3523 if (hive && adev->gmc.xgmi.num_physical_nodes > 1 &&
3524 !mutex_trylock(&hive->hive_lock))
3527 /* Start with adev pre asic reset first for soft reset check.*/
3528 amdgpu_device_lock_adev(adev);
3529 r = amdgpu_device_pre_asic_reset(adev,
3533 /*TODO Should we stop ?*/
3534 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3535 r, adev->ddev->unique);
3536 adev->asic_reset_res = r;
3539 /* Build list of devices to reset */
3540 if (need_full_reset && adev->gmc.xgmi.num_physical_nodes > 1) {
3542 amdgpu_device_unlock_adev(adev);
3547 * In case we are in XGMI hive mode device reset is done for all the
3548 * nodes in the hive to retrain all XGMI links and hence the reset
3549 * sequence is executed in loop on all nodes.
3551 device_list_handle = &hive->device_list;
3553 list_add_tail(&adev->gmc.xgmi.head, &device_list);
3554 device_list_handle = &device_list;
3557 retry: /* Rest of adevs pre asic reset from XGMI hive. */
3558 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3560 if (tmp_adev == adev)
3563 amdgpu_device_lock_adev(tmp_adev);
3564 r = amdgpu_device_pre_asic_reset(tmp_adev,
3567 /*TODO Should we stop ?*/
3569 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3570 r, tmp_adev->ddev->unique);
3571 tmp_adev->asic_reset_res = r;
3575 /* Actual ASIC resets if needed.*/
3576 /* TODO Implement XGMI hive reset logic for SRIOV */
3577 if (amdgpu_sriov_vf(adev)) {
3578 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3580 adev->asic_reset_res = r;
3582 r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
3583 if (r && r == -EAGAIN)
3587 /* Post ASIC reset for all devs .*/
3588 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3589 amdgpu_device_post_asic_reset(tmp_adev, tmp_adev == adev ? job : NULL);
3592 /* bad news, how to tell it to userspace ? */
3593 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3594 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3596 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
3599 amdgpu_device_unlock_adev(tmp_adev);
3602 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
3603 mutex_unlock(&hive->hive_lock);
3606 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
3611 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3613 * @adev: amdgpu_device pointer
3615 * Fetchs and stores in the driver the PCIE capabilities (gen speed
3616 * and lanes) of the slot the device is in. Handles APUs and
3617 * virtualized environments where PCIE config space may not be available.
3619 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3621 struct pci_dev *pdev;
3622 enum pci_bus_speed speed_cap;
3623 enum pcie_link_width link_width;
3625 if (amdgpu_pcie_gen_cap)
3626 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3628 if (amdgpu_pcie_lane_cap)
3629 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3631 /* covers APUs as well */
3632 if (pci_is_root_bus(adev->pdev->bus)) {
3633 if (adev->pm.pcie_gen_mask == 0)
3634 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3635 if (adev->pm.pcie_mlw_mask == 0)
3636 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3640 if (adev->pm.pcie_gen_mask == 0) {
3643 speed_cap = pcie_get_speed_cap(pdev);
3644 if (speed_cap == PCI_SPEED_UNKNOWN) {
3645 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3646 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3647 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3649 if (speed_cap == PCIE_SPEED_16_0GT)
3650 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3651 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3652 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3653 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
3654 else if (speed_cap == PCIE_SPEED_8_0GT)
3655 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3656 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3657 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3658 else if (speed_cap == PCIE_SPEED_5_0GT)
3659 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3660 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
3662 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
3665 pdev = adev->ddev->pdev->bus->self;
3666 speed_cap = pcie_get_speed_cap(pdev);
3667 if (speed_cap == PCI_SPEED_UNKNOWN) {
3668 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3669 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3671 if (speed_cap == PCIE_SPEED_16_0GT)
3672 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3673 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3674 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3675 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3676 else if (speed_cap == PCIE_SPEED_8_0GT)
3677 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3678 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3679 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3680 else if (speed_cap == PCIE_SPEED_5_0GT)
3681 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3682 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3684 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3688 if (adev->pm.pcie_mlw_mask == 0) {
3689 pdev = adev->ddev->pdev->bus->self;
3690 link_width = pcie_get_width_cap(pdev);
3691 if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3692 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
3694 switch (link_width) {
3696 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3697 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3698 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3699 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3700 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3701 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3702 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3705 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3706 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3707 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3708 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3709 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3710 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3713 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3714 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3715 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3716 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3717 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3720 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3721 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3722 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3723 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3726 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3727 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3728 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3731 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3732 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3735 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;