2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/amdgpu_drm.h>
37 #include <linux/vgaarb.h>
38 #include <linux/vga_switcheroo.h>
39 #include <linux/efi.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_i2c.h"
44 #include "amdgpu_atombios.h"
45 #include "amdgpu_atomfirmware.h"
47 #ifdef CONFIG_DRM_AMDGPU_SI
50 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #include "bif/bif_4_1_d.h"
57 #include <linux/pci.h>
58 #include <linux/firmware.h>
59 #include "amdgpu_vf_error.h"
61 #include "amdgpu_amdkfd.h"
62 #include "amdgpu_pm.h"
64 #include "amdgpu_xgmi.h"
65 #include "amdgpu_ras.h"
66 #include "amdgpu_pmu.h"
67 #include "amdgpu_fru_eeprom.h"
69 #include <linux/suspend.h>
70 #include <drm/task_barrier.h>
71 #include <linux/pm_runtime.h>
73 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
74 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
75 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
76 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
77 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
78 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
79 MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
80 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
81 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
82 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
83 MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
85 #define AMDGPU_RESUME_MS 2000
87 const char *amdgpu_asic_name[] = {
124 * DOC: pcie_replay_count
126 * The amdgpu driver provides a sysfs API for reporting the total number
127 * of PCIe replays (NAKs)
128 * The file pcie_replay_count is used for this and returns the total
129 * number of replays as a sum of the NAKs generated and NAKs received
132 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
133 struct device_attribute *attr, char *buf)
135 struct drm_device *ddev = dev_get_drvdata(dev);
136 struct amdgpu_device *adev = drm_to_adev(ddev);
137 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
139 return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
142 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
143 amdgpu_device_get_pcie_replay_count, NULL);
145 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
150 * The amdgpu driver provides a sysfs API for reporting the product name
152 * The file serial_number is used for this and returns the product name
153 * as returned from the FRU.
154 * NOTE: This is only available for certain server cards
157 static ssize_t amdgpu_device_get_product_name(struct device *dev,
158 struct device_attribute *attr, char *buf)
160 struct drm_device *ddev = dev_get_drvdata(dev);
161 struct amdgpu_device *adev = drm_to_adev(ddev);
163 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name);
166 static DEVICE_ATTR(product_name, S_IRUGO,
167 amdgpu_device_get_product_name, NULL);
170 * DOC: product_number
172 * The amdgpu driver provides a sysfs API for reporting the part number
174 * The file serial_number is used for this and returns the part number
175 * as returned from the FRU.
176 * NOTE: This is only available for certain server cards
179 static ssize_t amdgpu_device_get_product_number(struct device *dev,
180 struct device_attribute *attr, char *buf)
182 struct drm_device *ddev = dev_get_drvdata(dev);
183 struct amdgpu_device *adev = drm_to_adev(ddev);
185 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number);
188 static DEVICE_ATTR(product_number, S_IRUGO,
189 amdgpu_device_get_product_number, NULL);
194 * The amdgpu driver provides a sysfs API for reporting the serial number
196 * The file serial_number is used for this and returns the serial number
197 * as returned from the FRU.
198 * NOTE: This is only available for certain server cards
201 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
202 struct device_attribute *attr, char *buf)
204 struct drm_device *ddev = dev_get_drvdata(dev);
205 struct amdgpu_device *adev = drm_to_adev(ddev);
207 return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial);
210 static DEVICE_ATTR(serial_number, S_IRUGO,
211 amdgpu_device_get_serial_number, NULL);
214 * amdgpu_device_supports_atpx - Is the device a dGPU with HG/PX power control
216 * @dev: drm_device pointer
218 * Returns true if the device is a dGPU with HG/PX power control,
219 * otherwise return false.
221 bool amdgpu_device_supports_atpx(struct drm_device *dev)
223 struct amdgpu_device *adev = drm_to_adev(dev);
225 if (adev->flags & AMD_IS_PX)
231 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
233 * @dev: drm_device pointer
235 * Returns true if the device is a dGPU with HG/PX power control,
236 * otherwise return false.
238 bool amdgpu_device_supports_boco(struct drm_device *dev)
240 struct amdgpu_device *adev = drm_to_adev(dev);
248 * amdgpu_device_supports_baco - Does the device support BACO
250 * @dev: drm_device pointer
252 * Returns true if the device supporte BACO,
253 * otherwise return false.
255 bool amdgpu_device_supports_baco(struct drm_device *dev)
257 struct amdgpu_device *adev = drm_to_adev(dev);
259 return amdgpu_asic_supports_baco(adev);
263 * VRAM access helper functions
267 * amdgpu_device_vram_access - read/write a buffer in vram
269 * @adev: amdgpu_device pointer
270 * @pos: offset of the buffer in vram
271 * @buf: virtual address of the buffer in system memory
272 * @size: read/write size, sizeof(@buf) must > @size
273 * @write: true - write to vram, otherwise - read from vram
275 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
276 uint32_t *buf, size_t size, bool write)
284 last = min(pos + size, adev->gmc.visible_vram_size);
286 void __iomem *addr = adev->mman.aper_base_kaddr + pos;
287 size_t count = last - pos;
290 memcpy_toio(addr, buf, count);
292 amdgpu_asic_flush_hdp(adev, NULL);
294 amdgpu_asic_invalidate_hdp(adev, NULL);
296 memcpy_fromio(buf, addr, count);
308 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
309 for (last = pos + size; pos < last; pos += 4) {
310 uint32_t tmp = pos >> 31;
312 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
314 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
318 WREG32_NO_KIQ(mmMM_DATA, *buf++);
320 *buf++ = RREG32_NO_KIQ(mmMM_DATA);
322 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
326 * register access helper functions.
329 * amdgpu_device_rreg - read a memory mapped IO or indirect register
331 * @adev: amdgpu_device pointer
332 * @reg: dword aligned register offset
333 * @acc_flags: access flags which require special behavior
335 * Returns the 32 bit value from the offset specified.
337 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
338 uint32_t reg, uint32_t acc_flags)
342 if (adev->in_pci_err_recovery)
345 if ((reg * 4) < adev->rmmio_size) {
346 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
347 amdgpu_sriov_runtime(adev) &&
348 down_read_trylock(&adev->reset_sem)) {
349 ret = amdgpu_kiq_rreg(adev, reg);
350 up_read(&adev->reset_sem);
352 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
355 ret = adev->pcie_rreg(adev, reg * 4);
358 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
364 * MMIO register read with bytes helper functions
365 * @offset:bytes offset from MMIO start
370 * amdgpu_mm_rreg8 - read a memory mapped IO register
372 * @adev: amdgpu_device pointer
373 * @offset: byte aligned register offset
375 * Returns the 8 bit value from the offset specified.
377 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
379 if (adev->in_pci_err_recovery)
382 if (offset < adev->rmmio_size)
383 return (readb(adev->rmmio + offset));
388 * MMIO register write with bytes helper functions
389 * @offset:bytes offset from MMIO start
390 * @value: the value want to be written to the register
394 * amdgpu_mm_wreg8 - read a memory mapped IO register
396 * @adev: amdgpu_device pointer
397 * @offset: byte aligned register offset
398 * @value: 8 bit value to write
400 * Writes the value specified to the offset specified.
402 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
404 if (adev->in_pci_err_recovery)
407 if (offset < adev->rmmio_size)
408 writeb(value, adev->rmmio + offset);
414 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
416 * @adev: amdgpu_device pointer
417 * @reg: dword aligned register offset
418 * @v: 32 bit value to write to the register
419 * @acc_flags: access flags which require special behavior
421 * Writes the value specified to the offset specified.
423 void amdgpu_device_wreg(struct amdgpu_device *adev,
424 uint32_t reg, uint32_t v,
427 if (adev->in_pci_err_recovery)
430 if ((reg * 4) < adev->rmmio_size) {
431 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
432 amdgpu_sriov_runtime(adev) &&
433 down_read_trylock(&adev->reset_sem)) {
434 amdgpu_kiq_wreg(adev, reg, v);
435 up_read(&adev->reset_sem);
437 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
440 adev->pcie_wreg(adev, reg * 4, v);
443 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
447 * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range
449 * this function is invoked only the debugfs register access
451 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
452 uint32_t reg, uint32_t v)
454 if (adev->in_pci_err_recovery)
457 if (amdgpu_sriov_fullaccess(adev) &&
458 adev->gfx.rlc.funcs &&
459 adev->gfx.rlc.funcs->is_rlcg_access_range) {
460 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
461 return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);
463 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
468 * amdgpu_io_rreg - read an IO register
470 * @adev: amdgpu_device pointer
471 * @reg: dword aligned register offset
473 * Returns the 32 bit value from the offset specified.
475 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
477 if (adev->in_pci_err_recovery)
480 if ((reg * 4) < adev->rio_mem_size)
481 return ioread32(adev->rio_mem + (reg * 4));
483 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
484 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
489 * amdgpu_io_wreg - write to an IO register
491 * @adev: amdgpu_device pointer
492 * @reg: dword aligned register offset
493 * @v: 32 bit value to write to the register
495 * Writes the value specified to the offset specified.
497 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
499 if (adev->in_pci_err_recovery)
502 if ((reg * 4) < adev->rio_mem_size)
503 iowrite32(v, adev->rio_mem + (reg * 4));
505 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
506 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
511 * amdgpu_mm_rdoorbell - read a doorbell dword
513 * @adev: amdgpu_device pointer
514 * @index: doorbell index
516 * Returns the value in the doorbell aperture at the
517 * requested doorbell index (CIK).
519 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
521 if (adev->in_pci_err_recovery)
524 if (index < adev->doorbell.num_doorbells) {
525 return readl(adev->doorbell.ptr + index);
527 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
533 * amdgpu_mm_wdoorbell - write a doorbell dword
535 * @adev: amdgpu_device pointer
536 * @index: doorbell index
539 * Writes @v to the doorbell aperture at the
540 * requested doorbell index (CIK).
542 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
544 if (adev->in_pci_err_recovery)
547 if (index < adev->doorbell.num_doorbells) {
548 writel(v, adev->doorbell.ptr + index);
550 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
555 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
557 * @adev: amdgpu_device pointer
558 * @index: doorbell index
560 * Returns the value in the doorbell aperture at the
561 * requested doorbell index (VEGA10+).
563 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
565 if (adev->in_pci_err_recovery)
568 if (index < adev->doorbell.num_doorbells) {
569 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
571 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
577 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
579 * @adev: amdgpu_device pointer
580 * @index: doorbell index
583 * Writes @v to the doorbell aperture at the
584 * requested doorbell index (VEGA10+).
586 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
588 if (adev->in_pci_err_recovery)
591 if (index < adev->doorbell.num_doorbells) {
592 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
594 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
599 * amdgpu_device_indirect_rreg - read an indirect register
601 * @adev: amdgpu_device pointer
602 * @pcie_index: mmio register offset
603 * @pcie_data: mmio register offset
604 * @reg_addr: indirect register address to read from
606 * Returns the value of indirect register @reg_addr
608 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
609 u32 pcie_index, u32 pcie_data,
614 void __iomem *pcie_index_offset;
615 void __iomem *pcie_data_offset;
617 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
618 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
619 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
621 writel(reg_addr, pcie_index_offset);
622 readl(pcie_index_offset);
623 r = readl(pcie_data_offset);
624 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
630 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
632 * @adev: amdgpu_device pointer
633 * @pcie_index: mmio register offset
634 * @pcie_data: mmio register offset
635 * @reg_addr: indirect register address to read from
637 * Returns the value of indirect register @reg_addr
639 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
640 u32 pcie_index, u32 pcie_data,
645 void __iomem *pcie_index_offset;
646 void __iomem *pcie_data_offset;
648 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
649 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
650 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
652 /* read low 32 bits */
653 writel(reg_addr, pcie_index_offset);
654 readl(pcie_index_offset);
655 r = readl(pcie_data_offset);
656 /* read high 32 bits */
657 writel(reg_addr + 4, pcie_index_offset);
658 readl(pcie_index_offset);
659 r |= ((u64)readl(pcie_data_offset) << 32);
660 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
666 * amdgpu_device_indirect_wreg - write an indirect register address
668 * @adev: amdgpu_device pointer
669 * @pcie_index: mmio register offset
670 * @pcie_data: mmio register offset
671 * @reg_addr: indirect register offset
672 * @reg_data: indirect register data
675 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
676 u32 pcie_index, u32 pcie_data,
677 u32 reg_addr, u32 reg_data)
680 void __iomem *pcie_index_offset;
681 void __iomem *pcie_data_offset;
683 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
684 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
685 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
687 writel(reg_addr, pcie_index_offset);
688 readl(pcie_index_offset);
689 writel(reg_data, pcie_data_offset);
690 readl(pcie_data_offset);
691 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
695 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
697 * @adev: amdgpu_device pointer
698 * @pcie_index: mmio register offset
699 * @pcie_data: mmio register offset
700 * @reg_addr: indirect register offset
701 * @reg_data: indirect register data
704 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
705 u32 pcie_index, u32 pcie_data,
706 u32 reg_addr, u64 reg_data)
709 void __iomem *pcie_index_offset;
710 void __iomem *pcie_data_offset;
712 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
713 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
714 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
716 /* write low 32 bits */
717 writel(reg_addr, pcie_index_offset);
718 readl(pcie_index_offset);
719 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
720 readl(pcie_data_offset);
721 /* write high 32 bits */
722 writel(reg_addr + 4, pcie_index_offset);
723 readl(pcie_index_offset);
724 writel((u32)(reg_data >> 32), pcie_data_offset);
725 readl(pcie_data_offset);
726 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
730 * amdgpu_invalid_rreg - dummy reg read function
732 * @adev: amdgpu_device pointer
733 * @reg: offset of register
735 * Dummy register read function. Used for register blocks
736 * that certain asics don't have (all asics).
737 * Returns the value in the register.
739 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
741 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
747 * amdgpu_invalid_wreg - dummy reg write function
749 * @adev: amdgpu_device pointer
750 * @reg: offset of register
751 * @v: value to write to the register
753 * Dummy register read function. Used for register blocks
754 * that certain asics don't have (all asics).
756 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
758 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
764 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
766 * @adev: amdgpu_device pointer
767 * @reg: offset of register
769 * Dummy register read function. Used for register blocks
770 * that certain asics don't have (all asics).
771 * Returns the value in the register.
773 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
775 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
781 * amdgpu_invalid_wreg64 - dummy reg write function
783 * @adev: amdgpu_device pointer
784 * @reg: offset of register
785 * @v: value to write to the register
787 * Dummy register read function. Used for register blocks
788 * that certain asics don't have (all asics).
790 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
792 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
798 * amdgpu_block_invalid_rreg - dummy reg read function
800 * @adev: amdgpu_device pointer
801 * @block: offset of instance
802 * @reg: offset of register
804 * Dummy register read function. Used for register blocks
805 * that certain asics don't have (all asics).
806 * Returns the value in the register.
808 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
809 uint32_t block, uint32_t reg)
811 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
818 * amdgpu_block_invalid_wreg - dummy reg write function
820 * @adev: amdgpu_device pointer
821 * @block: offset of instance
822 * @reg: offset of register
823 * @v: value to write to the register
825 * Dummy register read function. Used for register blocks
826 * that certain asics don't have (all asics).
828 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
830 uint32_t reg, uint32_t v)
832 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
838 * amdgpu_device_asic_init - Wrapper for atom asic_init
840 * @adev: amdgpu_device pointer
842 * Does any asic specific work and then calls atom asic init.
844 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
846 amdgpu_asic_pre_asic_init(adev);
848 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
852 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
854 * @adev: amdgpu_device pointer
856 * Allocates a scratch page of VRAM for use by various things in the
859 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
861 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
862 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
863 &adev->vram_scratch.robj,
864 &adev->vram_scratch.gpu_addr,
865 (void **)&adev->vram_scratch.ptr);
869 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
871 * @adev: amdgpu_device pointer
873 * Frees the VRAM scratch page.
875 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
877 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
881 * amdgpu_device_program_register_sequence - program an array of registers.
883 * @adev: amdgpu_device pointer
884 * @registers: pointer to the register array
885 * @array_size: size of the register array
887 * Programs an array or registers with and and or masks.
888 * This is a helper for setting golden registers.
890 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
891 const u32 *registers,
892 const u32 array_size)
894 u32 tmp, reg, and_mask, or_mask;
900 for (i = 0; i < array_size; i +=3) {
901 reg = registers[i + 0];
902 and_mask = registers[i + 1];
903 or_mask = registers[i + 2];
905 if (and_mask == 0xffffffff) {
910 if (adev->family >= AMDGPU_FAMILY_AI)
911 tmp |= (or_mask & and_mask);
920 * amdgpu_device_pci_config_reset - reset the GPU
922 * @adev: amdgpu_device pointer
924 * Resets the GPU using the pci config reset sequence.
925 * Only applicable to asics prior to vega10.
927 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
929 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
933 * GPU doorbell aperture helpers function.
936 * amdgpu_device_doorbell_init - Init doorbell driver information.
938 * @adev: amdgpu_device pointer
940 * Init doorbell driver information (CIK)
941 * Returns 0 on success, error on failure.
943 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
946 /* No doorbell on SI hardware generation */
947 if (adev->asic_type < CHIP_BONAIRE) {
948 adev->doorbell.base = 0;
949 adev->doorbell.size = 0;
950 adev->doorbell.num_doorbells = 0;
951 adev->doorbell.ptr = NULL;
955 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
958 amdgpu_asic_init_doorbell_index(adev);
960 /* doorbell bar mapping */
961 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
962 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
964 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
965 adev->doorbell_index.max_assignment+1);
966 if (adev->doorbell.num_doorbells == 0)
969 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
970 * paging queue doorbell use the second page. The
971 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
972 * doorbells are in the first page. So with paging queue enabled,
973 * the max num_doorbells should + 1 page (0x400 in dword)
975 if (adev->asic_type >= CHIP_VEGA10)
976 adev->doorbell.num_doorbells += 0x400;
978 adev->doorbell.ptr = ioremap(adev->doorbell.base,
979 adev->doorbell.num_doorbells *
981 if (adev->doorbell.ptr == NULL)
988 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
990 * @adev: amdgpu_device pointer
992 * Tear down doorbell driver information (CIK)
994 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
996 iounmap(adev->doorbell.ptr);
997 adev->doorbell.ptr = NULL;
1003 * amdgpu_device_wb_*()
1004 * Writeback is the method by which the GPU updates special pages in memory
1005 * with the status of certain GPU events (fences, ring pointers,etc.).
1009 * amdgpu_device_wb_fini - Disable Writeback and free memory
1011 * @adev: amdgpu_device pointer
1013 * Disables Writeback and frees the Writeback memory (all asics).
1014 * Used at driver shutdown.
1016 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1018 if (adev->wb.wb_obj) {
1019 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1021 (void **)&adev->wb.wb);
1022 adev->wb.wb_obj = NULL;
1027 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
1029 * @adev: amdgpu_device pointer
1031 * Initializes writeback and allocates writeback memory (all asics).
1032 * Used at driver startup.
1033 * Returns 0 on success or an -error on failure.
1035 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1039 if (adev->wb.wb_obj == NULL) {
1040 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1041 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1042 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1043 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1044 (void **)&adev->wb.wb);
1046 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1050 adev->wb.num_wb = AMDGPU_MAX_WB;
1051 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1053 /* clear wb memory */
1054 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1061 * amdgpu_device_wb_get - Allocate a wb entry
1063 * @adev: amdgpu_device pointer
1066 * Allocate a wb slot for use by the driver (all asics).
1067 * Returns 0 on success or -EINVAL on failure.
1069 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1071 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1073 if (offset < adev->wb.num_wb) {
1074 __set_bit(offset, adev->wb.used);
1075 *wb = offset << 3; /* convert to dw offset */
1083 * amdgpu_device_wb_free - Free a wb entry
1085 * @adev: amdgpu_device pointer
1088 * Free a wb slot allocated for use by the driver (all asics)
1090 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1093 if (wb < adev->wb.num_wb)
1094 __clear_bit(wb, adev->wb.used);
1098 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1100 * @adev: amdgpu_device pointer
1102 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1103 * to fail, but if any of the BARs is not accessible after the size we abort
1104 * driver loading by returning -ENODEV.
1106 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1108 u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
1109 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
1110 struct pci_bus *root;
1111 struct resource *res;
1117 if (amdgpu_sriov_vf(adev))
1120 /* skip if the bios has already enabled large BAR */
1121 if (adev->gmc.real_vram_size &&
1122 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1125 /* Check if the root BUS has 64bit memory resources */
1126 root = adev->pdev->bus;
1127 while (root->parent)
1128 root = root->parent;
1130 pci_bus_for_each_resource(root, res, i) {
1131 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1132 res->start > 0x100000000ull)
1136 /* Trying to resize is pointless without a root hub window above 4GB */
1140 /* Disable memory decoding while we change the BAR addresses and size */
1141 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1142 pci_write_config_word(adev->pdev, PCI_COMMAND,
1143 cmd & ~PCI_COMMAND_MEMORY);
1145 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1146 amdgpu_device_doorbell_fini(adev);
1147 if (adev->asic_type >= CHIP_BONAIRE)
1148 pci_release_resource(adev->pdev, 2);
1150 pci_release_resource(adev->pdev, 0);
1152 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1154 DRM_INFO("Not enough PCI address space for a large BAR.");
1155 else if (r && r != -ENOTSUPP)
1156 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1158 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1160 /* When the doorbell or fb BAR isn't available we have no chance of
1163 r = amdgpu_device_doorbell_init(adev);
1164 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1167 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1173 * GPU helpers function.
1176 * amdgpu_device_need_post - check if the hw need post or not
1178 * @adev: amdgpu_device pointer
1180 * Check if the asic has been initialized (all asics) at driver startup
1181 * or post is needed if hw reset is performed.
1182 * Returns true if need or false if not.
1184 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1188 if (amdgpu_sriov_vf(adev))
1191 if (amdgpu_passthrough(adev)) {
1192 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1193 * some old smc fw still need driver do vPost otherwise gpu hang, while
1194 * those smc fw version above 22.15 doesn't have this flaw, so we force
1195 * vpost executed for smc version below 22.15
1197 if (adev->asic_type == CHIP_FIJI) {
1200 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1201 /* force vPost if error occured */
1205 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1206 if (fw_ver < 0x00160e00)
1211 if (adev->has_hw_reset) {
1212 adev->has_hw_reset = false;
1216 /* bios scratch used on CIK+ */
1217 if (adev->asic_type >= CHIP_BONAIRE)
1218 return amdgpu_atombios_scratch_need_asic_init(adev);
1220 /* check MEM_SIZE for older asics */
1221 reg = amdgpu_asic_get_config_memsize(adev);
1223 if ((reg != 0) && (reg != 0xffffffff))
1229 /* if we get transitioned to only one device, take VGA back */
1231 * amdgpu_device_vga_set_decode - enable/disable vga decode
1233 * @cookie: amdgpu_device pointer
1234 * @state: enable/disable vga decode
1236 * Enable/disable vga decode (all asics).
1237 * Returns VGA resource flags.
1239 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
1241 struct amdgpu_device *adev = cookie;
1242 amdgpu_asic_set_vga_state(adev, state);
1244 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1245 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1247 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1251 * amdgpu_device_check_block_size - validate the vm block size
1253 * @adev: amdgpu_device pointer
1255 * Validates the vm block size specified via module parameter.
1256 * The vm block size defines number of bits in page table versus page directory,
1257 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1258 * page table and the remaining bits are in the page directory.
1260 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1262 /* defines number of bits in page table versus page directory,
1263 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1264 * page table and the remaining bits are in the page directory */
1265 if (amdgpu_vm_block_size == -1)
1268 if (amdgpu_vm_block_size < 9) {
1269 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1270 amdgpu_vm_block_size);
1271 amdgpu_vm_block_size = -1;
1276 * amdgpu_device_check_vm_size - validate the vm size
1278 * @adev: amdgpu_device pointer
1280 * Validates the vm size in GB specified via module parameter.
1281 * The VM size is the size of the GPU virtual memory space in GB.
1283 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1285 /* no need to check the default value */
1286 if (amdgpu_vm_size == -1)
1289 if (amdgpu_vm_size < 1) {
1290 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1292 amdgpu_vm_size = -1;
1296 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1299 bool is_os_64 = (sizeof(void *) == 8);
1300 uint64_t total_memory;
1301 uint64_t dram_size_seven_GB = 0x1B8000000;
1302 uint64_t dram_size_three_GB = 0xB8000000;
1304 if (amdgpu_smu_memory_pool_size == 0)
1308 DRM_WARN("Not 64-bit OS, feature not supported\n");
1312 total_memory = (uint64_t)si.totalram * si.mem_unit;
1314 if ((amdgpu_smu_memory_pool_size == 1) ||
1315 (amdgpu_smu_memory_pool_size == 2)) {
1316 if (total_memory < dram_size_three_GB)
1318 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1319 (amdgpu_smu_memory_pool_size == 8)) {
1320 if (total_memory < dram_size_seven_GB)
1323 DRM_WARN("Smu memory pool size not supported\n");
1326 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1331 DRM_WARN("No enough system memory\n");
1333 adev->pm.smu_prv_buffer_size = 0;
1337 * amdgpu_device_check_arguments - validate module params
1339 * @adev: amdgpu_device pointer
1341 * Validates certain module parameters and updates
1342 * the associated values used by the driver (all asics).
1344 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1346 if (amdgpu_sched_jobs < 4) {
1347 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1349 amdgpu_sched_jobs = 4;
1350 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1351 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1353 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1356 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1357 /* gart size must be greater or equal to 32M */
1358 dev_warn(adev->dev, "gart size (%d) too small\n",
1360 amdgpu_gart_size = -1;
1363 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1364 /* gtt size must be greater or equal to 32M */
1365 dev_warn(adev->dev, "gtt size (%d) too small\n",
1367 amdgpu_gtt_size = -1;
1370 /* valid range is between 4 and 9 inclusive */
1371 if (amdgpu_vm_fragment_size != -1 &&
1372 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1373 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1374 amdgpu_vm_fragment_size = -1;
1377 if (amdgpu_sched_hw_submission < 2) {
1378 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1379 amdgpu_sched_hw_submission);
1380 amdgpu_sched_hw_submission = 2;
1381 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1382 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1383 amdgpu_sched_hw_submission);
1384 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1387 amdgpu_device_check_smu_prv_buffer_size(adev);
1389 amdgpu_device_check_vm_size(adev);
1391 amdgpu_device_check_block_size(adev);
1393 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1395 amdgpu_gmc_tmz_set(adev);
1397 amdgpu_gmc_noretry_set(adev);
1403 * amdgpu_switcheroo_set_state - set switcheroo state
1405 * @pdev: pci dev pointer
1406 * @state: vga_switcheroo state
1408 * Callback for the switcheroo driver. Suspends or resumes the
1409 * the asics before or after it is powered up using ACPI methods.
1411 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1412 enum vga_switcheroo_state state)
1414 struct drm_device *dev = pci_get_drvdata(pdev);
1417 if (amdgpu_device_supports_atpx(dev) && state == VGA_SWITCHEROO_OFF)
1420 if (state == VGA_SWITCHEROO_ON) {
1421 pr_info("switched on\n");
1422 /* don't suspend or resume card normally */
1423 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1425 pci_set_power_state(dev->pdev, PCI_D0);
1426 amdgpu_device_load_pci_state(dev->pdev);
1427 r = pci_enable_device(dev->pdev);
1429 DRM_WARN("pci_enable_device failed (%d)\n", r);
1430 amdgpu_device_resume(dev, true);
1432 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1433 drm_kms_helper_poll_enable(dev);
1435 pr_info("switched off\n");
1436 drm_kms_helper_poll_disable(dev);
1437 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1438 amdgpu_device_suspend(dev, true);
1439 amdgpu_device_cache_pci_state(dev->pdev);
1440 /* Shut down the device */
1441 pci_disable_device(dev->pdev);
1442 pci_set_power_state(dev->pdev, PCI_D3cold);
1443 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1448 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1450 * @pdev: pci dev pointer
1452 * Callback for the switcheroo driver. Check of the switcheroo
1453 * state can be changed.
1454 * Returns true if the state can be changed, false if not.
1456 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1458 struct drm_device *dev = pci_get_drvdata(pdev);
1461 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1462 * locking inversion with the driver load path. And the access here is
1463 * completely racy anyway. So don't bother with locking for now.
1465 return atomic_read(&dev->open_count) == 0;
1468 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1469 .set_gpu_state = amdgpu_switcheroo_set_state,
1471 .can_switch = amdgpu_switcheroo_can_switch,
1475 * amdgpu_device_ip_set_clockgating_state - set the CG state
1477 * @dev: amdgpu_device pointer
1478 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1479 * @state: clockgating state (gate or ungate)
1481 * Sets the requested clockgating state for all instances of
1482 * the hardware IP specified.
1483 * Returns the error code from the last instance.
1485 int amdgpu_device_ip_set_clockgating_state(void *dev,
1486 enum amd_ip_block_type block_type,
1487 enum amd_clockgating_state state)
1489 struct amdgpu_device *adev = dev;
1492 for (i = 0; i < adev->num_ip_blocks; i++) {
1493 if (!adev->ip_blocks[i].status.valid)
1495 if (adev->ip_blocks[i].version->type != block_type)
1497 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1499 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1500 (void *)adev, state);
1502 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1503 adev->ip_blocks[i].version->funcs->name, r);
1509 * amdgpu_device_ip_set_powergating_state - set the PG state
1511 * @dev: amdgpu_device pointer
1512 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1513 * @state: powergating state (gate or ungate)
1515 * Sets the requested powergating state for all instances of
1516 * the hardware IP specified.
1517 * Returns the error code from the last instance.
1519 int amdgpu_device_ip_set_powergating_state(void *dev,
1520 enum amd_ip_block_type block_type,
1521 enum amd_powergating_state state)
1523 struct amdgpu_device *adev = dev;
1526 for (i = 0; i < adev->num_ip_blocks; i++) {
1527 if (!adev->ip_blocks[i].status.valid)
1529 if (adev->ip_blocks[i].version->type != block_type)
1531 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1533 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1534 (void *)adev, state);
1536 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1537 adev->ip_blocks[i].version->funcs->name, r);
1543 * amdgpu_device_ip_get_clockgating_state - get the CG state
1545 * @adev: amdgpu_device pointer
1546 * @flags: clockgating feature flags
1548 * Walks the list of IPs on the device and updates the clockgating
1549 * flags for each IP.
1550 * Updates @flags with the feature flags for each hardware IP where
1551 * clockgating is enabled.
1553 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1558 for (i = 0; i < adev->num_ip_blocks; i++) {
1559 if (!adev->ip_blocks[i].status.valid)
1561 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1562 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1567 * amdgpu_device_ip_wait_for_idle - wait for idle
1569 * @adev: amdgpu_device pointer
1570 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1572 * Waits for the request hardware IP to be idle.
1573 * Returns 0 for success or a negative error code on failure.
1575 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1576 enum amd_ip_block_type block_type)
1580 for (i = 0; i < adev->num_ip_blocks; i++) {
1581 if (!adev->ip_blocks[i].status.valid)
1583 if (adev->ip_blocks[i].version->type == block_type) {
1584 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1595 * amdgpu_device_ip_is_idle - is the hardware IP idle
1597 * @adev: amdgpu_device pointer
1598 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1600 * Check if the hardware IP is idle or not.
1601 * Returns true if it the IP is idle, false if not.
1603 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1604 enum amd_ip_block_type block_type)
1608 for (i = 0; i < adev->num_ip_blocks; i++) {
1609 if (!adev->ip_blocks[i].status.valid)
1611 if (adev->ip_blocks[i].version->type == block_type)
1612 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1619 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1621 * @adev: amdgpu_device pointer
1622 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1624 * Returns a pointer to the hardware IP block structure
1625 * if it exists for the asic, otherwise NULL.
1627 struct amdgpu_ip_block *
1628 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1629 enum amd_ip_block_type type)
1633 for (i = 0; i < adev->num_ip_blocks; i++)
1634 if (adev->ip_blocks[i].version->type == type)
1635 return &adev->ip_blocks[i];
1641 * amdgpu_device_ip_block_version_cmp
1643 * @adev: amdgpu_device pointer
1644 * @type: enum amd_ip_block_type
1645 * @major: major version
1646 * @minor: minor version
1648 * return 0 if equal or greater
1649 * return 1 if smaller or the ip_block doesn't exist
1651 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1652 enum amd_ip_block_type type,
1653 u32 major, u32 minor)
1655 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1657 if (ip_block && ((ip_block->version->major > major) ||
1658 ((ip_block->version->major == major) &&
1659 (ip_block->version->minor >= minor))))
1666 * amdgpu_device_ip_block_add
1668 * @adev: amdgpu_device pointer
1669 * @ip_block_version: pointer to the IP to add
1671 * Adds the IP block driver information to the collection of IPs
1674 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1675 const struct amdgpu_ip_block_version *ip_block_version)
1677 if (!ip_block_version)
1680 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1681 ip_block_version->funcs->name);
1683 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1689 * amdgpu_device_enable_virtual_display - enable virtual display feature
1691 * @adev: amdgpu_device pointer
1693 * Enabled the virtual display feature if the user has enabled it via
1694 * the module parameter virtual_display. This feature provides a virtual
1695 * display hardware on headless boards or in virtualized environments.
1696 * This function parses and validates the configuration string specified by
1697 * the user and configues the virtual display configuration (number of
1698 * virtual connectors, crtcs, etc.) specified.
1700 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1702 adev->enable_virtual_display = false;
1704 if (amdgpu_virtual_display) {
1705 struct drm_device *ddev = adev_to_drm(adev);
1706 const char *pci_address_name = pci_name(ddev->pdev);
1707 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1709 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1710 pciaddstr_tmp = pciaddstr;
1711 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1712 pciaddname = strsep(&pciaddname_tmp, ",");
1713 if (!strcmp("all", pciaddname)
1714 || !strcmp(pci_address_name, pciaddname)) {
1718 adev->enable_virtual_display = true;
1721 res = kstrtol(pciaddname_tmp, 10,
1729 adev->mode_info.num_crtc = num_crtc;
1731 adev->mode_info.num_crtc = 1;
1737 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1738 amdgpu_virtual_display, pci_address_name,
1739 adev->enable_virtual_display, adev->mode_info.num_crtc);
1746 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1748 * @adev: amdgpu_device pointer
1750 * Parses the asic configuration parameters specified in the gpu info
1751 * firmware and makes them availale to the driver for use in configuring
1753 * Returns 0 on success, -EINVAL on failure.
1755 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1757 const char *chip_name;
1760 const struct gpu_info_firmware_header_v1_0 *hdr;
1762 adev->firmware.gpu_info_fw = NULL;
1764 if (adev->mman.discovery_bin) {
1765 amdgpu_discovery_get_gfx_info(adev);
1768 * FIXME: The bounding box is still needed by Navi12, so
1769 * temporarily read it from gpu_info firmware. Should be droped
1770 * when DAL no longer needs it.
1772 if (adev->asic_type != CHIP_NAVI12)
1776 switch (adev->asic_type) {
1777 #ifdef CONFIG_DRM_AMDGPU_SI
1784 #ifdef CONFIG_DRM_AMDGPU_CIK
1794 case CHIP_POLARIS10:
1795 case CHIP_POLARIS11:
1796 case CHIP_POLARIS12:
1801 case CHIP_SIENNA_CICHLID:
1802 case CHIP_NAVY_FLOUNDER:
1803 case CHIP_DIMGREY_CAVEFISH:
1807 chip_name = "vega10";
1810 chip_name = "vega12";
1813 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1814 chip_name = "raven2";
1815 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1816 chip_name = "picasso";
1818 chip_name = "raven";
1821 chip_name = "arcturus";
1824 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1825 chip_name = "renoir";
1827 chip_name = "green_sardine";
1830 chip_name = "navi10";
1833 chip_name = "navi14";
1836 chip_name = "navi12";
1839 chip_name = "vangogh";
1843 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1844 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1847 "Failed to load gpu_info firmware \"%s\"\n",
1851 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1854 "Failed to validate gpu_info firmware \"%s\"\n",
1859 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1860 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1862 switch (hdr->version_major) {
1865 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1866 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1867 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1870 * Should be droped when DAL no longer needs it.
1872 if (adev->asic_type == CHIP_NAVI12)
1873 goto parse_soc_bounding_box;
1875 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1876 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1877 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1878 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1879 adev->gfx.config.max_texture_channel_caches =
1880 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1881 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1882 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1883 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1884 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1885 adev->gfx.config.double_offchip_lds_buf =
1886 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1887 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1888 adev->gfx.cu_info.max_waves_per_simd =
1889 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1890 adev->gfx.cu_info.max_scratch_slots_per_cu =
1891 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1892 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1893 if (hdr->version_minor >= 1) {
1894 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1895 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1896 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1897 adev->gfx.config.num_sc_per_sh =
1898 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1899 adev->gfx.config.num_packer_per_sc =
1900 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1903 parse_soc_bounding_box:
1905 * soc bounding box info is not integrated in disocovery table,
1906 * we always need to parse it from gpu info firmware if needed.
1908 if (hdr->version_minor == 2) {
1909 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1910 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1911 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1912 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1918 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1927 * amdgpu_device_ip_early_init - run early init for hardware IPs
1929 * @adev: amdgpu_device pointer
1931 * Early initialization pass for hardware IPs. The hardware IPs that make
1932 * up each asic are discovered each IP's early_init callback is run. This
1933 * is the first stage in initializing the asic.
1934 * Returns 0 on success, negative error code on failure.
1936 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1940 amdgpu_device_enable_virtual_display(adev);
1942 if (amdgpu_sriov_vf(adev)) {
1943 r = amdgpu_virt_request_full_gpu(adev, true);
1948 switch (adev->asic_type) {
1949 #ifdef CONFIG_DRM_AMDGPU_SI
1955 adev->family = AMDGPU_FAMILY_SI;
1956 r = si_set_ip_blocks(adev);
1961 #ifdef CONFIG_DRM_AMDGPU_CIK
1967 if (adev->flags & AMD_IS_APU)
1968 adev->family = AMDGPU_FAMILY_KV;
1970 adev->family = AMDGPU_FAMILY_CI;
1972 r = cik_set_ip_blocks(adev);
1980 case CHIP_POLARIS10:
1981 case CHIP_POLARIS11:
1982 case CHIP_POLARIS12:
1986 if (adev->flags & AMD_IS_APU)
1987 adev->family = AMDGPU_FAMILY_CZ;
1989 adev->family = AMDGPU_FAMILY_VI;
1991 r = vi_set_ip_blocks(adev);
2001 if (adev->flags & AMD_IS_APU)
2002 adev->family = AMDGPU_FAMILY_RV;
2004 adev->family = AMDGPU_FAMILY_AI;
2006 r = soc15_set_ip_blocks(adev);
2013 case CHIP_SIENNA_CICHLID:
2014 case CHIP_NAVY_FLOUNDER:
2015 case CHIP_DIMGREY_CAVEFISH:
2017 if (adev->asic_type == CHIP_VANGOGH)
2018 adev->family = AMDGPU_FAMILY_VGH;
2020 adev->family = AMDGPU_FAMILY_NV;
2022 r = nv_set_ip_blocks(adev);
2027 /* FIXME: not supported yet */
2031 amdgpu_amdkfd_device_probe(adev);
2033 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2034 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2035 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2037 for (i = 0; i < adev->num_ip_blocks; i++) {
2038 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2039 DRM_ERROR("disabled ip block: %d <%s>\n",
2040 i, adev->ip_blocks[i].version->funcs->name);
2041 adev->ip_blocks[i].status.valid = false;
2043 if (adev->ip_blocks[i].version->funcs->early_init) {
2044 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2046 adev->ip_blocks[i].status.valid = false;
2048 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2049 adev->ip_blocks[i].version->funcs->name, r);
2052 adev->ip_blocks[i].status.valid = true;
2055 adev->ip_blocks[i].status.valid = true;
2058 /* get the vbios after the asic_funcs are set up */
2059 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2060 r = amdgpu_device_parse_gpu_info_fw(adev);
2065 if (!amdgpu_get_bios(adev))
2068 r = amdgpu_atombios_init(adev);
2070 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2071 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2077 adev->cg_flags &= amdgpu_cg_mask;
2078 adev->pg_flags &= amdgpu_pg_mask;
2083 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2087 for (i = 0; i < adev->num_ip_blocks; i++) {
2088 if (!adev->ip_blocks[i].status.sw)
2090 if (adev->ip_blocks[i].status.hw)
2092 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2093 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2094 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2095 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2097 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2098 adev->ip_blocks[i].version->funcs->name, r);
2101 adev->ip_blocks[i].status.hw = true;
2108 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2112 for (i = 0; i < adev->num_ip_blocks; i++) {
2113 if (!adev->ip_blocks[i].status.sw)
2115 if (adev->ip_blocks[i].status.hw)
2117 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2119 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2120 adev->ip_blocks[i].version->funcs->name, r);
2123 adev->ip_blocks[i].status.hw = true;
2129 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2133 uint32_t smu_version;
2135 if (adev->asic_type >= CHIP_VEGA10) {
2136 for (i = 0; i < adev->num_ip_blocks; i++) {
2137 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2140 /* no need to do the fw loading again if already done*/
2141 if (adev->ip_blocks[i].status.hw == true)
2144 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2145 r = adev->ip_blocks[i].version->funcs->resume(adev);
2147 DRM_ERROR("resume of IP block <%s> failed %d\n",
2148 adev->ip_blocks[i].version->funcs->name, r);
2152 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2154 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2155 adev->ip_blocks[i].version->funcs->name, r);
2160 adev->ip_blocks[i].status.hw = true;
2165 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2166 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2172 * amdgpu_device_ip_init - run init for hardware IPs
2174 * @adev: amdgpu_device pointer
2176 * Main initialization pass for hardware IPs. The list of all the hardware
2177 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2178 * are run. sw_init initializes the software state associated with each IP
2179 * and hw_init initializes the hardware associated with each IP.
2180 * Returns 0 on success, negative error code on failure.
2182 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2186 r = amdgpu_ras_init(adev);
2190 for (i = 0; i < adev->num_ip_blocks; i++) {
2191 if (!adev->ip_blocks[i].status.valid)
2193 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2195 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2196 adev->ip_blocks[i].version->funcs->name, r);
2199 adev->ip_blocks[i].status.sw = true;
2201 /* need to do gmc hw init early so we can allocate gpu mem */
2202 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2203 r = amdgpu_device_vram_scratch_init(adev);
2205 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
2208 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2210 DRM_ERROR("hw_init %d failed %d\n", i, r);
2213 r = amdgpu_device_wb_init(adev);
2215 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2218 adev->ip_blocks[i].status.hw = true;
2220 /* right after GMC hw init, we create CSA */
2221 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
2222 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2223 AMDGPU_GEM_DOMAIN_VRAM,
2226 DRM_ERROR("allocate CSA failed %d\n", r);
2233 if (amdgpu_sriov_vf(adev))
2234 amdgpu_virt_init_data_exchange(adev);
2236 r = amdgpu_ib_pool_init(adev);
2238 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2239 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2243 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2247 r = amdgpu_device_ip_hw_init_phase1(adev);
2251 r = amdgpu_device_fw_loading(adev);
2255 r = amdgpu_device_ip_hw_init_phase2(adev);
2260 * retired pages will be loaded from eeprom and reserved here,
2261 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2262 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2263 * for I2C communication which only true at this point.
2265 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2266 * failure from bad gpu situation and stop amdgpu init process
2267 * accordingly. For other failed cases, it will still release all
2268 * the resource and print error message, rather than returning one
2269 * negative value to upper level.
2271 * Note: theoretically, this should be called before all vram allocations
2272 * to protect retired page from abusing
2274 r = amdgpu_ras_recovery_init(adev);
2278 if (adev->gmc.xgmi.num_physical_nodes > 1)
2279 amdgpu_xgmi_add_device(adev);
2280 amdgpu_amdkfd_device_init(adev);
2282 amdgpu_fru_get_product_info(adev);
2285 if (amdgpu_sriov_vf(adev))
2286 amdgpu_virt_release_full_gpu(adev, true);
2292 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2294 * @adev: amdgpu_device pointer
2296 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2297 * this function before a GPU reset. If the value is retained after a
2298 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2300 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2302 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2306 * amdgpu_device_check_vram_lost - check if vram is valid
2308 * @adev: amdgpu_device pointer
2310 * Checks the reset magic value written to the gart pointer in VRAM.
2311 * The driver calls this after a GPU reset to see if the contents of
2312 * VRAM is lost or now.
2313 * returns true if vram is lost, false if not.
2315 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2317 if (memcmp(adev->gart.ptr, adev->reset_magic,
2318 AMDGPU_RESET_MAGIC_NUM))
2321 if (!amdgpu_in_reset(adev))
2325 * For all ASICs with baco/mode1 reset, the VRAM is
2326 * always assumed to be lost.
2328 switch (amdgpu_asic_reset_method(adev)) {
2329 case AMD_RESET_METHOD_BACO:
2330 case AMD_RESET_METHOD_MODE1:
2338 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2340 * @adev: amdgpu_device pointer
2341 * @state: clockgating state (gate or ungate)
2343 * The list of all the hardware IPs that make up the asic is walked and the
2344 * set_clockgating_state callbacks are run.
2345 * Late initialization pass enabling clockgating for hardware IPs.
2346 * Fini or suspend, pass disabling clockgating for hardware IPs.
2347 * Returns 0 on success, negative error code on failure.
2350 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2351 enum amd_clockgating_state state)
2355 if (amdgpu_emu_mode == 1)
2358 for (j = 0; j < adev->num_ip_blocks; j++) {
2359 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2360 if (!adev->ip_blocks[i].status.late_initialized)
2362 /* skip CG for VCE/UVD, it's handled specially */
2363 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2364 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2365 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2366 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2367 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2368 /* enable clockgating to save power */
2369 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2372 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2373 adev->ip_blocks[i].version->funcs->name, r);
2382 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
2386 if (amdgpu_emu_mode == 1)
2389 for (j = 0; j < adev->num_ip_blocks; j++) {
2390 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2391 if (!adev->ip_blocks[i].status.late_initialized)
2393 /* skip CG for VCE/UVD, it's handled specially */
2394 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2395 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2396 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2397 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2398 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2399 /* enable powergating to save power */
2400 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2403 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2404 adev->ip_blocks[i].version->funcs->name, r);
2412 static int amdgpu_device_enable_mgpu_fan_boost(void)
2414 struct amdgpu_gpu_instance *gpu_ins;
2415 struct amdgpu_device *adev;
2418 mutex_lock(&mgpu_info.mutex);
2421 * MGPU fan boost feature should be enabled
2422 * only when there are two or more dGPUs in
2425 if (mgpu_info.num_dgpu < 2)
2428 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2429 gpu_ins = &(mgpu_info.gpu_ins[i]);
2430 adev = gpu_ins->adev;
2431 if (!(adev->flags & AMD_IS_APU) &&
2432 !gpu_ins->mgpu_fan_enabled) {
2433 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2437 gpu_ins->mgpu_fan_enabled = 1;
2442 mutex_unlock(&mgpu_info.mutex);
2448 * amdgpu_device_ip_late_init - run late init for hardware IPs
2450 * @adev: amdgpu_device pointer
2452 * Late initialization pass for hardware IPs. The list of all the hardware
2453 * IPs that make up the asic is walked and the late_init callbacks are run.
2454 * late_init covers any special initialization that an IP requires
2455 * after all of the have been initialized or something that needs to happen
2456 * late in the init process.
2457 * Returns 0 on success, negative error code on failure.
2459 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2461 struct amdgpu_gpu_instance *gpu_instance;
2464 for (i = 0; i < adev->num_ip_blocks; i++) {
2465 if (!adev->ip_blocks[i].status.hw)
2467 if (adev->ip_blocks[i].version->funcs->late_init) {
2468 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2470 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2471 adev->ip_blocks[i].version->funcs->name, r);
2475 adev->ip_blocks[i].status.late_initialized = true;
2478 amdgpu_ras_set_error_query_ready(adev, true);
2480 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2481 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2483 amdgpu_device_fill_reset_magic(adev);
2485 r = amdgpu_device_enable_mgpu_fan_boost();
2487 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2490 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2491 mutex_lock(&mgpu_info.mutex);
2494 * Reset device p-state to low as this was booted with high.
2496 * This should be performed only after all devices from the same
2497 * hive get initialized.
2499 * However, it's unknown how many device in the hive in advance.
2500 * As this is counted one by one during devices initializations.
2502 * So, we wait for all XGMI interlinked devices initialized.
2503 * This may bring some delays as those devices may come from
2504 * different hives. But that should be OK.
2506 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2507 for (i = 0; i < mgpu_info.num_gpu; i++) {
2508 gpu_instance = &(mgpu_info.gpu_ins[i]);
2509 if (gpu_instance->adev->flags & AMD_IS_APU)
2512 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2513 AMDGPU_XGMI_PSTATE_MIN);
2515 DRM_ERROR("pstate setting failed (%d).\n", r);
2521 mutex_unlock(&mgpu_info.mutex);
2528 * amdgpu_device_ip_fini - run fini for hardware IPs
2530 * @adev: amdgpu_device pointer
2532 * Main teardown pass for hardware IPs. The list of all the hardware
2533 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2534 * are run. hw_fini tears down the hardware associated with each IP
2535 * and sw_fini tears down any software state associated with each IP.
2536 * Returns 0 on success, negative error code on failure.
2538 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2542 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2543 amdgpu_virt_release_ras_err_handler_data(adev);
2545 amdgpu_ras_pre_fini(adev);
2547 if (adev->gmc.xgmi.num_physical_nodes > 1)
2548 amdgpu_xgmi_remove_device(adev);
2550 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2551 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2553 amdgpu_amdkfd_device_fini(adev);
2555 /* need to disable SMC first */
2556 for (i = 0; i < adev->num_ip_blocks; i++) {
2557 if (!adev->ip_blocks[i].status.hw)
2559 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2560 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2561 /* XXX handle errors */
2563 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2564 adev->ip_blocks[i].version->funcs->name, r);
2566 adev->ip_blocks[i].status.hw = false;
2571 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2572 if (!adev->ip_blocks[i].status.hw)
2575 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2576 /* XXX handle errors */
2578 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2579 adev->ip_blocks[i].version->funcs->name, r);
2582 adev->ip_blocks[i].status.hw = false;
2586 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2587 if (!adev->ip_blocks[i].status.sw)
2590 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2591 amdgpu_ucode_free_bo(adev);
2592 amdgpu_free_static_csa(&adev->virt.csa_obj);
2593 amdgpu_device_wb_fini(adev);
2594 amdgpu_device_vram_scratch_fini(adev);
2595 amdgpu_ib_pool_fini(adev);
2598 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2599 /* XXX handle errors */
2601 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2602 adev->ip_blocks[i].version->funcs->name, r);
2604 adev->ip_blocks[i].status.sw = false;
2605 adev->ip_blocks[i].status.valid = false;
2608 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2609 if (!adev->ip_blocks[i].status.late_initialized)
2611 if (adev->ip_blocks[i].version->funcs->late_fini)
2612 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2613 adev->ip_blocks[i].status.late_initialized = false;
2616 amdgpu_ras_fini(adev);
2618 if (amdgpu_sriov_vf(adev))
2619 if (amdgpu_virt_release_full_gpu(adev, false))
2620 DRM_ERROR("failed to release exclusive mode on fini\n");
2626 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2628 * @work: work_struct.
2630 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2632 struct amdgpu_device *adev =
2633 container_of(work, struct amdgpu_device, delayed_init_work.work);
2636 r = amdgpu_ib_ring_tests(adev);
2638 DRM_ERROR("ib ring test failed (%d).\n", r);
2641 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2643 struct amdgpu_device *adev =
2644 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2646 mutex_lock(&adev->gfx.gfx_off_mutex);
2647 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2648 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2649 adev->gfx.gfx_off_state = true;
2651 mutex_unlock(&adev->gfx.gfx_off_mutex);
2655 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2657 * @adev: amdgpu_device pointer
2659 * Main suspend function for hardware IPs. The list of all the hardware
2660 * IPs that make up the asic is walked, clockgating is disabled and the
2661 * suspend callbacks are run. suspend puts the hardware and software state
2662 * in each IP into a state suitable for suspend.
2663 * Returns 0 on success, negative error code on failure.
2665 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2669 if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) {
2670 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2671 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2674 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2675 if (!adev->ip_blocks[i].status.valid)
2678 /* displays are handled separately */
2679 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2682 /* XXX handle errors */
2683 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2684 /* XXX handle errors */
2686 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2687 adev->ip_blocks[i].version->funcs->name, r);
2691 adev->ip_blocks[i].status.hw = false;
2698 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2700 * @adev: amdgpu_device pointer
2702 * Main suspend function for hardware IPs. The list of all the hardware
2703 * IPs that make up the asic is walked, clockgating is disabled and the
2704 * suspend callbacks are run. suspend puts the hardware and software state
2705 * in each IP into a state suitable for suspend.
2706 * Returns 0 on success, negative error code on failure.
2708 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2712 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2713 if (!adev->ip_blocks[i].status.valid)
2715 /* displays are handled in phase1 */
2716 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2718 /* PSP lost connection when err_event_athub occurs */
2719 if (amdgpu_ras_intr_triggered() &&
2720 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2721 adev->ip_blocks[i].status.hw = false;
2724 /* XXX handle errors */
2725 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2726 /* XXX handle errors */
2728 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2729 adev->ip_blocks[i].version->funcs->name, r);
2731 adev->ip_blocks[i].status.hw = false;
2732 /* handle putting the SMC in the appropriate state */
2733 if(!amdgpu_sriov_vf(adev)){
2734 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2735 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
2737 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2738 adev->mp1_state, r);
2743 adev->ip_blocks[i].status.hw = false;
2750 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2752 * @adev: amdgpu_device pointer
2754 * Main suspend function for hardware IPs. The list of all the hardware
2755 * IPs that make up the asic is walked, clockgating is disabled and the
2756 * suspend callbacks are run. suspend puts the hardware and software state
2757 * in each IP into a state suitable for suspend.
2758 * Returns 0 on success, negative error code on failure.
2760 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2764 if (amdgpu_sriov_vf(adev))
2765 amdgpu_virt_request_full_gpu(adev, false);
2767 r = amdgpu_device_ip_suspend_phase1(adev);
2770 r = amdgpu_device_ip_suspend_phase2(adev);
2772 if (amdgpu_sriov_vf(adev))
2773 amdgpu_virt_release_full_gpu(adev, false);
2778 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2782 static enum amd_ip_block_type ip_order[] = {
2783 AMD_IP_BLOCK_TYPE_GMC,
2784 AMD_IP_BLOCK_TYPE_COMMON,
2785 AMD_IP_BLOCK_TYPE_PSP,
2786 AMD_IP_BLOCK_TYPE_IH,
2789 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2791 struct amdgpu_ip_block *block;
2793 block = &adev->ip_blocks[i];
2794 block->status.hw = false;
2796 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
2798 if (block->version->type != ip_order[j] ||
2799 !block->status.valid)
2802 r = block->version->funcs->hw_init(adev);
2803 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2806 block->status.hw = true;
2813 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2817 static enum amd_ip_block_type ip_order[] = {
2818 AMD_IP_BLOCK_TYPE_SMC,
2819 AMD_IP_BLOCK_TYPE_DCE,
2820 AMD_IP_BLOCK_TYPE_GFX,
2821 AMD_IP_BLOCK_TYPE_SDMA,
2822 AMD_IP_BLOCK_TYPE_UVD,
2823 AMD_IP_BLOCK_TYPE_VCE,
2824 AMD_IP_BLOCK_TYPE_VCN
2827 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2829 struct amdgpu_ip_block *block;
2831 for (j = 0; j < adev->num_ip_blocks; j++) {
2832 block = &adev->ip_blocks[j];
2834 if (block->version->type != ip_order[i] ||
2835 !block->status.valid ||
2839 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
2840 r = block->version->funcs->resume(adev);
2842 r = block->version->funcs->hw_init(adev);
2844 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2847 block->status.hw = true;
2855 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2857 * @adev: amdgpu_device pointer
2859 * First resume function for hardware IPs. The list of all the hardware
2860 * IPs that make up the asic is walked and the resume callbacks are run for
2861 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2862 * after a suspend and updates the software state as necessary. This
2863 * function is also used for restoring the GPU after a GPU reset.
2864 * Returns 0 on success, negative error code on failure.
2866 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2870 for (i = 0; i < adev->num_ip_blocks; i++) {
2871 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2873 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2874 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2875 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2877 r = adev->ip_blocks[i].version->funcs->resume(adev);
2879 DRM_ERROR("resume of IP block <%s> failed %d\n",
2880 adev->ip_blocks[i].version->funcs->name, r);
2883 adev->ip_blocks[i].status.hw = true;
2891 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2893 * @adev: amdgpu_device pointer
2895 * First resume function for hardware IPs. The list of all the hardware
2896 * IPs that make up the asic is walked and the resume callbacks are run for
2897 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2898 * functional state after a suspend and updates the software state as
2899 * necessary. This function is also used for restoring the GPU after a GPU
2901 * Returns 0 on success, negative error code on failure.
2903 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2907 for (i = 0; i < adev->num_ip_blocks; i++) {
2908 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2910 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2911 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2912 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2913 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2915 r = adev->ip_blocks[i].version->funcs->resume(adev);
2917 DRM_ERROR("resume of IP block <%s> failed %d\n",
2918 adev->ip_blocks[i].version->funcs->name, r);
2921 adev->ip_blocks[i].status.hw = true;
2928 * amdgpu_device_ip_resume - run resume for hardware IPs
2930 * @adev: amdgpu_device pointer
2932 * Main resume function for hardware IPs. The hardware IPs
2933 * are split into two resume functions because they are
2934 * are also used in in recovering from a GPU reset and some additional
2935 * steps need to be take between them. In this case (S3/S4) they are
2937 * Returns 0 on success, negative error code on failure.
2939 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2943 r = amdgpu_device_ip_resume_phase1(adev);
2947 r = amdgpu_device_fw_loading(adev);
2951 r = amdgpu_device_ip_resume_phase2(adev);
2957 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2959 * @adev: amdgpu_device pointer
2961 * Query the VBIOS data tables to determine if the board supports SR-IOV.
2963 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2965 if (amdgpu_sriov_vf(adev)) {
2966 if (adev->is_atom_fw) {
2967 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2968 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2970 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2971 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2974 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2975 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2980 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2982 * @asic_type: AMD asic type
2984 * Check if there is DC (new modesetting infrastructre) support for an asic.
2985 * returns true if DC has support, false if not.
2987 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2989 switch (asic_type) {
2990 #if defined(CONFIG_DRM_AMD_DC)
2991 #if defined(CONFIG_DRM_AMD_DC_SI)
3002 * We have systems in the wild with these ASICs that require
3003 * LVDS and VGA support which is not supported with DC.
3005 * Fallback to the non-DC driver here by default so as not to
3006 * cause regressions.
3008 return amdgpu_dc > 0;
3012 case CHIP_POLARIS10:
3013 case CHIP_POLARIS11:
3014 case CHIP_POLARIS12:
3021 #if defined(CONFIG_DRM_AMD_DC_DCN)
3027 case CHIP_SIENNA_CICHLID:
3028 case CHIP_NAVY_FLOUNDER:
3029 case CHIP_DIMGREY_CAVEFISH:
3032 return amdgpu_dc != 0;
3036 DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
3037 "but isn't supported by ASIC, ignoring\n");
3043 * amdgpu_device_has_dc_support - check if dc is supported
3045 * @adev: amdgpu_device pointer
3047 * Returns true for supported, false for not supported
3049 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3051 if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display)
3054 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3058 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3060 struct amdgpu_device *adev =
3061 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3062 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3064 /* It's a bug to not have a hive within this function */
3069 * Use task barrier to synchronize all xgmi reset works across the
3070 * hive. task_barrier_enter and task_barrier_exit will block
3071 * until all the threads running the xgmi reset works reach
3072 * those points. task_barrier_full will do both blocks.
3074 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3076 task_barrier_enter(&hive->tb);
3077 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3079 if (adev->asic_reset_res)
3082 task_barrier_exit(&hive->tb);
3083 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3085 if (adev->asic_reset_res)
3088 if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
3089 adev->mmhub.funcs->reset_ras_error_count(adev);
3092 task_barrier_full(&hive->tb);
3093 adev->asic_reset_res = amdgpu_asic_reset(adev);
3097 if (adev->asic_reset_res)
3098 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3099 adev->asic_reset_res, adev_to_drm(adev)->unique);
3100 amdgpu_put_xgmi_hive(hive);
3103 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3105 char *input = amdgpu_lockup_timeout;
3106 char *timeout_setting = NULL;
3112 * By default timeout for non compute jobs is 10000.
3113 * And there is no timeout enforced on compute jobs.
3114 * In SR-IOV or passthrough mode, timeout for compute
3115 * jobs are 60000 by default.
3117 adev->gfx_timeout = msecs_to_jiffies(10000);
3118 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3119 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3120 adev->compute_timeout = msecs_to_jiffies(60000);
3122 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
3124 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3125 while ((timeout_setting = strsep(&input, ",")) &&
3126 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3127 ret = kstrtol(timeout_setting, 0, &timeout);
3134 } else if (timeout < 0) {
3135 timeout = MAX_SCHEDULE_TIMEOUT;
3137 timeout = msecs_to_jiffies(timeout);
3142 adev->gfx_timeout = timeout;
3145 adev->compute_timeout = timeout;
3148 adev->sdma_timeout = timeout;
3151 adev->video_timeout = timeout;
3158 * There is only one value specified and
3159 * it should apply to all non-compute jobs.
3162 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3163 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3164 adev->compute_timeout = adev->gfx_timeout;
3171 static const struct attribute *amdgpu_dev_attributes[] = {
3172 &dev_attr_product_name.attr,
3173 &dev_attr_product_number.attr,
3174 &dev_attr_serial_number.attr,
3175 &dev_attr_pcie_replay_count.attr,
3181 * amdgpu_device_init - initialize the driver
3183 * @adev: amdgpu_device pointer
3184 * @flags: driver flags
3186 * Initializes the driver info and hw (all asics).
3187 * Returns 0 for success or an error on failure.
3188 * Called at driver startup.
3190 int amdgpu_device_init(struct amdgpu_device *adev,
3193 struct drm_device *ddev = adev_to_drm(adev);
3194 struct pci_dev *pdev = adev->pdev;
3199 adev->shutdown = false;
3200 adev->flags = flags;
3202 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3203 adev->asic_type = amdgpu_force_asic_type;
3205 adev->asic_type = flags & AMD_ASIC_MASK;
3207 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3208 if (amdgpu_emu_mode == 1)
3209 adev->usec_timeout *= 10;
3210 adev->gmc.gart_size = 512 * 1024 * 1024;
3211 adev->accel_working = false;
3212 adev->num_rings = 0;
3213 adev->mman.buffer_funcs = NULL;
3214 adev->mman.buffer_funcs_ring = NULL;
3215 adev->vm_manager.vm_pte_funcs = NULL;
3216 adev->vm_manager.vm_pte_num_scheds = 0;
3217 adev->gmc.gmc_funcs = NULL;
3218 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3219 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3221 adev->smc_rreg = &amdgpu_invalid_rreg;
3222 adev->smc_wreg = &amdgpu_invalid_wreg;
3223 adev->pcie_rreg = &amdgpu_invalid_rreg;
3224 adev->pcie_wreg = &amdgpu_invalid_wreg;
3225 adev->pciep_rreg = &amdgpu_invalid_rreg;
3226 adev->pciep_wreg = &amdgpu_invalid_wreg;
3227 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3228 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3229 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3230 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3231 adev->didt_rreg = &amdgpu_invalid_rreg;
3232 adev->didt_wreg = &amdgpu_invalid_wreg;
3233 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3234 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3235 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3236 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3238 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3239 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3240 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3242 /* mutex initialization are all done here so we
3243 * can recall function without having locking issues */
3244 atomic_set(&adev->irq.ih.lock, 0);
3245 mutex_init(&adev->firmware.mutex);
3246 mutex_init(&adev->pm.mutex);
3247 mutex_init(&adev->gfx.gpu_clock_mutex);
3248 mutex_init(&adev->srbm_mutex);
3249 mutex_init(&adev->gfx.pipe_reserve_mutex);
3250 mutex_init(&adev->gfx.gfx_off_mutex);
3251 mutex_init(&adev->grbm_idx_mutex);
3252 mutex_init(&adev->mn_lock);
3253 mutex_init(&adev->virt.vf_errors.lock);
3254 hash_init(adev->mn_hash);
3255 atomic_set(&adev->in_gpu_reset, 0);
3256 init_rwsem(&adev->reset_sem);
3257 mutex_init(&adev->psp.mutex);
3258 mutex_init(&adev->notifier_lock);
3260 r = amdgpu_device_check_arguments(adev);
3264 spin_lock_init(&adev->mmio_idx_lock);
3265 spin_lock_init(&adev->smc_idx_lock);
3266 spin_lock_init(&adev->pcie_idx_lock);
3267 spin_lock_init(&adev->uvd_ctx_idx_lock);
3268 spin_lock_init(&adev->didt_idx_lock);
3269 spin_lock_init(&adev->gc_cac_idx_lock);
3270 spin_lock_init(&adev->se_cac_idx_lock);
3271 spin_lock_init(&adev->audio_endpt_idx_lock);
3272 spin_lock_init(&adev->mm_stats.lock);
3274 INIT_LIST_HEAD(&adev->shadow_list);
3275 mutex_init(&adev->shadow_list_lock);
3277 INIT_DELAYED_WORK(&adev->delayed_init_work,
3278 amdgpu_device_delayed_init_work_handler);
3279 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3280 amdgpu_device_delay_enable_gfx_off);
3282 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3284 adev->gfx.gfx_off_req_count = 1;
3285 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3287 atomic_set(&adev->throttling_logging_enabled, 1);
3289 * If throttling continues, logging will be performed every minute
3290 * to avoid log flooding. "-1" is subtracted since the thermal
3291 * throttling interrupt comes every second. Thus, the total logging
3292 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3293 * for throttling interrupt) = 60 seconds.
3295 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3296 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3298 /* Registers mapping */
3299 /* TODO: block userspace mapping of io register */
3300 if (adev->asic_type >= CHIP_BONAIRE) {
3301 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3302 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3304 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3305 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3308 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3309 if (adev->rmmio == NULL) {
3312 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3313 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3315 /* io port mapping */
3316 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3317 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
3318 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
3319 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
3323 if (adev->rio_mem == NULL)
3324 DRM_INFO("PCI I/O BAR is not found.\n");
3326 /* enable PCIE atomic ops */
3327 r = pci_enable_atomic_ops_to_root(adev->pdev,
3328 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3329 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3331 adev->have_atomics_support = false;
3332 DRM_INFO("PCIE atomic ops is not supported\n");
3334 adev->have_atomics_support = true;
3337 amdgpu_device_get_pcie_info(adev);
3340 DRM_INFO("MCBP is enabled\n");
3342 if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
3343 adev->enable_mes = true;
3345 /* detect hw virtualization here */
3346 amdgpu_detect_virtualization(adev);
3348 r = amdgpu_device_get_job_timeout_settings(adev);
3350 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3354 /* early init functions */
3355 r = amdgpu_device_ip_early_init(adev);
3359 /* doorbell bar mapping and doorbell index init*/
3360 amdgpu_device_doorbell_init(adev);
3362 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3363 /* this will fail for cards that aren't VGA class devices, just
3365 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3366 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
3368 if (amdgpu_device_supports_atpx(ddev))
3370 if (amdgpu_has_atpx() &&
3371 (amdgpu_is_atpx_hybrid() ||
3372 amdgpu_has_atpx_dgpu_power_cntl()) &&
3373 !pci_is_thunderbolt_attached(adev->pdev))
3374 vga_switcheroo_register_client(adev->pdev,
3375 &amdgpu_switcheroo_ops, atpx);
3377 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3379 if (amdgpu_emu_mode == 1) {
3380 /* post the asic on emulation mode */
3381 emu_soc_asic_init(adev);
3382 goto fence_driver_init;
3385 /* detect if we are with an SRIOV vbios */
3386 amdgpu_device_detect_sriov_bios(adev);
3388 /* check if we need to reset the asic
3389 * E.g., driver was not cleanly unloaded previously, etc.
3391 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3392 r = amdgpu_asic_reset(adev);
3394 dev_err(adev->dev, "asic reset on init failed\n");
3399 pci_enable_pcie_error_reporting(adev->ddev.pdev);
3401 /* Post card if necessary */
3402 if (amdgpu_device_need_post(adev)) {
3404 dev_err(adev->dev, "no vBIOS found\n");
3408 DRM_INFO("GPU posting now...\n");
3409 r = amdgpu_device_asic_init(adev);
3411 dev_err(adev->dev, "gpu post error!\n");
3416 if (adev->is_atom_fw) {
3417 /* Initialize clocks */
3418 r = amdgpu_atomfirmware_get_clock_info(adev);
3420 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3421 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3425 /* Initialize clocks */
3426 r = amdgpu_atombios_get_clock_info(adev);
3428 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3429 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3432 /* init i2c buses */
3433 if (!amdgpu_device_has_dc_support(adev))
3434 amdgpu_atombios_i2c_init(adev);
3439 r = amdgpu_fence_driver_init(adev);
3441 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
3442 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3446 /* init the mode config */
3447 drm_mode_config_init(adev_to_drm(adev));
3449 r = amdgpu_device_ip_init(adev);
3451 /* failed in exclusive mode due to timeout */
3452 if (amdgpu_sriov_vf(adev) &&
3453 !amdgpu_sriov_runtime(adev) &&
3454 amdgpu_virt_mmio_blocked(adev) &&
3455 !amdgpu_virt_wait_reset(adev)) {
3456 dev_err(adev->dev, "VF exclusive mode timeout\n");
3457 /* Don't send request since VF is inactive. */
3458 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3459 adev->virt.ops = NULL;
3463 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3464 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3469 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3470 adev->gfx.config.max_shader_engines,
3471 adev->gfx.config.max_sh_per_se,
3472 adev->gfx.config.max_cu_per_sh,
3473 adev->gfx.cu_info.number);
3475 adev->accel_working = true;
3477 amdgpu_vm_check_compute_bug(adev);
3479 /* Initialize the buffer migration limit. */
3480 if (amdgpu_moverate >= 0)
3481 max_MBps = amdgpu_moverate;
3483 max_MBps = 8; /* Allow 8 MB/s. */
3484 /* Get a log2 for easy divisions. */
3485 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3487 amdgpu_fbdev_init(adev);
3489 r = amdgpu_pm_sysfs_init(adev);
3491 adev->pm_sysfs_en = false;
3492 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3494 adev->pm_sysfs_en = true;
3496 r = amdgpu_ucode_sysfs_init(adev);
3498 adev->ucode_sysfs_en = false;
3499 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3501 adev->ucode_sysfs_en = true;
3503 if ((amdgpu_testing & 1)) {
3504 if (adev->accel_working)
3505 amdgpu_test_moves(adev);
3507 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
3509 if (amdgpu_benchmarking) {
3510 if (adev->accel_working)
3511 amdgpu_benchmark(adev, amdgpu_benchmarking);
3513 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
3517 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3518 * Otherwise the mgpu fan boost feature will be skipped due to the
3519 * gpu instance is counted less.
3521 amdgpu_register_gpu_instance(adev);
3523 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3524 * explicit gating rather than handling it automatically.
3526 r = amdgpu_device_ip_late_init(adev);
3528 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3529 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3534 amdgpu_ras_resume(adev);
3536 queue_delayed_work(system_wq, &adev->delayed_init_work,
3537 msecs_to_jiffies(AMDGPU_RESUME_MS));
3539 if (amdgpu_sriov_vf(adev))
3540 flush_delayed_work(&adev->delayed_init_work);
3542 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3544 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3546 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3547 r = amdgpu_pmu_init(adev);
3549 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3551 /* Have stored pci confspace at hand for restore in sudden PCI error */
3552 if (amdgpu_device_cache_pci_state(adev->pdev))
3553 pci_restore_state(pdev);
3558 amdgpu_vf_error_trans_all(adev);
3560 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3563 iounmap(adev->rmmio);
3570 * amdgpu_device_fini - tear down the driver
3572 * @adev: amdgpu_device pointer
3574 * Tear down the driver info (all asics).
3575 * Called at driver shutdown.
3577 void amdgpu_device_fini(struct amdgpu_device *adev)
3579 dev_info(adev->dev, "amdgpu: finishing device.\n");
3580 flush_delayed_work(&adev->delayed_init_work);
3581 adev->shutdown = true;
3583 kfree(adev->pci_state);
3585 /* make sure IB test finished before entering exclusive mode
3586 * to avoid preemption on IB test
3588 if (amdgpu_sriov_vf(adev)) {
3589 amdgpu_virt_request_full_gpu(adev, false);
3590 amdgpu_virt_fini_data_exchange(adev);
3593 /* disable all interrupts */
3594 amdgpu_irq_disable_all(adev);
3595 if (adev->mode_info.mode_config_initialized){
3596 if (!amdgpu_device_has_dc_support(adev))
3597 drm_helper_force_disable_all(adev_to_drm(adev));
3599 drm_atomic_helper_shutdown(adev_to_drm(adev));
3601 amdgpu_fence_driver_fini(adev);
3602 if (adev->pm_sysfs_en)
3603 amdgpu_pm_sysfs_fini(adev);
3604 amdgpu_fbdev_fini(adev);
3605 amdgpu_device_ip_fini(adev);
3606 release_firmware(adev->firmware.gpu_info_fw);
3607 adev->firmware.gpu_info_fw = NULL;
3608 adev->accel_working = false;
3609 /* free i2c buses */
3610 if (!amdgpu_device_has_dc_support(adev))
3611 amdgpu_i2c_fini(adev);
3613 if (amdgpu_emu_mode != 1)
3614 amdgpu_atombios_fini(adev);
3618 if (amdgpu_has_atpx() &&
3619 (amdgpu_is_atpx_hybrid() ||
3620 amdgpu_has_atpx_dgpu_power_cntl()) &&
3621 !pci_is_thunderbolt_attached(adev->pdev))
3622 vga_switcheroo_unregister_client(adev->pdev);
3623 if (amdgpu_device_supports_atpx(adev_to_drm(adev)))
3624 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3625 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3626 vga_client_register(adev->pdev, NULL, NULL, NULL);
3628 pci_iounmap(adev->pdev, adev->rio_mem);
3629 adev->rio_mem = NULL;
3630 iounmap(adev->rmmio);
3632 amdgpu_device_doorbell_fini(adev);
3634 if (adev->ucode_sysfs_en)
3635 amdgpu_ucode_sysfs_fini(adev);
3637 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
3638 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3639 amdgpu_pmu_fini(adev);
3640 if (adev->mman.discovery_bin)
3641 amdgpu_discovery_fini(adev);
3649 * amdgpu_device_suspend - initiate device suspend
3651 * @dev: drm dev pointer
3652 * @fbcon : notify the fbdev of suspend
3654 * Puts the hw in the suspend state (all asics).
3655 * Returns 0 for success or an error on failure.
3656 * Called at driver suspend.
3658 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
3660 struct amdgpu_device *adev;
3661 struct drm_crtc *crtc;
3662 struct drm_connector *connector;
3663 struct drm_connector_list_iter iter;
3666 adev = drm_to_adev(dev);
3668 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3671 adev->in_suspend = true;
3672 drm_kms_helper_poll_disable(dev);
3675 amdgpu_fbdev_set_suspend(adev, 1);
3677 cancel_delayed_work_sync(&adev->delayed_init_work);
3679 if (!amdgpu_device_has_dc_support(adev)) {
3680 /* turn off display hw */
3681 drm_modeset_lock_all(dev);
3682 drm_connector_list_iter_begin(dev, &iter);
3683 drm_for_each_connector_iter(connector, &iter)
3684 drm_helper_connector_dpms(connector,
3686 drm_connector_list_iter_end(&iter);
3687 drm_modeset_unlock_all(dev);
3688 /* unpin the front buffers and cursors */
3689 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3690 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3691 struct drm_framebuffer *fb = crtc->primary->fb;
3692 struct amdgpu_bo *robj;
3694 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3695 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3696 r = amdgpu_bo_reserve(aobj, true);
3698 amdgpu_bo_unpin(aobj);
3699 amdgpu_bo_unreserve(aobj);
3703 if (fb == NULL || fb->obj[0] == NULL) {
3706 robj = gem_to_amdgpu_bo(fb->obj[0]);
3707 /* don't unpin kernel fb objects */
3708 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
3709 r = amdgpu_bo_reserve(robj, true);
3711 amdgpu_bo_unpin(robj);
3712 amdgpu_bo_unreserve(robj);
3718 amdgpu_ras_suspend(adev);
3720 r = amdgpu_device_ip_suspend_phase1(adev);
3722 amdgpu_amdkfd_suspend(adev, !fbcon);
3724 /* evict vram memory */
3725 amdgpu_bo_evict_vram(adev);
3727 amdgpu_fence_driver_suspend(adev);
3729 if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev))
3730 r = amdgpu_device_ip_suspend_phase2(adev);
3732 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
3733 /* evict remaining vram memory
3734 * This second call to evict vram is to evict the gart page table
3737 amdgpu_bo_evict_vram(adev);
3743 * amdgpu_device_resume - initiate device resume
3745 * @dev: drm dev pointer
3746 * @fbcon : notify the fbdev of resume
3748 * Bring the hw back to operating state (all asics).
3749 * Returns 0 for success or an error on failure.
3750 * Called at driver resume.
3752 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
3754 struct drm_connector *connector;
3755 struct drm_connector_list_iter iter;
3756 struct amdgpu_device *adev = drm_to_adev(dev);
3757 struct drm_crtc *crtc;
3760 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3763 if (amdgpu_acpi_is_s0ix_supported(adev))
3764 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
3767 if (amdgpu_device_need_post(adev)) {
3768 r = amdgpu_device_asic_init(adev);
3770 dev_err(adev->dev, "amdgpu asic init failed\n");
3773 r = amdgpu_device_ip_resume(adev);
3775 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
3778 amdgpu_fence_driver_resume(adev);
3781 r = amdgpu_device_ip_late_init(adev);
3785 queue_delayed_work(system_wq, &adev->delayed_init_work,
3786 msecs_to_jiffies(AMDGPU_RESUME_MS));
3788 if (!amdgpu_device_has_dc_support(adev)) {
3790 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3791 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3793 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3794 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3795 r = amdgpu_bo_reserve(aobj, true);
3797 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3799 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
3800 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3801 amdgpu_bo_unreserve(aobj);
3806 r = amdgpu_amdkfd_resume(adev, !fbcon);
3810 /* Make sure IB tests flushed */
3811 flush_delayed_work(&adev->delayed_init_work);
3813 /* blat the mode back in */
3815 if (!amdgpu_device_has_dc_support(adev)) {
3817 drm_helper_resume_force_mode(dev);
3819 /* turn on display hw */
3820 drm_modeset_lock_all(dev);
3822 drm_connector_list_iter_begin(dev, &iter);
3823 drm_for_each_connector_iter(connector, &iter)
3824 drm_helper_connector_dpms(connector,
3826 drm_connector_list_iter_end(&iter);
3828 drm_modeset_unlock_all(dev);
3830 amdgpu_fbdev_set_suspend(adev, 0);
3833 drm_kms_helper_poll_enable(dev);
3835 amdgpu_ras_resume(adev);
3838 * Most of the connector probing functions try to acquire runtime pm
3839 * refs to ensure that the GPU is powered on when connector polling is
3840 * performed. Since we're calling this from a runtime PM callback,
3841 * trying to acquire rpm refs will cause us to deadlock.
3843 * Since we're guaranteed to be holding the rpm lock, it's safe to
3844 * temporarily disable the rpm helpers so this doesn't deadlock us.
3847 dev->dev->power.disable_depth++;
3849 if (!amdgpu_device_has_dc_support(adev))
3850 drm_helper_hpd_irq_event(dev);
3852 drm_kms_helper_hotplug_event(dev);
3854 dev->dev->power.disable_depth--;
3856 adev->in_suspend = false;
3862 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3864 * @adev: amdgpu_device pointer
3866 * The list of all the hardware IPs that make up the asic is walked and
3867 * the check_soft_reset callbacks are run. check_soft_reset determines
3868 * if the asic is still hung or not.
3869 * Returns true if any of the IPs are still in a hung state, false if not.
3871 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3874 bool asic_hang = false;
3876 if (amdgpu_sriov_vf(adev))
3879 if (amdgpu_asic_need_full_reset(adev))
3882 for (i = 0; i < adev->num_ip_blocks; i++) {
3883 if (!adev->ip_blocks[i].status.valid)
3885 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3886 adev->ip_blocks[i].status.hang =
3887 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3888 if (adev->ip_blocks[i].status.hang) {
3889 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3897 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3899 * @adev: amdgpu_device pointer
3901 * The list of all the hardware IPs that make up the asic is walked and the
3902 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3903 * handles any IP specific hardware or software state changes that are
3904 * necessary for a soft reset to succeed.
3905 * Returns 0 on success, negative error code on failure.
3907 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3911 for (i = 0; i < adev->num_ip_blocks; i++) {
3912 if (!adev->ip_blocks[i].status.valid)
3914 if (adev->ip_blocks[i].status.hang &&
3915 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3916 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3926 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3928 * @adev: amdgpu_device pointer
3930 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
3931 * reset is necessary to recover.
3932 * Returns true if a full asic reset is required, false if not.
3934 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3938 if (amdgpu_asic_need_full_reset(adev))
3941 for (i = 0; i < adev->num_ip_blocks; i++) {
3942 if (!adev->ip_blocks[i].status.valid)
3944 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3945 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3946 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3947 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3948 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3949 if (adev->ip_blocks[i].status.hang) {
3950 dev_info(adev->dev, "Some block need full reset!\n");
3959 * amdgpu_device_ip_soft_reset - do a soft reset
3961 * @adev: amdgpu_device pointer
3963 * The list of all the hardware IPs that make up the asic is walked and the
3964 * soft_reset callbacks are run if the block is hung. soft_reset handles any
3965 * IP specific hardware or software state changes that are necessary to soft
3967 * Returns 0 on success, negative error code on failure.
3969 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3973 for (i = 0; i < adev->num_ip_blocks; i++) {
3974 if (!adev->ip_blocks[i].status.valid)
3976 if (adev->ip_blocks[i].status.hang &&
3977 adev->ip_blocks[i].version->funcs->soft_reset) {
3978 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3988 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3990 * @adev: amdgpu_device pointer
3992 * The list of all the hardware IPs that make up the asic is walked and the
3993 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
3994 * handles any IP specific hardware or software state changes that are
3995 * necessary after the IP has been soft reset.
3996 * Returns 0 on success, negative error code on failure.
3998 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4002 for (i = 0; i < adev->num_ip_blocks; i++) {
4003 if (!adev->ip_blocks[i].status.valid)
4005 if (adev->ip_blocks[i].status.hang &&
4006 adev->ip_blocks[i].version->funcs->post_soft_reset)
4007 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4016 * amdgpu_device_recover_vram - Recover some VRAM contents
4018 * @adev: amdgpu_device pointer
4020 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4021 * restore things like GPUVM page tables after a GPU reset where
4022 * the contents of VRAM might be lost.
4025 * 0 on success, negative error code on failure.
4027 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4029 struct dma_fence *fence = NULL, *next = NULL;
4030 struct amdgpu_bo *shadow;
4033 if (amdgpu_sriov_runtime(adev))
4034 tmo = msecs_to_jiffies(8000);
4036 tmo = msecs_to_jiffies(100);
4038 dev_info(adev->dev, "recover vram bo from shadow start\n");
4039 mutex_lock(&adev->shadow_list_lock);
4040 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
4042 /* No need to recover an evicted BO */
4043 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
4044 shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
4045 shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
4048 r = amdgpu_bo_restore_shadow(shadow, &next);
4053 tmo = dma_fence_wait_timeout(fence, false, tmo);
4054 dma_fence_put(fence);
4059 } else if (tmo < 0) {
4067 mutex_unlock(&adev->shadow_list_lock);
4070 tmo = dma_fence_wait_timeout(fence, false, tmo);
4071 dma_fence_put(fence);
4073 if (r < 0 || tmo <= 0) {
4074 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4078 dev_info(adev->dev, "recover vram bo from shadow done\n");
4084 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4086 * @adev: amdgpu_device pointer
4087 * @from_hypervisor: request from hypervisor
4089 * do VF FLR and reinitialize Asic
4090 * return 0 means succeeded otherwise failed
4092 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4093 bool from_hypervisor)
4097 if (from_hypervisor)
4098 r = amdgpu_virt_request_full_gpu(adev, true);
4100 r = amdgpu_virt_reset_gpu(adev);
4104 amdgpu_amdkfd_pre_reset(adev);
4106 /* Resume IP prior to SMC */
4107 r = amdgpu_device_ip_reinit_early_sriov(adev);
4111 amdgpu_virt_init_data_exchange(adev);
4112 /* we need recover gart prior to run SMC/CP/SDMA resume */
4113 amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
4115 r = amdgpu_device_fw_loading(adev);
4119 /* now we are okay to resume SMC/CP/SDMA */
4120 r = amdgpu_device_ip_reinit_late_sriov(adev);
4124 amdgpu_irq_gpu_reset_resume_helper(adev);
4125 r = amdgpu_ib_ring_tests(adev);
4126 amdgpu_amdkfd_post_reset(adev);
4129 amdgpu_virt_release_full_gpu(adev, true);
4130 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4131 amdgpu_inc_vram_lost(adev);
4132 r = amdgpu_device_recover_vram(adev);
4139 * amdgpu_device_has_job_running - check if there is any job in mirror list
4141 * @adev: amdgpu_device pointer
4143 * check if there is any job in mirror list
4145 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4148 struct drm_sched_job *job;
4150 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4151 struct amdgpu_ring *ring = adev->rings[i];
4153 if (!ring || !ring->sched.thread)
4156 spin_lock(&ring->sched.job_list_lock);
4157 job = list_first_entry_or_null(&ring->sched.ring_mirror_list,
4158 struct drm_sched_job, node);
4159 spin_unlock(&ring->sched.job_list_lock);
4167 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4169 * @adev: amdgpu_device pointer
4171 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4174 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4176 if (!amdgpu_device_ip_check_soft_reset(adev)) {
4177 dev_info(adev->dev, "Timeout, but no hardware hang detected.\n");
4181 if (amdgpu_gpu_recovery == 0)
4184 if (amdgpu_sriov_vf(adev))
4187 if (amdgpu_gpu_recovery == -1) {
4188 switch (adev->asic_type) {
4194 case CHIP_POLARIS10:
4195 case CHIP_POLARIS11:
4196 case CHIP_POLARIS12:
4207 case CHIP_SIENNA_CICHLID:
4217 dev_info(adev->dev, "GPU recovery disabled.\n");
4222 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4223 struct amdgpu_job *job,
4224 bool *need_full_reset_arg)
4227 bool need_full_reset = *need_full_reset_arg;
4229 amdgpu_debugfs_wait_dump(adev);
4231 if (amdgpu_sriov_vf(adev)) {
4232 /* stop the data exchange thread */
4233 amdgpu_virt_fini_data_exchange(adev);
4236 /* block all schedulers and reset given job's ring */
4237 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4238 struct amdgpu_ring *ring = adev->rings[i];
4240 if (!ring || !ring->sched.thread)
4243 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4244 amdgpu_fence_driver_force_completion(ring);
4248 drm_sched_increase_karma(&job->base);
4250 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4251 if (!amdgpu_sriov_vf(adev)) {
4253 if (!need_full_reset)
4254 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4256 if (!need_full_reset) {
4257 amdgpu_device_ip_pre_soft_reset(adev);
4258 r = amdgpu_device_ip_soft_reset(adev);
4259 amdgpu_device_ip_post_soft_reset(adev);
4260 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4261 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4262 need_full_reset = true;
4266 if (need_full_reset)
4267 r = amdgpu_device_ip_suspend(adev);
4269 *need_full_reset_arg = need_full_reset;
4275 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
4276 struct list_head *device_list_handle,
4277 bool *need_full_reset_arg,
4280 struct amdgpu_device *tmp_adev = NULL;
4281 bool need_full_reset = *need_full_reset_arg, vram_lost = false;
4285 * ASIC reset has to be done on all HGMI hive nodes ASAP
4286 * to allow proper links negotiation in FW (within 1 sec)
4288 if (!skip_hw_reset && need_full_reset) {
4289 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4290 /* For XGMI run all resets in parallel to speed up the process */
4291 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4292 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4295 r = amdgpu_asic_reset(tmp_adev);
4298 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4299 r, adev_to_drm(tmp_adev)->unique);
4304 /* For XGMI wait for all resets to complete before proceed */
4306 list_for_each_entry(tmp_adev, device_list_handle,
4308 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4309 flush_work(&tmp_adev->xgmi_reset_work);
4310 r = tmp_adev->asic_reset_res;
4318 if (!r && amdgpu_ras_intr_triggered()) {
4319 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4320 if (tmp_adev->mmhub.funcs &&
4321 tmp_adev->mmhub.funcs->reset_ras_error_count)
4322 tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev);
4325 amdgpu_ras_intr_cleared();
4328 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4329 if (need_full_reset) {
4331 if (amdgpu_device_asic_init(tmp_adev))
4332 dev_warn(tmp_adev->dev, "asic atom init failed!");
4335 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4336 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4340 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4342 DRM_INFO("VRAM is lost due to GPU reset!\n");
4343 amdgpu_inc_vram_lost(tmp_adev);
4346 r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT));
4350 r = amdgpu_device_fw_loading(tmp_adev);
4354 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4359 amdgpu_device_fill_reset_magic(tmp_adev);
4362 * Add this ASIC as tracked as reset was already
4363 * complete successfully.
4365 amdgpu_register_gpu_instance(tmp_adev);
4367 r = amdgpu_device_ip_late_init(tmp_adev);
4371 amdgpu_fbdev_set_suspend(tmp_adev, 0);
4374 * The GPU enters bad state once faulty pages
4375 * by ECC has reached the threshold, and ras
4376 * recovery is scheduled next. So add one check
4377 * here to break recovery if it indeed exceeds
4378 * bad page threshold, and remind user to
4379 * retire this GPU or setting one bigger
4380 * bad_page_threshold value to fix this once
4381 * probing driver again.
4383 if (!amdgpu_ras_check_err_threshold(tmp_adev)) {
4385 amdgpu_ras_resume(tmp_adev);
4391 /* Update PSP FW topology after reset */
4392 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4393 r = amdgpu_xgmi_update_topology(hive, tmp_adev);
4399 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
4400 r = amdgpu_ib_ring_tests(tmp_adev);
4402 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
4403 r = amdgpu_device_ip_suspend(tmp_adev);
4404 need_full_reset = true;
4411 r = amdgpu_device_recover_vram(tmp_adev);
4413 tmp_adev->asic_reset_res = r;
4417 *need_full_reset_arg = need_full_reset;
4421 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev,
4422 struct amdgpu_hive_info *hive)
4424 if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)
4428 down_write_nest_lock(&adev->reset_sem, &hive->hive_lock);
4430 down_write(&adev->reset_sem);
4433 atomic_inc(&adev->gpu_reset_counter);
4434 switch (amdgpu_asic_reset_method(adev)) {
4435 case AMD_RESET_METHOD_MODE1:
4436 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
4438 case AMD_RESET_METHOD_MODE2:
4439 adev->mp1_state = PP_MP1_STATE_RESET;
4442 adev->mp1_state = PP_MP1_STATE_NONE;
4449 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
4451 amdgpu_vf_error_trans_all(adev);
4452 adev->mp1_state = PP_MP1_STATE_NONE;
4453 atomic_set(&adev->in_gpu_reset, 0);
4454 up_write(&adev->reset_sem);
4457 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
4459 struct pci_dev *p = NULL;
4461 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4462 adev->pdev->bus->number, 1);
4464 pm_runtime_enable(&(p->dev));
4465 pm_runtime_resume(&(p->dev));
4469 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
4471 enum amd_reset_method reset_method;
4472 struct pci_dev *p = NULL;
4476 * For now, only BACO and mode1 reset are confirmed
4477 * to suffer the audio issue without proper suspended.
4479 reset_method = amdgpu_asic_reset_method(adev);
4480 if ((reset_method != AMD_RESET_METHOD_BACO) &&
4481 (reset_method != AMD_RESET_METHOD_MODE1))
4484 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4485 adev->pdev->bus->number, 1);
4489 expires = pm_runtime_autosuspend_expiration(&(p->dev));
4492 * If we cannot get the audio device autosuspend delay,
4493 * a fixed 4S interval will be used. Considering 3S is
4494 * the audio controller default autosuspend delay setting.
4495 * 4S used here is guaranteed to cover that.
4497 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
4499 while (!pm_runtime_status_suspended(&(p->dev))) {
4500 if (!pm_runtime_suspend(&(p->dev)))
4503 if (expires < ktime_get_mono_fast_ns()) {
4504 dev_warn(adev->dev, "failed to suspend display audio\n");
4505 /* TODO: abort the succeeding gpu reset? */
4510 pm_runtime_disable(&(p->dev));
4516 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
4518 * @adev: amdgpu_device pointer
4519 * @job: which job trigger hang
4521 * Attempt to reset the GPU if it has hung (all asics).
4522 * Attempt to do soft-reset or full-reset and reinitialize Asic
4523 * Returns 0 for success or an error on failure.
4526 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
4527 struct amdgpu_job *job)
4529 struct list_head device_list, *device_list_handle = NULL;
4530 bool need_full_reset = false;
4531 bool job_signaled = false;
4532 struct amdgpu_hive_info *hive = NULL;
4533 struct amdgpu_device *tmp_adev = NULL;
4535 bool need_emergency_restart = false;
4536 bool audio_suspended = false;
4539 * Special case: RAS triggered and full reset isn't supported
4541 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
4544 * Flush RAM to disk so that after reboot
4545 * the user can read log and see why the system rebooted.
4547 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
4548 DRM_WARN("Emergency reboot.");
4551 emergency_restart();
4554 dev_info(adev->dev, "GPU %s begin!\n",
4555 need_emergency_restart ? "jobs stop":"reset");
4558 * Here we trylock to avoid chain of resets executing from
4559 * either trigger by jobs on different adevs in XGMI hive or jobs on
4560 * different schedulers for same device while this TO handler is running.
4561 * We always reset all schedulers for device and all devices for XGMI
4562 * hive so that should take care of them too.
4564 hive = amdgpu_get_xgmi_hive(adev);
4566 if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) {
4567 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
4568 job ? job->base.id : -1, hive->hive_id);
4569 amdgpu_put_xgmi_hive(hive);
4572 mutex_lock(&hive->hive_lock);
4576 * Build list of devices to reset.
4577 * In case we are in XGMI hive mode, resort the device list
4578 * to put adev in the 1st position.
4580 INIT_LIST_HEAD(&device_list);
4581 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4584 if (!list_is_first(&adev->gmc.xgmi.head, &hive->device_list))
4585 list_rotate_to_front(&adev->gmc.xgmi.head, &hive->device_list);
4586 device_list_handle = &hive->device_list;
4588 list_add_tail(&adev->gmc.xgmi.head, &device_list);
4589 device_list_handle = &device_list;
4592 /* block all schedulers and reset given job's ring */
4593 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4594 if (!amdgpu_device_lock_adev(tmp_adev, hive)) {
4595 dev_info(tmp_adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress",
4596 job ? job->base.id : -1);
4602 * Try to put the audio codec into suspend state
4603 * before gpu reset started.
4605 * Due to the power domain of the graphics device
4606 * is shared with AZ power domain. Without this,
4607 * we may change the audio hardware from behind
4608 * the audio driver's back. That will trigger
4609 * some audio codec errors.
4611 if (!amdgpu_device_suspend_display_audio(tmp_adev))
4612 audio_suspended = true;
4614 amdgpu_ras_set_error_query_ready(tmp_adev, false);
4616 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
4618 if (!amdgpu_sriov_vf(tmp_adev))
4619 amdgpu_amdkfd_pre_reset(tmp_adev);
4622 * Mark these ASICs to be reseted as untracked first
4623 * And add them back after reset completed
4625 amdgpu_unregister_gpu_instance(tmp_adev);
4627 amdgpu_fbdev_set_suspend(tmp_adev, 1);
4629 /* disable ras on ALL IPs */
4630 if (!need_emergency_restart &&
4631 amdgpu_device_ip_need_full_reset(tmp_adev))
4632 amdgpu_ras_suspend(tmp_adev);
4634 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4635 struct amdgpu_ring *ring = tmp_adev->rings[i];
4637 if (!ring || !ring->sched.thread)
4640 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
4642 if (need_emergency_restart)
4643 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
4647 if (need_emergency_restart)
4648 goto skip_sched_resume;
4651 * Must check guilty signal here since after this point all old
4652 * HW fences are force signaled.
4654 * job->base holds a reference to parent fence
4656 if (job && job->base.s_fence->parent &&
4657 dma_fence_is_signaled(job->base.s_fence->parent)) {
4658 job_signaled = true;
4659 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
4663 retry: /* Rest of adevs pre asic reset from XGMI hive. */
4664 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4665 r = amdgpu_device_pre_asic_reset(tmp_adev,
4666 (tmp_adev == adev) ? job : NULL,
4668 /*TODO Should we stop ?*/
4670 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
4671 r, adev_to_drm(tmp_adev)->unique);
4672 tmp_adev->asic_reset_res = r;
4676 /* Actual ASIC resets if needed.*/
4677 /* TODO Implement XGMI hive reset logic for SRIOV */
4678 if (amdgpu_sriov_vf(adev)) {
4679 r = amdgpu_device_reset_sriov(adev, job ? false : true);
4681 adev->asic_reset_res = r;
4683 r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset, false);
4684 if (r && r == -EAGAIN)
4690 /* Post ASIC reset for all devs .*/
4691 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4693 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4694 struct amdgpu_ring *ring = tmp_adev->rings[i];
4696 if (!ring || !ring->sched.thread)
4699 /* No point to resubmit jobs if we didn't HW reset*/
4700 if (!tmp_adev->asic_reset_res && !job_signaled)
4701 drm_sched_resubmit_jobs(&ring->sched);
4703 drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
4706 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
4707 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
4710 tmp_adev->asic_reset_res = 0;
4713 /* bad news, how to tell it to userspace ? */
4714 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
4715 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
4717 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
4722 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4723 /*unlock kfd: SRIOV would do it separately */
4724 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
4725 amdgpu_amdkfd_post_reset(tmp_adev);
4726 if (audio_suspended)
4727 amdgpu_device_resume_display_audio(tmp_adev);
4728 amdgpu_device_unlock_adev(tmp_adev);
4733 atomic_set(&hive->in_reset, 0);
4734 mutex_unlock(&hive->hive_lock);
4735 amdgpu_put_xgmi_hive(hive);
4739 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
4744 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
4746 * @adev: amdgpu_device pointer
4748 * Fetchs and stores in the driver the PCIE capabilities (gen speed
4749 * and lanes) of the slot the device is in. Handles APUs and
4750 * virtualized environments where PCIE config space may not be available.
4752 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
4754 struct pci_dev *pdev;
4755 enum pci_bus_speed speed_cap, platform_speed_cap;
4756 enum pcie_link_width platform_link_width;
4758 if (amdgpu_pcie_gen_cap)
4759 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
4761 if (amdgpu_pcie_lane_cap)
4762 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
4764 /* covers APUs as well */
4765 if (pci_is_root_bus(adev->pdev->bus)) {
4766 if (adev->pm.pcie_gen_mask == 0)
4767 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
4768 if (adev->pm.pcie_mlw_mask == 0)
4769 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4773 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
4776 pcie_bandwidth_available(adev->pdev, NULL,
4777 &platform_speed_cap, &platform_link_width);
4779 if (adev->pm.pcie_gen_mask == 0) {
4782 speed_cap = pcie_get_speed_cap(pdev);
4783 if (speed_cap == PCI_SPEED_UNKNOWN) {
4784 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4785 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4786 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4788 if (speed_cap == PCIE_SPEED_16_0GT)
4789 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4790 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4791 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4792 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
4793 else if (speed_cap == PCIE_SPEED_8_0GT)
4794 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4795 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4796 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4797 else if (speed_cap == PCIE_SPEED_5_0GT)
4798 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4799 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
4801 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
4804 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
4805 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4806 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4808 if (platform_speed_cap == PCIE_SPEED_16_0GT)
4809 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4810 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4811 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4812 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
4813 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
4814 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4815 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4816 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
4817 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
4818 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4819 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4821 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
4825 if (adev->pm.pcie_mlw_mask == 0) {
4826 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
4827 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
4829 switch (platform_link_width) {
4831 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
4832 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4833 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4834 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4835 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4836 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4837 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4840 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4841 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4842 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4843 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4844 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4845 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4848 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4849 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4850 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4851 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4852 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4855 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4856 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4857 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4858 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4861 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4862 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4863 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4866 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4867 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4870 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
4879 int amdgpu_device_baco_enter(struct drm_device *dev)
4881 struct amdgpu_device *adev = drm_to_adev(dev);
4882 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4884 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
4887 if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
4888 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
4890 return amdgpu_dpm_baco_enter(adev);
4893 int amdgpu_device_baco_exit(struct drm_device *dev)
4895 struct amdgpu_device *adev = drm_to_adev(dev);
4896 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4899 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
4902 ret = amdgpu_dpm_baco_exit(adev);
4906 if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
4907 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
4912 static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev)
4916 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4917 struct amdgpu_ring *ring = adev->rings[i];
4919 if (!ring || !ring->sched.thread)
4922 cancel_delayed_work_sync(&ring->sched.work_tdr);
4927 * amdgpu_pci_error_detected - Called when a PCI error is detected.
4928 * @pdev: PCI device struct
4929 * @state: PCI channel state
4931 * Description: Called when a PCI error is detected.
4933 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
4935 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4937 struct drm_device *dev = pci_get_drvdata(pdev);
4938 struct amdgpu_device *adev = drm_to_adev(dev);
4941 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
4943 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4944 DRM_WARN("No support for XGMI hive yet...");
4945 return PCI_ERS_RESULT_DISCONNECT;
4949 case pci_channel_io_normal:
4950 return PCI_ERS_RESULT_CAN_RECOVER;
4951 /* Fatal error, prepare for slot reset */
4952 case pci_channel_io_frozen:
4954 * Cancel and wait for all TDRs in progress if failing to
4955 * set adev->in_gpu_reset in amdgpu_device_lock_adev
4957 * Locking adev->reset_sem will prevent any external access
4958 * to GPU during PCI error recovery
4960 while (!amdgpu_device_lock_adev(adev, NULL))
4961 amdgpu_cancel_all_tdr(adev);
4964 * Block any work scheduling as we do for regular GPU reset
4965 * for the duration of the recovery
4967 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4968 struct amdgpu_ring *ring = adev->rings[i];
4970 if (!ring || !ring->sched.thread)
4973 drm_sched_stop(&ring->sched, NULL);
4975 return PCI_ERS_RESULT_NEED_RESET;
4976 case pci_channel_io_perm_failure:
4977 /* Permanent error, prepare for device removal */
4978 return PCI_ERS_RESULT_DISCONNECT;
4981 return PCI_ERS_RESULT_NEED_RESET;
4985 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
4986 * @pdev: pointer to PCI device
4988 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
4991 DRM_INFO("PCI error: mmio enabled callback!!\n");
4993 /* TODO - dump whatever for debugging purposes */
4995 /* This called only if amdgpu_pci_error_detected returns
4996 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
4997 * works, no need to reset slot.
5000 return PCI_ERS_RESULT_RECOVERED;
5004 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5005 * @pdev: PCI device struct
5007 * Description: This routine is called by the pci error recovery
5008 * code after the PCI slot has been reset, just before we
5009 * should resume normal operations.
5011 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5013 struct drm_device *dev = pci_get_drvdata(pdev);
5014 struct amdgpu_device *adev = drm_to_adev(dev);
5016 bool need_full_reset = true;
5018 struct list_head device_list;
5020 DRM_INFO("PCI error: slot reset callback!!\n");
5022 INIT_LIST_HEAD(&device_list);
5023 list_add_tail(&adev->gmc.xgmi.head, &device_list);
5025 /* wait for asic to come out of reset */
5028 /* Restore PCI confspace */
5029 amdgpu_device_load_pci_state(pdev);
5031 /* confirm ASIC came out of reset */
5032 for (i = 0; i < adev->usec_timeout; i++) {
5033 memsize = amdgpu_asic_get_config_memsize(adev);
5035 if (memsize != 0xffffffff)
5039 if (memsize == 0xffffffff) {
5044 adev->in_pci_err_recovery = true;
5045 r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset);
5046 adev->in_pci_err_recovery = false;
5050 r = amdgpu_do_asic_reset(NULL, &device_list, &need_full_reset, true);
5054 if (amdgpu_device_cache_pci_state(adev->pdev))
5055 pci_restore_state(adev->pdev);
5057 DRM_INFO("PCIe error recovery succeeded\n");
5059 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5060 amdgpu_device_unlock_adev(adev);
5063 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5067 * amdgpu_pci_resume() - resume normal ops after PCI reset
5068 * @pdev: pointer to PCI device
5070 * Called when the error recovery driver tells us that its
5071 * OK to resume normal operation.
5073 void amdgpu_pci_resume(struct pci_dev *pdev)
5075 struct drm_device *dev = pci_get_drvdata(pdev);
5076 struct amdgpu_device *adev = drm_to_adev(dev);
5080 DRM_INFO("PCI error: resume callback!!\n");
5082 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5083 struct amdgpu_ring *ring = adev->rings[i];
5085 if (!ring || !ring->sched.thread)
5089 drm_sched_resubmit_jobs(&ring->sched);
5090 drm_sched_start(&ring->sched, true);
5093 amdgpu_device_unlock_adev(adev);
5096 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5098 struct drm_device *dev = pci_get_drvdata(pdev);
5099 struct amdgpu_device *adev = drm_to_adev(dev);
5102 r = pci_save_state(pdev);
5104 kfree(adev->pci_state);
5106 adev->pci_state = pci_store_saved_state(pdev);
5108 if (!adev->pci_state) {
5109 DRM_ERROR("Failed to store PCI saved state");
5113 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5120 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5122 struct drm_device *dev = pci_get_drvdata(pdev);
5123 struct amdgpu_device *adev = drm_to_adev(dev);
5126 if (!adev->pci_state)
5129 r = pci_load_saved_state(pdev, adev->pci_state);
5132 pci_restore_state(pdev);
5134 DRM_WARN("Failed to load PCI state, err:%d\n", r);