2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
33 #include <linux/iommu.h>
34 #include <linux/pci.h>
35 #include <linux/devcoredump.h>
36 #include <generated/utsrelease.h>
37 #include <linux/pci-p2pdma.h>
39 #include <drm/drm_atomic_helper.h>
40 #include <drm/drm_fb_helper.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/amdgpu_drm.h>
43 #include <linux/vgaarb.h>
44 #include <linux/vga_switcheroo.h>
45 #include <linux/efi.h>
47 #include "amdgpu_trace.h"
48 #include "amdgpu_i2c.h"
50 #include "amdgpu_atombios.h"
51 #include "amdgpu_atomfirmware.h"
53 #ifdef CONFIG_DRM_AMDGPU_SI
56 #ifdef CONFIG_DRM_AMDGPU_CIK
62 #include "bif/bif_4_1_d.h"
63 #include <linux/firmware.h>
64 #include "amdgpu_vf_error.h"
66 #include "amdgpu_amdkfd.h"
67 #include "amdgpu_pm.h"
69 #include "amdgpu_xgmi.h"
70 #include "amdgpu_ras.h"
71 #include "amdgpu_pmu.h"
72 #include "amdgpu_fru_eeprom.h"
73 #include "amdgpu_reset.h"
75 #include <linux/suspend.h>
76 #include <drm/task_barrier.h>
77 #include <linux/pm_runtime.h>
79 #include <drm/drm_drv.h>
81 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
82 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
83 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
84 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
85 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
86 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
87 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
89 #define AMDGPU_RESUME_MS 2000
90 #define AMDGPU_MAX_RETRY_LIMIT 2
91 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
93 const char *amdgpu_asic_name[] = {
135 * DOC: pcie_replay_count
137 * The amdgpu driver provides a sysfs API for reporting the total number
138 * of PCIe replays (NAKs)
139 * The file pcie_replay_count is used for this and returns the total
140 * number of replays as a sum of the NAKs generated and NAKs received
143 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
144 struct device_attribute *attr, char *buf)
146 struct drm_device *ddev = dev_get_drvdata(dev);
147 struct amdgpu_device *adev = drm_to_adev(ddev);
148 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
150 return sysfs_emit(buf, "%llu\n", cnt);
153 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
154 amdgpu_device_get_pcie_replay_count, NULL);
156 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
161 * The amdgpu driver provides a sysfs API for reporting the product name
163 * The file serial_number is used for this and returns the product name
164 * as returned from the FRU.
165 * NOTE: This is only available for certain server cards
168 static ssize_t amdgpu_device_get_product_name(struct device *dev,
169 struct device_attribute *attr, char *buf)
171 struct drm_device *ddev = dev_get_drvdata(dev);
172 struct amdgpu_device *adev = drm_to_adev(ddev);
174 return sysfs_emit(buf, "%s\n", adev->product_name);
177 static DEVICE_ATTR(product_name, S_IRUGO,
178 amdgpu_device_get_product_name, NULL);
181 * DOC: product_number
183 * The amdgpu driver provides a sysfs API for reporting the part number
185 * The file serial_number is used for this and returns the part number
186 * as returned from the FRU.
187 * NOTE: This is only available for certain server cards
190 static ssize_t amdgpu_device_get_product_number(struct device *dev,
191 struct device_attribute *attr, char *buf)
193 struct drm_device *ddev = dev_get_drvdata(dev);
194 struct amdgpu_device *adev = drm_to_adev(ddev);
196 return sysfs_emit(buf, "%s\n", adev->product_number);
199 static DEVICE_ATTR(product_number, S_IRUGO,
200 amdgpu_device_get_product_number, NULL);
205 * The amdgpu driver provides a sysfs API for reporting the serial number
207 * The file serial_number is used for this and returns the serial number
208 * as returned from the FRU.
209 * NOTE: This is only available for certain server cards
212 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
213 struct device_attribute *attr, char *buf)
215 struct drm_device *ddev = dev_get_drvdata(dev);
216 struct amdgpu_device *adev = drm_to_adev(ddev);
218 return sysfs_emit(buf, "%s\n", adev->serial);
221 static DEVICE_ATTR(serial_number, S_IRUGO,
222 amdgpu_device_get_serial_number, NULL);
225 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
227 * @dev: drm_device pointer
229 * Returns true if the device is a dGPU with ATPX power control,
230 * otherwise return false.
232 bool amdgpu_device_supports_px(struct drm_device *dev)
234 struct amdgpu_device *adev = drm_to_adev(dev);
236 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
242 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
244 * @dev: drm_device pointer
246 * Returns true if the device is a dGPU with ACPI power control,
247 * otherwise return false.
249 bool amdgpu_device_supports_boco(struct drm_device *dev)
251 struct amdgpu_device *adev = drm_to_adev(dev);
254 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
260 * amdgpu_device_supports_baco - Does the device support BACO
262 * @dev: drm_device pointer
264 * Returns true if the device supporte BACO,
265 * otherwise return false.
267 bool amdgpu_device_supports_baco(struct drm_device *dev)
269 struct amdgpu_device *adev = drm_to_adev(dev);
271 return amdgpu_asic_supports_baco(adev);
275 * amdgpu_device_supports_smart_shift - Is the device dGPU with
276 * smart shift support
278 * @dev: drm_device pointer
280 * Returns true if the device is a dGPU with Smart Shift support,
281 * otherwise returns false.
283 bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
285 return (amdgpu_device_supports_boco(dev) &&
286 amdgpu_acpi_is_power_shift_control_supported());
290 * VRAM access helper functions
294 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
296 * @adev: amdgpu_device pointer
297 * @pos: offset of the buffer in vram
298 * @buf: virtual address of the buffer in system memory
299 * @size: read/write size, sizeof(@buf) must > @size
300 * @write: true - write to vram, otherwise - read from vram
302 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
303 void *buf, size_t size, bool write)
306 uint32_t hi = ~0, tmp = 0;
307 uint32_t *data = buf;
311 if (!drm_dev_enter(adev_to_drm(adev), &idx))
314 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
316 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
317 for (last = pos + size; pos < last; pos += 4) {
320 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
322 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
326 WREG32_NO_KIQ(mmMM_DATA, *data++);
328 *data++ = RREG32_NO_KIQ(mmMM_DATA);
331 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
336 * amdgpu_device_aper_access - access vram by vram aperature
338 * @adev: amdgpu_device pointer
339 * @pos: offset of the buffer in vram
340 * @buf: virtual address of the buffer in system memory
341 * @size: read/write size, sizeof(@buf) must > @size
342 * @write: true - write to vram, otherwise - read from vram
344 * The return value means how many bytes have been transferred.
346 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
347 void *buf, size_t size, bool write)
354 if (!adev->mman.aper_base_kaddr)
357 last = min(pos + size, adev->gmc.visible_vram_size);
359 addr = adev->mman.aper_base_kaddr + pos;
363 memcpy_toio(addr, buf, count);
365 amdgpu_device_flush_hdp(adev, NULL);
367 amdgpu_device_invalidate_hdp(adev, NULL);
369 memcpy_fromio(buf, addr, count);
381 * amdgpu_device_vram_access - read/write a buffer in vram
383 * @adev: amdgpu_device pointer
384 * @pos: offset of the buffer in vram
385 * @buf: virtual address of the buffer in system memory
386 * @size: read/write size, sizeof(@buf) must > @size
387 * @write: true - write to vram, otherwise - read from vram
389 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
390 void *buf, size_t size, bool write)
394 /* try to using vram apreature to access vram first */
395 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
398 /* using MM to access rest vram */
401 amdgpu_device_mm_access(adev, pos, buf, size, write);
406 * register access helper functions.
409 /* Check if hw access should be skipped because of hotplug or device error */
410 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
412 if (adev->no_hw_access)
415 #ifdef CONFIG_LOCKDEP
417 * This is a bit complicated to understand, so worth a comment. What we assert
418 * here is that the GPU reset is not running on another thread in parallel.
420 * For this we trylock the read side of the reset semaphore, if that succeeds
421 * we know that the reset is not running in paralell.
423 * If the trylock fails we assert that we are either already holding the read
424 * side of the lock or are the reset thread itself and hold the write side of
428 if (down_read_trylock(&adev->reset_domain->sem))
429 up_read(&adev->reset_domain->sem);
431 lockdep_assert_held(&adev->reset_domain->sem);
438 * amdgpu_device_rreg - read a memory mapped IO or indirect register
440 * @adev: amdgpu_device pointer
441 * @reg: dword aligned register offset
442 * @acc_flags: access flags which require special behavior
444 * Returns the 32 bit value from the offset specified.
446 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
447 uint32_t reg, uint32_t acc_flags)
451 if (amdgpu_device_skip_hw_access(adev))
454 if ((reg * 4) < adev->rmmio_size) {
455 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
456 amdgpu_sriov_runtime(adev) &&
457 down_read_trylock(&adev->reset_domain->sem)) {
458 ret = amdgpu_kiq_rreg(adev, reg);
459 up_read(&adev->reset_domain->sem);
461 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
464 ret = adev->pcie_rreg(adev, reg * 4);
467 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
473 * MMIO register read with bytes helper functions
474 * @offset:bytes offset from MMIO start
479 * amdgpu_mm_rreg8 - read a memory mapped IO register
481 * @adev: amdgpu_device pointer
482 * @offset: byte aligned register offset
484 * Returns the 8 bit value from the offset specified.
486 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
488 if (amdgpu_device_skip_hw_access(adev))
491 if (offset < adev->rmmio_size)
492 return (readb(adev->rmmio + offset));
497 * MMIO register write with bytes helper functions
498 * @offset:bytes offset from MMIO start
499 * @value: the value want to be written to the register
503 * amdgpu_mm_wreg8 - read a memory mapped IO register
505 * @adev: amdgpu_device pointer
506 * @offset: byte aligned register offset
507 * @value: 8 bit value to write
509 * Writes the value specified to the offset specified.
511 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
513 if (amdgpu_device_skip_hw_access(adev))
516 if (offset < adev->rmmio_size)
517 writeb(value, adev->rmmio + offset);
523 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
525 * @adev: amdgpu_device pointer
526 * @reg: dword aligned register offset
527 * @v: 32 bit value to write to the register
528 * @acc_flags: access flags which require special behavior
530 * Writes the value specified to the offset specified.
532 void amdgpu_device_wreg(struct amdgpu_device *adev,
533 uint32_t reg, uint32_t v,
536 if (amdgpu_device_skip_hw_access(adev))
539 if ((reg * 4) < adev->rmmio_size) {
540 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
541 amdgpu_sriov_runtime(adev) &&
542 down_read_trylock(&adev->reset_domain->sem)) {
543 amdgpu_kiq_wreg(adev, reg, v);
544 up_read(&adev->reset_domain->sem);
546 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
549 adev->pcie_wreg(adev, reg * 4, v);
552 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
556 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
558 * @adev: amdgpu_device pointer
559 * @reg: mmio/rlc register
562 * this function is invoked only for the debugfs register access
564 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
565 uint32_t reg, uint32_t v)
567 if (amdgpu_device_skip_hw_access(adev))
570 if (amdgpu_sriov_fullaccess(adev) &&
571 adev->gfx.rlc.funcs &&
572 adev->gfx.rlc.funcs->is_rlcg_access_range) {
573 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
574 return amdgpu_sriov_wreg(adev, reg, v, 0, 0);
575 } else if ((reg * 4) >= adev->rmmio_size) {
576 adev->pcie_wreg(adev, reg * 4, v);
578 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
583 * amdgpu_mm_rdoorbell - read a doorbell dword
585 * @adev: amdgpu_device pointer
586 * @index: doorbell index
588 * Returns the value in the doorbell aperture at the
589 * requested doorbell index (CIK).
591 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
593 if (amdgpu_device_skip_hw_access(adev))
596 if (index < adev->doorbell.num_doorbells) {
597 return readl(adev->doorbell.ptr + index);
599 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
605 * amdgpu_mm_wdoorbell - write a doorbell dword
607 * @adev: amdgpu_device pointer
608 * @index: doorbell index
611 * Writes @v to the doorbell aperture at the
612 * requested doorbell index (CIK).
614 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
616 if (amdgpu_device_skip_hw_access(adev))
619 if (index < adev->doorbell.num_doorbells) {
620 writel(v, adev->doorbell.ptr + index);
622 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
627 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
629 * @adev: amdgpu_device pointer
630 * @index: doorbell index
632 * Returns the value in the doorbell aperture at the
633 * requested doorbell index (VEGA10+).
635 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
637 if (amdgpu_device_skip_hw_access(adev))
640 if (index < adev->doorbell.num_doorbells) {
641 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
643 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
649 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
651 * @adev: amdgpu_device pointer
652 * @index: doorbell index
655 * Writes @v to the doorbell aperture at the
656 * requested doorbell index (VEGA10+).
658 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
660 if (amdgpu_device_skip_hw_access(adev))
663 if (index < adev->doorbell.num_doorbells) {
664 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
666 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
671 * amdgpu_device_indirect_rreg - read an indirect register
673 * @adev: amdgpu_device pointer
674 * @pcie_index: mmio register offset
675 * @pcie_data: mmio register offset
676 * @reg_addr: indirect register address to read from
678 * Returns the value of indirect register @reg_addr
680 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
681 u32 pcie_index, u32 pcie_data,
686 void __iomem *pcie_index_offset;
687 void __iomem *pcie_data_offset;
689 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
690 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
691 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
693 writel(reg_addr, pcie_index_offset);
694 readl(pcie_index_offset);
695 r = readl(pcie_data_offset);
696 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
702 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
704 * @adev: amdgpu_device pointer
705 * @pcie_index: mmio register offset
706 * @pcie_data: mmio register offset
707 * @reg_addr: indirect register address to read from
709 * Returns the value of indirect register @reg_addr
711 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
712 u32 pcie_index, u32 pcie_data,
717 void __iomem *pcie_index_offset;
718 void __iomem *pcie_data_offset;
720 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
721 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
722 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
724 /* read low 32 bits */
725 writel(reg_addr, pcie_index_offset);
726 readl(pcie_index_offset);
727 r = readl(pcie_data_offset);
728 /* read high 32 bits */
729 writel(reg_addr + 4, pcie_index_offset);
730 readl(pcie_index_offset);
731 r |= ((u64)readl(pcie_data_offset) << 32);
732 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
738 * amdgpu_device_indirect_wreg - write an indirect register address
740 * @adev: amdgpu_device pointer
741 * @pcie_index: mmio register offset
742 * @pcie_data: mmio register offset
743 * @reg_addr: indirect register offset
744 * @reg_data: indirect register data
747 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
748 u32 pcie_index, u32 pcie_data,
749 u32 reg_addr, u32 reg_data)
752 void __iomem *pcie_index_offset;
753 void __iomem *pcie_data_offset;
755 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
756 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
757 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
759 writel(reg_addr, pcie_index_offset);
760 readl(pcie_index_offset);
761 writel(reg_data, pcie_data_offset);
762 readl(pcie_data_offset);
763 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
767 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
769 * @adev: amdgpu_device pointer
770 * @pcie_index: mmio register offset
771 * @pcie_data: mmio register offset
772 * @reg_addr: indirect register offset
773 * @reg_data: indirect register data
776 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
777 u32 pcie_index, u32 pcie_data,
778 u32 reg_addr, u64 reg_data)
781 void __iomem *pcie_index_offset;
782 void __iomem *pcie_data_offset;
784 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
785 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
786 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
788 /* write low 32 bits */
789 writel(reg_addr, pcie_index_offset);
790 readl(pcie_index_offset);
791 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
792 readl(pcie_data_offset);
793 /* write high 32 bits */
794 writel(reg_addr + 4, pcie_index_offset);
795 readl(pcie_index_offset);
796 writel((u32)(reg_data >> 32), pcie_data_offset);
797 readl(pcie_data_offset);
798 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
802 * amdgpu_invalid_rreg - dummy reg read function
804 * @adev: amdgpu_device pointer
805 * @reg: offset of register
807 * Dummy register read function. Used for register blocks
808 * that certain asics don't have (all asics).
809 * Returns the value in the register.
811 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
813 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
819 * amdgpu_invalid_wreg - dummy reg write function
821 * @adev: amdgpu_device pointer
822 * @reg: offset of register
823 * @v: value to write to the register
825 * Dummy register read function. Used for register blocks
826 * that certain asics don't have (all asics).
828 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
830 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
836 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
838 * @adev: amdgpu_device pointer
839 * @reg: offset of register
841 * Dummy register read function. Used for register blocks
842 * that certain asics don't have (all asics).
843 * Returns the value in the register.
845 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
847 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
853 * amdgpu_invalid_wreg64 - dummy reg write function
855 * @adev: amdgpu_device pointer
856 * @reg: offset of register
857 * @v: value to write to the register
859 * Dummy register read function. Used for register blocks
860 * that certain asics don't have (all asics).
862 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
864 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
870 * amdgpu_block_invalid_rreg - dummy reg read function
872 * @adev: amdgpu_device pointer
873 * @block: offset of instance
874 * @reg: offset of register
876 * Dummy register read function. Used for register blocks
877 * that certain asics don't have (all asics).
878 * Returns the value in the register.
880 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
881 uint32_t block, uint32_t reg)
883 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
890 * amdgpu_block_invalid_wreg - dummy reg write function
892 * @adev: amdgpu_device pointer
893 * @block: offset of instance
894 * @reg: offset of register
895 * @v: value to write to the register
897 * Dummy register read function. Used for register blocks
898 * that certain asics don't have (all asics).
900 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
902 uint32_t reg, uint32_t v)
904 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
910 * amdgpu_device_asic_init - Wrapper for atom asic_init
912 * @adev: amdgpu_device pointer
914 * Does any asic specific work and then calls atom asic init.
916 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
918 amdgpu_asic_pre_asic_init(adev);
920 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
921 return amdgpu_atomfirmware_asic_init(adev, true);
923 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
927 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
929 * @adev: amdgpu_device pointer
931 * Allocates a scratch page of VRAM for use by various things in the
934 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
936 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
937 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
938 &adev->vram_scratch.robj,
939 &adev->vram_scratch.gpu_addr,
940 (void **)&adev->vram_scratch.ptr);
944 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
946 * @adev: amdgpu_device pointer
948 * Frees the VRAM scratch page.
950 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
952 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
956 * amdgpu_device_program_register_sequence - program an array of registers.
958 * @adev: amdgpu_device pointer
959 * @registers: pointer to the register array
960 * @array_size: size of the register array
962 * Programs an array or registers with and and or masks.
963 * This is a helper for setting golden registers.
965 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
966 const u32 *registers,
967 const u32 array_size)
969 u32 tmp, reg, and_mask, or_mask;
975 for (i = 0; i < array_size; i +=3) {
976 reg = registers[i + 0];
977 and_mask = registers[i + 1];
978 or_mask = registers[i + 2];
980 if (and_mask == 0xffffffff) {
985 if (adev->family >= AMDGPU_FAMILY_AI)
986 tmp |= (or_mask & and_mask);
995 * amdgpu_device_pci_config_reset - reset the GPU
997 * @adev: amdgpu_device pointer
999 * Resets the GPU using the pci config reset sequence.
1000 * Only applicable to asics prior to vega10.
1002 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1004 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1008 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1010 * @adev: amdgpu_device pointer
1012 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1014 int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1016 return pci_reset_function(adev->pdev);
1020 * GPU doorbell aperture helpers function.
1023 * amdgpu_device_doorbell_init - Init doorbell driver information.
1025 * @adev: amdgpu_device pointer
1027 * Init doorbell driver information (CIK)
1028 * Returns 0 on success, error on failure.
1030 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
1033 /* No doorbell on SI hardware generation */
1034 if (adev->asic_type < CHIP_BONAIRE) {
1035 adev->doorbell.base = 0;
1036 adev->doorbell.size = 0;
1037 adev->doorbell.num_doorbells = 0;
1038 adev->doorbell.ptr = NULL;
1042 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
1045 amdgpu_asic_init_doorbell_index(adev);
1047 /* doorbell bar mapping */
1048 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
1049 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
1051 if (adev->enable_mes) {
1052 adev->doorbell.num_doorbells =
1053 adev->doorbell.size / sizeof(u32);
1055 adev->doorbell.num_doorbells =
1056 min_t(u32, adev->doorbell.size / sizeof(u32),
1057 adev->doorbell_index.max_assignment+1);
1058 if (adev->doorbell.num_doorbells == 0)
1061 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
1062 * paging queue doorbell use the second page. The
1063 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
1064 * doorbells are in the first page. So with paging queue enabled,
1065 * the max num_doorbells should + 1 page (0x400 in dword)
1067 if (adev->asic_type >= CHIP_VEGA10)
1068 adev->doorbell.num_doorbells += 0x400;
1071 adev->doorbell.ptr = ioremap(adev->doorbell.base,
1072 adev->doorbell.num_doorbells *
1074 if (adev->doorbell.ptr == NULL)
1081 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
1083 * @adev: amdgpu_device pointer
1085 * Tear down doorbell driver information (CIK)
1087 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
1089 iounmap(adev->doorbell.ptr);
1090 adev->doorbell.ptr = NULL;
1096 * amdgpu_device_wb_*()
1097 * Writeback is the method by which the GPU updates special pages in memory
1098 * with the status of certain GPU events (fences, ring pointers,etc.).
1102 * amdgpu_device_wb_fini - Disable Writeback and free memory
1104 * @adev: amdgpu_device pointer
1106 * Disables Writeback and frees the Writeback memory (all asics).
1107 * Used at driver shutdown.
1109 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1111 if (adev->wb.wb_obj) {
1112 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1114 (void **)&adev->wb.wb);
1115 adev->wb.wb_obj = NULL;
1120 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1122 * @adev: amdgpu_device pointer
1124 * Initializes writeback and allocates writeback memory (all asics).
1125 * Used at driver startup.
1126 * Returns 0 on success or an -error on failure.
1128 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1132 if (adev->wb.wb_obj == NULL) {
1133 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1134 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1135 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1136 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1137 (void **)&adev->wb.wb);
1139 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1143 adev->wb.num_wb = AMDGPU_MAX_WB;
1144 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1146 /* clear wb memory */
1147 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1154 * amdgpu_device_wb_get - Allocate a wb entry
1156 * @adev: amdgpu_device pointer
1159 * Allocate a wb slot for use by the driver (all asics).
1160 * Returns 0 on success or -EINVAL on failure.
1162 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1164 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1166 if (offset < adev->wb.num_wb) {
1167 __set_bit(offset, adev->wb.used);
1168 *wb = offset << 3; /* convert to dw offset */
1176 * amdgpu_device_wb_free - Free a wb entry
1178 * @adev: amdgpu_device pointer
1181 * Free a wb slot allocated for use by the driver (all asics)
1183 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1186 if (wb < adev->wb.num_wb)
1187 __clear_bit(wb, adev->wb.used);
1191 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1193 * @adev: amdgpu_device pointer
1195 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1196 * to fail, but if any of the BARs is not accessible after the size we abort
1197 * driver loading by returning -ENODEV.
1199 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1201 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1202 struct pci_bus *root;
1203 struct resource *res;
1209 if (amdgpu_sriov_vf(adev))
1212 /* skip if the bios has already enabled large BAR */
1213 if (adev->gmc.real_vram_size &&
1214 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1217 /* Check if the root BUS has 64bit memory resources */
1218 root = adev->pdev->bus;
1219 while (root->parent)
1220 root = root->parent;
1222 pci_bus_for_each_resource(root, res, i) {
1223 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1224 res->start > 0x100000000ull)
1228 /* Trying to resize is pointless without a root hub window above 4GB */
1232 /* Limit the BAR size to what is available */
1233 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1236 /* Disable memory decoding while we change the BAR addresses and size */
1237 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1238 pci_write_config_word(adev->pdev, PCI_COMMAND,
1239 cmd & ~PCI_COMMAND_MEMORY);
1241 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1242 amdgpu_device_doorbell_fini(adev);
1243 if (adev->asic_type >= CHIP_BONAIRE)
1244 pci_release_resource(adev->pdev, 2);
1246 pci_release_resource(adev->pdev, 0);
1248 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1250 DRM_INFO("Not enough PCI address space for a large BAR.");
1251 else if (r && r != -ENOTSUPP)
1252 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1254 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1256 /* When the doorbell or fb BAR isn't available we have no chance of
1259 r = amdgpu_device_doorbell_init(adev);
1260 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1263 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1269 * GPU helpers function.
1272 * amdgpu_device_need_post - check if the hw need post or not
1274 * @adev: amdgpu_device pointer
1276 * Check if the asic has been initialized (all asics) at driver startup
1277 * or post is needed if hw reset is performed.
1278 * Returns true if need or false if not.
1280 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1284 if (amdgpu_sriov_vf(adev))
1287 if (amdgpu_passthrough(adev)) {
1288 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1289 * some old smc fw still need driver do vPost otherwise gpu hang, while
1290 * those smc fw version above 22.15 doesn't have this flaw, so we force
1291 * vpost executed for smc version below 22.15
1293 if (adev->asic_type == CHIP_FIJI) {
1296 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1297 /* force vPost if error occured */
1301 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1302 if (fw_ver < 0x00160e00)
1307 /* Don't post if we need to reset whole hive on init */
1308 if (adev->gmc.xgmi.pending_reset)
1311 if (adev->has_hw_reset) {
1312 adev->has_hw_reset = false;
1316 /* bios scratch used on CIK+ */
1317 if (adev->asic_type >= CHIP_BONAIRE)
1318 return amdgpu_atombios_scratch_need_asic_init(adev);
1320 /* check MEM_SIZE for older asics */
1321 reg = amdgpu_asic_get_config_memsize(adev);
1323 if ((reg != 0) && (reg != 0xffffffff))
1330 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1332 * @adev: amdgpu_device pointer
1334 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1335 * be set for this device.
1337 * Returns true if it should be used or false if not.
1339 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1341 switch (amdgpu_aspm) {
1351 return pcie_aspm_enabled(adev->pdev);
1354 /* if we get transitioned to only one device, take VGA back */
1356 * amdgpu_device_vga_set_decode - enable/disable vga decode
1358 * @pdev: PCI device pointer
1359 * @state: enable/disable vga decode
1361 * Enable/disable vga decode (all asics).
1362 * Returns VGA resource flags.
1364 static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1367 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1368 amdgpu_asic_set_vga_state(adev, state);
1370 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1371 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1373 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1377 * amdgpu_device_check_block_size - validate the vm block size
1379 * @adev: amdgpu_device pointer
1381 * Validates the vm block size specified via module parameter.
1382 * The vm block size defines number of bits in page table versus page directory,
1383 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1384 * page table and the remaining bits are in the page directory.
1386 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1388 /* defines number of bits in page table versus page directory,
1389 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1390 * page table and the remaining bits are in the page directory */
1391 if (amdgpu_vm_block_size == -1)
1394 if (amdgpu_vm_block_size < 9) {
1395 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1396 amdgpu_vm_block_size);
1397 amdgpu_vm_block_size = -1;
1402 * amdgpu_device_check_vm_size - validate the vm size
1404 * @adev: amdgpu_device pointer
1406 * Validates the vm size in GB specified via module parameter.
1407 * The VM size is the size of the GPU virtual memory space in GB.
1409 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1411 /* no need to check the default value */
1412 if (amdgpu_vm_size == -1)
1415 if (amdgpu_vm_size < 1) {
1416 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1418 amdgpu_vm_size = -1;
1422 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1425 bool is_os_64 = (sizeof(void *) == 8);
1426 uint64_t total_memory;
1427 uint64_t dram_size_seven_GB = 0x1B8000000;
1428 uint64_t dram_size_three_GB = 0xB8000000;
1430 if (amdgpu_smu_memory_pool_size == 0)
1434 DRM_WARN("Not 64-bit OS, feature not supported\n");
1438 total_memory = (uint64_t)si.totalram * si.mem_unit;
1440 if ((amdgpu_smu_memory_pool_size == 1) ||
1441 (amdgpu_smu_memory_pool_size == 2)) {
1442 if (total_memory < dram_size_three_GB)
1444 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1445 (amdgpu_smu_memory_pool_size == 8)) {
1446 if (total_memory < dram_size_seven_GB)
1449 DRM_WARN("Smu memory pool size not supported\n");
1452 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1457 DRM_WARN("No enough system memory\n");
1459 adev->pm.smu_prv_buffer_size = 0;
1462 static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1464 if (!(adev->flags & AMD_IS_APU) ||
1465 adev->asic_type < CHIP_RAVEN)
1468 switch (adev->asic_type) {
1470 if (adev->pdev->device == 0x15dd)
1471 adev->apu_flags |= AMD_APU_IS_RAVEN;
1472 if (adev->pdev->device == 0x15d8)
1473 adev->apu_flags |= AMD_APU_IS_PICASSO;
1476 if ((adev->pdev->device == 0x1636) ||
1477 (adev->pdev->device == 0x164c))
1478 adev->apu_flags |= AMD_APU_IS_RENOIR;
1480 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1483 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1485 case CHIP_YELLOW_CARP:
1487 case CHIP_CYAN_SKILLFISH:
1488 if ((adev->pdev->device == 0x13FE) ||
1489 (adev->pdev->device == 0x143F))
1490 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1500 * amdgpu_device_check_arguments - validate module params
1502 * @adev: amdgpu_device pointer
1504 * Validates certain module parameters and updates
1505 * the associated values used by the driver (all asics).
1507 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1509 if (amdgpu_sched_jobs < 4) {
1510 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1512 amdgpu_sched_jobs = 4;
1513 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1514 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1516 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1519 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1520 /* gart size must be greater or equal to 32M */
1521 dev_warn(adev->dev, "gart size (%d) too small\n",
1523 amdgpu_gart_size = -1;
1526 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1527 /* gtt size must be greater or equal to 32M */
1528 dev_warn(adev->dev, "gtt size (%d) too small\n",
1530 amdgpu_gtt_size = -1;
1533 /* valid range is between 4 and 9 inclusive */
1534 if (amdgpu_vm_fragment_size != -1 &&
1535 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1536 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1537 amdgpu_vm_fragment_size = -1;
1540 if (amdgpu_sched_hw_submission < 2) {
1541 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1542 amdgpu_sched_hw_submission);
1543 amdgpu_sched_hw_submission = 2;
1544 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1545 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1546 amdgpu_sched_hw_submission);
1547 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1550 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1551 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1552 amdgpu_reset_method = -1;
1555 amdgpu_device_check_smu_prv_buffer_size(adev);
1557 amdgpu_device_check_vm_size(adev);
1559 amdgpu_device_check_block_size(adev);
1561 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1567 * amdgpu_switcheroo_set_state - set switcheroo state
1569 * @pdev: pci dev pointer
1570 * @state: vga_switcheroo state
1572 * Callback for the switcheroo driver. Suspends or resumes
1573 * the asics before or after it is powered up using ACPI methods.
1575 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1576 enum vga_switcheroo_state state)
1578 struct drm_device *dev = pci_get_drvdata(pdev);
1581 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1584 if (state == VGA_SWITCHEROO_ON) {
1585 pr_info("switched on\n");
1586 /* don't suspend or resume card normally */
1587 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1589 pci_set_power_state(pdev, PCI_D0);
1590 amdgpu_device_load_pci_state(pdev);
1591 r = pci_enable_device(pdev);
1593 DRM_WARN("pci_enable_device failed (%d)\n", r);
1594 amdgpu_device_resume(dev, true);
1596 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1598 pr_info("switched off\n");
1599 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1600 amdgpu_device_suspend(dev, true);
1601 amdgpu_device_cache_pci_state(pdev);
1602 /* Shut down the device */
1603 pci_disable_device(pdev);
1604 pci_set_power_state(pdev, PCI_D3cold);
1605 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1610 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1612 * @pdev: pci dev pointer
1614 * Callback for the switcheroo driver. Check of the switcheroo
1615 * state can be changed.
1616 * Returns true if the state can be changed, false if not.
1618 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1620 struct drm_device *dev = pci_get_drvdata(pdev);
1623 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1624 * locking inversion with the driver load path. And the access here is
1625 * completely racy anyway. So don't bother with locking for now.
1627 return atomic_read(&dev->open_count) == 0;
1630 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1631 .set_gpu_state = amdgpu_switcheroo_set_state,
1633 .can_switch = amdgpu_switcheroo_can_switch,
1637 * amdgpu_device_ip_set_clockgating_state - set the CG state
1639 * @dev: amdgpu_device pointer
1640 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1641 * @state: clockgating state (gate or ungate)
1643 * Sets the requested clockgating state for all instances of
1644 * the hardware IP specified.
1645 * Returns the error code from the last instance.
1647 int amdgpu_device_ip_set_clockgating_state(void *dev,
1648 enum amd_ip_block_type block_type,
1649 enum amd_clockgating_state state)
1651 struct amdgpu_device *adev = dev;
1654 for (i = 0; i < adev->num_ip_blocks; i++) {
1655 if (!adev->ip_blocks[i].status.valid)
1657 if (adev->ip_blocks[i].version->type != block_type)
1659 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1661 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1662 (void *)adev, state);
1664 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1665 adev->ip_blocks[i].version->funcs->name, r);
1671 * amdgpu_device_ip_set_powergating_state - set the PG state
1673 * @dev: amdgpu_device pointer
1674 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1675 * @state: powergating state (gate or ungate)
1677 * Sets the requested powergating state for all instances of
1678 * the hardware IP specified.
1679 * Returns the error code from the last instance.
1681 int amdgpu_device_ip_set_powergating_state(void *dev,
1682 enum amd_ip_block_type block_type,
1683 enum amd_powergating_state state)
1685 struct amdgpu_device *adev = dev;
1688 for (i = 0; i < adev->num_ip_blocks; i++) {
1689 if (!adev->ip_blocks[i].status.valid)
1691 if (adev->ip_blocks[i].version->type != block_type)
1693 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1695 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1696 (void *)adev, state);
1698 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1699 adev->ip_blocks[i].version->funcs->name, r);
1705 * amdgpu_device_ip_get_clockgating_state - get the CG state
1707 * @adev: amdgpu_device pointer
1708 * @flags: clockgating feature flags
1710 * Walks the list of IPs on the device and updates the clockgating
1711 * flags for each IP.
1712 * Updates @flags with the feature flags for each hardware IP where
1713 * clockgating is enabled.
1715 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1720 for (i = 0; i < adev->num_ip_blocks; i++) {
1721 if (!adev->ip_blocks[i].status.valid)
1723 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1724 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1729 * amdgpu_device_ip_wait_for_idle - wait for idle
1731 * @adev: amdgpu_device pointer
1732 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1734 * Waits for the request hardware IP to be idle.
1735 * Returns 0 for success or a negative error code on failure.
1737 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1738 enum amd_ip_block_type block_type)
1742 for (i = 0; i < adev->num_ip_blocks; i++) {
1743 if (!adev->ip_blocks[i].status.valid)
1745 if (adev->ip_blocks[i].version->type == block_type) {
1746 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1757 * amdgpu_device_ip_is_idle - is the hardware IP idle
1759 * @adev: amdgpu_device pointer
1760 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1762 * Check if the hardware IP is idle or not.
1763 * Returns true if it the IP is idle, false if not.
1765 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1766 enum amd_ip_block_type block_type)
1770 for (i = 0; i < adev->num_ip_blocks; i++) {
1771 if (!adev->ip_blocks[i].status.valid)
1773 if (adev->ip_blocks[i].version->type == block_type)
1774 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1781 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1783 * @adev: amdgpu_device pointer
1784 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1786 * Returns a pointer to the hardware IP block structure
1787 * if it exists for the asic, otherwise NULL.
1789 struct amdgpu_ip_block *
1790 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1791 enum amd_ip_block_type type)
1795 for (i = 0; i < adev->num_ip_blocks; i++)
1796 if (adev->ip_blocks[i].version->type == type)
1797 return &adev->ip_blocks[i];
1803 * amdgpu_device_ip_block_version_cmp
1805 * @adev: amdgpu_device pointer
1806 * @type: enum amd_ip_block_type
1807 * @major: major version
1808 * @minor: minor version
1810 * return 0 if equal or greater
1811 * return 1 if smaller or the ip_block doesn't exist
1813 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1814 enum amd_ip_block_type type,
1815 u32 major, u32 minor)
1817 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1819 if (ip_block && ((ip_block->version->major > major) ||
1820 ((ip_block->version->major == major) &&
1821 (ip_block->version->minor >= minor))))
1828 * amdgpu_device_ip_block_add
1830 * @adev: amdgpu_device pointer
1831 * @ip_block_version: pointer to the IP to add
1833 * Adds the IP block driver information to the collection of IPs
1836 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1837 const struct amdgpu_ip_block_version *ip_block_version)
1839 if (!ip_block_version)
1842 switch (ip_block_version->type) {
1843 case AMD_IP_BLOCK_TYPE_VCN:
1844 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1847 case AMD_IP_BLOCK_TYPE_JPEG:
1848 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
1855 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1856 ip_block_version->funcs->name);
1858 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1864 * amdgpu_device_enable_virtual_display - enable virtual display feature
1866 * @adev: amdgpu_device pointer
1868 * Enabled the virtual display feature if the user has enabled it via
1869 * the module parameter virtual_display. This feature provides a virtual
1870 * display hardware on headless boards or in virtualized environments.
1871 * This function parses and validates the configuration string specified by
1872 * the user and configues the virtual display configuration (number of
1873 * virtual connectors, crtcs, etc.) specified.
1875 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1877 adev->enable_virtual_display = false;
1879 if (amdgpu_virtual_display) {
1880 const char *pci_address_name = pci_name(adev->pdev);
1881 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1883 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1884 pciaddstr_tmp = pciaddstr;
1885 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1886 pciaddname = strsep(&pciaddname_tmp, ",");
1887 if (!strcmp("all", pciaddname)
1888 || !strcmp(pci_address_name, pciaddname)) {
1892 adev->enable_virtual_display = true;
1895 res = kstrtol(pciaddname_tmp, 10,
1903 adev->mode_info.num_crtc = num_crtc;
1905 adev->mode_info.num_crtc = 1;
1911 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1912 amdgpu_virtual_display, pci_address_name,
1913 adev->enable_virtual_display, adev->mode_info.num_crtc);
1919 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
1921 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
1922 adev->mode_info.num_crtc = 1;
1923 adev->enable_virtual_display = true;
1924 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
1925 adev->enable_virtual_display, adev->mode_info.num_crtc);
1930 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1932 * @adev: amdgpu_device pointer
1934 * Parses the asic configuration parameters specified in the gpu info
1935 * firmware and makes them availale to the driver for use in configuring
1937 * Returns 0 on success, -EINVAL on failure.
1939 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1941 const char *chip_name;
1944 const struct gpu_info_firmware_header_v1_0 *hdr;
1946 adev->firmware.gpu_info_fw = NULL;
1948 if (adev->mman.discovery_bin) {
1950 * FIXME: The bounding box is still needed by Navi12, so
1951 * temporarily read it from gpu_info firmware. Should be dropped
1952 * when DAL no longer needs it.
1954 if (adev->asic_type != CHIP_NAVI12)
1958 switch (adev->asic_type) {
1962 chip_name = "vega10";
1965 chip_name = "vega12";
1968 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1969 chip_name = "raven2";
1970 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1971 chip_name = "picasso";
1973 chip_name = "raven";
1976 chip_name = "arcturus";
1979 chip_name = "navi12";
1983 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1984 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1987 "Failed to load gpu_info firmware \"%s\"\n",
1991 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1994 "Failed to validate gpu_info firmware \"%s\"\n",
1999 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2000 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2002 switch (hdr->version_major) {
2005 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2006 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2007 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2010 * Should be droped when DAL no longer needs it.
2012 if (adev->asic_type == CHIP_NAVI12)
2013 goto parse_soc_bounding_box;
2015 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2016 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2017 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2018 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2019 adev->gfx.config.max_texture_channel_caches =
2020 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2021 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2022 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2023 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2024 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2025 adev->gfx.config.double_offchip_lds_buf =
2026 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2027 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2028 adev->gfx.cu_info.max_waves_per_simd =
2029 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2030 adev->gfx.cu_info.max_scratch_slots_per_cu =
2031 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2032 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2033 if (hdr->version_minor >= 1) {
2034 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2035 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2036 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2037 adev->gfx.config.num_sc_per_sh =
2038 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2039 adev->gfx.config.num_packer_per_sc =
2040 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2043 parse_soc_bounding_box:
2045 * soc bounding box info is not integrated in disocovery table,
2046 * we always need to parse it from gpu info firmware if needed.
2048 if (hdr->version_minor == 2) {
2049 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2050 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2051 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2052 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2058 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2067 * amdgpu_device_ip_early_init - run early init for hardware IPs
2069 * @adev: amdgpu_device pointer
2071 * Early initialization pass for hardware IPs. The hardware IPs that make
2072 * up each asic are discovered each IP's early_init callback is run. This
2073 * is the first stage in initializing the asic.
2074 * Returns 0 on success, negative error code on failure.
2076 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2078 struct drm_device *dev = adev_to_drm(adev);
2079 struct pci_dev *parent;
2082 amdgpu_device_enable_virtual_display(adev);
2084 if (amdgpu_sriov_vf(adev)) {
2085 r = amdgpu_virt_request_full_gpu(adev, true);
2090 switch (adev->asic_type) {
2091 #ifdef CONFIG_DRM_AMDGPU_SI
2097 adev->family = AMDGPU_FAMILY_SI;
2098 r = si_set_ip_blocks(adev);
2103 #ifdef CONFIG_DRM_AMDGPU_CIK
2109 if (adev->flags & AMD_IS_APU)
2110 adev->family = AMDGPU_FAMILY_KV;
2112 adev->family = AMDGPU_FAMILY_CI;
2114 r = cik_set_ip_blocks(adev);
2122 case CHIP_POLARIS10:
2123 case CHIP_POLARIS11:
2124 case CHIP_POLARIS12:
2128 if (adev->flags & AMD_IS_APU)
2129 adev->family = AMDGPU_FAMILY_CZ;
2131 adev->family = AMDGPU_FAMILY_VI;
2133 r = vi_set_ip_blocks(adev);
2138 r = amdgpu_discovery_set_ip_blocks(adev);
2144 if (amdgpu_has_atpx() &&
2145 (amdgpu_is_atpx_hybrid() ||
2146 amdgpu_has_atpx_dgpu_power_cntl()) &&
2147 ((adev->flags & AMD_IS_APU) == 0) &&
2148 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
2149 adev->flags |= AMD_IS_PX;
2151 if (!(adev->flags & AMD_IS_APU)) {
2152 parent = pci_upstream_bridge(adev->pdev);
2153 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2156 amdgpu_amdkfd_device_probe(adev);
2158 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2159 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2160 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2161 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2162 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2164 for (i = 0; i < adev->num_ip_blocks; i++) {
2165 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2166 DRM_ERROR("disabled ip block: %d <%s>\n",
2167 i, adev->ip_blocks[i].version->funcs->name);
2168 adev->ip_blocks[i].status.valid = false;
2170 if (adev->ip_blocks[i].version->funcs->early_init) {
2171 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2173 adev->ip_blocks[i].status.valid = false;
2175 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2176 adev->ip_blocks[i].version->funcs->name, r);
2179 adev->ip_blocks[i].status.valid = true;
2182 adev->ip_blocks[i].status.valid = true;
2185 /* get the vbios after the asic_funcs are set up */
2186 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2187 r = amdgpu_device_parse_gpu_info_fw(adev);
2192 if (!amdgpu_get_bios(adev))
2195 r = amdgpu_atombios_init(adev);
2197 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2198 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2202 /*get pf2vf msg info at it's earliest time*/
2203 if (amdgpu_sriov_vf(adev))
2204 amdgpu_virt_init_data_exchange(adev);
2209 adev->cg_flags &= amdgpu_cg_mask;
2210 adev->pg_flags &= amdgpu_pg_mask;
2215 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2219 for (i = 0; i < adev->num_ip_blocks; i++) {
2220 if (!adev->ip_blocks[i].status.sw)
2222 if (adev->ip_blocks[i].status.hw)
2224 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2225 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2226 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2227 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2229 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2230 adev->ip_blocks[i].version->funcs->name, r);
2233 adev->ip_blocks[i].status.hw = true;
2240 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2244 for (i = 0; i < adev->num_ip_blocks; i++) {
2245 if (!adev->ip_blocks[i].status.sw)
2247 if (adev->ip_blocks[i].status.hw)
2249 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2251 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2252 adev->ip_blocks[i].version->funcs->name, r);
2255 adev->ip_blocks[i].status.hw = true;
2261 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2265 uint32_t smu_version;
2267 if (adev->asic_type >= CHIP_VEGA10) {
2268 for (i = 0; i < adev->num_ip_blocks; i++) {
2269 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2272 if (!adev->ip_blocks[i].status.sw)
2275 /* no need to do the fw loading again if already done*/
2276 if (adev->ip_blocks[i].status.hw == true)
2279 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2280 r = adev->ip_blocks[i].version->funcs->resume(adev);
2282 DRM_ERROR("resume of IP block <%s> failed %d\n",
2283 adev->ip_blocks[i].version->funcs->name, r);
2287 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2289 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2290 adev->ip_blocks[i].version->funcs->name, r);
2295 adev->ip_blocks[i].status.hw = true;
2300 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2301 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2306 static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2311 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2312 struct amdgpu_ring *ring = adev->rings[i];
2314 /* No need to setup the GPU scheduler for rings that don't need it */
2315 if (!ring || ring->no_scheduler)
2318 switch (ring->funcs->type) {
2319 case AMDGPU_RING_TYPE_GFX:
2320 timeout = adev->gfx_timeout;
2322 case AMDGPU_RING_TYPE_COMPUTE:
2323 timeout = adev->compute_timeout;
2325 case AMDGPU_RING_TYPE_SDMA:
2326 timeout = adev->sdma_timeout;
2329 timeout = adev->video_timeout;
2333 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
2334 ring->num_hw_submission, amdgpu_job_hang_limit,
2335 timeout, adev->reset_domain->wq,
2336 ring->sched_score, ring->name,
2339 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2350 * amdgpu_device_ip_init - run init for hardware IPs
2352 * @adev: amdgpu_device pointer
2354 * Main initialization pass for hardware IPs. The list of all the hardware
2355 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2356 * are run. sw_init initializes the software state associated with each IP
2357 * and hw_init initializes the hardware associated with each IP.
2358 * Returns 0 on success, negative error code on failure.
2360 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2364 r = amdgpu_ras_init(adev);
2368 for (i = 0; i < adev->num_ip_blocks; i++) {
2369 if (!adev->ip_blocks[i].status.valid)
2371 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2373 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2374 adev->ip_blocks[i].version->funcs->name, r);
2377 adev->ip_blocks[i].status.sw = true;
2379 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2380 /* need to do common hw init early so everything is set up for gmc */
2381 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2383 DRM_ERROR("hw_init %d failed %d\n", i, r);
2386 adev->ip_blocks[i].status.hw = true;
2387 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2388 /* need to do gmc hw init early so we can allocate gpu mem */
2389 /* Try to reserve bad pages early */
2390 if (amdgpu_sriov_vf(adev))
2391 amdgpu_virt_exchange_data(adev);
2393 r = amdgpu_device_vram_scratch_init(adev);
2395 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
2398 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2400 DRM_ERROR("hw_init %d failed %d\n", i, r);
2403 r = amdgpu_device_wb_init(adev);
2405 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2408 adev->ip_blocks[i].status.hw = true;
2410 /* right after GMC hw init, we create CSA */
2412 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2413 AMDGPU_GEM_DOMAIN_VRAM,
2416 DRM_ERROR("allocate CSA failed %d\n", r);
2423 if (amdgpu_sriov_vf(adev))
2424 amdgpu_virt_init_data_exchange(adev);
2426 r = amdgpu_ib_pool_init(adev);
2428 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2429 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2433 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2437 r = amdgpu_device_ip_hw_init_phase1(adev);
2441 r = amdgpu_device_fw_loading(adev);
2445 r = amdgpu_device_ip_hw_init_phase2(adev);
2450 * retired pages will be loaded from eeprom and reserved here,
2451 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2452 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2453 * for I2C communication which only true at this point.
2455 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2456 * failure from bad gpu situation and stop amdgpu init process
2457 * accordingly. For other failed cases, it will still release all
2458 * the resource and print error message, rather than returning one
2459 * negative value to upper level.
2461 * Note: theoretically, this should be called before all vram allocations
2462 * to protect retired page from abusing
2464 r = amdgpu_ras_recovery_init(adev);
2469 * In case of XGMI grab extra reference for reset domain for this device
2471 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2472 if (amdgpu_xgmi_add_device(adev) == 0) {
2473 if (!amdgpu_sriov_vf(adev)) {
2474 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2476 if (WARN_ON(!hive)) {
2481 if (!hive->reset_domain ||
2482 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2484 amdgpu_put_xgmi_hive(hive);
2488 /* Drop the early temporary reset domain we created for device */
2489 amdgpu_reset_put_reset_domain(adev->reset_domain);
2490 adev->reset_domain = hive->reset_domain;
2491 amdgpu_put_xgmi_hive(hive);
2496 r = amdgpu_device_init_schedulers(adev);
2500 /* Don't init kfd if whole hive need to be reset during init */
2501 if (!adev->gmc.xgmi.pending_reset)
2502 amdgpu_amdkfd_device_init(adev);
2504 amdgpu_fru_get_product_info(adev);
2507 if (amdgpu_sriov_vf(adev))
2508 amdgpu_virt_release_full_gpu(adev, true);
2514 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2516 * @adev: amdgpu_device pointer
2518 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2519 * this function before a GPU reset. If the value is retained after a
2520 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2522 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2524 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2528 * amdgpu_device_check_vram_lost - check if vram is valid
2530 * @adev: amdgpu_device pointer
2532 * Checks the reset magic value written to the gart pointer in VRAM.
2533 * The driver calls this after a GPU reset to see if the contents of
2534 * VRAM is lost or now.
2535 * returns true if vram is lost, false if not.
2537 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2539 if (memcmp(adev->gart.ptr, adev->reset_magic,
2540 AMDGPU_RESET_MAGIC_NUM))
2543 if (!amdgpu_in_reset(adev))
2547 * For all ASICs with baco/mode1 reset, the VRAM is
2548 * always assumed to be lost.
2550 switch (amdgpu_asic_reset_method(adev)) {
2551 case AMD_RESET_METHOD_BACO:
2552 case AMD_RESET_METHOD_MODE1:
2560 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2562 * @adev: amdgpu_device pointer
2563 * @state: clockgating state (gate or ungate)
2565 * The list of all the hardware IPs that make up the asic is walked and the
2566 * set_clockgating_state callbacks are run.
2567 * Late initialization pass enabling clockgating for hardware IPs.
2568 * Fini or suspend, pass disabling clockgating for hardware IPs.
2569 * Returns 0 on success, negative error code on failure.
2572 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2573 enum amd_clockgating_state state)
2577 if (amdgpu_emu_mode == 1)
2580 for (j = 0; j < adev->num_ip_blocks; j++) {
2581 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2582 if (!adev->ip_blocks[i].status.late_initialized)
2584 /* skip CG for GFX on S0ix */
2585 if (adev->in_s0ix &&
2586 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)
2588 /* skip CG for VCE/UVD, it's handled specially */
2589 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2590 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2591 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2592 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2593 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2594 /* enable clockgating to save power */
2595 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2598 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2599 adev->ip_blocks[i].version->funcs->name, r);
2608 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2609 enum amd_powergating_state state)
2613 if (amdgpu_emu_mode == 1)
2616 for (j = 0; j < adev->num_ip_blocks; j++) {
2617 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2618 if (!adev->ip_blocks[i].status.late_initialized)
2620 /* skip PG for GFX on S0ix */
2621 if (adev->in_s0ix &&
2622 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)
2624 /* skip CG for VCE/UVD, it's handled specially */
2625 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2626 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2627 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2628 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2629 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2630 /* enable powergating to save power */
2631 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2634 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2635 adev->ip_blocks[i].version->funcs->name, r);
2643 static int amdgpu_device_enable_mgpu_fan_boost(void)
2645 struct amdgpu_gpu_instance *gpu_ins;
2646 struct amdgpu_device *adev;
2649 mutex_lock(&mgpu_info.mutex);
2652 * MGPU fan boost feature should be enabled
2653 * only when there are two or more dGPUs in
2656 if (mgpu_info.num_dgpu < 2)
2659 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2660 gpu_ins = &(mgpu_info.gpu_ins[i]);
2661 adev = gpu_ins->adev;
2662 if (!(adev->flags & AMD_IS_APU) &&
2663 !gpu_ins->mgpu_fan_enabled) {
2664 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2668 gpu_ins->mgpu_fan_enabled = 1;
2673 mutex_unlock(&mgpu_info.mutex);
2679 * amdgpu_device_ip_late_init - run late init for hardware IPs
2681 * @adev: amdgpu_device pointer
2683 * Late initialization pass for hardware IPs. The list of all the hardware
2684 * IPs that make up the asic is walked and the late_init callbacks are run.
2685 * late_init covers any special initialization that an IP requires
2686 * after all of the have been initialized or something that needs to happen
2687 * late in the init process.
2688 * Returns 0 on success, negative error code on failure.
2690 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2692 struct amdgpu_gpu_instance *gpu_instance;
2695 for (i = 0; i < adev->num_ip_blocks; i++) {
2696 if (!adev->ip_blocks[i].status.hw)
2698 if (adev->ip_blocks[i].version->funcs->late_init) {
2699 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2701 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2702 adev->ip_blocks[i].version->funcs->name, r);
2706 adev->ip_blocks[i].status.late_initialized = true;
2709 r = amdgpu_ras_late_init(adev);
2711 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
2715 amdgpu_ras_set_error_query_ready(adev, true);
2717 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2718 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2720 amdgpu_device_fill_reset_magic(adev);
2722 r = amdgpu_device_enable_mgpu_fan_boost();
2724 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2726 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
2727 if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||
2728 adev->asic_type == CHIP_ALDEBARAN ))
2729 amdgpu_dpm_handle_passthrough_sbr(adev, true);
2731 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2732 mutex_lock(&mgpu_info.mutex);
2735 * Reset device p-state to low as this was booted with high.
2737 * This should be performed only after all devices from the same
2738 * hive get initialized.
2740 * However, it's unknown how many device in the hive in advance.
2741 * As this is counted one by one during devices initializations.
2743 * So, we wait for all XGMI interlinked devices initialized.
2744 * This may bring some delays as those devices may come from
2745 * different hives. But that should be OK.
2747 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2748 for (i = 0; i < mgpu_info.num_gpu; i++) {
2749 gpu_instance = &(mgpu_info.gpu_ins[i]);
2750 if (gpu_instance->adev->flags & AMD_IS_APU)
2753 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2754 AMDGPU_XGMI_PSTATE_MIN);
2756 DRM_ERROR("pstate setting failed (%d).\n", r);
2762 mutex_unlock(&mgpu_info.mutex);
2769 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
2771 * @adev: amdgpu_device pointer
2773 * For ASICs need to disable SMC first
2775 static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
2779 if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
2782 for (i = 0; i < adev->num_ip_blocks; i++) {
2783 if (!adev->ip_blocks[i].status.hw)
2785 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2786 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2787 /* XXX handle errors */
2789 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2790 adev->ip_blocks[i].version->funcs->name, r);
2792 adev->ip_blocks[i].status.hw = false;
2798 static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
2802 for (i = 0; i < adev->num_ip_blocks; i++) {
2803 if (!adev->ip_blocks[i].version->funcs->early_fini)
2806 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
2808 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
2809 adev->ip_blocks[i].version->funcs->name, r);
2813 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2814 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2816 amdgpu_amdkfd_suspend(adev, false);
2818 /* Workaroud for ASICs need to disable SMC first */
2819 amdgpu_device_smu_fini_early(adev);
2821 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2822 if (!adev->ip_blocks[i].status.hw)
2825 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2826 /* XXX handle errors */
2828 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2829 adev->ip_blocks[i].version->funcs->name, r);
2832 adev->ip_blocks[i].status.hw = false;
2835 if (amdgpu_sriov_vf(adev)) {
2836 if (amdgpu_virt_release_full_gpu(adev, false))
2837 DRM_ERROR("failed to release exclusive mode on fini\n");
2844 * amdgpu_device_ip_fini - run fini for hardware IPs
2846 * @adev: amdgpu_device pointer
2848 * Main teardown pass for hardware IPs. The list of all the hardware
2849 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2850 * are run. hw_fini tears down the hardware associated with each IP
2851 * and sw_fini tears down any software state associated with each IP.
2852 * Returns 0 on success, negative error code on failure.
2854 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2858 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2859 amdgpu_virt_release_ras_err_handler_data(adev);
2861 if (adev->gmc.xgmi.num_physical_nodes > 1)
2862 amdgpu_xgmi_remove_device(adev);
2864 amdgpu_amdkfd_device_fini_sw(adev);
2866 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2867 if (!adev->ip_blocks[i].status.sw)
2870 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2871 amdgpu_ucode_free_bo(adev);
2872 amdgpu_free_static_csa(&adev->virt.csa_obj);
2873 amdgpu_device_wb_fini(adev);
2874 amdgpu_device_vram_scratch_fini(adev);
2875 amdgpu_ib_pool_fini(adev);
2878 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2879 /* XXX handle errors */
2881 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2882 adev->ip_blocks[i].version->funcs->name, r);
2884 adev->ip_blocks[i].status.sw = false;
2885 adev->ip_blocks[i].status.valid = false;
2888 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2889 if (!adev->ip_blocks[i].status.late_initialized)
2891 if (adev->ip_blocks[i].version->funcs->late_fini)
2892 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2893 adev->ip_blocks[i].status.late_initialized = false;
2896 amdgpu_ras_fini(adev);
2902 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2904 * @work: work_struct.
2906 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2908 struct amdgpu_device *adev =
2909 container_of(work, struct amdgpu_device, delayed_init_work.work);
2912 r = amdgpu_ib_ring_tests(adev);
2914 DRM_ERROR("ib ring test failed (%d).\n", r);
2917 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2919 struct amdgpu_device *adev =
2920 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2922 WARN_ON_ONCE(adev->gfx.gfx_off_state);
2923 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
2925 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2926 adev->gfx.gfx_off_state = true;
2930 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2932 * @adev: amdgpu_device pointer
2934 * Main suspend function for hardware IPs. The list of all the hardware
2935 * IPs that make up the asic is walked, clockgating is disabled and the
2936 * suspend callbacks are run. suspend puts the hardware and software state
2937 * in each IP into a state suitable for suspend.
2938 * Returns 0 on success, negative error code on failure.
2940 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2944 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2945 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2948 * Per PMFW team's suggestion, driver needs to handle gfxoff
2949 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
2950 * scenario. Add the missing df cstate disablement here.
2952 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
2953 dev_warn(adev->dev, "Failed to disallow df cstate");
2955 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2956 if (!adev->ip_blocks[i].status.valid)
2959 /* displays are handled separately */
2960 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2963 /* XXX handle errors */
2964 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2965 /* XXX handle errors */
2967 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2968 adev->ip_blocks[i].version->funcs->name, r);
2972 adev->ip_blocks[i].status.hw = false;
2979 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2981 * @adev: amdgpu_device pointer
2983 * Main suspend function for hardware IPs. The list of all the hardware
2984 * IPs that make up the asic is walked, clockgating is disabled and the
2985 * suspend callbacks are run. suspend puts the hardware and software state
2986 * in each IP into a state suitable for suspend.
2987 * Returns 0 on success, negative error code on failure.
2989 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2994 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
2996 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2997 if (!adev->ip_blocks[i].status.valid)
2999 /* displays are handled in phase1 */
3000 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3002 /* PSP lost connection when err_event_athub occurs */
3003 if (amdgpu_ras_intr_triggered() &&
3004 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3005 adev->ip_blocks[i].status.hw = false;
3009 /* skip unnecessary suspend if we do not initialize them yet */
3010 if (adev->gmc.xgmi.pending_reset &&
3011 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3012 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
3013 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3014 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
3015 adev->ip_blocks[i].status.hw = false;
3019 /* skip suspend of gfx/mes and psp for S0ix
3020 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3021 * like at runtime. PSP is also part of the always on hardware
3022 * so no need to suspend it.
3024 if (adev->in_s0ix &&
3025 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3026 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3027 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3030 /* XXX handle errors */
3031 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3032 /* XXX handle errors */
3034 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3035 adev->ip_blocks[i].version->funcs->name, r);
3037 adev->ip_blocks[i].status.hw = false;
3038 /* handle putting the SMC in the appropriate state */
3039 if(!amdgpu_sriov_vf(adev)){
3040 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3041 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3043 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3044 adev->mp1_state, r);
3055 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3057 * @adev: amdgpu_device pointer
3059 * Main suspend function for hardware IPs. The list of all the hardware
3060 * IPs that make up the asic is walked, clockgating is disabled and the
3061 * suspend callbacks are run. suspend puts the hardware and software state
3062 * in each IP into a state suitable for suspend.
3063 * Returns 0 on success, negative error code on failure.
3065 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3069 if (amdgpu_sriov_vf(adev)) {
3070 amdgpu_virt_fini_data_exchange(adev);
3071 amdgpu_virt_request_full_gpu(adev, false);
3074 r = amdgpu_device_ip_suspend_phase1(adev);
3077 r = amdgpu_device_ip_suspend_phase2(adev);
3079 if (amdgpu_sriov_vf(adev))
3080 amdgpu_virt_release_full_gpu(adev, false);
3085 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3089 static enum amd_ip_block_type ip_order[] = {
3090 AMD_IP_BLOCK_TYPE_COMMON,
3091 AMD_IP_BLOCK_TYPE_GMC,
3092 AMD_IP_BLOCK_TYPE_PSP,
3093 AMD_IP_BLOCK_TYPE_IH,
3096 for (i = 0; i < adev->num_ip_blocks; i++) {
3098 struct amdgpu_ip_block *block;
3100 block = &adev->ip_blocks[i];
3101 block->status.hw = false;
3103 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3105 if (block->version->type != ip_order[j] ||
3106 !block->status.valid)
3109 r = block->version->funcs->hw_init(adev);
3110 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3113 block->status.hw = true;
3120 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3124 static enum amd_ip_block_type ip_order[] = {
3125 AMD_IP_BLOCK_TYPE_SMC,
3126 AMD_IP_BLOCK_TYPE_DCE,
3127 AMD_IP_BLOCK_TYPE_GFX,
3128 AMD_IP_BLOCK_TYPE_SDMA,
3129 AMD_IP_BLOCK_TYPE_UVD,
3130 AMD_IP_BLOCK_TYPE_VCE,
3131 AMD_IP_BLOCK_TYPE_VCN
3134 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3136 struct amdgpu_ip_block *block;
3138 for (j = 0; j < adev->num_ip_blocks; j++) {
3139 block = &adev->ip_blocks[j];
3141 if (block->version->type != ip_order[i] ||
3142 !block->status.valid ||
3146 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3147 r = block->version->funcs->resume(adev);
3149 r = block->version->funcs->hw_init(adev);
3151 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3154 block->status.hw = true;
3162 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3164 * @adev: amdgpu_device pointer
3166 * First resume function for hardware IPs. The list of all the hardware
3167 * IPs that make up the asic is walked and the resume callbacks are run for
3168 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3169 * after a suspend and updates the software state as necessary. This
3170 * function is also used for restoring the GPU after a GPU reset.
3171 * Returns 0 on success, negative error code on failure.
3173 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3177 for (i = 0; i < adev->num_ip_blocks; i++) {
3178 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3180 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3181 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3182 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3183 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3185 r = adev->ip_blocks[i].version->funcs->resume(adev);
3187 DRM_ERROR("resume of IP block <%s> failed %d\n",
3188 adev->ip_blocks[i].version->funcs->name, r);
3191 adev->ip_blocks[i].status.hw = true;
3199 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3201 * @adev: amdgpu_device pointer
3203 * First resume function for hardware IPs. The list of all the hardware
3204 * IPs that make up the asic is walked and the resume callbacks are run for
3205 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3206 * functional state after a suspend and updates the software state as
3207 * necessary. This function is also used for restoring the GPU after a GPU
3209 * Returns 0 on success, negative error code on failure.
3211 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3215 for (i = 0; i < adev->num_ip_blocks; i++) {
3216 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3218 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3219 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3220 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3221 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3223 r = adev->ip_blocks[i].version->funcs->resume(adev);
3225 DRM_ERROR("resume of IP block <%s> failed %d\n",
3226 adev->ip_blocks[i].version->funcs->name, r);
3229 adev->ip_blocks[i].status.hw = true;
3231 if (adev->in_s0ix && adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3232 /* disable gfxoff for IP resume. The gfxoff will be re-enabled in
3233 * amdgpu_device_resume() after IP resume.
3235 amdgpu_gfx_off_ctrl(adev, false);
3236 DRM_DEBUG("will disable gfxoff for re-initializing other blocks\n");
3245 * amdgpu_device_ip_resume - run resume for hardware IPs
3247 * @adev: amdgpu_device pointer
3249 * Main resume function for hardware IPs. The hardware IPs
3250 * are split into two resume functions because they are
3251 * are also used in in recovering from a GPU reset and some additional
3252 * steps need to be take between them. In this case (S3/S4) they are
3254 * Returns 0 on success, negative error code on failure.
3256 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3260 r = amdgpu_amdkfd_resume_iommu(adev);
3264 r = amdgpu_device_ip_resume_phase1(adev);
3268 r = amdgpu_device_fw_loading(adev);
3272 r = amdgpu_device_ip_resume_phase2(adev);
3278 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3280 * @adev: amdgpu_device pointer
3282 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3284 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3286 if (amdgpu_sriov_vf(adev)) {
3287 if (adev->is_atom_fw) {
3288 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3289 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3291 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3292 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3295 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3296 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3301 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3303 * @asic_type: AMD asic type
3305 * Check if there is DC (new modesetting infrastructre) support for an asic.
3306 * returns true if DC has support, false if not.
3308 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3310 switch (asic_type) {
3311 #ifdef CONFIG_DRM_AMDGPU_SI
3315 /* chips with no display hardware */
3317 #if defined(CONFIG_DRM_AMD_DC)
3323 * We have systems in the wild with these ASICs that require
3324 * LVDS and VGA support which is not supported with DC.
3326 * Fallback to the non-DC driver here by default so as not to
3327 * cause regressions.
3329 #if defined(CONFIG_DRM_AMD_DC_SI)
3330 return amdgpu_dc > 0;
3339 * We have systems in the wild with these ASICs that require
3340 * VGA support which is not supported with DC.
3342 * Fallback to the non-DC driver here by default so as not to
3343 * cause regressions.
3345 return amdgpu_dc > 0;
3347 return amdgpu_dc != 0;
3351 DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
3352 "but isn't supported by ASIC, ignoring\n");
3359 * amdgpu_device_has_dc_support - check if dc is supported
3361 * @adev: amdgpu_device pointer
3363 * Returns true for supported, false for not supported
3365 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3367 if (adev->enable_virtual_display ||
3368 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3371 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3374 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3376 struct amdgpu_device *adev =
3377 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3378 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3380 /* It's a bug to not have a hive within this function */
3385 * Use task barrier to synchronize all xgmi reset works across the
3386 * hive. task_barrier_enter and task_barrier_exit will block
3387 * until all the threads running the xgmi reset works reach
3388 * those points. task_barrier_full will do both blocks.
3390 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3392 task_barrier_enter(&hive->tb);
3393 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3395 if (adev->asic_reset_res)
3398 task_barrier_exit(&hive->tb);
3399 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3401 if (adev->asic_reset_res)
3404 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
3405 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
3406 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
3409 task_barrier_full(&hive->tb);
3410 adev->asic_reset_res = amdgpu_asic_reset(adev);
3414 if (adev->asic_reset_res)
3415 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3416 adev->asic_reset_res, adev_to_drm(adev)->unique);
3417 amdgpu_put_xgmi_hive(hive);
3420 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3422 char *input = amdgpu_lockup_timeout;
3423 char *timeout_setting = NULL;
3429 * By default timeout for non compute jobs is 10000
3430 * and 60000 for compute jobs.
3431 * In SR-IOV or passthrough mode, timeout for compute
3432 * jobs are 60000 by default.
3434 adev->gfx_timeout = msecs_to_jiffies(10000);
3435 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3436 if (amdgpu_sriov_vf(adev))
3437 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3438 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3440 adev->compute_timeout = msecs_to_jiffies(60000);
3442 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3443 while ((timeout_setting = strsep(&input, ",")) &&
3444 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3445 ret = kstrtol(timeout_setting, 0, &timeout);
3452 } else if (timeout < 0) {
3453 timeout = MAX_SCHEDULE_TIMEOUT;
3454 dev_warn(adev->dev, "lockup timeout disabled");
3455 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3457 timeout = msecs_to_jiffies(timeout);
3462 adev->gfx_timeout = timeout;
3465 adev->compute_timeout = timeout;
3468 adev->sdma_timeout = timeout;
3471 adev->video_timeout = timeout;
3478 * There is only one value specified and
3479 * it should apply to all non-compute jobs.
3482 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3483 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3484 adev->compute_timeout = adev->gfx_timeout;
3492 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3494 * @adev: amdgpu_device pointer
3496 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3498 static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3500 struct iommu_domain *domain;
3502 domain = iommu_get_domain_for_dev(adev->dev);
3503 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3504 adev->ram_is_direct_mapped = true;
3507 static const struct attribute *amdgpu_dev_attributes[] = {
3508 &dev_attr_product_name.attr,
3509 &dev_attr_product_number.attr,
3510 &dev_attr_serial_number.attr,
3511 &dev_attr_pcie_replay_count.attr,
3516 * amdgpu_device_init - initialize the driver
3518 * @adev: amdgpu_device pointer
3519 * @flags: driver flags
3521 * Initializes the driver info and hw (all asics).
3522 * Returns 0 for success or an error on failure.
3523 * Called at driver startup.
3525 int amdgpu_device_init(struct amdgpu_device *adev,
3528 struct drm_device *ddev = adev_to_drm(adev);
3529 struct pci_dev *pdev = adev->pdev;
3534 adev->shutdown = false;
3535 adev->flags = flags;
3537 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3538 adev->asic_type = amdgpu_force_asic_type;
3540 adev->asic_type = flags & AMD_ASIC_MASK;
3542 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3543 if (amdgpu_emu_mode == 1)
3544 adev->usec_timeout *= 10;
3545 adev->gmc.gart_size = 512 * 1024 * 1024;
3546 adev->accel_working = false;
3547 adev->num_rings = 0;
3548 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3549 adev->mman.buffer_funcs = NULL;
3550 adev->mman.buffer_funcs_ring = NULL;
3551 adev->vm_manager.vm_pte_funcs = NULL;
3552 adev->vm_manager.vm_pte_num_scheds = 0;
3553 adev->gmc.gmc_funcs = NULL;
3554 adev->harvest_ip_mask = 0x0;
3555 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3556 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3558 adev->smc_rreg = &amdgpu_invalid_rreg;
3559 adev->smc_wreg = &amdgpu_invalid_wreg;
3560 adev->pcie_rreg = &amdgpu_invalid_rreg;
3561 adev->pcie_wreg = &amdgpu_invalid_wreg;
3562 adev->pciep_rreg = &amdgpu_invalid_rreg;
3563 adev->pciep_wreg = &amdgpu_invalid_wreg;
3564 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3565 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3566 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3567 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3568 adev->didt_rreg = &amdgpu_invalid_rreg;
3569 adev->didt_wreg = &amdgpu_invalid_wreg;
3570 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3571 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3572 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3573 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3575 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3576 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3577 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3579 /* mutex initialization are all done here so we
3580 * can recall function without having locking issues */
3581 mutex_init(&adev->firmware.mutex);
3582 mutex_init(&adev->pm.mutex);
3583 mutex_init(&adev->gfx.gpu_clock_mutex);
3584 mutex_init(&adev->srbm_mutex);
3585 mutex_init(&adev->gfx.pipe_reserve_mutex);
3586 mutex_init(&adev->gfx.gfx_off_mutex);
3587 mutex_init(&adev->grbm_idx_mutex);
3588 mutex_init(&adev->mn_lock);
3589 mutex_init(&adev->virt.vf_errors.lock);
3590 hash_init(adev->mn_hash);
3591 mutex_init(&adev->psp.mutex);
3592 mutex_init(&adev->notifier_lock);
3593 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3594 mutex_init(&adev->benchmark_mutex);
3596 amdgpu_device_init_apu_flags(adev);
3598 r = amdgpu_device_check_arguments(adev);
3602 spin_lock_init(&adev->mmio_idx_lock);
3603 spin_lock_init(&adev->smc_idx_lock);
3604 spin_lock_init(&adev->pcie_idx_lock);
3605 spin_lock_init(&adev->uvd_ctx_idx_lock);
3606 spin_lock_init(&adev->didt_idx_lock);
3607 spin_lock_init(&adev->gc_cac_idx_lock);
3608 spin_lock_init(&adev->se_cac_idx_lock);
3609 spin_lock_init(&adev->audio_endpt_idx_lock);
3610 spin_lock_init(&adev->mm_stats.lock);
3612 INIT_LIST_HEAD(&adev->shadow_list);
3613 mutex_init(&adev->shadow_list_lock);
3615 INIT_LIST_HEAD(&adev->reset_list);
3617 INIT_LIST_HEAD(&adev->ras_list);
3619 INIT_DELAYED_WORK(&adev->delayed_init_work,
3620 amdgpu_device_delayed_init_work_handler);
3621 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3622 amdgpu_device_delay_enable_gfx_off);
3624 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3626 adev->gfx.gfx_off_req_count = 1;
3627 adev->gfx.gfx_off_residency = 0;
3628 adev->gfx.gfx_off_entrycount = 0;
3629 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3631 atomic_set(&adev->throttling_logging_enabled, 1);
3633 * If throttling continues, logging will be performed every minute
3634 * to avoid log flooding. "-1" is subtracted since the thermal
3635 * throttling interrupt comes every second. Thus, the total logging
3636 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3637 * for throttling interrupt) = 60 seconds.
3639 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3640 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3642 /* Registers mapping */
3643 /* TODO: block userspace mapping of io register */
3644 if (adev->asic_type >= CHIP_BONAIRE) {
3645 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3646 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3648 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3649 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3652 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
3653 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
3655 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3656 if (adev->rmmio == NULL) {
3659 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3660 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3662 amdgpu_device_get_pcie_info(adev);
3665 DRM_INFO("MCBP is enabled\n");
3668 * Reset domain needs to be present early, before XGMI hive discovered
3669 * (if any) and intitialized to use reset sem and in_gpu reset flag
3670 * early on during init and before calling to RREG32.
3672 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
3673 if (!adev->reset_domain)
3676 /* detect hw virtualization here */
3677 amdgpu_detect_virtualization(adev);
3679 r = amdgpu_device_get_job_timeout_settings(adev);
3681 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3685 /* early init functions */
3686 r = amdgpu_device_ip_early_init(adev);
3690 /* Enable TMZ based on IP_VERSION */
3691 amdgpu_gmc_tmz_set(adev);
3693 amdgpu_gmc_noretry_set(adev);
3694 /* Need to get xgmi info early to decide the reset behavior*/
3695 if (adev->gmc.xgmi.supported) {
3696 r = adev->gfxhub.funcs->get_xgmi_info(adev);
3701 /* enable PCIE atomic ops */
3702 if (amdgpu_sriov_vf(adev))
3703 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
3704 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
3705 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3707 adev->have_atomics_support =
3708 !pci_enable_atomic_ops_to_root(adev->pdev,
3709 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3710 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3711 if (!adev->have_atomics_support)
3712 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
3714 /* doorbell bar mapping and doorbell index init*/
3715 amdgpu_device_doorbell_init(adev);
3717 if (amdgpu_emu_mode == 1) {
3718 /* post the asic on emulation mode */
3719 emu_soc_asic_init(adev);
3720 goto fence_driver_init;
3723 amdgpu_reset_init(adev);
3725 /* detect if we are with an SRIOV vbios */
3726 amdgpu_device_detect_sriov_bios(adev);
3728 /* check if we need to reset the asic
3729 * E.g., driver was not cleanly unloaded previously, etc.
3731 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3732 if (adev->gmc.xgmi.num_physical_nodes) {
3733 dev_info(adev->dev, "Pending hive reset.\n");
3734 adev->gmc.xgmi.pending_reset = true;
3735 /* Only need to init necessary block for SMU to handle the reset */
3736 for (i = 0; i < adev->num_ip_blocks; i++) {
3737 if (!adev->ip_blocks[i].status.valid)
3739 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3740 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3741 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3742 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
3743 DRM_DEBUG("IP %s disabled for hw_init.\n",
3744 adev->ip_blocks[i].version->funcs->name);
3745 adev->ip_blocks[i].status.hw = true;
3749 r = amdgpu_asic_reset(adev);
3751 dev_err(adev->dev, "asic reset on init failed\n");
3757 pci_enable_pcie_error_reporting(adev->pdev);
3759 /* Post card if necessary */
3760 if (amdgpu_device_need_post(adev)) {
3762 dev_err(adev->dev, "no vBIOS found\n");
3766 DRM_INFO("GPU posting now...\n");
3767 r = amdgpu_device_asic_init(adev);
3769 dev_err(adev->dev, "gpu post error!\n");
3774 if (adev->is_atom_fw) {
3775 /* Initialize clocks */
3776 r = amdgpu_atomfirmware_get_clock_info(adev);
3778 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3779 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3783 /* Initialize clocks */
3784 r = amdgpu_atombios_get_clock_info(adev);
3786 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3787 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3790 /* init i2c buses */
3791 if (!amdgpu_device_has_dc_support(adev))
3792 amdgpu_atombios_i2c_init(adev);
3797 r = amdgpu_fence_driver_sw_init(adev);
3799 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
3800 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3804 /* init the mode config */
3805 drm_mode_config_init(adev_to_drm(adev));
3807 r = amdgpu_device_ip_init(adev);
3809 /* failed in exclusive mode due to timeout */
3810 if (amdgpu_sriov_vf(adev) &&
3811 !amdgpu_sriov_runtime(adev) &&
3812 amdgpu_virt_mmio_blocked(adev) &&
3813 !amdgpu_virt_wait_reset(adev)) {
3814 dev_err(adev->dev, "VF exclusive mode timeout\n");
3815 /* Don't send request since VF is inactive. */
3816 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3817 adev->virt.ops = NULL;
3819 goto release_ras_con;
3821 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3822 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3823 goto release_ras_con;
3826 amdgpu_fence_driver_hw_init(adev);
3829 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3830 adev->gfx.config.max_shader_engines,
3831 adev->gfx.config.max_sh_per_se,
3832 adev->gfx.config.max_cu_per_sh,
3833 adev->gfx.cu_info.number);
3835 adev->accel_working = true;
3837 amdgpu_vm_check_compute_bug(adev);
3839 /* Initialize the buffer migration limit. */
3840 if (amdgpu_moverate >= 0)
3841 max_MBps = amdgpu_moverate;
3843 max_MBps = 8; /* Allow 8 MB/s. */
3844 /* Get a log2 for easy divisions. */
3845 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3847 r = amdgpu_pm_sysfs_init(adev);
3849 adev->pm_sysfs_en = false;
3850 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3852 adev->pm_sysfs_en = true;
3854 r = amdgpu_ucode_sysfs_init(adev);
3856 adev->ucode_sysfs_en = false;
3857 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3859 adev->ucode_sysfs_en = true;
3861 r = amdgpu_psp_sysfs_init(adev);
3863 adev->psp_sysfs_en = false;
3864 if (!amdgpu_sriov_vf(adev))
3865 DRM_ERROR("Creating psp sysfs failed\n");
3867 adev->psp_sysfs_en = true;
3870 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3871 * Otherwise the mgpu fan boost feature will be skipped due to the
3872 * gpu instance is counted less.
3874 amdgpu_register_gpu_instance(adev);
3876 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3877 * explicit gating rather than handling it automatically.
3879 if (!adev->gmc.xgmi.pending_reset) {
3880 r = amdgpu_device_ip_late_init(adev);
3882 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3883 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3884 goto release_ras_con;
3887 amdgpu_ras_resume(adev);
3888 queue_delayed_work(system_wq, &adev->delayed_init_work,
3889 msecs_to_jiffies(AMDGPU_RESUME_MS));
3892 if (amdgpu_sriov_vf(adev))
3893 flush_delayed_work(&adev->delayed_init_work);
3895 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3897 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3899 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3900 r = amdgpu_pmu_init(adev);
3902 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3904 /* Have stored pci confspace at hand for restore in sudden PCI error */
3905 if (amdgpu_device_cache_pci_state(adev->pdev))
3906 pci_restore_state(pdev);
3908 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3909 /* this will fail for cards that aren't VGA class devices, just
3911 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3912 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
3914 if (amdgpu_device_supports_px(ddev)) {
3916 vga_switcheroo_register_client(adev->pdev,
3917 &amdgpu_switcheroo_ops, px);
3918 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3921 if (adev->gmc.xgmi.pending_reset)
3922 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
3923 msecs_to_jiffies(AMDGPU_RESUME_MS));
3925 amdgpu_device_check_iommu_direct_map(adev);
3930 amdgpu_release_ras_context(adev);
3933 amdgpu_vf_error_trans_all(adev);
3938 static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
3941 /* Clear all CPU mappings pointing to this device */
3942 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
3944 /* Unmap all mapped bars - Doorbell, registers and VRAM */
3945 amdgpu_device_doorbell_fini(adev);
3947 iounmap(adev->rmmio);
3949 if (adev->mman.aper_base_kaddr)
3950 iounmap(adev->mman.aper_base_kaddr);
3951 adev->mman.aper_base_kaddr = NULL;
3953 /* Memory manager related */
3954 if (!adev->gmc.xgmi.connected_to_cpu) {
3955 arch_phys_wc_del(adev->gmc.vram_mtrr);
3956 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
3961 * amdgpu_device_fini_hw - tear down the driver
3963 * @adev: amdgpu_device pointer
3965 * Tear down the driver info (all asics).
3966 * Called at driver shutdown.
3968 void amdgpu_device_fini_hw(struct amdgpu_device *adev)
3970 dev_info(adev->dev, "amdgpu: finishing device.\n");
3971 flush_delayed_work(&adev->delayed_init_work);
3972 adev->shutdown = true;
3974 /* make sure IB test finished before entering exclusive mode
3975 * to avoid preemption on IB test
3977 if (amdgpu_sriov_vf(adev)) {
3978 amdgpu_virt_request_full_gpu(adev, false);
3979 amdgpu_virt_fini_data_exchange(adev);
3982 /* disable all interrupts */
3983 amdgpu_irq_disable_all(adev);
3984 if (adev->mode_info.mode_config_initialized){
3985 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
3986 drm_helper_force_disable_all(adev_to_drm(adev));
3988 drm_atomic_helper_shutdown(adev_to_drm(adev));
3990 amdgpu_fence_driver_hw_fini(adev);
3992 if (adev->mman.initialized) {
3993 flush_delayed_work(&adev->mman.bdev.wq);
3994 ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3997 if (adev->pm_sysfs_en)
3998 amdgpu_pm_sysfs_fini(adev);
3999 if (adev->ucode_sysfs_en)
4000 amdgpu_ucode_sysfs_fini(adev);
4001 if (adev->psp_sysfs_en)
4002 amdgpu_psp_sysfs_fini(adev);
4003 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4005 /* disable ras feature must before hw fini */
4006 amdgpu_ras_pre_fini(adev);
4008 amdgpu_device_ip_fini_early(adev);
4010 amdgpu_irq_fini_hw(adev);
4012 if (adev->mman.initialized)
4013 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4015 amdgpu_gart_dummy_page_fini(adev);
4017 amdgpu_device_unmap_mmio(adev);
4021 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4025 amdgpu_fence_driver_sw_fini(adev);
4026 amdgpu_device_ip_fini(adev);
4027 release_firmware(adev->firmware.gpu_info_fw);
4028 adev->firmware.gpu_info_fw = NULL;
4029 adev->accel_working = false;
4030 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4032 amdgpu_reset_fini(adev);
4034 /* free i2c buses */
4035 if (!amdgpu_device_has_dc_support(adev))
4036 amdgpu_i2c_fini(adev);
4038 if (amdgpu_emu_mode != 1)
4039 amdgpu_atombios_fini(adev);
4043 if (amdgpu_device_supports_px(adev_to_drm(adev))) {
4044 vga_switcheroo_unregister_client(adev->pdev);
4045 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4047 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4048 vga_client_unregister(adev->pdev);
4050 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4052 iounmap(adev->rmmio);
4054 amdgpu_device_doorbell_fini(adev);
4058 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4059 amdgpu_pmu_fini(adev);
4060 if (adev->mman.discovery_bin)
4061 amdgpu_discovery_fini(adev);
4063 amdgpu_reset_put_reset_domain(adev->reset_domain);
4064 adev->reset_domain = NULL;
4066 kfree(adev->pci_state);
4071 * amdgpu_device_evict_resources - evict device resources
4072 * @adev: amdgpu device object
4074 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4075 * of the vram memory type. Mainly used for evicting device resources
4079 static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4083 /* No need to evict vram on APUs for suspend to ram or s2idle */
4084 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4087 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4089 DRM_WARN("evicting device resources failed\n");
4097 * amdgpu_device_suspend - initiate device suspend
4099 * @dev: drm dev pointer
4100 * @fbcon : notify the fbdev of suspend
4102 * Puts the hw in the suspend state (all asics).
4103 * Returns 0 for success or an error on failure.
4104 * Called at driver suspend.
4106 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4108 struct amdgpu_device *adev = drm_to_adev(dev);
4111 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4114 adev->in_suspend = true;
4116 /* Evict the majority of BOs before grabbing the full access */
4117 r = amdgpu_device_evict_resources(adev);
4121 if (amdgpu_sriov_vf(adev)) {
4122 amdgpu_virt_fini_data_exchange(adev);
4123 r = amdgpu_virt_request_full_gpu(adev, false);
4128 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4129 DRM_WARN("smart shift update failed\n");
4131 drm_kms_helper_poll_disable(dev);
4134 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4136 cancel_delayed_work_sync(&adev->delayed_init_work);
4138 amdgpu_ras_suspend(adev);
4140 amdgpu_device_ip_suspend_phase1(adev);
4143 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4145 r = amdgpu_device_evict_resources(adev);
4149 amdgpu_fence_driver_hw_fini(adev);
4151 amdgpu_device_ip_suspend_phase2(adev);
4153 if (amdgpu_sriov_vf(adev))
4154 amdgpu_virt_release_full_gpu(adev, false);
4160 * amdgpu_device_resume - initiate device resume
4162 * @dev: drm dev pointer
4163 * @fbcon : notify the fbdev of resume
4165 * Bring the hw back to operating state (all asics).
4166 * Returns 0 for success or an error on failure.
4167 * Called at driver resume.
4169 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4171 struct amdgpu_device *adev = drm_to_adev(dev);
4174 if (amdgpu_sriov_vf(adev)) {
4175 r = amdgpu_virt_request_full_gpu(adev, true);
4180 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4184 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4187 if (amdgpu_device_need_post(adev)) {
4188 r = amdgpu_device_asic_init(adev);
4190 dev_err(adev->dev, "amdgpu asic init failed\n");
4193 r = amdgpu_device_ip_resume(adev);
4196 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4199 amdgpu_fence_driver_hw_init(adev);
4201 r = amdgpu_device_ip_late_init(adev);
4205 queue_delayed_work(system_wq, &adev->delayed_init_work,
4206 msecs_to_jiffies(AMDGPU_RESUME_MS));
4208 if (!adev->in_s0ix) {
4209 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4215 if (amdgpu_sriov_vf(adev)) {
4216 amdgpu_virt_init_data_exchange(adev);
4217 amdgpu_virt_release_full_gpu(adev, true);
4223 /* Make sure IB tests flushed */
4224 flush_delayed_work(&adev->delayed_init_work);
4226 if (adev->in_s0ix) {
4227 /* re-enable gfxoff after IP resume. This re-enables gfxoff after
4228 * it was disabled for IP resume in amdgpu_device_ip_resume_phase2().
4230 amdgpu_gfx_off_ctrl(adev, true);
4231 DRM_DEBUG("will enable gfxoff for the mission mode\n");
4234 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4236 drm_kms_helper_poll_enable(dev);
4238 amdgpu_ras_resume(adev);
4240 if (adev->mode_info.num_crtc) {
4242 * Most of the connector probing functions try to acquire runtime pm
4243 * refs to ensure that the GPU is powered on when connector polling is
4244 * performed. Since we're calling this from a runtime PM callback,
4245 * trying to acquire rpm refs will cause us to deadlock.
4247 * Since we're guaranteed to be holding the rpm lock, it's safe to
4248 * temporarily disable the rpm helpers so this doesn't deadlock us.
4251 dev->dev->power.disable_depth++;
4253 if (!adev->dc_enabled)
4254 drm_helper_hpd_irq_event(dev);
4256 drm_kms_helper_hotplug_event(dev);
4258 dev->dev->power.disable_depth--;
4261 adev->in_suspend = false;
4263 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4264 DRM_WARN("smart shift update failed\n");
4270 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4272 * @adev: amdgpu_device pointer
4274 * The list of all the hardware IPs that make up the asic is walked and
4275 * the check_soft_reset callbacks are run. check_soft_reset determines
4276 * if the asic is still hung or not.
4277 * Returns true if any of the IPs are still in a hung state, false if not.
4279 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4282 bool asic_hang = false;
4284 if (amdgpu_sriov_vf(adev))
4287 if (amdgpu_asic_need_full_reset(adev))
4290 for (i = 0; i < adev->num_ip_blocks; i++) {
4291 if (!adev->ip_blocks[i].status.valid)
4293 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4294 adev->ip_blocks[i].status.hang =
4295 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4296 if (adev->ip_blocks[i].status.hang) {
4297 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4305 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4307 * @adev: amdgpu_device pointer
4309 * The list of all the hardware IPs that make up the asic is walked and the
4310 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4311 * handles any IP specific hardware or software state changes that are
4312 * necessary for a soft reset to succeed.
4313 * Returns 0 on success, negative error code on failure.
4315 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4319 for (i = 0; i < adev->num_ip_blocks; i++) {
4320 if (!adev->ip_blocks[i].status.valid)
4322 if (adev->ip_blocks[i].status.hang &&
4323 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4324 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4334 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4336 * @adev: amdgpu_device pointer
4338 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4339 * reset is necessary to recover.
4340 * Returns true if a full asic reset is required, false if not.
4342 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4346 if (amdgpu_asic_need_full_reset(adev))
4349 for (i = 0; i < adev->num_ip_blocks; i++) {
4350 if (!adev->ip_blocks[i].status.valid)
4352 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4353 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4354 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4355 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4356 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4357 if (adev->ip_blocks[i].status.hang) {
4358 dev_info(adev->dev, "Some block need full reset!\n");
4367 * amdgpu_device_ip_soft_reset - do a soft reset
4369 * @adev: amdgpu_device pointer
4371 * The list of all the hardware IPs that make up the asic is walked and the
4372 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4373 * IP specific hardware or software state changes that are necessary to soft
4375 * Returns 0 on success, negative error code on failure.
4377 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4381 for (i = 0; i < adev->num_ip_blocks; i++) {
4382 if (!adev->ip_blocks[i].status.valid)
4384 if (adev->ip_blocks[i].status.hang &&
4385 adev->ip_blocks[i].version->funcs->soft_reset) {
4386 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4396 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4398 * @adev: amdgpu_device pointer
4400 * The list of all the hardware IPs that make up the asic is walked and the
4401 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4402 * handles any IP specific hardware or software state changes that are
4403 * necessary after the IP has been soft reset.
4404 * Returns 0 on success, negative error code on failure.
4406 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4410 for (i = 0; i < adev->num_ip_blocks; i++) {
4411 if (!adev->ip_blocks[i].status.valid)
4413 if (adev->ip_blocks[i].status.hang &&
4414 adev->ip_blocks[i].version->funcs->post_soft_reset)
4415 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4424 * amdgpu_device_recover_vram - Recover some VRAM contents
4426 * @adev: amdgpu_device pointer
4428 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4429 * restore things like GPUVM page tables after a GPU reset where
4430 * the contents of VRAM might be lost.
4433 * 0 on success, negative error code on failure.
4435 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4437 struct dma_fence *fence = NULL, *next = NULL;
4438 struct amdgpu_bo *shadow;
4439 struct amdgpu_bo_vm *vmbo;
4442 if (amdgpu_sriov_runtime(adev))
4443 tmo = msecs_to_jiffies(8000);
4445 tmo = msecs_to_jiffies(100);
4447 dev_info(adev->dev, "recover vram bo from shadow start\n");
4448 mutex_lock(&adev->shadow_list_lock);
4449 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4451 /* No need to recover an evicted BO */
4452 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4453 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4454 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4457 r = amdgpu_bo_restore_shadow(shadow, &next);
4462 tmo = dma_fence_wait_timeout(fence, false, tmo);
4463 dma_fence_put(fence);
4468 } else if (tmo < 0) {
4476 mutex_unlock(&adev->shadow_list_lock);
4479 tmo = dma_fence_wait_timeout(fence, false, tmo);
4480 dma_fence_put(fence);
4482 if (r < 0 || tmo <= 0) {
4483 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4487 dev_info(adev->dev, "recover vram bo from shadow done\n");
4493 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4495 * @adev: amdgpu_device pointer
4496 * @from_hypervisor: request from hypervisor
4498 * do VF FLR and reinitialize Asic
4499 * return 0 means succeeded otherwise failed
4501 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4502 bool from_hypervisor)
4505 struct amdgpu_hive_info *hive = NULL;
4506 int retry_limit = 0;
4509 amdgpu_amdkfd_pre_reset(adev);
4511 if (from_hypervisor)
4512 r = amdgpu_virt_request_full_gpu(adev, true);
4514 r = amdgpu_virt_reset_gpu(adev);
4518 /* Resume IP prior to SMC */
4519 r = amdgpu_device_ip_reinit_early_sriov(adev);
4523 amdgpu_virt_init_data_exchange(adev);
4525 r = amdgpu_device_fw_loading(adev);
4529 /* now we are okay to resume SMC/CP/SDMA */
4530 r = amdgpu_device_ip_reinit_late_sriov(adev);
4534 hive = amdgpu_get_xgmi_hive(adev);
4535 /* Update PSP FW topology after reset */
4536 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
4537 r = amdgpu_xgmi_update_topology(hive, adev);
4540 amdgpu_put_xgmi_hive(hive);
4543 amdgpu_irq_gpu_reset_resume_helper(adev);
4544 r = amdgpu_ib_ring_tests(adev);
4546 amdgpu_amdkfd_post_reset(adev);
4550 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4551 amdgpu_inc_vram_lost(adev);
4552 r = amdgpu_device_recover_vram(adev);
4554 amdgpu_virt_release_full_gpu(adev, true);
4556 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
4557 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
4561 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
4568 * amdgpu_device_has_job_running - check if there is any job in mirror list
4570 * @adev: amdgpu_device pointer
4572 * check if there is any job in mirror list
4574 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4577 struct drm_sched_job *job;
4579 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4580 struct amdgpu_ring *ring = adev->rings[i];
4582 if (!ring || !ring->sched.thread)
4585 spin_lock(&ring->sched.job_list_lock);
4586 job = list_first_entry_or_null(&ring->sched.pending_list,
4587 struct drm_sched_job, list);
4588 spin_unlock(&ring->sched.job_list_lock);
4596 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4598 * @adev: amdgpu_device pointer
4600 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4603 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4606 if (amdgpu_gpu_recovery == 0)
4609 /* Skip soft reset check in fatal error mode */
4610 if (!amdgpu_ras_is_poison_mode_supported(adev))
4613 if (!amdgpu_device_ip_check_soft_reset(adev)) {
4614 dev_info(adev->dev,"Timeout, but no hardware hang detected.\n");
4618 if (amdgpu_sriov_vf(adev))
4621 if (amdgpu_gpu_recovery == -1) {
4622 switch (adev->asic_type) {
4623 #ifdef CONFIG_DRM_AMDGPU_SI
4630 #ifdef CONFIG_DRM_AMDGPU_CIK
4637 case CHIP_CYAN_SKILLFISH:
4647 dev_info(adev->dev, "GPU recovery disabled.\n");
4651 int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
4656 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
4658 dev_info(adev->dev, "GPU mode1 reset\n");
4661 pci_clear_master(adev->pdev);
4663 amdgpu_device_cache_pci_state(adev->pdev);
4665 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
4666 dev_info(adev->dev, "GPU smu mode1 reset\n");
4667 ret = amdgpu_dpm_mode1_reset(adev);
4669 dev_info(adev->dev, "GPU psp mode1 reset\n");
4670 ret = psp_gpu_reset(adev);
4674 dev_err(adev->dev, "GPU mode1 reset failed\n");
4676 amdgpu_device_load_pci_state(adev->pdev);
4678 /* wait for asic to come out of reset */
4679 for (i = 0; i < adev->usec_timeout; i++) {
4680 u32 memsize = adev->nbio.funcs->get_memsize(adev);
4682 if (memsize != 0xffffffff)
4687 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
4691 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4692 struct amdgpu_reset_context *reset_context)
4695 struct amdgpu_job *job = NULL;
4696 bool need_full_reset =
4697 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4699 if (reset_context->reset_req_dev == adev)
4700 job = reset_context->job;
4702 if (amdgpu_sriov_vf(adev)) {
4703 /* stop the data exchange thread */
4704 amdgpu_virt_fini_data_exchange(adev);
4707 amdgpu_fence_driver_isr_toggle(adev, true);
4709 /* block all schedulers and reset given job's ring */
4710 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4711 struct amdgpu_ring *ring = adev->rings[i];
4713 if (!ring || !ring->sched.thread)
4716 /*clear job fence from fence drv to avoid force_completion
4717 *leave NULL and vm flush fence in fence drv */
4718 amdgpu_fence_driver_clear_job_fences(ring);
4720 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4721 amdgpu_fence_driver_force_completion(ring);
4724 amdgpu_fence_driver_isr_toggle(adev, false);
4727 drm_sched_increase_karma(&job->base);
4729 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
4730 /* If reset handler not implemented, continue; otherwise return */
4736 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4737 if (!amdgpu_sriov_vf(adev)) {
4739 if (!need_full_reset)
4740 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4742 if (!need_full_reset && amdgpu_gpu_recovery) {
4743 amdgpu_device_ip_pre_soft_reset(adev);
4744 r = amdgpu_device_ip_soft_reset(adev);
4745 amdgpu_device_ip_post_soft_reset(adev);
4746 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4747 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4748 need_full_reset = true;
4752 if (need_full_reset)
4753 r = amdgpu_device_ip_suspend(adev);
4754 if (need_full_reset)
4755 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4757 clear_bit(AMDGPU_NEED_FULL_RESET,
4758 &reset_context->flags);
4764 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
4768 lockdep_assert_held(&adev->reset_domain->sem);
4770 for (i = 0; i < adev->num_regs; i++) {
4771 adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]);
4772 trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i],
4773 adev->reset_dump_reg_value[i]);
4779 #ifdef CONFIG_DEV_COREDUMP
4780 static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset,
4781 size_t count, void *data, size_t datalen)
4783 struct drm_printer p;
4784 struct amdgpu_device *adev = data;
4785 struct drm_print_iterator iter;
4790 iter.start = offset;
4791 iter.remain = count;
4793 p = drm_coredump_printer(&iter);
4795 drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
4796 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
4797 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
4798 drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec);
4799 if (adev->reset_task_info.pid)
4800 drm_printf(&p, "process_name: %s PID: %d\n",
4801 adev->reset_task_info.process_name,
4802 adev->reset_task_info.pid);
4804 if (adev->reset_vram_lost)
4805 drm_printf(&p, "VRAM is lost due to GPU reset!\n");
4806 if (adev->num_regs) {
4807 drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n");
4809 for (i = 0; i < adev->num_regs; i++)
4810 drm_printf(&p, "0x%08x: 0x%08x\n",
4811 adev->reset_dump_reg_list[i],
4812 adev->reset_dump_reg_value[i]);
4815 return count - iter.remain;
4818 static void amdgpu_devcoredump_free(void *data)
4822 static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev)
4824 struct drm_device *dev = adev_to_drm(adev);
4826 ktime_get_ts64(&adev->reset_time);
4827 dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_KERNEL,
4828 amdgpu_devcoredump_read, amdgpu_devcoredump_free);
4832 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
4833 struct amdgpu_reset_context *reset_context)
4835 struct amdgpu_device *tmp_adev = NULL;
4836 bool need_full_reset, skip_hw_reset, vram_lost = false;
4838 bool gpu_reset_for_dev_remove = 0;
4840 /* Try reset handler method first */
4841 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
4843 amdgpu_reset_reg_dumps(tmp_adev);
4845 reset_context->reset_device_list = device_list_handle;
4846 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
4847 /* If reset handler not implemented, continue; otherwise return */
4853 /* Reset handler not implemented, use the default method */
4855 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4856 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
4858 gpu_reset_for_dev_remove =
4859 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
4860 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4863 * ASIC reset has to be done on all XGMI hive nodes ASAP
4864 * to allow proper links negotiation in FW (within 1 sec)
4866 if (!skip_hw_reset && need_full_reset) {
4867 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4868 /* For XGMI run all resets in parallel to speed up the process */
4869 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4870 tmp_adev->gmc.xgmi.pending_reset = false;
4871 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4874 r = amdgpu_asic_reset(tmp_adev);
4877 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4878 r, adev_to_drm(tmp_adev)->unique);
4883 /* For XGMI wait for all resets to complete before proceed */
4885 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4886 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4887 flush_work(&tmp_adev->xgmi_reset_work);
4888 r = tmp_adev->asic_reset_res;
4896 if (!r && amdgpu_ras_intr_triggered()) {
4897 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4898 if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops &&
4899 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
4900 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev);
4903 amdgpu_ras_intr_cleared();
4906 /* Since the mode1 reset affects base ip blocks, the
4907 * phase1 ip blocks need to be resumed. Otherwise there
4908 * will be a BIOS signature error and the psp bootloader
4909 * can't load kdb on the next amdgpu install.
4911 if (gpu_reset_for_dev_remove) {
4912 list_for_each_entry(tmp_adev, device_list_handle, reset_list)
4913 amdgpu_device_ip_resume_phase1(tmp_adev);
4918 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4919 if (need_full_reset) {
4921 r = amdgpu_device_asic_init(tmp_adev);
4923 dev_warn(tmp_adev->dev, "asic atom init failed!");
4925 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4926 r = amdgpu_amdkfd_resume_iommu(tmp_adev);
4930 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4934 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4935 #ifdef CONFIG_DEV_COREDUMP
4936 tmp_adev->reset_vram_lost = vram_lost;
4937 memset(&tmp_adev->reset_task_info, 0,
4938 sizeof(tmp_adev->reset_task_info));
4939 if (reset_context->job && reset_context->job->vm)
4940 tmp_adev->reset_task_info =
4941 reset_context->job->vm->task_info;
4942 amdgpu_reset_capture_coredumpm(tmp_adev);
4945 DRM_INFO("VRAM is lost due to GPU reset!\n");
4946 amdgpu_inc_vram_lost(tmp_adev);
4949 r = amdgpu_device_fw_loading(tmp_adev);
4953 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4958 amdgpu_device_fill_reset_magic(tmp_adev);
4961 * Add this ASIC as tracked as reset was already
4962 * complete successfully.
4964 amdgpu_register_gpu_instance(tmp_adev);
4966 if (!reset_context->hive &&
4967 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4968 amdgpu_xgmi_add_device(tmp_adev);
4970 r = amdgpu_device_ip_late_init(tmp_adev);
4974 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
4977 * The GPU enters bad state once faulty pages
4978 * by ECC has reached the threshold, and ras
4979 * recovery is scheduled next. So add one check
4980 * here to break recovery if it indeed exceeds
4981 * bad page threshold, and remind user to
4982 * retire this GPU or setting one bigger
4983 * bad_page_threshold value to fix this once
4984 * probing driver again.
4986 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
4988 amdgpu_ras_resume(tmp_adev);
4994 /* Update PSP FW topology after reset */
4995 if (reset_context->hive &&
4996 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4997 r = amdgpu_xgmi_update_topology(
4998 reset_context->hive, tmp_adev);
5004 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5005 r = amdgpu_ib_ring_tests(tmp_adev);
5007 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5008 need_full_reset = true;
5015 r = amdgpu_device_recover_vram(tmp_adev);
5017 tmp_adev->asic_reset_res = r;
5021 if (need_full_reset)
5022 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5024 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5028 static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5031 switch (amdgpu_asic_reset_method(adev)) {
5032 case AMD_RESET_METHOD_MODE1:
5033 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5035 case AMD_RESET_METHOD_MODE2:
5036 adev->mp1_state = PP_MP1_STATE_RESET;
5039 adev->mp1_state = PP_MP1_STATE_NONE;
5044 static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5046 amdgpu_vf_error_trans_all(adev);
5047 adev->mp1_state = PP_MP1_STATE_NONE;
5050 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5052 struct pci_dev *p = NULL;
5054 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5055 adev->pdev->bus->number, 1);
5057 pm_runtime_enable(&(p->dev));
5058 pm_runtime_resume(&(p->dev));
5064 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5066 enum amd_reset_method reset_method;
5067 struct pci_dev *p = NULL;
5071 * For now, only BACO and mode1 reset are confirmed
5072 * to suffer the audio issue without proper suspended.
5074 reset_method = amdgpu_asic_reset_method(adev);
5075 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5076 (reset_method != AMD_RESET_METHOD_MODE1))
5079 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5080 adev->pdev->bus->number, 1);
5084 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5087 * If we cannot get the audio device autosuspend delay,
5088 * a fixed 4S interval will be used. Considering 3S is
5089 * the audio controller default autosuspend delay setting.
5090 * 4S used here is guaranteed to cover that.
5092 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5094 while (!pm_runtime_status_suspended(&(p->dev))) {
5095 if (!pm_runtime_suspend(&(p->dev)))
5098 if (expires < ktime_get_mono_fast_ns()) {
5099 dev_warn(adev->dev, "failed to suspend display audio\n");
5101 /* TODO: abort the succeeding gpu reset? */
5106 pm_runtime_disable(&(p->dev));
5112 static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5114 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5116 #if defined(CONFIG_DEBUG_FS)
5117 if (!amdgpu_sriov_vf(adev))
5118 cancel_work(&adev->reset_work);
5122 cancel_work(&adev->kfd.reset_work);
5124 if (amdgpu_sriov_vf(adev))
5125 cancel_work(&adev->virt.flr_work);
5127 if (con && adev->ras_enabled)
5128 cancel_work(&con->recovery_work);
5133 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5135 * @adev: amdgpu_device pointer
5136 * @job: which job trigger hang
5138 * Attempt to reset the GPU if it has hung (all asics).
5139 * Attempt to do soft-reset or full-reset and reinitialize Asic
5140 * Returns 0 for success or an error on failure.
5143 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5144 struct amdgpu_job *job,
5145 struct amdgpu_reset_context *reset_context)
5147 struct list_head device_list, *device_list_handle = NULL;
5148 bool job_signaled = false;
5149 struct amdgpu_hive_info *hive = NULL;
5150 struct amdgpu_device *tmp_adev = NULL;
5152 bool need_emergency_restart = false;
5153 bool audio_suspended = false;
5154 bool gpu_reset_for_dev_remove = false;
5156 gpu_reset_for_dev_remove =
5157 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5158 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5161 * Special case: RAS triggered and full reset isn't supported
5163 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5166 * Flush RAM to disk so that after reboot
5167 * the user can read log and see why the system rebooted.
5169 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
5170 DRM_WARN("Emergency reboot.");
5173 emergency_restart();
5176 dev_info(adev->dev, "GPU %s begin!\n",
5177 need_emergency_restart ? "jobs stop":"reset");
5179 if (!amdgpu_sriov_vf(adev))
5180 hive = amdgpu_get_xgmi_hive(adev);
5182 mutex_lock(&hive->hive_lock);
5184 reset_context->job = job;
5185 reset_context->hive = hive;
5187 * Build list of devices to reset.
5188 * In case we are in XGMI hive mode, resort the device list
5189 * to put adev in the 1st position.
5191 INIT_LIST_HEAD(&device_list);
5192 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5193 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5194 list_add_tail(&tmp_adev->reset_list, &device_list);
5195 if (gpu_reset_for_dev_remove && adev->shutdown)
5196 tmp_adev->shutdown = true;
5198 if (!list_is_first(&adev->reset_list, &device_list))
5199 list_rotate_to_front(&adev->reset_list, &device_list);
5200 device_list_handle = &device_list;
5202 list_add_tail(&adev->reset_list, &device_list);
5203 device_list_handle = &device_list;
5206 /* We need to lock reset domain only once both for XGMI and single device */
5207 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5209 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5211 /* block all schedulers and reset given job's ring */
5212 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5214 amdgpu_device_set_mp1_state(tmp_adev);
5217 * Try to put the audio codec into suspend state
5218 * before gpu reset started.
5220 * Due to the power domain of the graphics device
5221 * is shared with AZ power domain. Without this,
5222 * we may change the audio hardware from behind
5223 * the audio driver's back. That will trigger
5224 * some audio codec errors.
5226 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5227 audio_suspended = true;
5229 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5231 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5233 if (!amdgpu_sriov_vf(tmp_adev))
5234 amdgpu_amdkfd_pre_reset(tmp_adev);
5237 * Mark these ASICs to be reseted as untracked first
5238 * And add them back after reset completed
5240 amdgpu_unregister_gpu_instance(tmp_adev);
5242 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5244 /* disable ras on ALL IPs */
5245 if (!need_emergency_restart &&
5246 amdgpu_device_ip_need_full_reset(tmp_adev))
5247 amdgpu_ras_suspend(tmp_adev);
5249 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5250 struct amdgpu_ring *ring = tmp_adev->rings[i];
5252 if (!ring || !ring->sched.thread)
5255 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5257 if (need_emergency_restart)
5258 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5260 atomic_inc(&tmp_adev->gpu_reset_counter);
5263 if (need_emergency_restart)
5264 goto skip_sched_resume;
5267 * Must check guilty signal here since after this point all old
5268 * HW fences are force signaled.
5270 * job->base holds a reference to parent fence
5272 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5273 job_signaled = true;
5274 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5278 retry: /* Rest of adevs pre asic reset from XGMI hive. */
5279 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5280 if (gpu_reset_for_dev_remove) {
5281 /* Workaroud for ASICs need to disable SMC first */
5282 amdgpu_device_smu_fini_early(tmp_adev);
5284 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5285 /*TODO Should we stop ?*/
5287 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5288 r, adev_to_drm(tmp_adev)->unique);
5289 tmp_adev->asic_reset_res = r;
5293 * Drop all pending non scheduler resets. Scheduler resets
5294 * were already dropped during drm_sched_stop
5296 amdgpu_device_stop_pending_resets(tmp_adev);
5299 /* Actual ASIC resets if needed.*/
5300 /* Host driver will handle XGMI hive reset for SRIOV */
5301 if (amdgpu_sriov_vf(adev)) {
5302 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5304 adev->asic_reset_res = r;
5306 /* Aldebaran supports ras in SRIOV, so need resume ras during reset */
5307 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
5308 amdgpu_ras_resume(adev);
5310 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5311 if (r && r == -EAGAIN)
5314 if (!r && gpu_reset_for_dev_remove)
5320 /* Post ASIC reset for all devs .*/
5321 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5323 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5324 struct amdgpu_ring *ring = tmp_adev->rings[i];
5326 if (!ring || !ring->sched.thread)
5329 drm_sched_start(&ring->sched, true);
5332 if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))
5333 amdgpu_mes_self_test(tmp_adev);
5335 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) {
5336 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5339 if (tmp_adev->asic_reset_res)
5340 r = tmp_adev->asic_reset_res;
5342 tmp_adev->asic_reset_res = 0;
5345 /* bad news, how to tell it to userspace ? */
5346 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5347 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5349 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5350 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5351 DRM_WARN("smart shift update failed\n");
5356 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5357 /* unlock kfd: SRIOV would do it separately */
5358 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5359 amdgpu_amdkfd_post_reset(tmp_adev);
5361 /* kfd_post_reset will do nothing if kfd device is not initialized,
5362 * need to bring up kfd here if it's not be initialized before
5364 if (!adev->kfd.init_complete)
5365 amdgpu_amdkfd_device_init(adev);
5367 if (audio_suspended)
5368 amdgpu_device_resume_display_audio(tmp_adev);
5370 amdgpu_device_unset_mp1_state(tmp_adev);
5372 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5376 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5378 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5381 mutex_unlock(&hive->hive_lock);
5382 amdgpu_put_xgmi_hive(hive);
5386 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5388 atomic_set(&adev->reset_domain->reset_res, r);
5393 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5395 * @adev: amdgpu_device pointer
5397 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5398 * and lanes) of the slot the device is in. Handles APUs and
5399 * virtualized environments where PCIE config space may not be available.
5401 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5403 struct pci_dev *pdev;
5404 enum pci_bus_speed speed_cap, platform_speed_cap;
5405 enum pcie_link_width platform_link_width;
5407 if (amdgpu_pcie_gen_cap)
5408 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5410 if (amdgpu_pcie_lane_cap)
5411 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5413 /* covers APUs as well */
5414 if (pci_is_root_bus(adev->pdev->bus)) {
5415 if (adev->pm.pcie_gen_mask == 0)
5416 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5417 if (adev->pm.pcie_mlw_mask == 0)
5418 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5422 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5425 pcie_bandwidth_available(adev->pdev, NULL,
5426 &platform_speed_cap, &platform_link_width);
5428 if (adev->pm.pcie_gen_mask == 0) {
5431 speed_cap = pcie_get_speed_cap(pdev);
5432 if (speed_cap == PCI_SPEED_UNKNOWN) {
5433 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5434 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5435 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5437 if (speed_cap == PCIE_SPEED_32_0GT)
5438 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5439 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5440 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5441 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5442 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5443 else if (speed_cap == PCIE_SPEED_16_0GT)
5444 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5445 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5446 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5447 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5448 else if (speed_cap == PCIE_SPEED_8_0GT)
5449 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5450 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5451 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5452 else if (speed_cap == PCIE_SPEED_5_0GT)
5453 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5454 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5456 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5459 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5460 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5461 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5463 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5464 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5465 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5466 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5467 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5468 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5469 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5470 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5471 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5472 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5473 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5474 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5475 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5476 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5477 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5478 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5479 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5480 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5482 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5486 if (adev->pm.pcie_mlw_mask == 0) {
5487 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5488 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5490 switch (platform_link_width) {
5492 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5493 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5494 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5495 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5496 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5497 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5498 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5501 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5502 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5503 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5504 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5505 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5506 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5509 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5510 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5511 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5512 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5513 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5516 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5517 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5518 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5519 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5522 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5523 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5524 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5527 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5528 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5531 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5541 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5543 * @adev: amdgpu_device pointer
5544 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5546 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5547 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5550 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5551 struct amdgpu_device *peer_adev)
5553 #ifdef CONFIG_HSA_AMD_P2P
5554 uint64_t address_mask = peer_adev->dev->dma_mask ?
5555 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5556 resource_size_t aper_limit =
5557 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5559 !adev->gmc.xgmi.connected_to_cpu &&
5560 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
5562 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
5563 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
5564 !(adev->gmc.aper_base & address_mask ||
5565 aper_limit & address_mask));
5571 int amdgpu_device_baco_enter(struct drm_device *dev)
5573 struct amdgpu_device *adev = drm_to_adev(dev);
5574 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5576 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
5579 if (ras && adev->ras_enabled &&
5580 adev->nbio.funcs->enable_doorbell_interrupt)
5581 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5583 return amdgpu_dpm_baco_enter(adev);
5586 int amdgpu_device_baco_exit(struct drm_device *dev)
5588 struct amdgpu_device *adev = drm_to_adev(dev);
5589 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5592 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
5595 ret = amdgpu_dpm_baco_exit(adev);
5599 if (ras && adev->ras_enabled &&
5600 adev->nbio.funcs->enable_doorbell_interrupt)
5601 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
5603 if (amdgpu_passthrough(adev) &&
5604 adev->nbio.funcs->clear_doorbell_interrupt)
5605 adev->nbio.funcs->clear_doorbell_interrupt(adev);
5611 * amdgpu_pci_error_detected - Called when a PCI error is detected.
5612 * @pdev: PCI device struct
5613 * @state: PCI channel state
5615 * Description: Called when a PCI error is detected.
5617 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
5619 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5621 struct drm_device *dev = pci_get_drvdata(pdev);
5622 struct amdgpu_device *adev = drm_to_adev(dev);
5625 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
5627 if (adev->gmc.xgmi.num_physical_nodes > 1) {
5628 DRM_WARN("No support for XGMI hive yet...");
5629 return PCI_ERS_RESULT_DISCONNECT;
5632 adev->pci_channel_state = state;
5635 case pci_channel_io_normal:
5636 return PCI_ERS_RESULT_CAN_RECOVER;
5637 /* Fatal error, prepare for slot reset */
5638 case pci_channel_io_frozen:
5640 * Locking adev->reset_domain->sem will prevent any external access
5641 * to GPU during PCI error recovery
5643 amdgpu_device_lock_reset_domain(adev->reset_domain);
5644 amdgpu_device_set_mp1_state(adev);
5647 * Block any work scheduling as we do for regular GPU reset
5648 * for the duration of the recovery
5650 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5651 struct amdgpu_ring *ring = adev->rings[i];
5653 if (!ring || !ring->sched.thread)
5656 drm_sched_stop(&ring->sched, NULL);
5658 atomic_inc(&adev->gpu_reset_counter);
5659 return PCI_ERS_RESULT_NEED_RESET;
5660 case pci_channel_io_perm_failure:
5661 /* Permanent error, prepare for device removal */
5662 return PCI_ERS_RESULT_DISCONNECT;
5665 return PCI_ERS_RESULT_NEED_RESET;
5669 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
5670 * @pdev: pointer to PCI device
5672 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
5675 DRM_INFO("PCI error: mmio enabled callback!!\n");
5677 /* TODO - dump whatever for debugging purposes */
5679 /* This called only if amdgpu_pci_error_detected returns
5680 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
5681 * works, no need to reset slot.
5684 return PCI_ERS_RESULT_RECOVERED;
5688 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5689 * @pdev: PCI device struct
5691 * Description: This routine is called by the pci error recovery
5692 * code after the PCI slot has been reset, just before we
5693 * should resume normal operations.
5695 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5697 struct drm_device *dev = pci_get_drvdata(pdev);
5698 struct amdgpu_device *adev = drm_to_adev(dev);
5700 struct amdgpu_reset_context reset_context;
5702 struct list_head device_list;
5704 DRM_INFO("PCI error: slot reset callback!!\n");
5706 memset(&reset_context, 0, sizeof(reset_context));
5708 INIT_LIST_HEAD(&device_list);
5709 list_add_tail(&adev->reset_list, &device_list);
5711 /* wait for asic to come out of reset */
5714 /* Restore PCI confspace */
5715 amdgpu_device_load_pci_state(pdev);
5717 /* confirm ASIC came out of reset */
5718 for (i = 0; i < adev->usec_timeout; i++) {
5719 memsize = amdgpu_asic_get_config_memsize(adev);
5721 if (memsize != 0xffffffff)
5725 if (memsize == 0xffffffff) {
5730 reset_context.method = AMD_RESET_METHOD_NONE;
5731 reset_context.reset_req_dev = adev;
5732 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
5733 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
5735 adev->no_hw_access = true;
5736 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
5737 adev->no_hw_access = false;
5741 r = amdgpu_do_asic_reset(&device_list, &reset_context);
5745 if (amdgpu_device_cache_pci_state(adev->pdev))
5746 pci_restore_state(adev->pdev);
5748 DRM_INFO("PCIe error recovery succeeded\n");
5750 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5751 amdgpu_device_unset_mp1_state(adev);
5752 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5755 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5759 * amdgpu_pci_resume() - resume normal ops after PCI reset
5760 * @pdev: pointer to PCI device
5762 * Called when the error recovery driver tells us that its
5763 * OK to resume normal operation.
5765 void amdgpu_pci_resume(struct pci_dev *pdev)
5767 struct drm_device *dev = pci_get_drvdata(pdev);
5768 struct amdgpu_device *adev = drm_to_adev(dev);
5772 DRM_INFO("PCI error: resume callback!!\n");
5774 /* Only continue execution for the case of pci_channel_io_frozen */
5775 if (adev->pci_channel_state != pci_channel_io_frozen)
5778 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5779 struct amdgpu_ring *ring = adev->rings[i];
5781 if (!ring || !ring->sched.thread)
5784 drm_sched_start(&ring->sched, true);
5787 amdgpu_device_unset_mp1_state(adev);
5788 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5791 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5793 struct drm_device *dev = pci_get_drvdata(pdev);
5794 struct amdgpu_device *adev = drm_to_adev(dev);
5797 r = pci_save_state(pdev);
5799 kfree(adev->pci_state);
5801 adev->pci_state = pci_store_saved_state(pdev);
5803 if (!adev->pci_state) {
5804 DRM_ERROR("Failed to store PCI saved state");
5808 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5815 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5817 struct drm_device *dev = pci_get_drvdata(pdev);
5818 struct amdgpu_device *adev = drm_to_adev(dev);
5821 if (!adev->pci_state)
5824 r = pci_load_saved_state(pdev, adev->pci_state);
5827 pci_restore_state(pdev);
5829 DRM_WARN("Failed to load PCI state, err:%d\n", r);
5836 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
5837 struct amdgpu_ring *ring)
5839 #ifdef CONFIG_X86_64
5840 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5843 if (adev->gmc.xgmi.connected_to_cpu)
5846 if (ring && ring->funcs->emit_hdp_flush)
5847 amdgpu_ring_emit_hdp_flush(ring);
5849 amdgpu_asic_flush_hdp(adev, ring);
5852 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
5853 struct amdgpu_ring *ring)
5855 #ifdef CONFIG_X86_64
5856 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5859 if (adev->gmc.xgmi.connected_to_cpu)
5862 amdgpu_asic_invalidate_hdp(adev, ring);
5865 int amdgpu_in_reset(struct amdgpu_device *adev)
5867 return atomic_read(&adev->reset_domain->in_gpu_reset);
5871 * amdgpu_device_halt() - bring hardware to some kind of halt state
5873 * @adev: amdgpu_device pointer
5875 * Bring hardware to some kind of halt state so that no one can touch it
5876 * any more. It will help to maintain error context when error occurred.
5877 * Compare to a simple hang, the system will keep stable at least for SSH
5878 * access. Then it should be trivial to inspect the hardware state and
5879 * see what's going on. Implemented as following:
5881 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
5882 * clears all CPU mappings to device, disallows remappings through page faults
5883 * 2. amdgpu_irq_disable_all() disables all interrupts
5884 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
5885 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
5886 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
5887 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
5888 * flush any in flight DMA operations
5890 void amdgpu_device_halt(struct amdgpu_device *adev)
5892 struct pci_dev *pdev = adev->pdev;
5893 struct drm_device *ddev = adev_to_drm(adev);
5895 drm_dev_unplug(ddev);
5897 amdgpu_irq_disable_all(adev);
5899 amdgpu_fence_driver_hw_fini(adev);
5901 adev->no_hw_access = true;
5903 amdgpu_device_unmap_mmio(adev);
5905 pci_disable_device(pdev);
5906 pci_wait_for_pending_transaction(pdev);
5909 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
5912 unsigned long flags, address, data;
5915 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5916 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5918 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5919 WREG32(address, reg * 4);
5920 (void)RREG32(address);
5922 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5926 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
5929 unsigned long flags, address, data;
5931 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5932 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5934 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5935 WREG32(address, reg * 4);
5936 (void)RREG32(address);
5939 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5943 * amdgpu_device_switch_gang - switch to a new gang
5944 * @adev: amdgpu_device pointer
5945 * @gang: the gang to switch to
5947 * Try to switch to a new gang.
5948 * Returns: NULL if we switched to the new gang or a reference to the current
5951 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
5952 struct dma_fence *gang)
5954 struct dma_fence *old = NULL;
5959 old = dma_fence_get_rcu_safe(&adev->gang_submit);
5965 if (!dma_fence_is_signaled(old))
5968 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
5975 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
5977 switch (adev->asic_type) {
5978 #ifdef CONFIG_DRM_AMDGPU_SI
5982 /* chips with no display hardware */
5984 #ifdef CONFIG_DRM_AMDGPU_SI
5990 #ifdef CONFIG_DRM_AMDGPU_CIK
5999 case CHIP_POLARIS10:
6000 case CHIP_POLARIS11:
6001 case CHIP_POLARIS12:
6005 /* chips with display hardware */
6009 if (!adev->ip_versions[DCE_HWIP][0] ||
6010 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))