2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/amdgpu_drm.h>
37 #include <linux/vgaarb.h>
38 #include <linux/vga_switcheroo.h>
39 #include <linux/efi.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_i2c.h"
44 #include "amdgpu_atombios.h"
45 #include "amdgpu_atomfirmware.h"
47 #ifdef CONFIG_DRM_AMDGPU_SI
50 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #include "bif/bif_4_1_d.h"
57 #include <linux/pci.h>
58 #include <linux/firmware.h>
59 #include "amdgpu_vf_error.h"
61 #include "amdgpu_amdkfd.h"
62 #include "amdgpu_pm.h"
64 #include "amdgpu_xgmi.h"
65 #include "amdgpu_ras.h"
66 #include "amdgpu_pmu.h"
67 #include "amdgpu_fru_eeprom.h"
69 #include <linux/suspend.h>
70 #include <drm/task_barrier.h>
71 #include <linux/pm_runtime.h>
73 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
74 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
75 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
76 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
77 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
78 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
79 MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
80 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
81 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
82 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
83 MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
85 #define AMDGPU_RESUME_MS 2000
87 const char *amdgpu_asic_name[] = {
125 * DOC: pcie_replay_count
127 * The amdgpu driver provides a sysfs API for reporting the total number
128 * of PCIe replays (NAKs)
129 * The file pcie_replay_count is used for this and returns the total
130 * number of replays as a sum of the NAKs generated and NAKs received
133 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
134 struct device_attribute *attr, char *buf)
136 struct drm_device *ddev = dev_get_drvdata(dev);
137 struct amdgpu_device *adev = drm_to_adev(ddev);
138 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
140 return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
143 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
144 amdgpu_device_get_pcie_replay_count, NULL);
146 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
151 * The amdgpu driver provides a sysfs API for reporting the product name
153 * The file serial_number is used for this and returns the product name
154 * as returned from the FRU.
155 * NOTE: This is only available for certain server cards
158 static ssize_t amdgpu_device_get_product_name(struct device *dev,
159 struct device_attribute *attr, char *buf)
161 struct drm_device *ddev = dev_get_drvdata(dev);
162 struct amdgpu_device *adev = drm_to_adev(ddev);
164 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name);
167 static DEVICE_ATTR(product_name, S_IRUGO,
168 amdgpu_device_get_product_name, NULL);
171 * DOC: product_number
173 * The amdgpu driver provides a sysfs API for reporting the part number
175 * The file serial_number is used for this and returns the part number
176 * as returned from the FRU.
177 * NOTE: This is only available for certain server cards
180 static ssize_t amdgpu_device_get_product_number(struct device *dev,
181 struct device_attribute *attr, char *buf)
183 struct drm_device *ddev = dev_get_drvdata(dev);
184 struct amdgpu_device *adev = drm_to_adev(ddev);
186 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number);
189 static DEVICE_ATTR(product_number, S_IRUGO,
190 amdgpu_device_get_product_number, NULL);
195 * The amdgpu driver provides a sysfs API for reporting the serial number
197 * The file serial_number is used for this and returns the serial number
198 * as returned from the FRU.
199 * NOTE: This is only available for certain server cards
202 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
203 struct device_attribute *attr, char *buf)
205 struct drm_device *ddev = dev_get_drvdata(dev);
206 struct amdgpu_device *adev = drm_to_adev(ddev);
208 return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial);
211 static DEVICE_ATTR(serial_number, S_IRUGO,
212 amdgpu_device_get_serial_number, NULL);
215 * amdgpu_device_supports_atpx - Is the device a dGPU with HG/PX power control
217 * @dev: drm_device pointer
219 * Returns true if the device is a dGPU with HG/PX power control,
220 * otherwise return false.
222 bool amdgpu_device_supports_atpx(struct drm_device *dev)
224 struct amdgpu_device *adev = drm_to_adev(dev);
226 if (adev->flags & AMD_IS_PX)
232 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
234 * @dev: drm_device pointer
236 * Returns true if the device is a dGPU with HG/PX power control,
237 * otherwise return false.
239 bool amdgpu_device_supports_boco(struct drm_device *dev)
241 struct amdgpu_device *adev = drm_to_adev(dev);
249 * amdgpu_device_supports_baco - Does the device support BACO
251 * @dev: drm_device pointer
253 * Returns true if the device supporte BACO,
254 * otherwise return false.
256 bool amdgpu_device_supports_baco(struct drm_device *dev)
258 struct amdgpu_device *adev = drm_to_adev(dev);
260 return amdgpu_asic_supports_baco(adev);
264 * VRAM access helper functions
268 * amdgpu_device_vram_access - read/write a buffer in vram
270 * @adev: amdgpu_device pointer
271 * @pos: offset of the buffer in vram
272 * @buf: virtual address of the buffer in system memory
273 * @size: read/write size, sizeof(@buf) must > @size
274 * @write: true - write to vram, otherwise - read from vram
276 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
277 uint32_t *buf, size_t size, bool write)
285 last = min(pos + size, adev->gmc.visible_vram_size);
287 void __iomem *addr = adev->mman.aper_base_kaddr + pos;
288 size_t count = last - pos;
291 memcpy_toio(addr, buf, count);
293 amdgpu_asic_flush_hdp(adev, NULL);
295 amdgpu_asic_invalidate_hdp(adev, NULL);
297 memcpy_fromio(buf, addr, count);
309 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
310 for (last = pos + size; pos < last; pos += 4) {
311 uint32_t tmp = pos >> 31;
313 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
315 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
319 WREG32_NO_KIQ(mmMM_DATA, *buf++);
321 *buf++ = RREG32_NO_KIQ(mmMM_DATA);
323 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
327 * register access helper functions.
330 * amdgpu_device_rreg - read a memory mapped IO or indirect register
332 * @adev: amdgpu_device pointer
333 * @reg: dword aligned register offset
334 * @acc_flags: access flags which require special behavior
336 * Returns the 32 bit value from the offset specified.
338 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
339 uint32_t reg, uint32_t acc_flags)
343 if (adev->in_pci_err_recovery)
346 if ((reg * 4) < adev->rmmio_size) {
347 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
348 amdgpu_sriov_runtime(adev) &&
349 down_read_trylock(&adev->reset_sem)) {
350 ret = amdgpu_kiq_rreg(adev, reg);
351 up_read(&adev->reset_sem);
353 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
356 ret = adev->pcie_rreg(adev, reg * 4);
359 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
365 * MMIO register read with bytes helper functions
366 * @offset:bytes offset from MMIO start
371 * amdgpu_mm_rreg8 - read a memory mapped IO register
373 * @adev: amdgpu_device pointer
374 * @offset: byte aligned register offset
376 * Returns the 8 bit value from the offset specified.
378 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
380 if (adev->in_pci_err_recovery)
383 if (offset < adev->rmmio_size)
384 return (readb(adev->rmmio + offset));
389 * MMIO register write with bytes helper functions
390 * @offset:bytes offset from MMIO start
391 * @value: the value want to be written to the register
395 * amdgpu_mm_wreg8 - read a memory mapped IO register
397 * @adev: amdgpu_device pointer
398 * @offset: byte aligned register offset
399 * @value: 8 bit value to write
401 * Writes the value specified to the offset specified.
403 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
405 if (adev->in_pci_err_recovery)
408 if (offset < adev->rmmio_size)
409 writeb(value, adev->rmmio + offset);
415 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
417 * @adev: amdgpu_device pointer
418 * @reg: dword aligned register offset
419 * @v: 32 bit value to write to the register
420 * @acc_flags: access flags which require special behavior
422 * Writes the value specified to the offset specified.
424 void amdgpu_device_wreg(struct amdgpu_device *adev,
425 uint32_t reg, uint32_t v,
428 if (adev->in_pci_err_recovery)
431 if ((reg * 4) < adev->rmmio_size) {
432 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
433 amdgpu_sriov_runtime(adev) &&
434 down_read_trylock(&adev->reset_sem)) {
435 amdgpu_kiq_wreg(adev, reg, v);
436 up_read(&adev->reset_sem);
438 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
441 adev->pcie_wreg(adev, reg * 4, v);
444 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
448 * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range
450 * this function is invoked only the debugfs register access
452 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
453 uint32_t reg, uint32_t v)
455 if (adev->in_pci_err_recovery)
458 if (amdgpu_sriov_fullaccess(adev) &&
459 adev->gfx.rlc.funcs &&
460 adev->gfx.rlc.funcs->is_rlcg_access_range) {
461 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
462 return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);
464 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
469 * amdgpu_io_rreg - read an IO register
471 * @adev: amdgpu_device pointer
472 * @reg: dword aligned register offset
474 * Returns the 32 bit value from the offset specified.
476 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
478 if (adev->in_pci_err_recovery)
481 if ((reg * 4) < adev->rio_mem_size)
482 return ioread32(adev->rio_mem + (reg * 4));
484 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
485 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
490 * amdgpu_io_wreg - write to an IO register
492 * @adev: amdgpu_device pointer
493 * @reg: dword aligned register offset
494 * @v: 32 bit value to write to the register
496 * Writes the value specified to the offset specified.
498 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
500 if (adev->in_pci_err_recovery)
503 if ((reg * 4) < adev->rio_mem_size)
504 iowrite32(v, adev->rio_mem + (reg * 4));
506 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
507 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
512 * amdgpu_mm_rdoorbell - read a doorbell dword
514 * @adev: amdgpu_device pointer
515 * @index: doorbell index
517 * Returns the value in the doorbell aperture at the
518 * requested doorbell index (CIK).
520 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
522 if (adev->in_pci_err_recovery)
525 if (index < adev->doorbell.num_doorbells) {
526 return readl(adev->doorbell.ptr + index);
528 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
534 * amdgpu_mm_wdoorbell - write a doorbell dword
536 * @adev: amdgpu_device pointer
537 * @index: doorbell index
540 * Writes @v to the doorbell aperture at the
541 * requested doorbell index (CIK).
543 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
545 if (adev->in_pci_err_recovery)
548 if (index < adev->doorbell.num_doorbells) {
549 writel(v, adev->doorbell.ptr + index);
551 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
556 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
558 * @adev: amdgpu_device pointer
559 * @index: doorbell index
561 * Returns the value in the doorbell aperture at the
562 * requested doorbell index (VEGA10+).
564 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
566 if (adev->in_pci_err_recovery)
569 if (index < adev->doorbell.num_doorbells) {
570 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
572 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
578 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
580 * @adev: amdgpu_device pointer
581 * @index: doorbell index
584 * Writes @v to the doorbell aperture at the
585 * requested doorbell index (VEGA10+).
587 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
589 if (adev->in_pci_err_recovery)
592 if (index < adev->doorbell.num_doorbells) {
593 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
595 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
600 * amdgpu_device_indirect_rreg - read an indirect register
602 * @adev: amdgpu_device pointer
603 * @pcie_index: mmio register offset
604 * @pcie_data: mmio register offset
605 * @reg_addr: indirect register address to read from
607 * Returns the value of indirect register @reg_addr
609 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
610 u32 pcie_index, u32 pcie_data,
615 void __iomem *pcie_index_offset;
616 void __iomem *pcie_data_offset;
618 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
619 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
620 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
622 writel(reg_addr, pcie_index_offset);
623 readl(pcie_index_offset);
624 r = readl(pcie_data_offset);
625 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
631 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
633 * @adev: amdgpu_device pointer
634 * @pcie_index: mmio register offset
635 * @pcie_data: mmio register offset
636 * @reg_addr: indirect register address to read from
638 * Returns the value of indirect register @reg_addr
640 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
641 u32 pcie_index, u32 pcie_data,
646 void __iomem *pcie_index_offset;
647 void __iomem *pcie_data_offset;
649 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
650 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
651 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
653 /* read low 32 bits */
654 writel(reg_addr, pcie_index_offset);
655 readl(pcie_index_offset);
656 r = readl(pcie_data_offset);
657 /* read high 32 bits */
658 writel(reg_addr + 4, pcie_index_offset);
659 readl(pcie_index_offset);
660 r |= ((u64)readl(pcie_data_offset) << 32);
661 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
667 * amdgpu_device_indirect_wreg - write an indirect register address
669 * @adev: amdgpu_device pointer
670 * @pcie_index: mmio register offset
671 * @pcie_data: mmio register offset
672 * @reg_addr: indirect register offset
673 * @reg_data: indirect register data
676 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
677 u32 pcie_index, u32 pcie_data,
678 u32 reg_addr, u32 reg_data)
681 void __iomem *pcie_index_offset;
682 void __iomem *pcie_data_offset;
684 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
685 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
686 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
688 writel(reg_addr, pcie_index_offset);
689 readl(pcie_index_offset);
690 writel(reg_data, pcie_data_offset);
691 readl(pcie_data_offset);
692 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
696 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
698 * @adev: amdgpu_device pointer
699 * @pcie_index: mmio register offset
700 * @pcie_data: mmio register offset
701 * @reg_addr: indirect register offset
702 * @reg_data: indirect register data
705 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
706 u32 pcie_index, u32 pcie_data,
707 u32 reg_addr, u64 reg_data)
710 void __iomem *pcie_index_offset;
711 void __iomem *pcie_data_offset;
713 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
714 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
715 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
717 /* write low 32 bits */
718 writel(reg_addr, pcie_index_offset);
719 readl(pcie_index_offset);
720 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
721 readl(pcie_data_offset);
722 /* write high 32 bits */
723 writel(reg_addr + 4, pcie_index_offset);
724 readl(pcie_index_offset);
725 writel((u32)(reg_data >> 32), pcie_data_offset);
726 readl(pcie_data_offset);
727 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
731 * amdgpu_invalid_rreg - dummy reg read function
733 * @adev: amdgpu_device pointer
734 * @reg: offset of register
736 * Dummy register read function. Used for register blocks
737 * that certain asics don't have (all asics).
738 * Returns the value in the register.
740 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
742 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
748 * amdgpu_invalid_wreg - dummy reg write function
750 * @adev: amdgpu_device pointer
751 * @reg: offset of register
752 * @v: value to write to the register
754 * Dummy register read function. Used for register blocks
755 * that certain asics don't have (all asics).
757 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
759 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
765 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
767 * @adev: amdgpu_device pointer
768 * @reg: offset of register
770 * Dummy register read function. Used for register blocks
771 * that certain asics don't have (all asics).
772 * Returns the value in the register.
774 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
776 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
782 * amdgpu_invalid_wreg64 - dummy reg write function
784 * @adev: amdgpu_device pointer
785 * @reg: offset of register
786 * @v: value to write to the register
788 * Dummy register read function. Used for register blocks
789 * that certain asics don't have (all asics).
791 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
793 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
799 * amdgpu_block_invalid_rreg - dummy reg read function
801 * @adev: amdgpu_device pointer
802 * @block: offset of instance
803 * @reg: offset of register
805 * Dummy register read function. Used for register blocks
806 * that certain asics don't have (all asics).
807 * Returns the value in the register.
809 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
810 uint32_t block, uint32_t reg)
812 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
819 * amdgpu_block_invalid_wreg - dummy reg write function
821 * @adev: amdgpu_device pointer
822 * @block: offset of instance
823 * @reg: offset of register
824 * @v: value to write to the register
826 * Dummy register read function. Used for register blocks
827 * that certain asics don't have (all asics).
829 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
831 uint32_t reg, uint32_t v)
833 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
839 * amdgpu_device_asic_init - Wrapper for atom asic_init
841 * @adev: amdgpu_device pointer
843 * Does any asic specific work and then calls atom asic init.
845 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
847 amdgpu_asic_pre_asic_init(adev);
849 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
853 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
855 * @adev: amdgpu_device pointer
857 * Allocates a scratch page of VRAM for use by various things in the
860 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
862 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
863 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
864 &adev->vram_scratch.robj,
865 &adev->vram_scratch.gpu_addr,
866 (void **)&adev->vram_scratch.ptr);
870 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
872 * @adev: amdgpu_device pointer
874 * Frees the VRAM scratch page.
876 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
878 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
882 * amdgpu_device_program_register_sequence - program an array of registers.
884 * @adev: amdgpu_device pointer
885 * @registers: pointer to the register array
886 * @array_size: size of the register array
888 * Programs an array or registers with and and or masks.
889 * This is a helper for setting golden registers.
891 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
892 const u32 *registers,
893 const u32 array_size)
895 u32 tmp, reg, and_mask, or_mask;
901 for (i = 0; i < array_size; i +=3) {
902 reg = registers[i + 0];
903 and_mask = registers[i + 1];
904 or_mask = registers[i + 2];
906 if (and_mask == 0xffffffff) {
911 if (adev->family >= AMDGPU_FAMILY_AI)
912 tmp |= (or_mask & and_mask);
921 * amdgpu_device_pci_config_reset - reset the GPU
923 * @adev: amdgpu_device pointer
925 * Resets the GPU using the pci config reset sequence.
926 * Only applicable to asics prior to vega10.
928 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
930 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
934 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
936 * @adev: amdgpu_device pointer
938 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
940 int amdgpu_device_pci_reset(struct amdgpu_device *adev)
942 return pci_reset_function(adev->pdev);
946 * GPU doorbell aperture helpers function.
949 * amdgpu_device_doorbell_init - Init doorbell driver information.
951 * @adev: amdgpu_device pointer
953 * Init doorbell driver information (CIK)
954 * Returns 0 on success, error on failure.
956 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
959 /* No doorbell on SI hardware generation */
960 if (adev->asic_type < CHIP_BONAIRE) {
961 adev->doorbell.base = 0;
962 adev->doorbell.size = 0;
963 adev->doorbell.num_doorbells = 0;
964 adev->doorbell.ptr = NULL;
968 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
971 amdgpu_asic_init_doorbell_index(adev);
973 /* doorbell bar mapping */
974 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
975 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
977 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
978 adev->doorbell_index.max_assignment+1);
979 if (adev->doorbell.num_doorbells == 0)
982 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
983 * paging queue doorbell use the second page. The
984 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
985 * doorbells are in the first page. So with paging queue enabled,
986 * the max num_doorbells should + 1 page (0x400 in dword)
988 if (adev->asic_type >= CHIP_VEGA10)
989 adev->doorbell.num_doorbells += 0x400;
991 adev->doorbell.ptr = ioremap(adev->doorbell.base,
992 adev->doorbell.num_doorbells *
994 if (adev->doorbell.ptr == NULL)
1001 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
1003 * @adev: amdgpu_device pointer
1005 * Tear down doorbell driver information (CIK)
1007 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
1009 iounmap(adev->doorbell.ptr);
1010 adev->doorbell.ptr = NULL;
1016 * amdgpu_device_wb_*()
1017 * Writeback is the method by which the GPU updates special pages in memory
1018 * with the status of certain GPU events (fences, ring pointers,etc.).
1022 * amdgpu_device_wb_fini - Disable Writeback and free memory
1024 * @adev: amdgpu_device pointer
1026 * Disables Writeback and frees the Writeback memory (all asics).
1027 * Used at driver shutdown.
1029 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1031 if (adev->wb.wb_obj) {
1032 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1034 (void **)&adev->wb.wb);
1035 adev->wb.wb_obj = NULL;
1040 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
1042 * @adev: amdgpu_device pointer
1044 * Initializes writeback and allocates writeback memory (all asics).
1045 * Used at driver startup.
1046 * Returns 0 on success or an -error on failure.
1048 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1052 if (adev->wb.wb_obj == NULL) {
1053 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1054 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1055 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1056 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1057 (void **)&adev->wb.wb);
1059 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1063 adev->wb.num_wb = AMDGPU_MAX_WB;
1064 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1066 /* clear wb memory */
1067 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1074 * amdgpu_device_wb_get - Allocate a wb entry
1076 * @adev: amdgpu_device pointer
1079 * Allocate a wb slot for use by the driver (all asics).
1080 * Returns 0 on success or -EINVAL on failure.
1082 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1084 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1086 if (offset < adev->wb.num_wb) {
1087 __set_bit(offset, adev->wb.used);
1088 *wb = offset << 3; /* convert to dw offset */
1096 * amdgpu_device_wb_free - Free a wb entry
1098 * @adev: amdgpu_device pointer
1101 * Free a wb slot allocated for use by the driver (all asics)
1103 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1106 if (wb < adev->wb.num_wb)
1107 __clear_bit(wb, adev->wb.used);
1111 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1113 * @adev: amdgpu_device pointer
1115 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1116 * to fail, but if any of the BARs is not accessible after the size we abort
1117 * driver loading by returning -ENODEV.
1119 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1121 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1122 struct pci_bus *root;
1123 struct resource *res;
1129 if (amdgpu_sriov_vf(adev))
1132 /* skip if the bios has already enabled large BAR */
1133 if (adev->gmc.real_vram_size &&
1134 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1137 /* Check if the root BUS has 64bit memory resources */
1138 root = adev->pdev->bus;
1139 while (root->parent)
1140 root = root->parent;
1142 pci_bus_for_each_resource(root, res, i) {
1143 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1144 res->start > 0x100000000ull)
1148 /* Trying to resize is pointless without a root hub window above 4GB */
1152 /* Limit the BAR size to what is available */
1153 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1156 /* Disable memory decoding while we change the BAR addresses and size */
1157 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1158 pci_write_config_word(adev->pdev, PCI_COMMAND,
1159 cmd & ~PCI_COMMAND_MEMORY);
1161 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1162 amdgpu_device_doorbell_fini(adev);
1163 if (adev->asic_type >= CHIP_BONAIRE)
1164 pci_release_resource(adev->pdev, 2);
1166 pci_release_resource(adev->pdev, 0);
1168 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1170 DRM_INFO("Not enough PCI address space for a large BAR.");
1171 else if (r && r != -ENOTSUPP)
1172 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1174 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1176 /* When the doorbell or fb BAR isn't available we have no chance of
1179 r = amdgpu_device_doorbell_init(adev);
1180 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1183 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1189 * GPU helpers function.
1192 * amdgpu_device_need_post - check if the hw need post or not
1194 * @adev: amdgpu_device pointer
1196 * Check if the asic has been initialized (all asics) at driver startup
1197 * or post is needed if hw reset is performed.
1198 * Returns true if need or false if not.
1200 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1204 if (amdgpu_sriov_vf(adev))
1207 if (amdgpu_passthrough(adev)) {
1208 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1209 * some old smc fw still need driver do vPost otherwise gpu hang, while
1210 * those smc fw version above 22.15 doesn't have this flaw, so we force
1211 * vpost executed for smc version below 22.15
1213 if (adev->asic_type == CHIP_FIJI) {
1216 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1217 /* force vPost if error occured */
1221 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1222 if (fw_ver < 0x00160e00)
1227 /* Don't post if we need to reset whole hive on init */
1228 if (adev->gmc.xgmi.pending_reset)
1231 if (adev->has_hw_reset) {
1232 adev->has_hw_reset = false;
1236 /* bios scratch used on CIK+ */
1237 if (adev->asic_type >= CHIP_BONAIRE)
1238 return amdgpu_atombios_scratch_need_asic_init(adev);
1240 /* check MEM_SIZE for older asics */
1241 reg = amdgpu_asic_get_config_memsize(adev);
1243 if ((reg != 0) && (reg != 0xffffffff))
1249 /* if we get transitioned to only one device, take VGA back */
1251 * amdgpu_device_vga_set_decode - enable/disable vga decode
1253 * @cookie: amdgpu_device pointer
1254 * @state: enable/disable vga decode
1256 * Enable/disable vga decode (all asics).
1257 * Returns VGA resource flags.
1259 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
1261 struct amdgpu_device *adev = cookie;
1262 amdgpu_asic_set_vga_state(adev, state);
1264 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1265 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1267 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1271 * amdgpu_device_check_block_size - validate the vm block size
1273 * @adev: amdgpu_device pointer
1275 * Validates the vm block size specified via module parameter.
1276 * The vm block size defines number of bits in page table versus page directory,
1277 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1278 * page table and the remaining bits are in the page directory.
1280 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1282 /* defines number of bits in page table versus page directory,
1283 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1284 * page table and the remaining bits are in the page directory */
1285 if (amdgpu_vm_block_size == -1)
1288 if (amdgpu_vm_block_size < 9) {
1289 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1290 amdgpu_vm_block_size);
1291 amdgpu_vm_block_size = -1;
1296 * amdgpu_device_check_vm_size - validate the vm size
1298 * @adev: amdgpu_device pointer
1300 * Validates the vm size in GB specified via module parameter.
1301 * The VM size is the size of the GPU virtual memory space in GB.
1303 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1305 /* no need to check the default value */
1306 if (amdgpu_vm_size == -1)
1309 if (amdgpu_vm_size < 1) {
1310 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1312 amdgpu_vm_size = -1;
1316 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1319 bool is_os_64 = (sizeof(void *) == 8);
1320 uint64_t total_memory;
1321 uint64_t dram_size_seven_GB = 0x1B8000000;
1322 uint64_t dram_size_three_GB = 0xB8000000;
1324 if (amdgpu_smu_memory_pool_size == 0)
1328 DRM_WARN("Not 64-bit OS, feature not supported\n");
1332 total_memory = (uint64_t)si.totalram * si.mem_unit;
1334 if ((amdgpu_smu_memory_pool_size == 1) ||
1335 (amdgpu_smu_memory_pool_size == 2)) {
1336 if (total_memory < dram_size_three_GB)
1338 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1339 (amdgpu_smu_memory_pool_size == 8)) {
1340 if (total_memory < dram_size_seven_GB)
1343 DRM_WARN("Smu memory pool size not supported\n");
1346 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1351 DRM_WARN("No enough system memory\n");
1353 adev->pm.smu_prv_buffer_size = 0;
1357 * amdgpu_device_check_arguments - validate module params
1359 * @adev: amdgpu_device pointer
1361 * Validates certain module parameters and updates
1362 * the associated values used by the driver (all asics).
1364 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1366 if (amdgpu_sched_jobs < 4) {
1367 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1369 amdgpu_sched_jobs = 4;
1370 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1371 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1373 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1376 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1377 /* gart size must be greater or equal to 32M */
1378 dev_warn(adev->dev, "gart size (%d) too small\n",
1380 amdgpu_gart_size = -1;
1383 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1384 /* gtt size must be greater or equal to 32M */
1385 dev_warn(adev->dev, "gtt size (%d) too small\n",
1387 amdgpu_gtt_size = -1;
1390 /* valid range is between 4 and 9 inclusive */
1391 if (amdgpu_vm_fragment_size != -1 &&
1392 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1393 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1394 amdgpu_vm_fragment_size = -1;
1397 if (amdgpu_sched_hw_submission < 2) {
1398 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1399 amdgpu_sched_hw_submission);
1400 amdgpu_sched_hw_submission = 2;
1401 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1402 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1403 amdgpu_sched_hw_submission);
1404 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1407 amdgpu_device_check_smu_prv_buffer_size(adev);
1409 amdgpu_device_check_vm_size(adev);
1411 amdgpu_device_check_block_size(adev);
1413 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1415 amdgpu_gmc_tmz_set(adev);
1417 amdgpu_gmc_noretry_set(adev);
1423 * amdgpu_switcheroo_set_state - set switcheroo state
1425 * @pdev: pci dev pointer
1426 * @state: vga_switcheroo state
1428 * Callback for the switcheroo driver. Suspends or resumes the
1429 * the asics before or after it is powered up using ACPI methods.
1431 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1432 enum vga_switcheroo_state state)
1434 struct drm_device *dev = pci_get_drvdata(pdev);
1437 if (amdgpu_device_supports_atpx(dev) && state == VGA_SWITCHEROO_OFF)
1440 if (state == VGA_SWITCHEROO_ON) {
1441 pr_info("switched on\n");
1442 /* don't suspend or resume card normally */
1443 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1445 pci_set_power_state(pdev, PCI_D0);
1446 amdgpu_device_load_pci_state(pdev);
1447 r = pci_enable_device(pdev);
1449 DRM_WARN("pci_enable_device failed (%d)\n", r);
1450 amdgpu_device_resume(dev, true);
1452 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1454 pr_info("switched off\n");
1455 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1456 amdgpu_device_suspend(dev, true);
1457 amdgpu_device_cache_pci_state(pdev);
1458 /* Shut down the device */
1459 pci_disable_device(pdev);
1460 pci_set_power_state(pdev, PCI_D3cold);
1461 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1466 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1468 * @pdev: pci dev pointer
1470 * Callback for the switcheroo driver. Check of the switcheroo
1471 * state can be changed.
1472 * Returns true if the state can be changed, false if not.
1474 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1476 struct drm_device *dev = pci_get_drvdata(pdev);
1479 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1480 * locking inversion with the driver load path. And the access here is
1481 * completely racy anyway. So don't bother with locking for now.
1483 return atomic_read(&dev->open_count) == 0;
1486 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1487 .set_gpu_state = amdgpu_switcheroo_set_state,
1489 .can_switch = amdgpu_switcheroo_can_switch,
1493 * amdgpu_device_ip_set_clockgating_state - set the CG state
1495 * @dev: amdgpu_device pointer
1496 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1497 * @state: clockgating state (gate or ungate)
1499 * Sets the requested clockgating state for all instances of
1500 * the hardware IP specified.
1501 * Returns the error code from the last instance.
1503 int amdgpu_device_ip_set_clockgating_state(void *dev,
1504 enum amd_ip_block_type block_type,
1505 enum amd_clockgating_state state)
1507 struct amdgpu_device *adev = dev;
1510 for (i = 0; i < adev->num_ip_blocks; i++) {
1511 if (!adev->ip_blocks[i].status.valid)
1513 if (adev->ip_blocks[i].version->type != block_type)
1515 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1517 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1518 (void *)adev, state);
1520 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1521 adev->ip_blocks[i].version->funcs->name, r);
1527 * amdgpu_device_ip_set_powergating_state - set the PG state
1529 * @dev: amdgpu_device pointer
1530 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1531 * @state: powergating state (gate or ungate)
1533 * Sets the requested powergating state for all instances of
1534 * the hardware IP specified.
1535 * Returns the error code from the last instance.
1537 int amdgpu_device_ip_set_powergating_state(void *dev,
1538 enum amd_ip_block_type block_type,
1539 enum amd_powergating_state state)
1541 struct amdgpu_device *adev = dev;
1544 for (i = 0; i < adev->num_ip_blocks; i++) {
1545 if (!adev->ip_blocks[i].status.valid)
1547 if (adev->ip_blocks[i].version->type != block_type)
1549 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1551 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1552 (void *)adev, state);
1554 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1555 adev->ip_blocks[i].version->funcs->name, r);
1561 * amdgpu_device_ip_get_clockgating_state - get the CG state
1563 * @adev: amdgpu_device pointer
1564 * @flags: clockgating feature flags
1566 * Walks the list of IPs on the device and updates the clockgating
1567 * flags for each IP.
1568 * Updates @flags with the feature flags for each hardware IP where
1569 * clockgating is enabled.
1571 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1576 for (i = 0; i < adev->num_ip_blocks; i++) {
1577 if (!adev->ip_blocks[i].status.valid)
1579 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1580 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1585 * amdgpu_device_ip_wait_for_idle - wait for idle
1587 * @adev: amdgpu_device pointer
1588 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1590 * Waits for the request hardware IP to be idle.
1591 * Returns 0 for success or a negative error code on failure.
1593 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1594 enum amd_ip_block_type block_type)
1598 for (i = 0; i < adev->num_ip_blocks; i++) {
1599 if (!adev->ip_blocks[i].status.valid)
1601 if (adev->ip_blocks[i].version->type == block_type) {
1602 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1613 * amdgpu_device_ip_is_idle - is the hardware IP idle
1615 * @adev: amdgpu_device pointer
1616 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1618 * Check if the hardware IP is idle or not.
1619 * Returns true if it the IP is idle, false if not.
1621 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1622 enum amd_ip_block_type block_type)
1626 for (i = 0; i < adev->num_ip_blocks; i++) {
1627 if (!adev->ip_blocks[i].status.valid)
1629 if (adev->ip_blocks[i].version->type == block_type)
1630 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1637 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1639 * @adev: amdgpu_device pointer
1640 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1642 * Returns a pointer to the hardware IP block structure
1643 * if it exists for the asic, otherwise NULL.
1645 struct amdgpu_ip_block *
1646 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1647 enum amd_ip_block_type type)
1651 for (i = 0; i < adev->num_ip_blocks; i++)
1652 if (adev->ip_blocks[i].version->type == type)
1653 return &adev->ip_blocks[i];
1659 * amdgpu_device_ip_block_version_cmp
1661 * @adev: amdgpu_device pointer
1662 * @type: enum amd_ip_block_type
1663 * @major: major version
1664 * @minor: minor version
1666 * return 0 if equal or greater
1667 * return 1 if smaller or the ip_block doesn't exist
1669 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1670 enum amd_ip_block_type type,
1671 u32 major, u32 minor)
1673 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1675 if (ip_block && ((ip_block->version->major > major) ||
1676 ((ip_block->version->major == major) &&
1677 (ip_block->version->minor >= minor))))
1684 * amdgpu_device_ip_block_add
1686 * @adev: amdgpu_device pointer
1687 * @ip_block_version: pointer to the IP to add
1689 * Adds the IP block driver information to the collection of IPs
1692 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1693 const struct amdgpu_ip_block_version *ip_block_version)
1695 if (!ip_block_version)
1698 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1699 ip_block_version->funcs->name);
1701 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1707 * amdgpu_device_enable_virtual_display - enable virtual display feature
1709 * @adev: amdgpu_device pointer
1711 * Enabled the virtual display feature if the user has enabled it via
1712 * the module parameter virtual_display. This feature provides a virtual
1713 * display hardware on headless boards or in virtualized environments.
1714 * This function parses and validates the configuration string specified by
1715 * the user and configues the virtual display configuration (number of
1716 * virtual connectors, crtcs, etc.) specified.
1718 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1720 adev->enable_virtual_display = false;
1722 if (amdgpu_virtual_display) {
1723 const char *pci_address_name = pci_name(adev->pdev);
1724 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1726 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1727 pciaddstr_tmp = pciaddstr;
1728 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1729 pciaddname = strsep(&pciaddname_tmp, ",");
1730 if (!strcmp("all", pciaddname)
1731 || !strcmp(pci_address_name, pciaddname)) {
1735 adev->enable_virtual_display = true;
1738 res = kstrtol(pciaddname_tmp, 10,
1746 adev->mode_info.num_crtc = num_crtc;
1748 adev->mode_info.num_crtc = 1;
1754 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1755 amdgpu_virtual_display, pci_address_name,
1756 adev->enable_virtual_display, adev->mode_info.num_crtc);
1763 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1765 * @adev: amdgpu_device pointer
1767 * Parses the asic configuration parameters specified in the gpu info
1768 * firmware and makes them availale to the driver for use in configuring
1770 * Returns 0 on success, -EINVAL on failure.
1772 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1774 const char *chip_name;
1777 const struct gpu_info_firmware_header_v1_0 *hdr;
1779 adev->firmware.gpu_info_fw = NULL;
1781 if (adev->mman.discovery_bin) {
1782 amdgpu_discovery_get_gfx_info(adev);
1785 * FIXME: The bounding box is still needed by Navi12, so
1786 * temporarily read it from gpu_info firmware. Should be droped
1787 * when DAL no longer needs it.
1789 if (adev->asic_type != CHIP_NAVI12)
1793 switch (adev->asic_type) {
1794 #ifdef CONFIG_DRM_AMDGPU_SI
1801 #ifdef CONFIG_DRM_AMDGPU_CIK
1811 case CHIP_POLARIS10:
1812 case CHIP_POLARIS11:
1813 case CHIP_POLARIS12:
1818 case CHIP_ALDEBARAN:
1819 case CHIP_SIENNA_CICHLID:
1820 case CHIP_NAVY_FLOUNDER:
1821 case CHIP_DIMGREY_CAVEFISH:
1825 chip_name = "vega10";
1828 chip_name = "vega12";
1831 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1832 chip_name = "raven2";
1833 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1834 chip_name = "picasso";
1836 chip_name = "raven";
1839 chip_name = "arcturus";
1842 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1843 chip_name = "renoir";
1845 chip_name = "green_sardine";
1848 chip_name = "navi10";
1851 chip_name = "navi14";
1854 chip_name = "navi12";
1857 chip_name = "vangogh";
1861 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1862 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1865 "Failed to load gpu_info firmware \"%s\"\n",
1869 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1872 "Failed to validate gpu_info firmware \"%s\"\n",
1877 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1878 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1880 switch (hdr->version_major) {
1883 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1884 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1885 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1888 * Should be droped when DAL no longer needs it.
1890 if (adev->asic_type == CHIP_NAVI12)
1891 goto parse_soc_bounding_box;
1893 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1894 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1895 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1896 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1897 adev->gfx.config.max_texture_channel_caches =
1898 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1899 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1900 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1901 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1902 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1903 adev->gfx.config.double_offchip_lds_buf =
1904 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1905 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1906 adev->gfx.cu_info.max_waves_per_simd =
1907 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1908 adev->gfx.cu_info.max_scratch_slots_per_cu =
1909 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1910 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1911 if (hdr->version_minor >= 1) {
1912 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1913 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1914 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1915 adev->gfx.config.num_sc_per_sh =
1916 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1917 adev->gfx.config.num_packer_per_sc =
1918 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1921 parse_soc_bounding_box:
1923 * soc bounding box info is not integrated in disocovery table,
1924 * we always need to parse it from gpu info firmware if needed.
1926 if (hdr->version_minor == 2) {
1927 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1928 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1929 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1930 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1936 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1945 * amdgpu_device_ip_early_init - run early init for hardware IPs
1947 * @adev: amdgpu_device pointer
1949 * Early initialization pass for hardware IPs. The hardware IPs that make
1950 * up each asic are discovered each IP's early_init callback is run. This
1951 * is the first stage in initializing the asic.
1952 * Returns 0 on success, negative error code on failure.
1954 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1958 amdgpu_device_enable_virtual_display(adev);
1960 if (amdgpu_sriov_vf(adev)) {
1961 r = amdgpu_virt_request_full_gpu(adev, true);
1966 switch (adev->asic_type) {
1967 #ifdef CONFIG_DRM_AMDGPU_SI
1973 adev->family = AMDGPU_FAMILY_SI;
1974 r = si_set_ip_blocks(adev);
1979 #ifdef CONFIG_DRM_AMDGPU_CIK
1985 if (adev->flags & AMD_IS_APU)
1986 adev->family = AMDGPU_FAMILY_KV;
1988 adev->family = AMDGPU_FAMILY_CI;
1990 r = cik_set_ip_blocks(adev);
1998 case CHIP_POLARIS10:
1999 case CHIP_POLARIS11:
2000 case CHIP_POLARIS12:
2004 if (adev->flags & AMD_IS_APU)
2005 adev->family = AMDGPU_FAMILY_CZ;
2007 adev->family = AMDGPU_FAMILY_VI;
2009 r = vi_set_ip_blocks(adev);
2019 case CHIP_ALDEBARAN:
2020 if (adev->flags & AMD_IS_APU)
2021 adev->family = AMDGPU_FAMILY_RV;
2023 adev->family = AMDGPU_FAMILY_AI;
2025 r = soc15_set_ip_blocks(adev);
2032 case CHIP_SIENNA_CICHLID:
2033 case CHIP_NAVY_FLOUNDER:
2034 case CHIP_DIMGREY_CAVEFISH:
2036 if (adev->asic_type == CHIP_VANGOGH)
2037 adev->family = AMDGPU_FAMILY_VGH;
2039 adev->family = AMDGPU_FAMILY_NV;
2041 r = nv_set_ip_blocks(adev);
2046 /* FIXME: not supported yet */
2050 amdgpu_amdkfd_device_probe(adev);
2052 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2053 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2054 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2055 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2056 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2058 for (i = 0; i < adev->num_ip_blocks; i++) {
2059 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2060 DRM_ERROR("disabled ip block: %d <%s>\n",
2061 i, adev->ip_blocks[i].version->funcs->name);
2062 adev->ip_blocks[i].status.valid = false;
2064 if (adev->ip_blocks[i].version->funcs->early_init) {
2065 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2067 adev->ip_blocks[i].status.valid = false;
2069 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2070 adev->ip_blocks[i].version->funcs->name, r);
2073 adev->ip_blocks[i].status.valid = true;
2076 adev->ip_blocks[i].status.valid = true;
2079 /* get the vbios after the asic_funcs are set up */
2080 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2081 r = amdgpu_device_parse_gpu_info_fw(adev);
2086 if (!amdgpu_get_bios(adev))
2089 r = amdgpu_atombios_init(adev);
2091 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2092 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2098 adev->cg_flags &= amdgpu_cg_mask;
2099 adev->pg_flags &= amdgpu_pg_mask;
2104 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2108 for (i = 0; i < adev->num_ip_blocks; i++) {
2109 if (!adev->ip_blocks[i].status.sw)
2111 if (adev->ip_blocks[i].status.hw)
2113 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2114 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2115 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2116 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2118 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2119 adev->ip_blocks[i].version->funcs->name, r);
2122 adev->ip_blocks[i].status.hw = true;
2129 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2133 for (i = 0; i < adev->num_ip_blocks; i++) {
2134 if (!adev->ip_blocks[i].status.sw)
2136 if (adev->ip_blocks[i].status.hw)
2138 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2140 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2141 adev->ip_blocks[i].version->funcs->name, r);
2144 adev->ip_blocks[i].status.hw = true;
2150 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2154 uint32_t smu_version;
2156 if (adev->asic_type >= CHIP_VEGA10) {
2157 for (i = 0; i < adev->num_ip_blocks; i++) {
2158 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2161 if (!adev->ip_blocks[i].status.sw)
2164 /* no need to do the fw loading again if already done*/
2165 if (adev->ip_blocks[i].status.hw == true)
2168 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2169 r = adev->ip_blocks[i].version->funcs->resume(adev);
2171 DRM_ERROR("resume of IP block <%s> failed %d\n",
2172 adev->ip_blocks[i].version->funcs->name, r);
2176 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2178 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2179 adev->ip_blocks[i].version->funcs->name, r);
2184 adev->ip_blocks[i].status.hw = true;
2189 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2190 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2196 * amdgpu_device_ip_init - run init for hardware IPs
2198 * @adev: amdgpu_device pointer
2200 * Main initialization pass for hardware IPs. The list of all the hardware
2201 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2202 * are run. sw_init initializes the software state associated with each IP
2203 * and hw_init initializes the hardware associated with each IP.
2204 * Returns 0 on success, negative error code on failure.
2206 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2210 r = amdgpu_ras_init(adev);
2214 for (i = 0; i < adev->num_ip_blocks; i++) {
2215 if (!adev->ip_blocks[i].status.valid)
2217 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2219 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2220 adev->ip_blocks[i].version->funcs->name, r);
2223 adev->ip_blocks[i].status.sw = true;
2225 /* need to do gmc hw init early so we can allocate gpu mem */
2226 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2227 r = amdgpu_device_vram_scratch_init(adev);
2229 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
2232 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2234 DRM_ERROR("hw_init %d failed %d\n", i, r);
2237 r = amdgpu_device_wb_init(adev);
2239 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2242 adev->ip_blocks[i].status.hw = true;
2244 /* right after GMC hw init, we create CSA */
2245 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
2246 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2247 AMDGPU_GEM_DOMAIN_VRAM,
2250 DRM_ERROR("allocate CSA failed %d\n", r);
2257 if (amdgpu_sriov_vf(adev))
2258 amdgpu_virt_init_data_exchange(adev);
2260 r = amdgpu_ib_pool_init(adev);
2262 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2263 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2267 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2271 r = amdgpu_device_ip_hw_init_phase1(adev);
2275 r = amdgpu_device_fw_loading(adev);
2279 r = amdgpu_device_ip_hw_init_phase2(adev);
2284 * retired pages will be loaded from eeprom and reserved here,
2285 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2286 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2287 * for I2C communication which only true at this point.
2289 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2290 * failure from bad gpu situation and stop amdgpu init process
2291 * accordingly. For other failed cases, it will still release all
2292 * the resource and print error message, rather than returning one
2293 * negative value to upper level.
2295 * Note: theoretically, this should be called before all vram allocations
2296 * to protect retired page from abusing
2298 r = amdgpu_ras_recovery_init(adev);
2302 if (adev->gmc.xgmi.num_physical_nodes > 1)
2303 amdgpu_xgmi_add_device(adev);
2305 /* Don't init kfd if whole hive need to be reset during init */
2306 if (!adev->gmc.xgmi.pending_reset)
2307 amdgpu_amdkfd_device_init(adev);
2309 amdgpu_fru_get_product_info(adev);
2312 if (amdgpu_sriov_vf(adev))
2313 amdgpu_virt_release_full_gpu(adev, true);
2319 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2321 * @adev: amdgpu_device pointer
2323 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2324 * this function before a GPU reset. If the value is retained after a
2325 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2327 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2329 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2333 * amdgpu_device_check_vram_lost - check if vram is valid
2335 * @adev: amdgpu_device pointer
2337 * Checks the reset magic value written to the gart pointer in VRAM.
2338 * The driver calls this after a GPU reset to see if the contents of
2339 * VRAM is lost or now.
2340 * returns true if vram is lost, false if not.
2342 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2344 if (memcmp(adev->gart.ptr, adev->reset_magic,
2345 AMDGPU_RESET_MAGIC_NUM))
2348 if (!amdgpu_in_reset(adev))
2352 * For all ASICs with baco/mode1 reset, the VRAM is
2353 * always assumed to be lost.
2355 switch (amdgpu_asic_reset_method(adev)) {
2356 case AMD_RESET_METHOD_BACO:
2357 case AMD_RESET_METHOD_MODE1:
2365 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2367 * @adev: amdgpu_device pointer
2368 * @state: clockgating state (gate or ungate)
2370 * The list of all the hardware IPs that make up the asic is walked and the
2371 * set_clockgating_state callbacks are run.
2372 * Late initialization pass enabling clockgating for hardware IPs.
2373 * Fini or suspend, pass disabling clockgating for hardware IPs.
2374 * Returns 0 on success, negative error code on failure.
2377 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2378 enum amd_clockgating_state state)
2382 if (amdgpu_emu_mode == 1)
2385 for (j = 0; j < adev->num_ip_blocks; j++) {
2386 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2387 if (!adev->ip_blocks[i].status.late_initialized)
2389 /* skip CG for VCE/UVD, it's handled specially */
2390 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2391 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2392 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2393 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2394 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2395 /* enable clockgating to save power */
2396 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2399 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2400 adev->ip_blocks[i].version->funcs->name, r);
2409 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
2413 if (amdgpu_emu_mode == 1)
2416 for (j = 0; j < adev->num_ip_blocks; j++) {
2417 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2418 if (!adev->ip_blocks[i].status.late_initialized)
2420 /* skip CG for VCE/UVD, it's handled specially */
2421 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2422 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2423 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2424 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2425 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2426 /* enable powergating to save power */
2427 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2430 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2431 adev->ip_blocks[i].version->funcs->name, r);
2439 static int amdgpu_device_enable_mgpu_fan_boost(void)
2441 struct amdgpu_gpu_instance *gpu_ins;
2442 struct amdgpu_device *adev;
2445 mutex_lock(&mgpu_info.mutex);
2448 * MGPU fan boost feature should be enabled
2449 * only when there are two or more dGPUs in
2452 if (mgpu_info.num_dgpu < 2)
2455 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2456 gpu_ins = &(mgpu_info.gpu_ins[i]);
2457 adev = gpu_ins->adev;
2458 if (!(adev->flags & AMD_IS_APU) &&
2459 !gpu_ins->mgpu_fan_enabled) {
2460 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2464 gpu_ins->mgpu_fan_enabled = 1;
2469 mutex_unlock(&mgpu_info.mutex);
2475 * amdgpu_device_ip_late_init - run late init for hardware IPs
2477 * @adev: amdgpu_device pointer
2479 * Late initialization pass for hardware IPs. The list of all the hardware
2480 * IPs that make up the asic is walked and the late_init callbacks are run.
2481 * late_init covers any special initialization that an IP requires
2482 * after all of the have been initialized or something that needs to happen
2483 * late in the init process.
2484 * Returns 0 on success, negative error code on failure.
2486 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2488 struct amdgpu_gpu_instance *gpu_instance;
2491 for (i = 0; i < adev->num_ip_blocks; i++) {
2492 if (!adev->ip_blocks[i].status.hw)
2494 if (adev->ip_blocks[i].version->funcs->late_init) {
2495 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2497 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2498 adev->ip_blocks[i].version->funcs->name, r);
2502 adev->ip_blocks[i].status.late_initialized = true;
2505 amdgpu_ras_set_error_query_ready(adev, true);
2507 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2508 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2510 amdgpu_device_fill_reset_magic(adev);
2512 r = amdgpu_device_enable_mgpu_fan_boost();
2514 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2517 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2518 mutex_lock(&mgpu_info.mutex);
2521 * Reset device p-state to low as this was booted with high.
2523 * This should be performed only after all devices from the same
2524 * hive get initialized.
2526 * However, it's unknown how many device in the hive in advance.
2527 * As this is counted one by one during devices initializations.
2529 * So, we wait for all XGMI interlinked devices initialized.
2530 * This may bring some delays as those devices may come from
2531 * different hives. But that should be OK.
2533 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2534 for (i = 0; i < mgpu_info.num_gpu; i++) {
2535 gpu_instance = &(mgpu_info.gpu_ins[i]);
2536 if (gpu_instance->adev->flags & AMD_IS_APU)
2539 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2540 AMDGPU_XGMI_PSTATE_MIN);
2542 DRM_ERROR("pstate setting failed (%d).\n", r);
2548 mutex_unlock(&mgpu_info.mutex);
2555 * amdgpu_device_ip_fini - run fini for hardware IPs
2557 * @adev: amdgpu_device pointer
2559 * Main teardown pass for hardware IPs. The list of all the hardware
2560 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2561 * are run. hw_fini tears down the hardware associated with each IP
2562 * and sw_fini tears down any software state associated with each IP.
2563 * Returns 0 on success, negative error code on failure.
2565 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2569 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2570 amdgpu_virt_release_ras_err_handler_data(adev);
2572 amdgpu_ras_pre_fini(adev);
2574 if (adev->gmc.xgmi.num_physical_nodes > 1)
2575 amdgpu_xgmi_remove_device(adev);
2577 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2578 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2580 amdgpu_amdkfd_device_fini(adev);
2582 /* need to disable SMC first */
2583 for (i = 0; i < adev->num_ip_blocks; i++) {
2584 if (!adev->ip_blocks[i].status.hw)
2586 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2587 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2588 /* XXX handle errors */
2590 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2591 adev->ip_blocks[i].version->funcs->name, r);
2593 adev->ip_blocks[i].status.hw = false;
2598 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2599 if (!adev->ip_blocks[i].status.hw)
2602 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2603 /* XXX handle errors */
2605 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2606 adev->ip_blocks[i].version->funcs->name, r);
2609 adev->ip_blocks[i].status.hw = false;
2613 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2614 if (!adev->ip_blocks[i].status.sw)
2617 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2618 amdgpu_ucode_free_bo(adev);
2619 amdgpu_free_static_csa(&adev->virt.csa_obj);
2620 amdgpu_device_wb_fini(adev);
2621 amdgpu_device_vram_scratch_fini(adev);
2622 amdgpu_ib_pool_fini(adev);
2625 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2626 /* XXX handle errors */
2628 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2629 adev->ip_blocks[i].version->funcs->name, r);
2631 adev->ip_blocks[i].status.sw = false;
2632 adev->ip_blocks[i].status.valid = false;
2635 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2636 if (!adev->ip_blocks[i].status.late_initialized)
2638 if (adev->ip_blocks[i].version->funcs->late_fini)
2639 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2640 adev->ip_blocks[i].status.late_initialized = false;
2643 amdgpu_ras_fini(adev);
2645 if (amdgpu_sriov_vf(adev))
2646 if (amdgpu_virt_release_full_gpu(adev, false))
2647 DRM_ERROR("failed to release exclusive mode on fini\n");
2653 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2655 * @work: work_struct.
2657 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2659 struct amdgpu_device *adev =
2660 container_of(work, struct amdgpu_device, delayed_init_work.work);
2663 r = amdgpu_ib_ring_tests(adev);
2665 DRM_ERROR("ib ring test failed (%d).\n", r);
2668 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2670 struct amdgpu_device *adev =
2671 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2673 mutex_lock(&adev->gfx.gfx_off_mutex);
2674 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2675 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2676 adev->gfx.gfx_off_state = true;
2678 mutex_unlock(&adev->gfx.gfx_off_mutex);
2682 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2684 * @adev: amdgpu_device pointer
2686 * Main suspend function for hardware IPs. The list of all the hardware
2687 * IPs that make up the asic is walked, clockgating is disabled and the
2688 * suspend callbacks are run. suspend puts the hardware and software state
2689 * in each IP into a state suitable for suspend.
2690 * Returns 0 on success, negative error code on failure.
2692 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2696 if (adev->in_poweroff_reboot_com ||
2697 !amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) {
2698 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2699 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2702 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2703 if (!adev->ip_blocks[i].status.valid)
2706 /* displays are handled separately */
2707 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2710 /* XXX handle errors */
2711 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2712 /* XXX handle errors */
2714 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2715 adev->ip_blocks[i].version->funcs->name, r);
2719 adev->ip_blocks[i].status.hw = false;
2726 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2728 * @adev: amdgpu_device pointer
2730 * Main suspend function for hardware IPs. The list of all the hardware
2731 * IPs that make up the asic is walked, clockgating is disabled and the
2732 * suspend callbacks are run. suspend puts the hardware and software state
2733 * in each IP into a state suitable for suspend.
2734 * Returns 0 on success, negative error code on failure.
2736 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2740 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2741 if (!adev->ip_blocks[i].status.valid)
2743 /* displays are handled in phase1 */
2744 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2746 /* PSP lost connection when err_event_athub occurs */
2747 if (amdgpu_ras_intr_triggered() &&
2748 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2749 adev->ip_blocks[i].status.hw = false;
2753 /* skip unnecessary suspend if we do not initialize them yet */
2754 if (adev->gmc.xgmi.pending_reset &&
2755 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2756 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
2757 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2758 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
2759 adev->ip_blocks[i].status.hw = false;
2762 /* XXX handle errors */
2763 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2764 /* XXX handle errors */
2766 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2767 adev->ip_blocks[i].version->funcs->name, r);
2769 adev->ip_blocks[i].status.hw = false;
2770 /* handle putting the SMC in the appropriate state */
2771 if(!amdgpu_sriov_vf(adev)){
2772 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2773 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
2775 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2776 adev->mp1_state, r);
2781 adev->ip_blocks[i].status.hw = false;
2788 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2790 * @adev: amdgpu_device pointer
2792 * Main suspend function for hardware IPs. The list of all the hardware
2793 * IPs that make up the asic is walked, clockgating is disabled and the
2794 * suspend callbacks are run. suspend puts the hardware and software state
2795 * in each IP into a state suitable for suspend.
2796 * Returns 0 on success, negative error code on failure.
2798 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2802 if (amdgpu_sriov_vf(adev)) {
2803 amdgpu_virt_fini_data_exchange(adev);
2804 amdgpu_virt_request_full_gpu(adev, false);
2807 r = amdgpu_device_ip_suspend_phase1(adev);
2810 r = amdgpu_device_ip_suspend_phase2(adev);
2812 if (amdgpu_sriov_vf(adev))
2813 amdgpu_virt_release_full_gpu(adev, false);
2818 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2822 static enum amd_ip_block_type ip_order[] = {
2823 AMD_IP_BLOCK_TYPE_GMC,
2824 AMD_IP_BLOCK_TYPE_COMMON,
2825 AMD_IP_BLOCK_TYPE_PSP,
2826 AMD_IP_BLOCK_TYPE_IH,
2829 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2831 struct amdgpu_ip_block *block;
2833 block = &adev->ip_blocks[i];
2834 block->status.hw = false;
2836 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
2838 if (block->version->type != ip_order[j] ||
2839 !block->status.valid)
2842 r = block->version->funcs->hw_init(adev);
2843 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2846 block->status.hw = true;
2853 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2857 static enum amd_ip_block_type ip_order[] = {
2858 AMD_IP_BLOCK_TYPE_SMC,
2859 AMD_IP_BLOCK_TYPE_DCE,
2860 AMD_IP_BLOCK_TYPE_GFX,
2861 AMD_IP_BLOCK_TYPE_SDMA,
2862 AMD_IP_BLOCK_TYPE_UVD,
2863 AMD_IP_BLOCK_TYPE_VCE,
2864 AMD_IP_BLOCK_TYPE_VCN
2867 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2869 struct amdgpu_ip_block *block;
2871 for (j = 0; j < adev->num_ip_blocks; j++) {
2872 block = &adev->ip_blocks[j];
2874 if (block->version->type != ip_order[i] ||
2875 !block->status.valid ||
2879 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
2880 r = block->version->funcs->resume(adev);
2882 r = block->version->funcs->hw_init(adev);
2884 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2887 block->status.hw = true;
2895 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2897 * @adev: amdgpu_device pointer
2899 * First resume function for hardware IPs. The list of all the hardware
2900 * IPs that make up the asic is walked and the resume callbacks are run for
2901 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2902 * after a suspend and updates the software state as necessary. This
2903 * function is also used for restoring the GPU after a GPU reset.
2904 * Returns 0 on success, negative error code on failure.
2906 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2910 for (i = 0; i < adev->num_ip_blocks; i++) {
2911 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2913 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2914 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2915 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2917 r = adev->ip_blocks[i].version->funcs->resume(adev);
2919 DRM_ERROR("resume of IP block <%s> failed %d\n",
2920 adev->ip_blocks[i].version->funcs->name, r);
2923 adev->ip_blocks[i].status.hw = true;
2931 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2933 * @adev: amdgpu_device pointer
2935 * First resume function for hardware IPs. The list of all the hardware
2936 * IPs that make up the asic is walked and the resume callbacks are run for
2937 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2938 * functional state after a suspend and updates the software state as
2939 * necessary. This function is also used for restoring the GPU after a GPU
2941 * Returns 0 on success, negative error code on failure.
2943 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2947 for (i = 0; i < adev->num_ip_blocks; i++) {
2948 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2950 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2951 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2952 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2953 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2955 r = adev->ip_blocks[i].version->funcs->resume(adev);
2957 DRM_ERROR("resume of IP block <%s> failed %d\n",
2958 adev->ip_blocks[i].version->funcs->name, r);
2961 adev->ip_blocks[i].status.hw = true;
2968 * amdgpu_device_ip_resume - run resume for hardware IPs
2970 * @adev: amdgpu_device pointer
2972 * Main resume function for hardware IPs. The hardware IPs
2973 * are split into two resume functions because they are
2974 * are also used in in recovering from a GPU reset and some additional
2975 * steps need to be take between them. In this case (S3/S4) they are
2977 * Returns 0 on success, negative error code on failure.
2979 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2983 r = amdgpu_device_ip_resume_phase1(adev);
2987 r = amdgpu_device_fw_loading(adev);
2991 r = amdgpu_device_ip_resume_phase2(adev);
2997 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2999 * @adev: amdgpu_device pointer
3001 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3003 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3005 if (amdgpu_sriov_vf(adev)) {
3006 if (adev->is_atom_fw) {
3007 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
3008 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3010 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3011 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3014 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3015 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3020 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3022 * @asic_type: AMD asic type
3024 * Check if there is DC (new modesetting infrastructre) support for an asic.
3025 * returns true if DC has support, false if not.
3027 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3029 switch (asic_type) {
3030 #if defined(CONFIG_DRM_AMD_DC)
3031 #if defined(CONFIG_DRM_AMD_DC_SI)
3042 * We have systems in the wild with these ASICs that require
3043 * LVDS and VGA support which is not supported with DC.
3045 * Fallback to the non-DC driver here by default so as not to
3046 * cause regressions.
3048 return amdgpu_dc > 0;
3052 case CHIP_POLARIS10:
3053 case CHIP_POLARIS11:
3054 case CHIP_POLARIS12:
3061 #if defined(CONFIG_DRM_AMD_DC_DCN)
3067 case CHIP_SIENNA_CICHLID:
3068 case CHIP_NAVY_FLOUNDER:
3069 case CHIP_DIMGREY_CAVEFISH:
3072 return amdgpu_dc != 0;
3076 DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
3077 "but isn't supported by ASIC, ignoring\n");
3083 * amdgpu_device_has_dc_support - check if dc is supported
3085 * @adev: amdgpu_device pointer
3087 * Returns true for supported, false for not supported
3089 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3091 if (amdgpu_sriov_vf(adev) || adev->enable_virtual_display)
3094 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3098 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3100 struct amdgpu_device *adev =
3101 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3102 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3104 /* It's a bug to not have a hive within this function */
3109 * Use task barrier to synchronize all xgmi reset works across the
3110 * hive. task_barrier_enter and task_barrier_exit will block
3111 * until all the threads running the xgmi reset works reach
3112 * those points. task_barrier_full will do both blocks.
3114 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3116 task_barrier_enter(&hive->tb);
3117 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3119 if (adev->asic_reset_res)
3122 task_barrier_exit(&hive->tb);
3123 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3125 if (adev->asic_reset_res)
3128 if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
3129 adev->mmhub.funcs->reset_ras_error_count(adev);
3132 task_barrier_full(&hive->tb);
3133 adev->asic_reset_res = amdgpu_asic_reset(adev);
3137 if (adev->asic_reset_res)
3138 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3139 adev->asic_reset_res, adev_to_drm(adev)->unique);
3140 amdgpu_put_xgmi_hive(hive);
3143 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3145 char *input = amdgpu_lockup_timeout;
3146 char *timeout_setting = NULL;
3152 * By default timeout for non compute jobs is 10000.
3153 * And there is no timeout enforced on compute jobs.
3154 * In SR-IOV or passthrough mode, timeout for compute
3155 * jobs are 60000 by default.
3157 adev->gfx_timeout = msecs_to_jiffies(10000);
3158 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3159 if (amdgpu_sriov_vf(adev))
3160 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3161 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3162 else if (amdgpu_passthrough(adev))
3163 adev->compute_timeout = msecs_to_jiffies(60000);
3165 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
3167 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3168 while ((timeout_setting = strsep(&input, ",")) &&
3169 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3170 ret = kstrtol(timeout_setting, 0, &timeout);
3177 } else if (timeout < 0) {
3178 timeout = MAX_SCHEDULE_TIMEOUT;
3180 timeout = msecs_to_jiffies(timeout);
3185 adev->gfx_timeout = timeout;
3188 adev->compute_timeout = timeout;
3191 adev->sdma_timeout = timeout;
3194 adev->video_timeout = timeout;
3201 * There is only one value specified and
3202 * it should apply to all non-compute jobs.
3205 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3206 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3207 adev->compute_timeout = adev->gfx_timeout;
3214 static const struct attribute *amdgpu_dev_attributes[] = {
3215 &dev_attr_product_name.attr,
3216 &dev_attr_product_number.attr,
3217 &dev_attr_serial_number.attr,
3218 &dev_attr_pcie_replay_count.attr,
3224 * amdgpu_device_init - initialize the driver
3226 * @adev: amdgpu_device pointer
3227 * @flags: driver flags
3229 * Initializes the driver info and hw (all asics).
3230 * Returns 0 for success or an error on failure.
3231 * Called at driver startup.
3233 int amdgpu_device_init(struct amdgpu_device *adev,
3236 struct drm_device *ddev = adev_to_drm(adev);
3237 struct pci_dev *pdev = adev->pdev;
3242 adev->shutdown = false;
3243 adev->flags = flags;
3245 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3246 adev->asic_type = amdgpu_force_asic_type;
3248 adev->asic_type = flags & AMD_ASIC_MASK;
3250 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3251 if (amdgpu_emu_mode == 1)
3252 adev->usec_timeout *= 10;
3253 adev->gmc.gart_size = 512 * 1024 * 1024;
3254 adev->accel_working = false;
3255 adev->num_rings = 0;
3256 adev->mman.buffer_funcs = NULL;
3257 adev->mman.buffer_funcs_ring = NULL;
3258 adev->vm_manager.vm_pte_funcs = NULL;
3259 adev->vm_manager.vm_pte_num_scheds = 0;
3260 adev->gmc.gmc_funcs = NULL;
3261 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3262 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3264 adev->smc_rreg = &amdgpu_invalid_rreg;
3265 adev->smc_wreg = &amdgpu_invalid_wreg;
3266 adev->pcie_rreg = &amdgpu_invalid_rreg;
3267 adev->pcie_wreg = &amdgpu_invalid_wreg;
3268 adev->pciep_rreg = &amdgpu_invalid_rreg;
3269 adev->pciep_wreg = &amdgpu_invalid_wreg;
3270 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3271 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3272 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3273 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3274 adev->didt_rreg = &amdgpu_invalid_rreg;
3275 adev->didt_wreg = &amdgpu_invalid_wreg;
3276 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3277 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3278 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3279 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3281 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3282 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3283 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3285 /* mutex initialization are all done here so we
3286 * can recall function without having locking issues */
3287 atomic_set(&adev->irq.ih.lock, 0);
3288 mutex_init(&adev->firmware.mutex);
3289 mutex_init(&adev->pm.mutex);
3290 mutex_init(&adev->gfx.gpu_clock_mutex);
3291 mutex_init(&adev->srbm_mutex);
3292 mutex_init(&adev->gfx.pipe_reserve_mutex);
3293 mutex_init(&adev->gfx.gfx_off_mutex);
3294 mutex_init(&adev->grbm_idx_mutex);
3295 mutex_init(&adev->mn_lock);
3296 mutex_init(&adev->virt.vf_errors.lock);
3297 hash_init(adev->mn_hash);
3298 atomic_set(&adev->in_gpu_reset, 0);
3299 init_rwsem(&adev->reset_sem);
3300 mutex_init(&adev->psp.mutex);
3301 mutex_init(&adev->notifier_lock);
3303 r = amdgpu_device_check_arguments(adev);
3307 spin_lock_init(&adev->mmio_idx_lock);
3308 spin_lock_init(&adev->smc_idx_lock);
3309 spin_lock_init(&adev->pcie_idx_lock);
3310 spin_lock_init(&adev->uvd_ctx_idx_lock);
3311 spin_lock_init(&adev->didt_idx_lock);
3312 spin_lock_init(&adev->gc_cac_idx_lock);
3313 spin_lock_init(&adev->se_cac_idx_lock);
3314 spin_lock_init(&adev->audio_endpt_idx_lock);
3315 spin_lock_init(&adev->mm_stats.lock);
3317 INIT_LIST_HEAD(&adev->shadow_list);
3318 mutex_init(&adev->shadow_list_lock);
3320 INIT_LIST_HEAD(&adev->reset_list);
3322 INIT_DELAYED_WORK(&adev->delayed_init_work,
3323 amdgpu_device_delayed_init_work_handler);
3324 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3325 amdgpu_device_delay_enable_gfx_off);
3327 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3329 adev->gfx.gfx_off_req_count = 1;
3330 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3332 atomic_set(&adev->throttling_logging_enabled, 1);
3334 * If throttling continues, logging will be performed every minute
3335 * to avoid log flooding. "-1" is subtracted since the thermal
3336 * throttling interrupt comes every second. Thus, the total logging
3337 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3338 * for throttling interrupt) = 60 seconds.
3340 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3341 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3343 /* Registers mapping */
3344 /* TODO: block userspace mapping of io register */
3345 if (adev->asic_type >= CHIP_BONAIRE) {
3346 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3347 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3349 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3350 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3353 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3354 if (adev->rmmio == NULL) {
3357 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3358 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3360 /* io port mapping */
3361 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3362 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
3363 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
3364 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
3368 if (adev->rio_mem == NULL)
3369 DRM_INFO("PCI I/O BAR is not found.\n");
3371 /* enable PCIE atomic ops */
3372 r = pci_enable_atomic_ops_to_root(adev->pdev,
3373 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3374 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3376 adev->have_atomics_support = false;
3377 DRM_INFO("PCIE atomic ops is not supported\n");
3379 adev->have_atomics_support = true;
3382 amdgpu_device_get_pcie_info(adev);
3385 DRM_INFO("MCBP is enabled\n");
3387 if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
3388 adev->enable_mes = true;
3390 /* detect hw virtualization here */
3391 amdgpu_detect_virtualization(adev);
3393 r = amdgpu_device_get_job_timeout_settings(adev);
3395 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3399 /* early init functions */
3400 r = amdgpu_device_ip_early_init(adev);
3404 /* doorbell bar mapping and doorbell index init*/
3405 amdgpu_device_doorbell_init(adev);
3407 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3408 /* this will fail for cards that aren't VGA class devices, just
3410 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3411 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
3413 if (amdgpu_device_supports_atpx(ddev))
3415 if (amdgpu_has_atpx() &&
3416 (amdgpu_is_atpx_hybrid() ||
3417 amdgpu_has_atpx_dgpu_power_cntl()) &&
3418 !pci_is_thunderbolt_attached(adev->pdev))
3419 vga_switcheroo_register_client(adev->pdev,
3420 &amdgpu_switcheroo_ops, atpx);
3422 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3424 if (amdgpu_emu_mode == 1) {
3425 /* post the asic on emulation mode */
3426 emu_soc_asic_init(adev);
3427 goto fence_driver_init;
3430 /* detect if we are with an SRIOV vbios */
3431 amdgpu_device_detect_sriov_bios(adev);
3433 /* check if we need to reset the asic
3434 * E.g., driver was not cleanly unloaded previously, etc.
3436 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3437 if (adev->gmc.xgmi.num_physical_nodes) {
3438 dev_info(adev->dev, "Pending hive reset.\n");
3439 adev->gmc.xgmi.pending_reset = true;
3440 /* Only need to init necessary block for SMU to handle the reset */
3441 for (i = 0; i < adev->num_ip_blocks; i++) {
3442 if (!adev->ip_blocks[i].status.valid)
3444 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3445 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3446 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3447 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
3448 DRM_DEBUG("IP %s disabled for hw_init.\n",
3449 adev->ip_blocks[i].version->funcs->name);
3450 adev->ip_blocks[i].status.hw = true;
3454 r = amdgpu_asic_reset(adev);
3456 dev_err(adev->dev, "asic reset on init failed\n");
3462 pci_enable_pcie_error_reporting(adev->pdev);
3464 /* Post card if necessary */
3465 if (amdgpu_device_need_post(adev)) {
3467 dev_err(adev->dev, "no vBIOS found\n");
3471 DRM_INFO("GPU posting now...\n");
3472 r = amdgpu_device_asic_init(adev);
3474 dev_err(adev->dev, "gpu post error!\n");
3479 if (adev->is_atom_fw) {
3480 /* Initialize clocks */
3481 r = amdgpu_atomfirmware_get_clock_info(adev);
3483 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3484 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3488 /* Initialize clocks */
3489 r = amdgpu_atombios_get_clock_info(adev);
3491 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3492 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3495 /* init i2c buses */
3496 if (!amdgpu_device_has_dc_support(adev))
3497 amdgpu_atombios_i2c_init(adev);
3502 r = amdgpu_fence_driver_init(adev);
3504 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
3505 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3509 /* init the mode config */
3510 drm_mode_config_init(adev_to_drm(adev));
3512 r = amdgpu_device_ip_init(adev);
3514 /* failed in exclusive mode due to timeout */
3515 if (amdgpu_sriov_vf(adev) &&
3516 !amdgpu_sriov_runtime(adev) &&
3517 amdgpu_virt_mmio_blocked(adev) &&
3518 !amdgpu_virt_wait_reset(adev)) {
3519 dev_err(adev->dev, "VF exclusive mode timeout\n");
3520 /* Don't send request since VF is inactive. */
3521 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3522 adev->virt.ops = NULL;
3526 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3527 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3532 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3533 adev->gfx.config.max_shader_engines,
3534 adev->gfx.config.max_sh_per_se,
3535 adev->gfx.config.max_cu_per_sh,
3536 adev->gfx.cu_info.number);
3538 adev->accel_working = true;
3540 amdgpu_vm_check_compute_bug(adev);
3542 /* Initialize the buffer migration limit. */
3543 if (amdgpu_moverate >= 0)
3544 max_MBps = amdgpu_moverate;
3546 max_MBps = 8; /* Allow 8 MB/s. */
3547 /* Get a log2 for easy divisions. */
3548 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3550 amdgpu_fbdev_init(adev);
3552 r = amdgpu_pm_sysfs_init(adev);
3554 adev->pm_sysfs_en = false;
3555 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3557 adev->pm_sysfs_en = true;
3559 r = amdgpu_ucode_sysfs_init(adev);
3561 adev->ucode_sysfs_en = false;
3562 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3564 adev->ucode_sysfs_en = true;
3566 if ((amdgpu_testing & 1)) {
3567 if (adev->accel_working)
3568 amdgpu_test_moves(adev);
3570 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
3572 if (amdgpu_benchmarking) {
3573 if (adev->accel_working)
3574 amdgpu_benchmark(adev, amdgpu_benchmarking);
3576 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
3580 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3581 * Otherwise the mgpu fan boost feature will be skipped due to the
3582 * gpu instance is counted less.
3584 amdgpu_register_gpu_instance(adev);
3586 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3587 * explicit gating rather than handling it automatically.
3589 if (!adev->gmc.xgmi.pending_reset) {
3590 r = amdgpu_device_ip_late_init(adev);
3592 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3593 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3597 amdgpu_ras_resume(adev);
3598 queue_delayed_work(system_wq, &adev->delayed_init_work,
3599 msecs_to_jiffies(AMDGPU_RESUME_MS));
3602 if (amdgpu_sriov_vf(adev))
3603 flush_delayed_work(&adev->delayed_init_work);
3605 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3607 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3609 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3610 r = amdgpu_pmu_init(adev);
3612 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3614 /* Have stored pci confspace at hand for restore in sudden PCI error */
3615 if (amdgpu_device_cache_pci_state(adev->pdev))
3616 pci_restore_state(pdev);
3618 /* Enable lightSBR on SMU in passthrough + xgmi configuration */
3619 if (amdgpu_passthrough(adev) && adev->gmc.xgmi.num_physical_nodes > 1)
3620 smu_set_light_sbr(&adev->smu, true);
3622 if (adev->gmc.xgmi.pending_reset)
3623 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
3624 msecs_to_jiffies(AMDGPU_RESUME_MS));
3629 amdgpu_vf_error_trans_all(adev);
3631 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3634 iounmap(adev->rmmio);
3641 * amdgpu_device_fini - tear down the driver
3643 * @adev: amdgpu_device pointer
3645 * Tear down the driver info (all asics).
3646 * Called at driver shutdown.
3648 void amdgpu_device_fini(struct amdgpu_device *adev)
3650 dev_info(adev->dev, "amdgpu: finishing device.\n");
3651 flush_delayed_work(&adev->delayed_init_work);
3652 ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3653 adev->shutdown = true;
3655 kfree(adev->pci_state);
3657 /* make sure IB test finished before entering exclusive mode
3658 * to avoid preemption on IB test
3660 if (amdgpu_sriov_vf(adev)) {
3661 amdgpu_virt_request_full_gpu(adev, false);
3662 amdgpu_virt_fini_data_exchange(adev);
3665 /* disable all interrupts */
3666 amdgpu_irq_disable_all(adev);
3667 if (adev->mode_info.mode_config_initialized){
3668 if (!amdgpu_device_has_dc_support(adev))
3669 drm_helper_force_disable_all(adev_to_drm(adev));
3671 drm_atomic_helper_shutdown(adev_to_drm(adev));
3673 amdgpu_fence_driver_fini(adev);
3674 if (adev->pm_sysfs_en)
3675 amdgpu_pm_sysfs_fini(adev);
3676 amdgpu_fbdev_fini(adev);
3677 amdgpu_device_ip_fini(adev);
3678 release_firmware(adev->firmware.gpu_info_fw);
3679 adev->firmware.gpu_info_fw = NULL;
3680 adev->accel_working = false;
3681 /* free i2c buses */
3682 if (!amdgpu_device_has_dc_support(adev))
3683 amdgpu_i2c_fini(adev);
3685 if (amdgpu_emu_mode != 1)
3686 amdgpu_atombios_fini(adev);
3690 if (amdgpu_has_atpx() &&
3691 (amdgpu_is_atpx_hybrid() ||
3692 amdgpu_has_atpx_dgpu_power_cntl()) &&
3693 !pci_is_thunderbolt_attached(adev->pdev))
3694 vga_switcheroo_unregister_client(adev->pdev);
3695 if (amdgpu_device_supports_atpx(adev_to_drm(adev)))
3696 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3697 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3698 vga_client_register(adev->pdev, NULL, NULL, NULL);
3700 pci_iounmap(adev->pdev, adev->rio_mem);
3701 adev->rio_mem = NULL;
3702 iounmap(adev->rmmio);
3704 amdgpu_device_doorbell_fini(adev);
3706 if (adev->ucode_sysfs_en)
3707 amdgpu_ucode_sysfs_fini(adev);
3709 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
3710 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3711 amdgpu_pmu_fini(adev);
3712 if (adev->mman.discovery_bin)
3713 amdgpu_discovery_fini(adev);
3721 * amdgpu_device_suspend - initiate device suspend
3723 * @dev: drm dev pointer
3724 * @fbcon : notify the fbdev of suspend
3726 * Puts the hw in the suspend state (all asics).
3727 * Returns 0 for success or an error on failure.
3728 * Called at driver suspend.
3730 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
3732 struct amdgpu_device *adev;
3733 struct drm_crtc *crtc;
3734 struct drm_connector *connector;
3735 struct drm_connector_list_iter iter;
3738 adev = drm_to_adev(dev);
3740 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3743 adev->in_suspend = true;
3744 drm_kms_helper_poll_disable(dev);
3747 amdgpu_fbdev_set_suspend(adev, 1);
3749 cancel_delayed_work_sync(&adev->delayed_init_work);
3751 if (!amdgpu_device_has_dc_support(adev)) {
3752 /* turn off display hw */
3753 drm_modeset_lock_all(dev);
3754 drm_connector_list_iter_begin(dev, &iter);
3755 drm_for_each_connector_iter(connector, &iter)
3756 drm_helper_connector_dpms(connector,
3758 drm_connector_list_iter_end(&iter);
3759 drm_modeset_unlock_all(dev);
3760 /* unpin the front buffers and cursors */
3761 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3762 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3763 struct drm_framebuffer *fb = crtc->primary->fb;
3764 struct amdgpu_bo *robj;
3766 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3767 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3768 r = amdgpu_bo_reserve(aobj, true);
3770 amdgpu_bo_unpin(aobj);
3771 amdgpu_bo_unreserve(aobj);
3775 if (fb == NULL || fb->obj[0] == NULL) {
3778 robj = gem_to_amdgpu_bo(fb->obj[0]);
3779 /* don't unpin kernel fb objects */
3780 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
3781 r = amdgpu_bo_reserve(robj, true);
3783 amdgpu_bo_unpin(robj);
3784 amdgpu_bo_unreserve(robj);
3790 amdgpu_ras_suspend(adev);
3792 r = amdgpu_device_ip_suspend_phase1(adev);
3794 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
3796 /* evict vram memory */
3797 amdgpu_bo_evict_vram(adev);
3799 amdgpu_fence_driver_suspend(adev);
3801 if (adev->in_poweroff_reboot_com ||
3802 !amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev))
3803 r = amdgpu_device_ip_suspend_phase2(adev);
3805 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
3806 /* evict remaining vram memory
3807 * This second call to evict vram is to evict the gart page table
3810 amdgpu_bo_evict_vram(adev);
3816 * amdgpu_device_resume - initiate device resume
3818 * @dev: drm dev pointer
3819 * @fbcon : notify the fbdev of resume
3821 * Bring the hw back to operating state (all asics).
3822 * Returns 0 for success or an error on failure.
3823 * Called at driver resume.
3825 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
3827 struct drm_connector *connector;
3828 struct drm_connector_list_iter iter;
3829 struct amdgpu_device *adev = drm_to_adev(dev);
3830 struct drm_crtc *crtc;
3833 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3836 if (amdgpu_acpi_is_s0ix_supported(adev))
3837 amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
3840 if (amdgpu_device_need_post(adev)) {
3841 r = amdgpu_device_asic_init(adev);
3843 dev_err(adev->dev, "amdgpu asic init failed\n");
3846 r = amdgpu_device_ip_resume(adev);
3848 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
3851 amdgpu_fence_driver_resume(adev);
3854 r = amdgpu_device_ip_late_init(adev);
3858 queue_delayed_work(system_wq, &adev->delayed_init_work,
3859 msecs_to_jiffies(AMDGPU_RESUME_MS));
3861 if (!amdgpu_device_has_dc_support(adev)) {
3863 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3864 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3866 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3867 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3868 r = amdgpu_bo_reserve(aobj, true);
3870 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3872 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
3873 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3874 amdgpu_bo_unreserve(aobj);
3879 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
3883 /* Make sure IB tests flushed */
3884 flush_delayed_work(&adev->delayed_init_work);
3886 /* blat the mode back in */
3888 if (!amdgpu_device_has_dc_support(adev)) {
3890 drm_helper_resume_force_mode(dev);
3892 /* turn on display hw */
3893 drm_modeset_lock_all(dev);
3895 drm_connector_list_iter_begin(dev, &iter);
3896 drm_for_each_connector_iter(connector, &iter)
3897 drm_helper_connector_dpms(connector,
3899 drm_connector_list_iter_end(&iter);
3901 drm_modeset_unlock_all(dev);
3903 amdgpu_fbdev_set_suspend(adev, 0);
3906 drm_kms_helper_poll_enable(dev);
3908 amdgpu_ras_resume(adev);
3911 * Most of the connector probing functions try to acquire runtime pm
3912 * refs to ensure that the GPU is powered on when connector polling is
3913 * performed. Since we're calling this from a runtime PM callback,
3914 * trying to acquire rpm refs will cause us to deadlock.
3916 * Since we're guaranteed to be holding the rpm lock, it's safe to
3917 * temporarily disable the rpm helpers so this doesn't deadlock us.
3920 dev->dev->power.disable_depth++;
3922 if (!amdgpu_device_has_dc_support(adev))
3923 drm_helper_hpd_irq_event(dev);
3925 drm_kms_helper_hotplug_event(dev);
3927 dev->dev->power.disable_depth--;
3929 adev->in_suspend = false;
3935 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3937 * @adev: amdgpu_device pointer
3939 * The list of all the hardware IPs that make up the asic is walked and
3940 * the check_soft_reset callbacks are run. check_soft_reset determines
3941 * if the asic is still hung or not.
3942 * Returns true if any of the IPs are still in a hung state, false if not.
3944 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3947 bool asic_hang = false;
3949 if (amdgpu_sriov_vf(adev))
3952 if (amdgpu_asic_need_full_reset(adev))
3955 for (i = 0; i < adev->num_ip_blocks; i++) {
3956 if (!adev->ip_blocks[i].status.valid)
3958 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3959 adev->ip_blocks[i].status.hang =
3960 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3961 if (adev->ip_blocks[i].status.hang) {
3962 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3970 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3972 * @adev: amdgpu_device pointer
3974 * The list of all the hardware IPs that make up the asic is walked and the
3975 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3976 * handles any IP specific hardware or software state changes that are
3977 * necessary for a soft reset to succeed.
3978 * Returns 0 on success, negative error code on failure.
3980 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3984 for (i = 0; i < adev->num_ip_blocks; i++) {
3985 if (!adev->ip_blocks[i].status.valid)
3987 if (adev->ip_blocks[i].status.hang &&
3988 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3989 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3999 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4001 * @adev: amdgpu_device pointer
4003 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4004 * reset is necessary to recover.
4005 * Returns true if a full asic reset is required, false if not.
4007 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4011 if (amdgpu_asic_need_full_reset(adev))
4014 for (i = 0; i < adev->num_ip_blocks; i++) {
4015 if (!adev->ip_blocks[i].status.valid)
4017 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4018 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4019 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4020 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4021 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4022 if (adev->ip_blocks[i].status.hang) {
4023 dev_info(adev->dev, "Some block need full reset!\n");
4032 * amdgpu_device_ip_soft_reset - do a soft reset
4034 * @adev: amdgpu_device pointer
4036 * The list of all the hardware IPs that make up the asic is walked and the
4037 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4038 * IP specific hardware or software state changes that are necessary to soft
4040 * Returns 0 on success, negative error code on failure.
4042 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4046 for (i = 0; i < adev->num_ip_blocks; i++) {
4047 if (!adev->ip_blocks[i].status.valid)
4049 if (adev->ip_blocks[i].status.hang &&
4050 adev->ip_blocks[i].version->funcs->soft_reset) {
4051 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4061 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4063 * @adev: amdgpu_device pointer
4065 * The list of all the hardware IPs that make up the asic is walked and the
4066 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4067 * handles any IP specific hardware or software state changes that are
4068 * necessary after the IP has been soft reset.
4069 * Returns 0 on success, negative error code on failure.
4071 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4075 for (i = 0; i < adev->num_ip_blocks; i++) {
4076 if (!adev->ip_blocks[i].status.valid)
4078 if (adev->ip_blocks[i].status.hang &&
4079 adev->ip_blocks[i].version->funcs->post_soft_reset)
4080 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4089 * amdgpu_device_recover_vram - Recover some VRAM contents
4091 * @adev: amdgpu_device pointer
4093 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4094 * restore things like GPUVM page tables after a GPU reset where
4095 * the contents of VRAM might be lost.
4098 * 0 on success, negative error code on failure.
4100 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4102 struct dma_fence *fence = NULL, *next = NULL;
4103 struct amdgpu_bo *shadow;
4106 if (amdgpu_sriov_runtime(adev))
4107 tmo = msecs_to_jiffies(8000);
4109 tmo = msecs_to_jiffies(100);
4111 dev_info(adev->dev, "recover vram bo from shadow start\n");
4112 mutex_lock(&adev->shadow_list_lock);
4113 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
4115 /* No need to recover an evicted BO */
4116 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
4117 shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
4118 shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
4121 r = amdgpu_bo_restore_shadow(shadow, &next);
4126 tmo = dma_fence_wait_timeout(fence, false, tmo);
4127 dma_fence_put(fence);
4132 } else if (tmo < 0) {
4140 mutex_unlock(&adev->shadow_list_lock);
4143 tmo = dma_fence_wait_timeout(fence, false, tmo);
4144 dma_fence_put(fence);
4146 if (r < 0 || tmo <= 0) {
4147 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4151 dev_info(adev->dev, "recover vram bo from shadow done\n");
4157 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4159 * @adev: amdgpu_device pointer
4160 * @from_hypervisor: request from hypervisor
4162 * do VF FLR and reinitialize Asic
4163 * return 0 means succeeded otherwise failed
4165 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4166 bool from_hypervisor)
4170 if (from_hypervisor)
4171 r = amdgpu_virt_request_full_gpu(adev, true);
4173 r = amdgpu_virt_reset_gpu(adev);
4177 amdgpu_amdkfd_pre_reset(adev);
4179 /* Resume IP prior to SMC */
4180 r = amdgpu_device_ip_reinit_early_sriov(adev);
4184 amdgpu_virt_init_data_exchange(adev);
4185 /* we need recover gart prior to run SMC/CP/SDMA resume */
4186 amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
4188 r = amdgpu_device_fw_loading(adev);
4192 /* now we are okay to resume SMC/CP/SDMA */
4193 r = amdgpu_device_ip_reinit_late_sriov(adev);
4197 amdgpu_irq_gpu_reset_resume_helper(adev);
4198 r = amdgpu_ib_ring_tests(adev);
4199 amdgpu_amdkfd_post_reset(adev);
4202 amdgpu_virt_release_full_gpu(adev, true);
4203 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4204 amdgpu_inc_vram_lost(adev);
4205 r = amdgpu_device_recover_vram(adev);
4212 * amdgpu_device_has_job_running - check if there is any job in mirror list
4214 * @adev: amdgpu_device pointer
4216 * check if there is any job in mirror list
4218 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4221 struct drm_sched_job *job;
4223 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4224 struct amdgpu_ring *ring = adev->rings[i];
4226 if (!ring || !ring->sched.thread)
4229 spin_lock(&ring->sched.job_list_lock);
4230 job = list_first_entry_or_null(&ring->sched.pending_list,
4231 struct drm_sched_job, list);
4232 spin_unlock(&ring->sched.job_list_lock);
4240 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4242 * @adev: amdgpu_device pointer
4244 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4247 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4249 if (!amdgpu_device_ip_check_soft_reset(adev)) {
4250 dev_info(adev->dev, "Timeout, but no hardware hang detected.\n");
4254 if (amdgpu_gpu_recovery == 0)
4257 if (amdgpu_sriov_vf(adev))
4260 if (amdgpu_gpu_recovery == -1) {
4261 switch (adev->asic_type) {
4267 case CHIP_POLARIS10:
4268 case CHIP_POLARIS11:
4269 case CHIP_POLARIS12:
4280 case CHIP_SIENNA_CICHLID:
4281 case CHIP_NAVY_FLOUNDER:
4282 case CHIP_DIMGREY_CAVEFISH:
4292 dev_info(adev->dev, "GPU recovery disabled.\n");
4296 int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
4301 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
4303 dev_info(adev->dev, "GPU mode1 reset\n");
4306 pci_clear_master(adev->pdev);
4308 amdgpu_device_cache_pci_state(adev->pdev);
4310 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
4311 dev_info(adev->dev, "GPU smu mode1 reset\n");
4312 ret = amdgpu_dpm_mode1_reset(adev);
4314 dev_info(adev->dev, "GPU psp mode1 reset\n");
4315 ret = psp_gpu_reset(adev);
4319 dev_err(adev->dev, "GPU mode1 reset failed\n");
4321 amdgpu_device_load_pci_state(adev->pdev);
4323 /* wait for asic to come out of reset */
4324 for (i = 0; i < adev->usec_timeout; i++) {
4325 u32 memsize = adev->nbio.funcs->get_memsize(adev);
4327 if (memsize != 0xffffffff)
4332 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
4336 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4337 struct amdgpu_job *job,
4338 bool *need_full_reset_arg)
4341 bool need_full_reset = *need_full_reset_arg;
4343 /* no need to dump if device is not in good state during probe period */
4344 if (!adev->gmc.xgmi.pending_reset)
4345 amdgpu_debugfs_wait_dump(adev);
4347 if (amdgpu_sriov_vf(adev)) {
4348 /* stop the data exchange thread */
4349 amdgpu_virt_fini_data_exchange(adev);
4352 /* block all schedulers and reset given job's ring */
4353 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4354 struct amdgpu_ring *ring = adev->rings[i];
4356 if (!ring || !ring->sched.thread)
4359 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4360 amdgpu_fence_driver_force_completion(ring);
4364 drm_sched_increase_karma(&job->base);
4366 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4367 if (!amdgpu_sriov_vf(adev)) {
4369 if (!need_full_reset)
4370 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4372 if (!need_full_reset) {
4373 amdgpu_device_ip_pre_soft_reset(adev);
4374 r = amdgpu_device_ip_soft_reset(adev);
4375 amdgpu_device_ip_post_soft_reset(adev);
4376 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4377 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4378 need_full_reset = true;
4382 if (need_full_reset)
4383 r = amdgpu_device_ip_suspend(adev);
4385 *need_full_reset_arg = need_full_reset;
4391 int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
4392 struct list_head *device_list_handle,
4393 bool *need_full_reset_arg,
4396 struct amdgpu_device *tmp_adev = NULL;
4397 bool need_full_reset = *need_full_reset_arg, vram_lost = false;
4401 * ASIC reset has to be done on all XGMI hive nodes ASAP
4402 * to allow proper links negotiation in FW (within 1 sec)
4404 if (!skip_hw_reset && need_full_reset) {
4405 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4406 /* For XGMI run all resets in parallel to speed up the process */
4407 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4408 tmp_adev->gmc.xgmi.pending_reset = false;
4409 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4412 r = amdgpu_asic_reset(tmp_adev);
4415 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4416 r, adev_to_drm(tmp_adev)->unique);
4421 /* For XGMI wait for all resets to complete before proceed */
4423 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4424 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4425 flush_work(&tmp_adev->xgmi_reset_work);
4426 r = tmp_adev->asic_reset_res;
4434 if (!r && amdgpu_ras_intr_triggered()) {
4435 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4436 if (tmp_adev->mmhub.funcs &&
4437 tmp_adev->mmhub.funcs->reset_ras_error_count)
4438 tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev);
4441 amdgpu_ras_intr_cleared();
4444 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4445 if (need_full_reset) {
4447 r = amdgpu_device_asic_init(tmp_adev);
4449 dev_warn(tmp_adev->dev, "asic atom init failed!");
4451 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4452 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4456 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4458 DRM_INFO("VRAM is lost due to GPU reset!\n");
4459 amdgpu_inc_vram_lost(tmp_adev);
4462 r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT));
4466 r = amdgpu_device_fw_loading(tmp_adev);
4470 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4475 amdgpu_device_fill_reset_magic(tmp_adev);
4478 * Add this ASIC as tracked as reset was already
4479 * complete successfully.
4481 amdgpu_register_gpu_instance(tmp_adev);
4483 if (!hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4484 amdgpu_xgmi_add_device(tmp_adev);
4486 r = amdgpu_device_ip_late_init(tmp_adev);
4490 amdgpu_fbdev_set_suspend(tmp_adev, 0);
4493 * The GPU enters bad state once faulty pages
4494 * by ECC has reached the threshold, and ras
4495 * recovery is scheduled next. So add one check
4496 * here to break recovery if it indeed exceeds
4497 * bad page threshold, and remind user to
4498 * retire this GPU or setting one bigger
4499 * bad_page_threshold value to fix this once
4500 * probing driver again.
4502 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
4504 amdgpu_ras_resume(tmp_adev);
4510 /* Update PSP FW topology after reset */
4511 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4512 r = amdgpu_xgmi_update_topology(hive, tmp_adev);
4518 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
4519 r = amdgpu_ib_ring_tests(tmp_adev);
4521 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
4522 r = amdgpu_device_ip_suspend(tmp_adev);
4523 need_full_reset = true;
4530 r = amdgpu_device_recover_vram(tmp_adev);
4532 tmp_adev->asic_reset_res = r;
4536 *need_full_reset_arg = need_full_reset;
4540 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev,
4541 struct amdgpu_hive_info *hive)
4543 if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)
4547 down_write_nest_lock(&adev->reset_sem, &hive->hive_lock);
4549 down_write(&adev->reset_sem);
4552 switch (amdgpu_asic_reset_method(adev)) {
4553 case AMD_RESET_METHOD_MODE1:
4554 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
4556 case AMD_RESET_METHOD_MODE2:
4557 adev->mp1_state = PP_MP1_STATE_RESET;
4560 adev->mp1_state = PP_MP1_STATE_NONE;
4567 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
4569 amdgpu_vf_error_trans_all(adev);
4570 adev->mp1_state = PP_MP1_STATE_NONE;
4571 atomic_set(&adev->in_gpu_reset, 0);
4572 up_write(&adev->reset_sem);
4576 * to lockup a list of amdgpu devices in a hive safely, if not a hive
4577 * with multiple nodes, it will be similar as amdgpu_device_lock_adev.
4579 * unlock won't require roll back.
4581 static int amdgpu_device_lock_hive_adev(struct amdgpu_device *adev, struct amdgpu_hive_info *hive)
4583 struct amdgpu_device *tmp_adev = NULL;
4585 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4587 dev_err(adev->dev, "Hive is NULL while device has multiple xgmi nodes");
4590 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
4591 if (!amdgpu_device_lock_adev(tmp_adev, hive))
4594 } else if (!amdgpu_device_lock_adev(adev, hive))
4599 if (!list_is_first(&tmp_adev->gmc.xgmi.head, &hive->device_list)) {
4601 * if the lockup iteration break in the middle of a hive,
4602 * it may means there may has a race issue,
4603 * or a hive device locked up independently.
4604 * we may be in trouble and may not, so will try to roll back
4605 * the lock and give out a warnning.
4607 dev_warn(tmp_adev->dev, "Hive lock iteration broke in the middle. Rolling back to unlock");
4608 list_for_each_entry_continue_reverse(tmp_adev, &hive->device_list, gmc.xgmi.head) {
4609 amdgpu_device_unlock_adev(tmp_adev);
4615 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
4617 struct pci_dev *p = NULL;
4619 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4620 adev->pdev->bus->number, 1);
4622 pm_runtime_enable(&(p->dev));
4623 pm_runtime_resume(&(p->dev));
4627 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
4629 enum amd_reset_method reset_method;
4630 struct pci_dev *p = NULL;
4634 * For now, only BACO and mode1 reset are confirmed
4635 * to suffer the audio issue without proper suspended.
4637 reset_method = amdgpu_asic_reset_method(adev);
4638 if ((reset_method != AMD_RESET_METHOD_BACO) &&
4639 (reset_method != AMD_RESET_METHOD_MODE1))
4642 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4643 adev->pdev->bus->number, 1);
4647 expires = pm_runtime_autosuspend_expiration(&(p->dev));
4650 * If we cannot get the audio device autosuspend delay,
4651 * a fixed 4S interval will be used. Considering 3S is
4652 * the audio controller default autosuspend delay setting.
4653 * 4S used here is guaranteed to cover that.
4655 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
4657 while (!pm_runtime_status_suspended(&(p->dev))) {
4658 if (!pm_runtime_suspend(&(p->dev)))
4661 if (expires < ktime_get_mono_fast_ns()) {
4662 dev_warn(adev->dev, "failed to suspend display audio\n");
4663 /* TODO: abort the succeeding gpu reset? */
4668 pm_runtime_disable(&(p->dev));
4674 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
4676 * @adev: amdgpu_device pointer
4677 * @job: which job trigger hang
4679 * Attempt to reset the GPU if it has hung (all asics).
4680 * Attempt to do soft-reset or full-reset and reinitialize Asic
4681 * Returns 0 for success or an error on failure.
4684 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
4685 struct amdgpu_job *job)
4687 struct list_head device_list, *device_list_handle = NULL;
4688 bool need_full_reset = false;
4689 bool job_signaled = false;
4690 struct amdgpu_hive_info *hive = NULL;
4691 struct amdgpu_device *tmp_adev = NULL;
4693 bool need_emergency_restart = false;
4694 bool audio_suspended = false;
4697 * Special case: RAS triggered and full reset isn't supported
4699 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
4702 * Flush RAM to disk so that after reboot
4703 * the user can read log and see why the system rebooted.
4705 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
4706 DRM_WARN("Emergency reboot.");
4709 emergency_restart();
4712 dev_info(adev->dev, "GPU %s begin!\n",
4713 need_emergency_restart ? "jobs stop":"reset");
4716 * Here we trylock to avoid chain of resets executing from
4717 * either trigger by jobs on different adevs in XGMI hive or jobs on
4718 * different schedulers for same device while this TO handler is running.
4719 * We always reset all schedulers for device and all devices for XGMI
4720 * hive so that should take care of them too.
4722 hive = amdgpu_get_xgmi_hive(adev);
4724 if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) {
4725 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
4726 job ? job->base.id : -1, hive->hive_id);
4727 amdgpu_put_xgmi_hive(hive);
4729 drm_sched_increase_karma(&job->base);
4732 mutex_lock(&hive->hive_lock);
4736 * lock the device before we try to operate the linked list
4737 * if didn't get the device lock, don't touch the linked list since
4738 * others may iterating it.
4740 r = amdgpu_device_lock_hive_adev(adev, hive);
4742 dev_info(adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress",
4743 job ? job->base.id : -1);
4745 /* even we skipped this reset, still need to set the job to guilty */
4747 drm_sched_increase_karma(&job->base);
4752 * Build list of devices to reset.
4753 * In case we are in XGMI hive mode, resort the device list
4754 * to put adev in the 1st position.
4756 INIT_LIST_HEAD(&device_list);
4757 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4758 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head)
4759 list_add_tail(&tmp_adev->reset_list, &device_list);
4760 if (!list_is_first(&adev->reset_list, &device_list))
4761 list_rotate_to_front(&adev->reset_list, &device_list);
4762 device_list_handle = &device_list;
4764 list_add_tail(&adev->reset_list, &device_list);
4765 device_list_handle = &device_list;
4768 /* block all schedulers and reset given job's ring */
4769 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4771 * Try to put the audio codec into suspend state
4772 * before gpu reset started.
4774 * Due to the power domain of the graphics device
4775 * is shared with AZ power domain. Without this,
4776 * we may change the audio hardware from behind
4777 * the audio driver's back. That will trigger
4778 * some audio codec errors.
4780 if (!amdgpu_device_suspend_display_audio(tmp_adev))
4781 audio_suspended = true;
4783 amdgpu_ras_set_error_query_ready(tmp_adev, false);
4785 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
4787 if (!amdgpu_sriov_vf(tmp_adev))
4788 amdgpu_amdkfd_pre_reset(tmp_adev);
4791 * Mark these ASICs to be reseted as untracked first
4792 * And add them back after reset completed
4794 amdgpu_unregister_gpu_instance(tmp_adev);
4796 amdgpu_fbdev_set_suspend(tmp_adev, 1);
4798 /* disable ras on ALL IPs */
4799 if (!need_emergency_restart &&
4800 amdgpu_device_ip_need_full_reset(tmp_adev))
4801 amdgpu_ras_suspend(tmp_adev);
4803 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4804 struct amdgpu_ring *ring = tmp_adev->rings[i];
4806 if (!ring || !ring->sched.thread)
4809 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
4811 if (need_emergency_restart)
4812 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
4814 atomic_inc(&tmp_adev->gpu_reset_counter);
4817 if (need_emergency_restart)
4818 goto skip_sched_resume;
4821 * Must check guilty signal here since after this point all old
4822 * HW fences are force signaled.
4824 * job->base holds a reference to parent fence
4826 if (job && job->base.s_fence->parent &&
4827 dma_fence_is_signaled(job->base.s_fence->parent)) {
4828 job_signaled = true;
4829 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
4833 retry: /* Rest of adevs pre asic reset from XGMI hive. */
4834 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4835 r = amdgpu_device_pre_asic_reset(tmp_adev,
4836 (tmp_adev == adev) ? job : NULL,
4838 /*TODO Should we stop ?*/
4840 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
4841 r, adev_to_drm(tmp_adev)->unique);
4842 tmp_adev->asic_reset_res = r;
4846 /* Actual ASIC resets if needed.*/
4847 /* TODO Implement XGMI hive reset logic for SRIOV */
4848 if (amdgpu_sriov_vf(adev)) {
4849 r = amdgpu_device_reset_sriov(adev, job ? false : true);
4851 adev->asic_reset_res = r;
4853 r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset, false);
4854 if (r && r == -EAGAIN)
4860 /* Post ASIC reset for all devs .*/
4861 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4863 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4864 struct amdgpu_ring *ring = tmp_adev->rings[i];
4866 if (!ring || !ring->sched.thread)
4869 /* No point to resubmit jobs if we didn't HW reset*/
4870 if (!tmp_adev->asic_reset_res && !job_signaled)
4871 drm_sched_resubmit_jobs(&ring->sched);
4873 drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
4876 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
4877 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
4880 tmp_adev->asic_reset_res = 0;
4883 /* bad news, how to tell it to userspace ? */
4884 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
4885 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
4887 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
4892 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4893 /* unlock kfd: SRIOV would do it separately */
4894 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
4895 amdgpu_amdkfd_post_reset(tmp_adev);
4897 /* kfd_post_reset will do nothing if kfd device is not initialized,
4898 * need to bring up kfd here if it's not be initialized before
4900 if (!adev->kfd.init_complete)
4901 amdgpu_amdkfd_device_init(adev);
4903 if (audio_suspended)
4904 amdgpu_device_resume_display_audio(tmp_adev);
4905 amdgpu_device_unlock_adev(tmp_adev);
4910 atomic_set(&hive->in_reset, 0);
4911 mutex_unlock(&hive->hive_lock);
4912 amdgpu_put_xgmi_hive(hive);
4915 if (r && r != -EAGAIN)
4916 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
4921 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
4923 * @adev: amdgpu_device pointer
4925 * Fetchs and stores in the driver the PCIE capabilities (gen speed
4926 * and lanes) of the slot the device is in. Handles APUs and
4927 * virtualized environments where PCIE config space may not be available.
4929 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
4931 struct pci_dev *pdev;
4932 enum pci_bus_speed speed_cap, platform_speed_cap;
4933 enum pcie_link_width platform_link_width;
4935 if (amdgpu_pcie_gen_cap)
4936 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
4938 if (amdgpu_pcie_lane_cap)
4939 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
4941 /* covers APUs as well */
4942 if (pci_is_root_bus(adev->pdev->bus)) {
4943 if (adev->pm.pcie_gen_mask == 0)
4944 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
4945 if (adev->pm.pcie_mlw_mask == 0)
4946 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4950 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
4953 pcie_bandwidth_available(adev->pdev, NULL,
4954 &platform_speed_cap, &platform_link_width);
4956 if (adev->pm.pcie_gen_mask == 0) {
4959 speed_cap = pcie_get_speed_cap(pdev);
4960 if (speed_cap == PCI_SPEED_UNKNOWN) {
4961 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4962 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4963 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4965 if (speed_cap == PCIE_SPEED_32_0GT)
4966 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4967 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4968 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4969 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
4970 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
4971 else if (speed_cap == PCIE_SPEED_16_0GT)
4972 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4973 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4974 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4975 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
4976 else if (speed_cap == PCIE_SPEED_8_0GT)
4977 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4978 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4979 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4980 else if (speed_cap == PCIE_SPEED_5_0GT)
4981 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4982 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
4984 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
4987 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
4988 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4989 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4991 if (platform_speed_cap == PCIE_SPEED_32_0GT)
4992 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4993 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4994 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4995 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
4996 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
4997 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
4998 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4999 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5000 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5001 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5002 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5003 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5004 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5005 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5006 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5007 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5008 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5010 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5014 if (adev->pm.pcie_mlw_mask == 0) {
5015 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5016 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5018 switch (platform_link_width) {
5020 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5021 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5022 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5023 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5024 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5025 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5026 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5029 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5030 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5031 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5032 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5033 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5034 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5037 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5038 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5039 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5040 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5041 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5044 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5045 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5046 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5047 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5050 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5051 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5052 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5055 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5056 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5059 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5068 int amdgpu_device_baco_enter(struct drm_device *dev)
5070 struct amdgpu_device *adev = drm_to_adev(dev);
5071 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5073 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
5076 if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
5077 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5079 return amdgpu_dpm_baco_enter(adev);
5082 int amdgpu_device_baco_exit(struct drm_device *dev)
5084 struct amdgpu_device *adev = drm_to_adev(dev);
5085 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5088 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
5091 ret = amdgpu_dpm_baco_exit(adev);
5095 if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
5096 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
5101 static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev)
5105 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5106 struct amdgpu_ring *ring = adev->rings[i];
5108 if (!ring || !ring->sched.thread)
5111 cancel_delayed_work_sync(&ring->sched.work_tdr);
5116 * amdgpu_pci_error_detected - Called when a PCI error is detected.
5117 * @pdev: PCI device struct
5118 * @state: PCI channel state
5120 * Description: Called when a PCI error is detected.
5122 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
5124 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5126 struct drm_device *dev = pci_get_drvdata(pdev);
5127 struct amdgpu_device *adev = drm_to_adev(dev);
5130 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
5132 if (adev->gmc.xgmi.num_physical_nodes > 1) {
5133 DRM_WARN("No support for XGMI hive yet...");
5134 return PCI_ERS_RESULT_DISCONNECT;
5138 case pci_channel_io_normal:
5139 return PCI_ERS_RESULT_CAN_RECOVER;
5140 /* Fatal error, prepare for slot reset */
5141 case pci_channel_io_frozen:
5143 * Cancel and wait for all TDRs in progress if failing to
5144 * set adev->in_gpu_reset in amdgpu_device_lock_adev
5146 * Locking adev->reset_sem will prevent any external access
5147 * to GPU during PCI error recovery
5149 while (!amdgpu_device_lock_adev(adev, NULL))
5150 amdgpu_cancel_all_tdr(adev);
5153 * Block any work scheduling as we do for regular GPU reset
5154 * for the duration of the recovery
5156 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5157 struct amdgpu_ring *ring = adev->rings[i];
5159 if (!ring || !ring->sched.thread)
5162 drm_sched_stop(&ring->sched, NULL);
5164 atomic_inc(&adev->gpu_reset_counter);
5165 return PCI_ERS_RESULT_NEED_RESET;
5166 case pci_channel_io_perm_failure:
5167 /* Permanent error, prepare for device removal */
5168 return PCI_ERS_RESULT_DISCONNECT;
5171 return PCI_ERS_RESULT_NEED_RESET;
5175 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
5176 * @pdev: pointer to PCI device
5178 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
5181 DRM_INFO("PCI error: mmio enabled callback!!\n");
5183 /* TODO - dump whatever for debugging purposes */
5185 /* This called only if amdgpu_pci_error_detected returns
5186 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
5187 * works, no need to reset slot.
5190 return PCI_ERS_RESULT_RECOVERED;
5194 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5195 * @pdev: PCI device struct
5197 * Description: This routine is called by the pci error recovery
5198 * code after the PCI slot has been reset, just before we
5199 * should resume normal operations.
5201 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5203 struct drm_device *dev = pci_get_drvdata(pdev);
5204 struct amdgpu_device *adev = drm_to_adev(dev);
5206 bool need_full_reset = true;
5208 struct list_head device_list;
5210 DRM_INFO("PCI error: slot reset callback!!\n");
5212 INIT_LIST_HEAD(&device_list);
5213 list_add_tail(&adev->reset_list, &device_list);
5215 /* wait for asic to come out of reset */
5218 /* Restore PCI confspace */
5219 amdgpu_device_load_pci_state(pdev);
5221 /* confirm ASIC came out of reset */
5222 for (i = 0; i < adev->usec_timeout; i++) {
5223 memsize = amdgpu_asic_get_config_memsize(adev);
5225 if (memsize != 0xffffffff)
5229 if (memsize == 0xffffffff) {
5234 adev->in_pci_err_recovery = true;
5235 r = amdgpu_device_pre_asic_reset(adev, NULL, &need_full_reset);
5236 adev->in_pci_err_recovery = false;
5240 r = amdgpu_do_asic_reset(NULL, &device_list, &need_full_reset, true);
5244 if (amdgpu_device_cache_pci_state(adev->pdev))
5245 pci_restore_state(adev->pdev);
5247 DRM_INFO("PCIe error recovery succeeded\n");
5249 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5250 amdgpu_device_unlock_adev(adev);
5253 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5257 * amdgpu_pci_resume() - resume normal ops after PCI reset
5258 * @pdev: pointer to PCI device
5260 * Called when the error recovery driver tells us that its
5261 * OK to resume normal operation.
5263 void amdgpu_pci_resume(struct pci_dev *pdev)
5265 struct drm_device *dev = pci_get_drvdata(pdev);
5266 struct amdgpu_device *adev = drm_to_adev(dev);
5270 DRM_INFO("PCI error: resume callback!!\n");
5272 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5273 struct amdgpu_ring *ring = adev->rings[i];
5275 if (!ring || !ring->sched.thread)
5279 drm_sched_resubmit_jobs(&ring->sched);
5280 drm_sched_start(&ring->sched, true);
5283 amdgpu_device_unlock_adev(adev);
5286 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5288 struct drm_device *dev = pci_get_drvdata(pdev);
5289 struct amdgpu_device *adev = drm_to_adev(dev);
5292 r = pci_save_state(pdev);
5294 kfree(adev->pci_state);
5296 adev->pci_state = pci_store_saved_state(pdev);
5298 if (!adev->pci_state) {
5299 DRM_ERROR("Failed to store PCI saved state");
5303 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5310 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5312 struct drm_device *dev = pci_get_drvdata(pdev);
5313 struct amdgpu_device *adev = drm_to_adev(dev);
5316 if (!adev->pci_state)
5319 r = pci_load_saved_state(pdev, adev->pci_state);
5322 pci_restore_state(pdev);
5324 DRM_WARN("Failed to load PCI state, err:%d\n", r);