2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
33 #include <linux/iommu.h>
34 #include <linux/pci.h>
35 #include <linux/pci-p2pdma.h>
36 #include <linux/apple-gmux.h>
38 #include <drm/drm_aperture.h>
39 #include <drm/drm_atomic_helper.h>
40 #include <drm/drm_crtc_helper.h>
41 #include <drm/drm_fb_helper.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/amdgpu_drm.h>
44 #include <linux/device.h>
45 #include <linux/vgaarb.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/efi.h>
49 #include "amdgpu_trace.h"
50 #include "amdgpu_i2c.h"
52 #include "amdgpu_atombios.h"
53 #include "amdgpu_atomfirmware.h"
55 #ifdef CONFIG_DRM_AMDGPU_SI
58 #ifdef CONFIG_DRM_AMDGPU_CIK
64 #include "bif/bif_4_1_d.h"
65 #include <linux/firmware.h>
66 #include "amdgpu_vf_error.h"
68 #include "amdgpu_amdkfd.h"
69 #include "amdgpu_pm.h"
71 #include "amdgpu_xgmi.h"
72 #include "amdgpu_ras.h"
73 #include "amdgpu_pmu.h"
74 #include "amdgpu_fru_eeprom.h"
75 #include "amdgpu_reset.h"
76 #include "amdgpu_virt.h"
78 #include <linux/suspend.h>
79 #include <drm/task_barrier.h>
80 #include <linux/pm_runtime.h>
82 #include <drm/drm_drv.h>
84 #if IS_ENABLED(CONFIG_X86)
85 #include <asm/intel-family.h>
88 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
89 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
90 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
91 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
92 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
93 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
94 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
96 #define AMDGPU_RESUME_MS 2000
97 #define AMDGPU_MAX_RETRY_LIMIT 2
98 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
100 static const struct drm_driver amdgpu_kms_driver;
102 const char *amdgpu_asic_name[] = {
144 * DOC: pcie_replay_count
146 * The amdgpu driver provides a sysfs API for reporting the total number
147 * of PCIe replays (NAKs)
148 * The file pcie_replay_count is used for this and returns the total
149 * number of replays as a sum of the NAKs generated and NAKs received
152 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
153 struct device_attribute *attr, char *buf)
155 struct drm_device *ddev = dev_get_drvdata(dev);
156 struct amdgpu_device *adev = drm_to_adev(ddev);
157 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
159 return sysfs_emit(buf, "%llu\n", cnt);
162 static DEVICE_ATTR(pcie_replay_count, 0444,
163 amdgpu_device_get_pcie_replay_count, NULL);
168 * The amdgpu driver provides a sysfs API for giving board related information.
169 * It provides the form factor information in the format
173 * Possible form factor values
175 * - "cem" - PCIE CEM card
176 * - "oam" - Open Compute Accelerator Module
177 * - "unknown" - Not known
181 static ssize_t amdgpu_device_get_board_info(struct device *dev,
182 struct device_attribute *attr,
185 struct drm_device *ddev = dev_get_drvdata(dev);
186 struct amdgpu_device *adev = drm_to_adev(ddev);
187 enum amdgpu_pkg_type pkg_type = AMDGPU_PKG_TYPE_CEM;
190 if (adev->smuio.funcs && adev->smuio.funcs->get_pkg_type)
191 pkg_type = adev->smuio.funcs->get_pkg_type(adev);
194 case AMDGPU_PKG_TYPE_CEM:
197 case AMDGPU_PKG_TYPE_OAM:
205 return sysfs_emit(buf, "%s : %s\n", "type", pkg);
208 static DEVICE_ATTR(board_info, 0444, amdgpu_device_get_board_info, NULL);
210 static struct attribute *amdgpu_board_attrs[] = {
211 &dev_attr_board_info.attr,
215 static umode_t amdgpu_board_attrs_is_visible(struct kobject *kobj,
216 struct attribute *attr, int n)
218 struct device *dev = kobj_to_dev(kobj);
219 struct drm_device *ddev = dev_get_drvdata(dev);
220 struct amdgpu_device *adev = drm_to_adev(ddev);
222 if (adev->flags & AMD_IS_APU)
228 static const struct attribute_group amdgpu_board_attrs_group = {
229 .attrs = amdgpu_board_attrs,
230 .is_visible = amdgpu_board_attrs_is_visible
233 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
237 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
239 * @dev: drm_device pointer
241 * Returns true if the device is a dGPU with ATPX power control,
242 * otherwise return false.
244 bool amdgpu_device_supports_px(struct drm_device *dev)
246 struct amdgpu_device *adev = drm_to_adev(dev);
248 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
254 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
256 * @dev: drm_device pointer
258 * Returns true if the device is a dGPU with ACPI power control,
259 * otherwise return false.
261 bool amdgpu_device_supports_boco(struct drm_device *dev)
263 struct amdgpu_device *adev = drm_to_adev(dev);
266 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
272 * amdgpu_device_supports_baco - Does the device support BACO
274 * @dev: drm_device pointer
276 * Returns true if the device supporte BACO,
277 * otherwise return false.
279 bool amdgpu_device_supports_baco(struct drm_device *dev)
281 struct amdgpu_device *adev = drm_to_adev(dev);
283 return amdgpu_asic_supports_baco(adev);
287 * amdgpu_device_supports_smart_shift - Is the device dGPU with
288 * smart shift support
290 * @dev: drm_device pointer
292 * Returns true if the device is a dGPU with Smart Shift support,
293 * otherwise returns false.
295 bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
297 return (amdgpu_device_supports_boco(dev) &&
298 amdgpu_acpi_is_power_shift_control_supported());
302 * VRAM access helper functions
306 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
308 * @adev: amdgpu_device pointer
309 * @pos: offset of the buffer in vram
310 * @buf: virtual address of the buffer in system memory
311 * @size: read/write size, sizeof(@buf) must > @size
312 * @write: true - write to vram, otherwise - read from vram
314 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
315 void *buf, size_t size, bool write)
318 uint32_t hi = ~0, tmp = 0;
319 uint32_t *data = buf;
323 if (!drm_dev_enter(adev_to_drm(adev), &idx))
326 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
328 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
329 for (last = pos + size; pos < last; pos += 4) {
332 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
334 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
338 WREG32_NO_KIQ(mmMM_DATA, *data++);
340 *data++ = RREG32_NO_KIQ(mmMM_DATA);
343 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
348 * amdgpu_device_aper_access - access vram by vram aperature
350 * @adev: amdgpu_device pointer
351 * @pos: offset of the buffer in vram
352 * @buf: virtual address of the buffer in system memory
353 * @size: read/write size, sizeof(@buf) must > @size
354 * @write: true - write to vram, otherwise - read from vram
356 * The return value means how many bytes have been transferred.
358 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
359 void *buf, size_t size, bool write)
366 if (!adev->mman.aper_base_kaddr)
369 last = min(pos + size, adev->gmc.visible_vram_size);
371 addr = adev->mman.aper_base_kaddr + pos;
375 memcpy_toio(addr, buf, count);
376 /* Make sure HDP write cache flush happens without any reordering
377 * after the system memory contents are sent over PCIe device
380 amdgpu_device_flush_hdp(adev, NULL);
382 amdgpu_device_invalidate_hdp(adev, NULL);
383 /* Make sure HDP read cache is invalidated before issuing a read
387 memcpy_fromio(buf, addr, count);
399 * amdgpu_device_vram_access - read/write a buffer in vram
401 * @adev: amdgpu_device pointer
402 * @pos: offset of the buffer in vram
403 * @buf: virtual address of the buffer in system memory
404 * @size: read/write size, sizeof(@buf) must > @size
405 * @write: true - write to vram, otherwise - read from vram
407 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
408 void *buf, size_t size, bool write)
412 /* try to using vram apreature to access vram first */
413 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
416 /* using MM to access rest vram */
419 amdgpu_device_mm_access(adev, pos, buf, size, write);
424 * register access helper functions.
427 /* Check if hw access should be skipped because of hotplug or device error */
428 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
430 if (adev->no_hw_access)
433 #ifdef CONFIG_LOCKDEP
435 * This is a bit complicated to understand, so worth a comment. What we assert
436 * here is that the GPU reset is not running on another thread in parallel.
438 * For this we trylock the read side of the reset semaphore, if that succeeds
439 * we know that the reset is not running in paralell.
441 * If the trylock fails we assert that we are either already holding the read
442 * side of the lock or are the reset thread itself and hold the write side of
446 if (down_read_trylock(&adev->reset_domain->sem))
447 up_read(&adev->reset_domain->sem);
449 lockdep_assert_held(&adev->reset_domain->sem);
456 * amdgpu_device_rreg - read a memory mapped IO or indirect register
458 * @adev: amdgpu_device pointer
459 * @reg: dword aligned register offset
460 * @acc_flags: access flags which require special behavior
462 * Returns the 32 bit value from the offset specified.
464 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
465 uint32_t reg, uint32_t acc_flags)
469 if (amdgpu_device_skip_hw_access(adev))
472 if ((reg * 4) < adev->rmmio_size) {
473 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
474 amdgpu_sriov_runtime(adev) &&
475 down_read_trylock(&adev->reset_domain->sem)) {
476 ret = amdgpu_kiq_rreg(adev, reg, 0);
477 up_read(&adev->reset_domain->sem);
479 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
482 ret = adev->pcie_rreg(adev, reg * 4);
485 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
491 * MMIO register read with bytes helper functions
492 * @offset:bytes offset from MMIO start
496 * amdgpu_mm_rreg8 - read a memory mapped IO register
498 * @adev: amdgpu_device pointer
499 * @offset: byte aligned register offset
501 * Returns the 8 bit value from the offset specified.
503 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
505 if (amdgpu_device_skip_hw_access(adev))
508 if (offset < adev->rmmio_size)
509 return (readb(adev->rmmio + offset));
515 * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC
517 * @adev: amdgpu_device pointer
518 * @reg: dword aligned register offset
519 * @acc_flags: access flags which require special behavior
520 * @xcc_id: xcc accelerated compute core id
522 * Returns the 32 bit value from the offset specified.
524 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
525 uint32_t reg, uint32_t acc_flags,
528 uint32_t ret, rlcg_flag;
530 if (amdgpu_device_skip_hw_access(adev))
533 if ((reg * 4) < adev->rmmio_size) {
534 if (amdgpu_sriov_vf(adev) &&
535 !amdgpu_sriov_runtime(adev) &&
536 adev->gfx.rlc.rlcg_reg_access_supported &&
537 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
540 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, xcc_id);
541 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
542 amdgpu_sriov_runtime(adev) &&
543 down_read_trylock(&adev->reset_domain->sem)) {
544 ret = amdgpu_kiq_rreg(adev, reg, xcc_id);
545 up_read(&adev->reset_domain->sem);
547 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
550 ret = adev->pcie_rreg(adev, reg * 4);
557 * MMIO register write with bytes helper functions
558 * @offset:bytes offset from MMIO start
559 * @value: the value want to be written to the register
563 * amdgpu_mm_wreg8 - read a memory mapped IO register
565 * @adev: amdgpu_device pointer
566 * @offset: byte aligned register offset
567 * @value: 8 bit value to write
569 * Writes the value specified to the offset specified.
571 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
573 if (amdgpu_device_skip_hw_access(adev))
576 if (offset < adev->rmmio_size)
577 writeb(value, adev->rmmio + offset);
583 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
585 * @adev: amdgpu_device pointer
586 * @reg: dword aligned register offset
587 * @v: 32 bit value to write to the register
588 * @acc_flags: access flags which require special behavior
590 * Writes the value specified to the offset specified.
592 void amdgpu_device_wreg(struct amdgpu_device *adev,
593 uint32_t reg, uint32_t v,
596 if (amdgpu_device_skip_hw_access(adev))
599 if ((reg * 4) < adev->rmmio_size) {
600 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
601 amdgpu_sriov_runtime(adev) &&
602 down_read_trylock(&adev->reset_domain->sem)) {
603 amdgpu_kiq_wreg(adev, reg, v, 0);
604 up_read(&adev->reset_domain->sem);
606 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
609 adev->pcie_wreg(adev, reg * 4, v);
612 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
616 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
618 * @adev: amdgpu_device pointer
619 * @reg: mmio/rlc register
621 * @xcc_id: xcc accelerated compute core id
623 * this function is invoked only for the debugfs register access
625 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
626 uint32_t reg, uint32_t v,
629 if (amdgpu_device_skip_hw_access(adev))
632 if (amdgpu_sriov_fullaccess(adev) &&
633 adev->gfx.rlc.funcs &&
634 adev->gfx.rlc.funcs->is_rlcg_access_range) {
635 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
636 return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
637 } else if ((reg * 4) >= adev->rmmio_size) {
638 adev->pcie_wreg(adev, reg * 4, v);
640 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
645 * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC
647 * @adev: amdgpu_device pointer
648 * @reg: dword aligned register offset
649 * @v: 32 bit value to write to the register
650 * @acc_flags: access flags which require special behavior
651 * @xcc_id: xcc accelerated compute core id
653 * Writes the value specified to the offset specified.
655 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
656 uint32_t reg, uint32_t v,
657 uint32_t acc_flags, uint32_t xcc_id)
661 if (amdgpu_device_skip_hw_access(adev))
664 if ((reg * 4) < adev->rmmio_size) {
665 if (amdgpu_sriov_vf(adev) &&
666 !amdgpu_sriov_runtime(adev) &&
667 adev->gfx.rlc.rlcg_reg_access_supported &&
668 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
671 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, xcc_id);
672 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
673 amdgpu_sriov_runtime(adev) &&
674 down_read_trylock(&adev->reset_domain->sem)) {
675 amdgpu_kiq_wreg(adev, reg, v, xcc_id);
676 up_read(&adev->reset_domain->sem);
678 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
681 adev->pcie_wreg(adev, reg * 4, v);
686 * amdgpu_device_indirect_rreg - read an indirect register
688 * @adev: amdgpu_device pointer
689 * @reg_addr: indirect register address to read from
691 * Returns the value of indirect register @reg_addr
693 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
696 unsigned long flags, pcie_index, pcie_data;
697 void __iomem *pcie_index_offset;
698 void __iomem *pcie_data_offset;
701 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
702 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
704 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
705 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
706 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
708 writel(reg_addr, pcie_index_offset);
709 readl(pcie_index_offset);
710 r = readl(pcie_data_offset);
711 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
716 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
719 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
721 void __iomem *pcie_index_offset;
722 void __iomem *pcie_index_hi_offset;
723 void __iomem *pcie_data_offset;
725 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
726 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
727 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
728 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
732 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
733 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
734 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
735 if (pcie_index_hi != 0)
736 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
739 writel(reg_addr, pcie_index_offset);
740 readl(pcie_index_offset);
741 if (pcie_index_hi != 0) {
742 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
743 readl(pcie_index_hi_offset);
745 r = readl(pcie_data_offset);
747 /* clear the high bits */
748 if (pcie_index_hi != 0) {
749 writel(0, pcie_index_hi_offset);
750 readl(pcie_index_hi_offset);
753 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
759 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
761 * @adev: amdgpu_device pointer
762 * @reg_addr: indirect register address to read from
764 * Returns the value of indirect register @reg_addr
766 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
769 unsigned long flags, pcie_index, pcie_data;
770 void __iomem *pcie_index_offset;
771 void __iomem *pcie_data_offset;
774 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
775 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
777 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
778 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
779 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
781 /* read low 32 bits */
782 writel(reg_addr, pcie_index_offset);
783 readl(pcie_index_offset);
784 r = readl(pcie_data_offset);
785 /* read high 32 bits */
786 writel(reg_addr + 4, pcie_index_offset);
787 readl(pcie_index_offset);
788 r |= ((u64)readl(pcie_data_offset) << 32);
789 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
794 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
797 unsigned long flags, pcie_index, pcie_data;
798 unsigned long pcie_index_hi = 0;
799 void __iomem *pcie_index_offset;
800 void __iomem *pcie_index_hi_offset;
801 void __iomem *pcie_data_offset;
804 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
805 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
806 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
807 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
809 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
810 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
811 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
812 if (pcie_index_hi != 0)
813 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
816 /* read low 32 bits */
817 writel(reg_addr, pcie_index_offset);
818 readl(pcie_index_offset);
819 if (pcie_index_hi != 0) {
820 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
821 readl(pcie_index_hi_offset);
823 r = readl(pcie_data_offset);
824 /* read high 32 bits */
825 writel(reg_addr + 4, pcie_index_offset);
826 readl(pcie_index_offset);
827 if (pcie_index_hi != 0) {
828 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
829 readl(pcie_index_hi_offset);
831 r |= ((u64)readl(pcie_data_offset) << 32);
833 /* clear the high bits */
834 if (pcie_index_hi != 0) {
835 writel(0, pcie_index_hi_offset);
836 readl(pcie_index_hi_offset);
839 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
845 * amdgpu_device_indirect_wreg - write an indirect register address
847 * @adev: amdgpu_device pointer
848 * @reg_addr: indirect register offset
849 * @reg_data: indirect register data
852 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
853 u32 reg_addr, u32 reg_data)
855 unsigned long flags, pcie_index, pcie_data;
856 void __iomem *pcie_index_offset;
857 void __iomem *pcie_data_offset;
859 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
860 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
862 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
863 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
864 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
866 writel(reg_addr, pcie_index_offset);
867 readl(pcie_index_offset);
868 writel(reg_data, pcie_data_offset);
869 readl(pcie_data_offset);
870 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
873 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
874 u64 reg_addr, u32 reg_data)
876 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
877 void __iomem *pcie_index_offset;
878 void __iomem *pcie_index_hi_offset;
879 void __iomem *pcie_data_offset;
881 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
882 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
883 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
884 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
888 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
889 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
890 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
891 if (pcie_index_hi != 0)
892 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
895 writel(reg_addr, pcie_index_offset);
896 readl(pcie_index_offset);
897 if (pcie_index_hi != 0) {
898 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
899 readl(pcie_index_hi_offset);
901 writel(reg_data, pcie_data_offset);
902 readl(pcie_data_offset);
904 /* clear the high bits */
905 if (pcie_index_hi != 0) {
906 writel(0, pcie_index_hi_offset);
907 readl(pcie_index_hi_offset);
910 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
914 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
916 * @adev: amdgpu_device pointer
917 * @reg_addr: indirect register offset
918 * @reg_data: indirect register data
921 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
922 u32 reg_addr, u64 reg_data)
924 unsigned long flags, pcie_index, pcie_data;
925 void __iomem *pcie_index_offset;
926 void __iomem *pcie_data_offset;
928 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
929 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
931 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
932 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
933 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
935 /* write low 32 bits */
936 writel(reg_addr, pcie_index_offset);
937 readl(pcie_index_offset);
938 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
939 readl(pcie_data_offset);
940 /* write high 32 bits */
941 writel(reg_addr + 4, pcie_index_offset);
942 readl(pcie_index_offset);
943 writel((u32)(reg_data >> 32), pcie_data_offset);
944 readl(pcie_data_offset);
945 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
948 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
949 u64 reg_addr, u64 reg_data)
951 unsigned long flags, pcie_index, pcie_data;
952 unsigned long pcie_index_hi = 0;
953 void __iomem *pcie_index_offset;
954 void __iomem *pcie_index_hi_offset;
955 void __iomem *pcie_data_offset;
957 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
958 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
959 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
960 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
962 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
963 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
964 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
965 if (pcie_index_hi != 0)
966 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
969 /* write low 32 bits */
970 writel(reg_addr, pcie_index_offset);
971 readl(pcie_index_offset);
972 if (pcie_index_hi != 0) {
973 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
974 readl(pcie_index_hi_offset);
976 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
977 readl(pcie_data_offset);
978 /* write high 32 bits */
979 writel(reg_addr + 4, pcie_index_offset);
980 readl(pcie_index_offset);
981 if (pcie_index_hi != 0) {
982 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
983 readl(pcie_index_hi_offset);
985 writel((u32)(reg_data >> 32), pcie_data_offset);
986 readl(pcie_data_offset);
988 /* clear the high bits */
989 if (pcie_index_hi != 0) {
990 writel(0, pcie_index_hi_offset);
991 readl(pcie_index_hi_offset);
994 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
998 * amdgpu_device_get_rev_id - query device rev_id
1000 * @adev: amdgpu_device pointer
1002 * Return device rev_id
1004 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)
1006 return adev->nbio.funcs->get_rev_id(adev);
1010 * amdgpu_invalid_rreg - dummy reg read function
1012 * @adev: amdgpu_device pointer
1013 * @reg: offset of register
1015 * Dummy register read function. Used for register blocks
1016 * that certain asics don't have (all asics).
1017 * Returns the value in the register.
1019 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
1021 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
1026 static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
1028 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1034 * amdgpu_invalid_wreg - dummy reg write function
1036 * @adev: amdgpu_device pointer
1037 * @reg: offset of register
1038 * @v: value to write to the register
1040 * Dummy register read function. Used for register blocks
1041 * that certain asics don't have (all asics).
1043 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
1045 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
1050 static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
1052 DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",
1058 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
1060 * @adev: amdgpu_device pointer
1061 * @reg: offset of register
1063 * Dummy register read function. Used for register blocks
1064 * that certain asics don't have (all asics).
1065 * Returns the value in the register.
1067 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
1069 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
1074 static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)
1076 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1082 * amdgpu_invalid_wreg64 - dummy reg write function
1084 * @adev: amdgpu_device pointer
1085 * @reg: offset of register
1086 * @v: value to write to the register
1088 * Dummy register read function. Used for register blocks
1089 * that certain asics don't have (all asics).
1091 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
1093 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
1098 static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)
1100 DRM_ERROR("Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",
1106 * amdgpu_block_invalid_rreg - dummy reg read function
1108 * @adev: amdgpu_device pointer
1109 * @block: offset of instance
1110 * @reg: offset of register
1112 * Dummy register read function. Used for register blocks
1113 * that certain asics don't have (all asics).
1114 * Returns the value in the register.
1116 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
1117 uint32_t block, uint32_t reg)
1119 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
1126 * amdgpu_block_invalid_wreg - dummy reg write function
1128 * @adev: amdgpu_device pointer
1129 * @block: offset of instance
1130 * @reg: offset of register
1131 * @v: value to write to the register
1133 * Dummy register read function. Used for register blocks
1134 * that certain asics don't have (all asics).
1136 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
1138 uint32_t reg, uint32_t v)
1140 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
1146 * amdgpu_device_asic_init - Wrapper for atom asic_init
1148 * @adev: amdgpu_device pointer
1150 * Does any asic specific work and then calls atom asic init.
1152 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
1156 amdgpu_asic_pre_asic_init(adev);
1158 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1159 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) {
1160 amdgpu_psp_wait_for_bootloader(adev);
1161 ret = amdgpu_atomfirmware_asic_init(adev, true);
1162 /* TODO: check the return val and stop device initialization if boot fails */
1163 amdgpu_psp_query_boot_status(adev);
1166 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
1173 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
1175 * @adev: amdgpu_device pointer
1177 * Allocates a scratch page of VRAM for use by various things in the
1180 static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
1182 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
1183 AMDGPU_GEM_DOMAIN_VRAM |
1184 AMDGPU_GEM_DOMAIN_GTT,
1185 &adev->mem_scratch.robj,
1186 &adev->mem_scratch.gpu_addr,
1187 (void **)&adev->mem_scratch.ptr);
1191 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
1193 * @adev: amdgpu_device pointer
1195 * Frees the VRAM scratch page.
1197 static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
1199 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
1203 * amdgpu_device_program_register_sequence - program an array of registers.
1205 * @adev: amdgpu_device pointer
1206 * @registers: pointer to the register array
1207 * @array_size: size of the register array
1209 * Programs an array or registers with and or masks.
1210 * This is a helper for setting golden registers.
1212 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1213 const u32 *registers,
1214 const u32 array_size)
1216 u32 tmp, reg, and_mask, or_mask;
1222 for (i = 0; i < array_size; i += 3) {
1223 reg = registers[i + 0];
1224 and_mask = registers[i + 1];
1225 or_mask = registers[i + 2];
1227 if (and_mask == 0xffffffff) {
1232 if (adev->family >= AMDGPU_FAMILY_AI)
1233 tmp |= (or_mask & and_mask);
1242 * amdgpu_device_pci_config_reset - reset the GPU
1244 * @adev: amdgpu_device pointer
1246 * Resets the GPU using the pci config reset sequence.
1247 * Only applicable to asics prior to vega10.
1249 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1251 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1255 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1257 * @adev: amdgpu_device pointer
1259 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1261 int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1263 return pci_reset_function(adev->pdev);
1267 * amdgpu_device_wb_*()
1268 * Writeback is the method by which the GPU updates special pages in memory
1269 * with the status of certain GPU events (fences, ring pointers,etc.).
1273 * amdgpu_device_wb_fini - Disable Writeback and free memory
1275 * @adev: amdgpu_device pointer
1277 * Disables Writeback and frees the Writeback memory (all asics).
1278 * Used at driver shutdown.
1280 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1282 if (adev->wb.wb_obj) {
1283 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1285 (void **)&adev->wb.wb);
1286 adev->wb.wb_obj = NULL;
1291 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1293 * @adev: amdgpu_device pointer
1295 * Initializes writeback and allocates writeback memory (all asics).
1296 * Used at driver startup.
1297 * Returns 0 on success or an -error on failure.
1299 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1303 if (adev->wb.wb_obj == NULL) {
1304 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1305 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1306 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1307 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1308 (void **)&adev->wb.wb);
1310 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1314 adev->wb.num_wb = AMDGPU_MAX_WB;
1315 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1317 /* clear wb memory */
1318 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1325 * amdgpu_device_wb_get - Allocate a wb entry
1327 * @adev: amdgpu_device pointer
1330 * Allocate a wb slot for use by the driver (all asics).
1331 * Returns 0 on success or -EINVAL on failure.
1333 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1335 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1337 if (offset < adev->wb.num_wb) {
1338 __set_bit(offset, adev->wb.used);
1339 *wb = offset << 3; /* convert to dw offset */
1347 * amdgpu_device_wb_free - Free a wb entry
1349 * @adev: amdgpu_device pointer
1352 * Free a wb slot allocated for use by the driver (all asics)
1354 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1357 if (wb < adev->wb.num_wb)
1358 __clear_bit(wb, adev->wb.used);
1362 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1364 * @adev: amdgpu_device pointer
1366 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1367 * to fail, but if any of the BARs is not accessible after the size we abort
1368 * driver loading by returning -ENODEV.
1370 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1372 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1373 struct pci_bus *root;
1374 struct resource *res;
1379 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
1383 if (amdgpu_sriov_vf(adev))
1386 /* skip if the bios has already enabled large BAR */
1387 if (adev->gmc.real_vram_size &&
1388 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1391 /* Check if the root BUS has 64bit memory resources */
1392 root = adev->pdev->bus;
1393 while (root->parent)
1394 root = root->parent;
1396 pci_bus_for_each_resource(root, res, i) {
1397 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1398 res->start > 0x100000000ull)
1402 /* Trying to resize is pointless without a root hub window above 4GB */
1406 /* Limit the BAR size to what is available */
1407 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1410 /* Disable memory decoding while we change the BAR addresses and size */
1411 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1412 pci_write_config_word(adev->pdev, PCI_COMMAND,
1413 cmd & ~PCI_COMMAND_MEMORY);
1415 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1416 amdgpu_doorbell_fini(adev);
1417 if (adev->asic_type >= CHIP_BONAIRE)
1418 pci_release_resource(adev->pdev, 2);
1420 pci_release_resource(adev->pdev, 0);
1422 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1424 DRM_INFO("Not enough PCI address space for a large BAR.");
1425 else if (r && r != -ENOTSUPP)
1426 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1428 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1430 /* When the doorbell or fb BAR isn't available we have no chance of
1433 r = amdgpu_doorbell_init(adev);
1434 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1437 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1442 static bool amdgpu_device_read_bios(struct amdgpu_device *adev)
1444 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
1451 * GPU helpers function.
1454 * amdgpu_device_need_post - check if the hw need post or not
1456 * @adev: amdgpu_device pointer
1458 * Check if the asic has been initialized (all asics) at driver startup
1459 * or post is needed if hw reset is performed.
1460 * Returns true if need or false if not.
1462 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1466 if (amdgpu_sriov_vf(adev))
1469 if (!amdgpu_device_read_bios(adev))
1472 if (amdgpu_passthrough(adev)) {
1473 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1474 * some old smc fw still need driver do vPost otherwise gpu hang, while
1475 * those smc fw version above 22.15 doesn't have this flaw, so we force
1476 * vpost executed for smc version below 22.15
1478 if (adev->asic_type == CHIP_FIJI) {
1482 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1483 /* force vPost if error occured */
1487 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1488 if (fw_ver < 0x00160e00)
1493 /* Don't post if we need to reset whole hive on init */
1494 if (adev->gmc.xgmi.pending_reset)
1497 if (adev->has_hw_reset) {
1498 adev->has_hw_reset = false;
1502 /* bios scratch used on CIK+ */
1503 if (adev->asic_type >= CHIP_BONAIRE)
1504 return amdgpu_atombios_scratch_need_asic_init(adev);
1506 /* check MEM_SIZE for older asics */
1507 reg = amdgpu_asic_get_config_memsize(adev);
1509 if ((reg != 0) && (reg != 0xffffffff))
1516 * Check whether seamless boot is supported.
1518 * So far we only support seamless boot on DCE 3.0 or later.
1519 * If users report that it works on older ASICS as well, we may
1522 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)
1524 switch (amdgpu_seamless) {
1532 DRM_ERROR("Invalid value for amdgpu.seamless: %d\n",
1537 if (!(adev->flags & AMD_IS_APU))
1540 if (adev->mman.keep_stolen_vga_memory)
1543 return adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0);
1547 * Intel hosts such as Rocket Lake, Alder Lake, Raptor Lake and Sapphire Rapids
1548 * don't support dynamic speed switching. Until we have confirmation from Intel
1549 * that a specific host supports it, it's safer that we keep it disabled for all.
1551 * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
1552 * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
1554 static bool amdgpu_device_pcie_dynamic_switching_supported(void)
1556 #if IS_ENABLED(CONFIG_X86)
1557 struct cpuinfo_x86 *c = &cpu_data(0);
1559 if (c->x86_vendor == X86_VENDOR_INTEL)
1566 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1568 * @adev: amdgpu_device pointer
1570 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1571 * be set for this device.
1573 * Returns true if it should be used or false if not.
1575 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1577 switch (amdgpu_aspm) {
1587 if (adev->flags & AMD_IS_APU)
1589 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK))
1591 return pcie_aspm_enabled(adev->pdev);
1594 /* if we get transitioned to only one device, take VGA back */
1596 * amdgpu_device_vga_set_decode - enable/disable vga decode
1598 * @pdev: PCI device pointer
1599 * @state: enable/disable vga decode
1601 * Enable/disable vga decode (all asics).
1602 * Returns VGA resource flags.
1604 static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1607 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1609 amdgpu_asic_set_vga_state(adev, state);
1611 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1612 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1614 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1618 * amdgpu_device_check_block_size - validate the vm block size
1620 * @adev: amdgpu_device pointer
1622 * Validates the vm block size specified via module parameter.
1623 * The vm block size defines number of bits in page table versus page directory,
1624 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1625 * page table and the remaining bits are in the page directory.
1627 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1629 /* defines number of bits in page table versus page directory,
1630 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1631 * page table and the remaining bits are in the page directory
1633 if (amdgpu_vm_block_size == -1)
1636 if (amdgpu_vm_block_size < 9) {
1637 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1638 amdgpu_vm_block_size);
1639 amdgpu_vm_block_size = -1;
1644 * amdgpu_device_check_vm_size - validate the vm size
1646 * @adev: amdgpu_device pointer
1648 * Validates the vm size in GB specified via module parameter.
1649 * The VM size is the size of the GPU virtual memory space in GB.
1651 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1653 /* no need to check the default value */
1654 if (amdgpu_vm_size == -1)
1657 if (amdgpu_vm_size < 1) {
1658 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1660 amdgpu_vm_size = -1;
1664 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1667 bool is_os_64 = (sizeof(void *) == 8);
1668 uint64_t total_memory;
1669 uint64_t dram_size_seven_GB = 0x1B8000000;
1670 uint64_t dram_size_three_GB = 0xB8000000;
1672 if (amdgpu_smu_memory_pool_size == 0)
1676 DRM_WARN("Not 64-bit OS, feature not supported\n");
1680 total_memory = (uint64_t)si.totalram * si.mem_unit;
1682 if ((amdgpu_smu_memory_pool_size == 1) ||
1683 (amdgpu_smu_memory_pool_size == 2)) {
1684 if (total_memory < dram_size_three_GB)
1686 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1687 (amdgpu_smu_memory_pool_size == 8)) {
1688 if (total_memory < dram_size_seven_GB)
1691 DRM_WARN("Smu memory pool size not supported\n");
1694 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1699 DRM_WARN("No enough system memory\n");
1701 adev->pm.smu_prv_buffer_size = 0;
1704 static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1706 if (!(adev->flags & AMD_IS_APU) ||
1707 adev->asic_type < CHIP_RAVEN)
1710 switch (adev->asic_type) {
1712 if (adev->pdev->device == 0x15dd)
1713 adev->apu_flags |= AMD_APU_IS_RAVEN;
1714 if (adev->pdev->device == 0x15d8)
1715 adev->apu_flags |= AMD_APU_IS_PICASSO;
1718 if ((adev->pdev->device == 0x1636) ||
1719 (adev->pdev->device == 0x164c))
1720 adev->apu_flags |= AMD_APU_IS_RENOIR;
1722 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1725 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1727 case CHIP_YELLOW_CARP:
1729 case CHIP_CYAN_SKILLFISH:
1730 if ((adev->pdev->device == 0x13FE) ||
1731 (adev->pdev->device == 0x143F))
1732 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1742 * amdgpu_device_check_arguments - validate module params
1744 * @adev: amdgpu_device pointer
1746 * Validates certain module parameters and updates
1747 * the associated values used by the driver (all asics).
1749 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1751 if (amdgpu_sched_jobs < 4) {
1752 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1754 amdgpu_sched_jobs = 4;
1755 } else if (!is_power_of_2(amdgpu_sched_jobs)) {
1756 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1758 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1761 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1762 /* gart size must be greater or equal to 32M */
1763 dev_warn(adev->dev, "gart size (%d) too small\n",
1765 amdgpu_gart_size = -1;
1768 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1769 /* gtt size must be greater or equal to 32M */
1770 dev_warn(adev->dev, "gtt size (%d) too small\n",
1772 amdgpu_gtt_size = -1;
1775 /* valid range is between 4 and 9 inclusive */
1776 if (amdgpu_vm_fragment_size != -1 &&
1777 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1778 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1779 amdgpu_vm_fragment_size = -1;
1782 if (amdgpu_sched_hw_submission < 2) {
1783 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1784 amdgpu_sched_hw_submission);
1785 amdgpu_sched_hw_submission = 2;
1786 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1787 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1788 amdgpu_sched_hw_submission);
1789 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1792 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1793 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1794 amdgpu_reset_method = -1;
1797 amdgpu_device_check_smu_prv_buffer_size(adev);
1799 amdgpu_device_check_vm_size(adev);
1801 amdgpu_device_check_block_size(adev);
1803 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1809 * amdgpu_switcheroo_set_state - set switcheroo state
1811 * @pdev: pci dev pointer
1812 * @state: vga_switcheroo state
1814 * Callback for the switcheroo driver. Suspends or resumes
1815 * the asics before or after it is powered up using ACPI methods.
1817 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1818 enum vga_switcheroo_state state)
1820 struct drm_device *dev = pci_get_drvdata(pdev);
1823 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1826 if (state == VGA_SWITCHEROO_ON) {
1827 pr_info("switched on\n");
1828 /* don't suspend or resume card normally */
1829 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1831 pci_set_power_state(pdev, PCI_D0);
1832 amdgpu_device_load_pci_state(pdev);
1833 r = pci_enable_device(pdev);
1835 DRM_WARN("pci_enable_device failed (%d)\n", r);
1836 amdgpu_device_resume(dev, true);
1838 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1840 pr_info("switched off\n");
1841 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1842 amdgpu_device_prepare(dev);
1843 amdgpu_device_suspend(dev, true);
1844 amdgpu_device_cache_pci_state(pdev);
1845 /* Shut down the device */
1846 pci_disable_device(pdev);
1847 pci_set_power_state(pdev, PCI_D3cold);
1848 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1853 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1855 * @pdev: pci dev pointer
1857 * Callback for the switcheroo driver. Check of the switcheroo
1858 * state can be changed.
1859 * Returns true if the state can be changed, false if not.
1861 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1863 struct drm_device *dev = pci_get_drvdata(pdev);
1866 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1867 * locking inversion with the driver load path. And the access here is
1868 * completely racy anyway. So don't bother with locking for now.
1870 return atomic_read(&dev->open_count) == 0;
1873 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1874 .set_gpu_state = amdgpu_switcheroo_set_state,
1876 .can_switch = amdgpu_switcheroo_can_switch,
1880 * amdgpu_device_ip_set_clockgating_state - set the CG state
1882 * @dev: amdgpu_device pointer
1883 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1884 * @state: clockgating state (gate or ungate)
1886 * Sets the requested clockgating state for all instances of
1887 * the hardware IP specified.
1888 * Returns the error code from the last instance.
1890 int amdgpu_device_ip_set_clockgating_state(void *dev,
1891 enum amd_ip_block_type block_type,
1892 enum amd_clockgating_state state)
1894 struct amdgpu_device *adev = dev;
1897 for (i = 0; i < adev->num_ip_blocks; i++) {
1898 if (!adev->ip_blocks[i].status.valid)
1900 if (adev->ip_blocks[i].version->type != block_type)
1902 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1904 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1905 (void *)adev, state);
1907 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1908 adev->ip_blocks[i].version->funcs->name, r);
1914 * amdgpu_device_ip_set_powergating_state - set the PG state
1916 * @dev: amdgpu_device pointer
1917 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1918 * @state: powergating state (gate or ungate)
1920 * Sets the requested powergating state for all instances of
1921 * the hardware IP specified.
1922 * Returns the error code from the last instance.
1924 int amdgpu_device_ip_set_powergating_state(void *dev,
1925 enum amd_ip_block_type block_type,
1926 enum amd_powergating_state state)
1928 struct amdgpu_device *adev = dev;
1931 for (i = 0; i < adev->num_ip_blocks; i++) {
1932 if (!adev->ip_blocks[i].status.valid)
1934 if (adev->ip_blocks[i].version->type != block_type)
1936 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1938 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1939 (void *)adev, state);
1941 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1942 adev->ip_blocks[i].version->funcs->name, r);
1948 * amdgpu_device_ip_get_clockgating_state - get the CG state
1950 * @adev: amdgpu_device pointer
1951 * @flags: clockgating feature flags
1953 * Walks the list of IPs on the device and updates the clockgating
1954 * flags for each IP.
1955 * Updates @flags with the feature flags for each hardware IP where
1956 * clockgating is enabled.
1958 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1963 for (i = 0; i < adev->num_ip_blocks; i++) {
1964 if (!adev->ip_blocks[i].status.valid)
1966 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1967 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1972 * amdgpu_device_ip_wait_for_idle - wait for idle
1974 * @adev: amdgpu_device pointer
1975 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1977 * Waits for the request hardware IP to be idle.
1978 * Returns 0 for success or a negative error code on failure.
1980 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1981 enum amd_ip_block_type block_type)
1985 for (i = 0; i < adev->num_ip_blocks; i++) {
1986 if (!adev->ip_blocks[i].status.valid)
1988 if (adev->ip_blocks[i].version->type == block_type) {
1989 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
2000 * amdgpu_device_ip_is_idle - is the hardware IP idle
2002 * @adev: amdgpu_device pointer
2003 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2005 * Check if the hardware IP is idle or not.
2006 * Returns true if it the IP is idle, false if not.
2008 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
2009 enum amd_ip_block_type block_type)
2013 for (i = 0; i < adev->num_ip_blocks; i++) {
2014 if (!adev->ip_blocks[i].status.valid)
2016 if (adev->ip_blocks[i].version->type == block_type)
2017 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
2024 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
2026 * @adev: amdgpu_device pointer
2027 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
2029 * Returns a pointer to the hardware IP block structure
2030 * if it exists for the asic, otherwise NULL.
2032 struct amdgpu_ip_block *
2033 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
2034 enum amd_ip_block_type type)
2038 for (i = 0; i < adev->num_ip_blocks; i++)
2039 if (adev->ip_blocks[i].version->type == type)
2040 return &adev->ip_blocks[i];
2046 * amdgpu_device_ip_block_version_cmp
2048 * @adev: amdgpu_device pointer
2049 * @type: enum amd_ip_block_type
2050 * @major: major version
2051 * @minor: minor version
2053 * return 0 if equal or greater
2054 * return 1 if smaller or the ip_block doesn't exist
2056 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
2057 enum amd_ip_block_type type,
2058 u32 major, u32 minor)
2060 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
2062 if (ip_block && ((ip_block->version->major > major) ||
2063 ((ip_block->version->major == major) &&
2064 (ip_block->version->minor >= minor))))
2071 * amdgpu_device_ip_block_add
2073 * @adev: amdgpu_device pointer
2074 * @ip_block_version: pointer to the IP to add
2076 * Adds the IP block driver information to the collection of IPs
2079 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
2080 const struct amdgpu_ip_block_version *ip_block_version)
2082 if (!ip_block_version)
2085 switch (ip_block_version->type) {
2086 case AMD_IP_BLOCK_TYPE_VCN:
2087 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
2090 case AMD_IP_BLOCK_TYPE_JPEG:
2091 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
2098 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
2099 ip_block_version->funcs->name);
2101 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
2107 * amdgpu_device_enable_virtual_display - enable virtual display feature
2109 * @adev: amdgpu_device pointer
2111 * Enabled the virtual display feature if the user has enabled it via
2112 * the module parameter virtual_display. This feature provides a virtual
2113 * display hardware on headless boards or in virtualized environments.
2114 * This function parses and validates the configuration string specified by
2115 * the user and configues the virtual display configuration (number of
2116 * virtual connectors, crtcs, etc.) specified.
2118 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
2120 adev->enable_virtual_display = false;
2122 if (amdgpu_virtual_display) {
2123 const char *pci_address_name = pci_name(adev->pdev);
2124 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
2126 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
2127 pciaddstr_tmp = pciaddstr;
2128 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
2129 pciaddname = strsep(&pciaddname_tmp, ",");
2130 if (!strcmp("all", pciaddname)
2131 || !strcmp(pci_address_name, pciaddname)) {
2135 adev->enable_virtual_display = true;
2138 res = kstrtol(pciaddname_tmp, 10,
2146 adev->mode_info.num_crtc = num_crtc;
2148 adev->mode_info.num_crtc = 1;
2154 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
2155 amdgpu_virtual_display, pci_address_name,
2156 adev->enable_virtual_display, adev->mode_info.num_crtc);
2162 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
2164 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
2165 adev->mode_info.num_crtc = 1;
2166 adev->enable_virtual_display = true;
2167 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
2168 adev->enable_virtual_display, adev->mode_info.num_crtc);
2173 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
2175 * @adev: amdgpu_device pointer
2177 * Parses the asic configuration parameters specified in the gpu info
2178 * firmware and makes them availale to the driver for use in configuring
2180 * Returns 0 on success, -EINVAL on failure.
2182 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
2184 const char *chip_name;
2187 const struct gpu_info_firmware_header_v1_0 *hdr;
2189 adev->firmware.gpu_info_fw = NULL;
2191 if (adev->mman.discovery_bin)
2194 switch (adev->asic_type) {
2198 chip_name = "vega10";
2201 chip_name = "vega12";
2204 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
2205 chip_name = "raven2";
2206 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
2207 chip_name = "picasso";
2209 chip_name = "raven";
2212 chip_name = "arcturus";
2215 chip_name = "navi12";
2219 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
2220 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name);
2223 "Failed to get gpu_info firmware \"%s\"\n",
2228 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2229 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2231 switch (hdr->version_major) {
2234 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2235 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2236 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2239 * Should be droped when DAL no longer needs it.
2241 if (adev->asic_type == CHIP_NAVI12)
2242 goto parse_soc_bounding_box;
2244 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2245 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2246 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2247 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2248 adev->gfx.config.max_texture_channel_caches =
2249 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2250 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2251 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2252 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2253 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2254 adev->gfx.config.double_offchip_lds_buf =
2255 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2256 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2257 adev->gfx.cu_info.max_waves_per_simd =
2258 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2259 adev->gfx.cu_info.max_scratch_slots_per_cu =
2260 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2261 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2262 if (hdr->version_minor >= 1) {
2263 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2264 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2265 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2266 adev->gfx.config.num_sc_per_sh =
2267 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2268 adev->gfx.config.num_packer_per_sc =
2269 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2272 parse_soc_bounding_box:
2274 * soc bounding box info is not integrated in disocovery table,
2275 * we always need to parse it from gpu info firmware if needed.
2277 if (hdr->version_minor == 2) {
2278 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2279 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2280 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2281 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2287 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2296 * amdgpu_device_ip_early_init - run early init for hardware IPs
2298 * @adev: amdgpu_device pointer
2300 * Early initialization pass for hardware IPs. The hardware IPs that make
2301 * up each asic are discovered each IP's early_init callback is run. This
2302 * is the first stage in initializing the asic.
2303 * Returns 0 on success, negative error code on failure.
2305 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2307 struct pci_dev *parent;
2311 amdgpu_device_enable_virtual_display(adev);
2313 if (amdgpu_sriov_vf(adev)) {
2314 r = amdgpu_virt_request_full_gpu(adev, true);
2319 switch (adev->asic_type) {
2320 #ifdef CONFIG_DRM_AMDGPU_SI
2326 adev->family = AMDGPU_FAMILY_SI;
2327 r = si_set_ip_blocks(adev);
2332 #ifdef CONFIG_DRM_AMDGPU_CIK
2338 if (adev->flags & AMD_IS_APU)
2339 adev->family = AMDGPU_FAMILY_KV;
2341 adev->family = AMDGPU_FAMILY_CI;
2343 r = cik_set_ip_blocks(adev);
2351 case CHIP_POLARIS10:
2352 case CHIP_POLARIS11:
2353 case CHIP_POLARIS12:
2357 if (adev->flags & AMD_IS_APU)
2358 adev->family = AMDGPU_FAMILY_CZ;
2360 adev->family = AMDGPU_FAMILY_VI;
2362 r = vi_set_ip_blocks(adev);
2367 r = amdgpu_discovery_set_ip_blocks(adev);
2373 if (amdgpu_has_atpx() &&
2374 (amdgpu_is_atpx_hybrid() ||
2375 amdgpu_has_atpx_dgpu_power_cntl()) &&
2376 ((adev->flags & AMD_IS_APU) == 0) &&
2377 !dev_is_removable(&adev->pdev->dev))
2378 adev->flags |= AMD_IS_PX;
2380 if (!(adev->flags & AMD_IS_APU)) {
2381 parent = pcie_find_root_port(adev->pdev);
2382 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2386 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2387 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2388 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2389 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2390 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2391 if (!amdgpu_device_pcie_dynamic_switching_supported())
2392 adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;
2395 for (i = 0; i < adev->num_ip_blocks; i++) {
2396 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2397 DRM_WARN("disabled ip block: %d <%s>\n",
2398 i, adev->ip_blocks[i].version->funcs->name);
2399 adev->ip_blocks[i].status.valid = false;
2401 if (adev->ip_blocks[i].version->funcs->early_init) {
2402 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2404 adev->ip_blocks[i].status.valid = false;
2406 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2407 adev->ip_blocks[i].version->funcs->name, r);
2410 adev->ip_blocks[i].status.valid = true;
2413 adev->ip_blocks[i].status.valid = true;
2416 /* get the vbios after the asic_funcs are set up */
2417 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2418 r = amdgpu_device_parse_gpu_info_fw(adev);
2423 if (amdgpu_device_read_bios(adev)) {
2424 if (!amdgpu_get_bios(adev))
2427 r = amdgpu_atombios_init(adev);
2429 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2430 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2435 /*get pf2vf msg info at it's earliest time*/
2436 if (amdgpu_sriov_vf(adev))
2437 amdgpu_virt_init_data_exchange(adev);
2444 amdgpu_amdkfd_device_probe(adev);
2445 adev->cg_flags &= amdgpu_cg_mask;
2446 adev->pg_flags &= amdgpu_pg_mask;
2451 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2455 for (i = 0; i < adev->num_ip_blocks; i++) {
2456 if (!adev->ip_blocks[i].status.sw)
2458 if (adev->ip_blocks[i].status.hw)
2460 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2461 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2462 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2463 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2465 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2466 adev->ip_blocks[i].version->funcs->name, r);
2469 adev->ip_blocks[i].status.hw = true;
2476 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2480 for (i = 0; i < adev->num_ip_blocks; i++) {
2481 if (!adev->ip_blocks[i].status.sw)
2483 if (adev->ip_blocks[i].status.hw)
2485 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2487 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2488 adev->ip_blocks[i].version->funcs->name, r);
2491 adev->ip_blocks[i].status.hw = true;
2497 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2501 uint32_t smu_version;
2503 if (adev->asic_type >= CHIP_VEGA10) {
2504 for (i = 0; i < adev->num_ip_blocks; i++) {
2505 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2508 if (!adev->ip_blocks[i].status.sw)
2511 /* no need to do the fw loading again if already done*/
2512 if (adev->ip_blocks[i].status.hw == true)
2515 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2516 r = adev->ip_blocks[i].version->funcs->resume(adev);
2518 DRM_ERROR("resume of IP block <%s> failed %d\n",
2519 adev->ip_blocks[i].version->funcs->name, r);
2523 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2525 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2526 adev->ip_blocks[i].version->funcs->name, r);
2531 adev->ip_blocks[i].status.hw = true;
2536 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2537 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2542 static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2547 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2548 struct amdgpu_ring *ring = adev->rings[i];
2550 /* No need to setup the GPU scheduler for rings that don't need it */
2551 if (!ring || ring->no_scheduler)
2554 switch (ring->funcs->type) {
2555 case AMDGPU_RING_TYPE_GFX:
2556 timeout = adev->gfx_timeout;
2558 case AMDGPU_RING_TYPE_COMPUTE:
2559 timeout = adev->compute_timeout;
2561 case AMDGPU_RING_TYPE_SDMA:
2562 timeout = adev->sdma_timeout;
2565 timeout = adev->video_timeout;
2569 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
2570 DRM_SCHED_PRIORITY_COUNT,
2571 ring->num_hw_submission, 0,
2572 timeout, adev->reset_domain->wq,
2573 ring->sched_score, ring->name,
2576 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2580 r = amdgpu_uvd_entity_init(adev, ring);
2582 DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n",
2586 r = amdgpu_vce_entity_init(adev, ring);
2588 DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n",
2594 amdgpu_xcp_update_partition_sched_list(adev);
2601 * amdgpu_device_ip_init - run init for hardware IPs
2603 * @adev: amdgpu_device pointer
2605 * Main initialization pass for hardware IPs. The list of all the hardware
2606 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2607 * are run. sw_init initializes the software state associated with each IP
2608 * and hw_init initializes the hardware associated with each IP.
2609 * Returns 0 on success, negative error code on failure.
2611 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2615 r = amdgpu_ras_init(adev);
2619 for (i = 0; i < adev->num_ip_blocks; i++) {
2620 if (!adev->ip_blocks[i].status.valid)
2622 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2624 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2625 adev->ip_blocks[i].version->funcs->name, r);
2628 adev->ip_blocks[i].status.sw = true;
2630 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2631 /* need to do common hw init early so everything is set up for gmc */
2632 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2634 DRM_ERROR("hw_init %d failed %d\n", i, r);
2637 adev->ip_blocks[i].status.hw = true;
2638 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2639 /* need to do gmc hw init early so we can allocate gpu mem */
2640 /* Try to reserve bad pages early */
2641 if (amdgpu_sriov_vf(adev))
2642 amdgpu_virt_exchange_data(adev);
2644 r = amdgpu_device_mem_scratch_init(adev);
2646 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2649 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2651 DRM_ERROR("hw_init %d failed %d\n", i, r);
2654 r = amdgpu_device_wb_init(adev);
2656 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2659 adev->ip_blocks[i].status.hw = true;
2661 /* right after GMC hw init, we create CSA */
2662 if (adev->gfx.mcbp) {
2663 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2664 AMDGPU_GEM_DOMAIN_VRAM |
2665 AMDGPU_GEM_DOMAIN_GTT,
2668 DRM_ERROR("allocate CSA failed %d\n", r);
2675 if (amdgpu_sriov_vf(adev))
2676 amdgpu_virt_init_data_exchange(adev);
2678 r = amdgpu_ib_pool_init(adev);
2680 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2681 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2685 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2689 r = amdgpu_device_ip_hw_init_phase1(adev);
2693 r = amdgpu_device_fw_loading(adev);
2697 r = amdgpu_device_ip_hw_init_phase2(adev);
2702 * retired pages will be loaded from eeprom and reserved here,
2703 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2704 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2705 * for I2C communication which only true at this point.
2707 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2708 * failure from bad gpu situation and stop amdgpu init process
2709 * accordingly. For other failed cases, it will still release all
2710 * the resource and print error message, rather than returning one
2711 * negative value to upper level.
2713 * Note: theoretically, this should be called before all vram allocations
2714 * to protect retired page from abusing
2716 r = amdgpu_ras_recovery_init(adev);
2721 * In case of XGMI grab extra reference for reset domain for this device
2723 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2724 if (amdgpu_xgmi_add_device(adev) == 0) {
2725 if (!amdgpu_sriov_vf(adev)) {
2726 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2728 if (WARN_ON(!hive)) {
2733 if (!hive->reset_domain ||
2734 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2736 amdgpu_put_xgmi_hive(hive);
2740 /* Drop the early temporary reset domain we created for device */
2741 amdgpu_reset_put_reset_domain(adev->reset_domain);
2742 adev->reset_domain = hive->reset_domain;
2743 amdgpu_put_xgmi_hive(hive);
2748 r = amdgpu_device_init_schedulers(adev);
2752 if (adev->mman.buffer_funcs_ring->sched.ready)
2753 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2755 /* Don't init kfd if whole hive need to be reset during init */
2756 if (!adev->gmc.xgmi.pending_reset) {
2757 kgd2kfd_init_zone_device(adev);
2758 amdgpu_amdkfd_device_init(adev);
2761 amdgpu_fru_get_product_info(adev);
2769 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2771 * @adev: amdgpu_device pointer
2773 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2774 * this function before a GPU reset. If the value is retained after a
2775 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2777 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2779 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2783 * amdgpu_device_check_vram_lost - check if vram is valid
2785 * @adev: amdgpu_device pointer
2787 * Checks the reset magic value written to the gart pointer in VRAM.
2788 * The driver calls this after a GPU reset to see if the contents of
2789 * VRAM is lost or now.
2790 * returns true if vram is lost, false if not.
2792 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2794 if (memcmp(adev->gart.ptr, adev->reset_magic,
2795 AMDGPU_RESET_MAGIC_NUM))
2798 if (!amdgpu_in_reset(adev))
2802 * For all ASICs with baco/mode1 reset, the VRAM is
2803 * always assumed to be lost.
2805 switch (amdgpu_asic_reset_method(adev)) {
2806 case AMD_RESET_METHOD_BACO:
2807 case AMD_RESET_METHOD_MODE1:
2815 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2817 * @adev: amdgpu_device pointer
2818 * @state: clockgating state (gate or ungate)
2820 * The list of all the hardware IPs that make up the asic is walked and the
2821 * set_clockgating_state callbacks are run.
2822 * Late initialization pass enabling clockgating for hardware IPs.
2823 * Fini or suspend, pass disabling clockgating for hardware IPs.
2824 * Returns 0 on success, negative error code on failure.
2827 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2828 enum amd_clockgating_state state)
2832 if (amdgpu_emu_mode == 1)
2835 for (j = 0; j < adev->num_ip_blocks; j++) {
2836 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2837 if (!adev->ip_blocks[i].status.late_initialized)
2839 /* skip CG for GFX, SDMA on S0ix */
2840 if (adev->in_s0ix &&
2841 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2842 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2844 /* skip CG for VCE/UVD, it's handled specially */
2845 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2846 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2847 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2848 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2849 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2850 /* enable clockgating to save power */
2851 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2854 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2855 adev->ip_blocks[i].version->funcs->name, r);
2864 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2865 enum amd_powergating_state state)
2869 if (amdgpu_emu_mode == 1)
2872 for (j = 0; j < adev->num_ip_blocks; j++) {
2873 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2874 if (!adev->ip_blocks[i].status.late_initialized)
2876 /* skip PG for GFX, SDMA on S0ix */
2877 if (adev->in_s0ix &&
2878 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2879 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2881 /* skip CG for VCE/UVD, it's handled specially */
2882 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2883 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2884 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2885 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2886 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2887 /* enable powergating to save power */
2888 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2891 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2892 adev->ip_blocks[i].version->funcs->name, r);
2900 static int amdgpu_device_enable_mgpu_fan_boost(void)
2902 struct amdgpu_gpu_instance *gpu_ins;
2903 struct amdgpu_device *adev;
2906 mutex_lock(&mgpu_info.mutex);
2909 * MGPU fan boost feature should be enabled
2910 * only when there are two or more dGPUs in
2913 if (mgpu_info.num_dgpu < 2)
2916 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2917 gpu_ins = &(mgpu_info.gpu_ins[i]);
2918 adev = gpu_ins->adev;
2919 if (!(adev->flags & AMD_IS_APU) &&
2920 !gpu_ins->mgpu_fan_enabled) {
2921 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2925 gpu_ins->mgpu_fan_enabled = 1;
2930 mutex_unlock(&mgpu_info.mutex);
2936 * amdgpu_device_ip_late_init - run late init for hardware IPs
2938 * @adev: amdgpu_device pointer
2940 * Late initialization pass for hardware IPs. The list of all the hardware
2941 * IPs that make up the asic is walked and the late_init callbacks are run.
2942 * late_init covers any special initialization that an IP requires
2943 * after all of the have been initialized or something that needs to happen
2944 * late in the init process.
2945 * Returns 0 on success, negative error code on failure.
2947 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2949 struct amdgpu_gpu_instance *gpu_instance;
2952 for (i = 0; i < adev->num_ip_blocks; i++) {
2953 if (!adev->ip_blocks[i].status.hw)
2955 if (adev->ip_blocks[i].version->funcs->late_init) {
2956 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2958 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2959 adev->ip_blocks[i].version->funcs->name, r);
2963 adev->ip_blocks[i].status.late_initialized = true;
2966 r = amdgpu_ras_late_init(adev);
2968 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
2972 amdgpu_ras_set_error_query_ready(adev, true);
2974 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2975 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2977 amdgpu_device_fill_reset_magic(adev);
2979 r = amdgpu_device_enable_mgpu_fan_boost();
2981 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2983 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
2984 if (amdgpu_passthrough(adev) &&
2985 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
2986 adev->asic_type == CHIP_ALDEBARAN))
2987 amdgpu_dpm_handle_passthrough_sbr(adev, true);
2989 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2990 mutex_lock(&mgpu_info.mutex);
2993 * Reset device p-state to low as this was booted with high.
2995 * This should be performed only after all devices from the same
2996 * hive get initialized.
2998 * However, it's unknown how many device in the hive in advance.
2999 * As this is counted one by one during devices initializations.
3001 * So, we wait for all XGMI interlinked devices initialized.
3002 * This may bring some delays as those devices may come from
3003 * different hives. But that should be OK.
3005 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
3006 for (i = 0; i < mgpu_info.num_gpu; i++) {
3007 gpu_instance = &(mgpu_info.gpu_ins[i]);
3008 if (gpu_instance->adev->flags & AMD_IS_APU)
3011 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
3012 AMDGPU_XGMI_PSTATE_MIN);
3014 DRM_ERROR("pstate setting failed (%d).\n", r);
3020 mutex_unlock(&mgpu_info.mutex);
3027 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
3029 * @adev: amdgpu_device pointer
3031 * For ASICs need to disable SMC first
3033 static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
3037 if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0))
3040 for (i = 0; i < adev->num_ip_blocks; i++) {
3041 if (!adev->ip_blocks[i].status.hw)
3043 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3044 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
3045 /* XXX handle errors */
3047 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3048 adev->ip_blocks[i].version->funcs->name, r);
3050 adev->ip_blocks[i].status.hw = false;
3056 static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
3060 for (i = 0; i < adev->num_ip_blocks; i++) {
3061 if (!adev->ip_blocks[i].version->funcs->early_fini)
3064 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
3066 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
3067 adev->ip_blocks[i].version->funcs->name, r);
3071 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3072 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3074 amdgpu_amdkfd_suspend(adev, false);
3076 /* Workaroud for ASICs need to disable SMC first */
3077 amdgpu_device_smu_fini_early(adev);
3079 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3080 if (!adev->ip_blocks[i].status.hw)
3083 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
3084 /* XXX handle errors */
3086 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3087 adev->ip_blocks[i].version->funcs->name, r);
3090 adev->ip_blocks[i].status.hw = false;
3093 if (amdgpu_sriov_vf(adev)) {
3094 if (amdgpu_virt_release_full_gpu(adev, false))
3095 DRM_ERROR("failed to release exclusive mode on fini\n");
3102 * amdgpu_device_ip_fini - run fini for hardware IPs
3104 * @adev: amdgpu_device pointer
3106 * Main teardown pass for hardware IPs. The list of all the hardware
3107 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
3108 * are run. hw_fini tears down the hardware associated with each IP
3109 * and sw_fini tears down any software state associated with each IP.
3110 * Returns 0 on success, negative error code on failure.
3112 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
3116 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
3117 amdgpu_virt_release_ras_err_handler_data(adev);
3119 if (adev->gmc.xgmi.num_physical_nodes > 1)
3120 amdgpu_xgmi_remove_device(adev);
3122 amdgpu_amdkfd_device_fini_sw(adev);
3124 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3125 if (!adev->ip_blocks[i].status.sw)
3128 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
3129 amdgpu_ucode_free_bo(adev);
3130 amdgpu_free_static_csa(&adev->virt.csa_obj);
3131 amdgpu_device_wb_fini(adev);
3132 amdgpu_device_mem_scratch_fini(adev);
3133 amdgpu_ib_pool_fini(adev);
3136 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
3137 /* XXX handle errors */
3139 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
3140 adev->ip_blocks[i].version->funcs->name, r);
3142 adev->ip_blocks[i].status.sw = false;
3143 adev->ip_blocks[i].status.valid = false;
3146 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3147 if (!adev->ip_blocks[i].status.late_initialized)
3149 if (adev->ip_blocks[i].version->funcs->late_fini)
3150 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
3151 adev->ip_blocks[i].status.late_initialized = false;
3154 amdgpu_ras_fini(adev);
3160 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
3162 * @work: work_struct.
3164 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
3166 struct amdgpu_device *adev =
3167 container_of(work, struct amdgpu_device, delayed_init_work.work);
3170 r = amdgpu_ib_ring_tests(adev);
3172 DRM_ERROR("ib ring test failed (%d).\n", r);
3175 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
3177 struct amdgpu_device *adev =
3178 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
3180 WARN_ON_ONCE(adev->gfx.gfx_off_state);
3181 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
3183 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
3184 adev->gfx.gfx_off_state = true;
3188 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
3190 * @adev: amdgpu_device pointer
3192 * Main suspend function for hardware IPs. The list of all the hardware
3193 * IPs that make up the asic is walked, clockgating is disabled and the
3194 * suspend callbacks are run. suspend puts the hardware and software state
3195 * in each IP into a state suitable for suspend.
3196 * Returns 0 on success, negative error code on failure.
3198 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
3202 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3203 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3206 * Per PMFW team's suggestion, driver needs to handle gfxoff
3207 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
3208 * scenario. Add the missing df cstate disablement here.
3210 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
3211 dev_warn(adev->dev, "Failed to disallow df cstate");
3213 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3214 if (!adev->ip_blocks[i].status.valid)
3217 /* displays are handled separately */
3218 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
3221 /* XXX handle errors */
3222 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3223 /* XXX handle errors */
3225 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3226 adev->ip_blocks[i].version->funcs->name, r);
3230 adev->ip_blocks[i].status.hw = false;
3237 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
3239 * @adev: amdgpu_device pointer
3241 * Main suspend function for hardware IPs. The list of all the hardware
3242 * IPs that make up the asic is walked, clockgating is disabled and the
3243 * suspend callbacks are run. suspend puts the hardware and software state
3244 * in each IP into a state suitable for suspend.
3245 * Returns 0 on success, negative error code on failure.
3247 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
3252 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
3254 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3255 if (!adev->ip_blocks[i].status.valid)
3257 /* displays are handled in phase1 */
3258 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3260 /* PSP lost connection when err_event_athub occurs */
3261 if (amdgpu_ras_intr_triggered() &&
3262 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3263 adev->ip_blocks[i].status.hw = false;
3267 /* skip unnecessary suspend if we do not initialize them yet */
3268 if (adev->gmc.xgmi.pending_reset &&
3269 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3270 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
3271 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3272 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
3273 adev->ip_blocks[i].status.hw = false;
3277 /* skip suspend of gfx/mes and psp for S0ix
3278 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3279 * like at runtime. PSP is also part of the always on hardware
3280 * so no need to suspend it.
3282 if (adev->in_s0ix &&
3283 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3284 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3285 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3288 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
3289 if (adev->in_s0ix &&
3290 (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >=
3291 IP_VERSION(5, 0, 0)) &&
3292 (adev->ip_blocks[i].version->type ==
3293 AMD_IP_BLOCK_TYPE_SDMA))
3296 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
3297 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
3298 * from this location and RLC Autoload automatically also gets loaded
3299 * from here based on PMFW -> PSP message during re-init sequence.
3300 * Therefore, the psp suspend & resume should be skipped to avoid destroy
3301 * the TMR and reload FWs again for IMU enabled APU ASICs.
3303 if (amdgpu_in_reset(adev) &&
3304 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3305 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3308 /* XXX handle errors */
3309 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3310 /* XXX handle errors */
3312 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3313 adev->ip_blocks[i].version->funcs->name, r);
3315 adev->ip_blocks[i].status.hw = false;
3316 /* handle putting the SMC in the appropriate state */
3317 if (!amdgpu_sriov_vf(adev)) {
3318 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3319 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3321 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3322 adev->mp1_state, r);
3333 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3335 * @adev: amdgpu_device pointer
3337 * Main suspend function for hardware IPs. The list of all the hardware
3338 * IPs that make up the asic is walked, clockgating is disabled and the
3339 * suspend callbacks are run. suspend puts the hardware and software state
3340 * in each IP into a state suitable for suspend.
3341 * Returns 0 on success, negative error code on failure.
3343 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3347 if (amdgpu_sriov_vf(adev)) {
3348 amdgpu_virt_fini_data_exchange(adev);
3349 amdgpu_virt_request_full_gpu(adev, false);
3352 amdgpu_ttm_set_buffer_funcs_status(adev, false);
3354 r = amdgpu_device_ip_suspend_phase1(adev);
3357 r = amdgpu_device_ip_suspend_phase2(adev);
3359 if (amdgpu_sriov_vf(adev))
3360 amdgpu_virt_release_full_gpu(adev, false);
3365 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3369 static enum amd_ip_block_type ip_order[] = {
3370 AMD_IP_BLOCK_TYPE_COMMON,
3371 AMD_IP_BLOCK_TYPE_GMC,
3372 AMD_IP_BLOCK_TYPE_PSP,
3373 AMD_IP_BLOCK_TYPE_IH,
3376 for (i = 0; i < adev->num_ip_blocks; i++) {
3378 struct amdgpu_ip_block *block;
3380 block = &adev->ip_blocks[i];
3381 block->status.hw = false;
3383 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3385 if (block->version->type != ip_order[j] ||
3386 !block->status.valid)
3389 r = block->version->funcs->hw_init(adev);
3390 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3393 block->status.hw = true;
3400 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3404 static enum amd_ip_block_type ip_order[] = {
3405 AMD_IP_BLOCK_TYPE_SMC,
3406 AMD_IP_BLOCK_TYPE_DCE,
3407 AMD_IP_BLOCK_TYPE_GFX,
3408 AMD_IP_BLOCK_TYPE_SDMA,
3409 AMD_IP_BLOCK_TYPE_MES,
3410 AMD_IP_BLOCK_TYPE_UVD,
3411 AMD_IP_BLOCK_TYPE_VCE,
3412 AMD_IP_BLOCK_TYPE_VCN,
3413 AMD_IP_BLOCK_TYPE_JPEG
3416 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3418 struct amdgpu_ip_block *block;
3420 for (j = 0; j < adev->num_ip_blocks; j++) {
3421 block = &adev->ip_blocks[j];
3423 if (block->version->type != ip_order[i] ||
3424 !block->status.valid ||
3428 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3429 r = block->version->funcs->resume(adev);
3431 r = block->version->funcs->hw_init(adev);
3433 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3436 block->status.hw = true;
3444 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3446 * @adev: amdgpu_device pointer
3448 * First resume function for hardware IPs. The list of all the hardware
3449 * IPs that make up the asic is walked and the resume callbacks are run for
3450 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3451 * after a suspend and updates the software state as necessary. This
3452 * function is also used for restoring the GPU after a GPU reset.
3453 * Returns 0 on success, negative error code on failure.
3455 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3459 for (i = 0; i < adev->num_ip_blocks; i++) {
3460 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3462 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3463 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3464 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3465 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3467 r = adev->ip_blocks[i].version->funcs->resume(adev);
3469 DRM_ERROR("resume of IP block <%s> failed %d\n",
3470 adev->ip_blocks[i].version->funcs->name, r);
3473 adev->ip_blocks[i].status.hw = true;
3481 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3483 * @adev: amdgpu_device pointer
3485 * First resume function for hardware IPs. The list of all the hardware
3486 * IPs that make up the asic is walked and the resume callbacks are run for
3487 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3488 * functional state after a suspend and updates the software state as
3489 * necessary. This function is also used for restoring the GPU after a GPU
3491 * Returns 0 on success, negative error code on failure.
3493 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3497 for (i = 0; i < adev->num_ip_blocks; i++) {
3498 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3500 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3501 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3502 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3503 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3505 r = adev->ip_blocks[i].version->funcs->resume(adev);
3507 DRM_ERROR("resume of IP block <%s> failed %d\n",
3508 adev->ip_blocks[i].version->funcs->name, r);
3511 adev->ip_blocks[i].status.hw = true;
3518 * amdgpu_device_ip_resume - run resume for hardware IPs
3520 * @adev: amdgpu_device pointer
3522 * Main resume function for hardware IPs. The hardware IPs
3523 * are split into two resume functions because they are
3524 * also used in recovering from a GPU reset and some additional
3525 * steps need to be take between them. In this case (S3/S4) they are
3527 * Returns 0 on success, negative error code on failure.
3529 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3533 r = amdgpu_device_ip_resume_phase1(adev);
3537 r = amdgpu_device_fw_loading(adev);
3541 r = amdgpu_device_ip_resume_phase2(adev);
3543 if (adev->mman.buffer_funcs_ring->sched.ready)
3544 amdgpu_ttm_set_buffer_funcs_status(adev, true);
3550 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3552 * @adev: amdgpu_device pointer
3554 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3556 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3558 if (amdgpu_sriov_vf(adev)) {
3559 if (adev->is_atom_fw) {
3560 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3561 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3563 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3564 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3567 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3568 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3573 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3575 * @asic_type: AMD asic type
3577 * Check if there is DC (new modesetting infrastructre) support for an asic.
3578 * returns true if DC has support, false if not.
3580 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3582 switch (asic_type) {
3583 #ifdef CONFIG_DRM_AMDGPU_SI
3587 /* chips with no display hardware */
3589 #if defined(CONFIG_DRM_AMD_DC)
3595 * We have systems in the wild with these ASICs that require
3596 * LVDS and VGA support which is not supported with DC.
3598 * Fallback to the non-DC driver here by default so as not to
3599 * cause regressions.
3601 #if defined(CONFIG_DRM_AMD_DC_SI)
3602 return amdgpu_dc > 0;
3611 * We have systems in the wild with these ASICs that require
3612 * VGA support which is not supported with DC.
3614 * Fallback to the non-DC driver here by default so as not to
3615 * cause regressions.
3617 return amdgpu_dc > 0;
3619 return amdgpu_dc != 0;
3623 DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");
3630 * amdgpu_device_has_dc_support - check if dc is supported
3632 * @adev: amdgpu_device pointer
3634 * Returns true for supported, false for not supported
3636 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3638 if (adev->enable_virtual_display ||
3639 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3642 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3645 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3647 struct amdgpu_device *adev =
3648 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3649 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3651 /* It's a bug to not have a hive within this function */
3656 * Use task barrier to synchronize all xgmi reset works across the
3657 * hive. task_barrier_enter and task_barrier_exit will block
3658 * until all the threads running the xgmi reset works reach
3659 * those points. task_barrier_full will do both blocks.
3661 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3663 task_barrier_enter(&hive->tb);
3664 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3666 if (adev->asic_reset_res)
3669 task_barrier_exit(&hive->tb);
3670 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3672 if (adev->asic_reset_res)
3675 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
3678 task_barrier_full(&hive->tb);
3679 adev->asic_reset_res = amdgpu_asic_reset(adev);
3683 if (adev->asic_reset_res)
3684 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3685 adev->asic_reset_res, adev_to_drm(adev)->unique);
3686 amdgpu_put_xgmi_hive(hive);
3689 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3691 char *input = amdgpu_lockup_timeout;
3692 char *timeout_setting = NULL;
3698 * By default timeout for non compute jobs is 10000
3699 * and 60000 for compute jobs.
3700 * In SR-IOV or passthrough mode, timeout for compute
3701 * jobs are 60000 by default.
3703 adev->gfx_timeout = msecs_to_jiffies(10000);
3704 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3705 if (amdgpu_sriov_vf(adev))
3706 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3707 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3709 adev->compute_timeout = msecs_to_jiffies(60000);
3711 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3712 while ((timeout_setting = strsep(&input, ",")) &&
3713 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3714 ret = kstrtol(timeout_setting, 0, &timeout);
3721 } else if (timeout < 0) {
3722 timeout = MAX_SCHEDULE_TIMEOUT;
3723 dev_warn(adev->dev, "lockup timeout disabled");
3724 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3726 timeout = msecs_to_jiffies(timeout);
3731 adev->gfx_timeout = timeout;
3734 adev->compute_timeout = timeout;
3737 adev->sdma_timeout = timeout;
3740 adev->video_timeout = timeout;
3747 * There is only one value specified and
3748 * it should apply to all non-compute jobs.
3751 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3752 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3753 adev->compute_timeout = adev->gfx_timeout;
3761 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3763 * @adev: amdgpu_device pointer
3765 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3767 static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3769 struct iommu_domain *domain;
3771 domain = iommu_get_domain_for_dev(adev->dev);
3772 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3773 adev->ram_is_direct_mapped = true;
3776 static const struct attribute *amdgpu_dev_attributes[] = {
3777 &dev_attr_pcie_replay_count.attr,
3781 static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
3783 if (amdgpu_mcbp == 1)
3784 adev->gfx.mcbp = true;
3785 else if (amdgpu_mcbp == 0)
3786 adev->gfx.mcbp = false;
3788 if (amdgpu_sriov_vf(adev))
3789 adev->gfx.mcbp = true;
3792 DRM_INFO("MCBP is enabled\n");
3796 * amdgpu_device_init - initialize the driver
3798 * @adev: amdgpu_device pointer
3799 * @flags: driver flags
3801 * Initializes the driver info and hw (all asics).
3802 * Returns 0 for success or an error on failure.
3803 * Called at driver startup.
3805 int amdgpu_device_init(struct amdgpu_device *adev,
3808 struct drm_device *ddev = adev_to_drm(adev);
3809 struct pci_dev *pdev = adev->pdev;
3815 adev->shutdown = false;
3816 adev->flags = flags;
3818 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3819 adev->asic_type = amdgpu_force_asic_type;
3821 adev->asic_type = flags & AMD_ASIC_MASK;
3823 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3824 if (amdgpu_emu_mode == 1)
3825 adev->usec_timeout *= 10;
3826 adev->gmc.gart_size = 512 * 1024 * 1024;
3827 adev->accel_working = false;
3828 adev->num_rings = 0;
3829 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3830 adev->mman.buffer_funcs = NULL;
3831 adev->mman.buffer_funcs_ring = NULL;
3832 adev->vm_manager.vm_pte_funcs = NULL;
3833 adev->vm_manager.vm_pte_num_scheds = 0;
3834 adev->gmc.gmc_funcs = NULL;
3835 adev->harvest_ip_mask = 0x0;
3836 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3837 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3839 adev->smc_rreg = &amdgpu_invalid_rreg;
3840 adev->smc_wreg = &amdgpu_invalid_wreg;
3841 adev->pcie_rreg = &amdgpu_invalid_rreg;
3842 adev->pcie_wreg = &amdgpu_invalid_wreg;
3843 adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext;
3844 adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext;
3845 adev->pciep_rreg = &amdgpu_invalid_rreg;
3846 adev->pciep_wreg = &amdgpu_invalid_wreg;
3847 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3848 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3849 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext;
3850 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext;
3851 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3852 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3853 adev->didt_rreg = &amdgpu_invalid_rreg;
3854 adev->didt_wreg = &amdgpu_invalid_wreg;
3855 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3856 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3857 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3858 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3860 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3861 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3862 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3864 /* mutex initialization are all done here so we
3865 * can recall function without having locking issues
3867 mutex_init(&adev->firmware.mutex);
3868 mutex_init(&adev->pm.mutex);
3869 mutex_init(&adev->gfx.gpu_clock_mutex);
3870 mutex_init(&adev->srbm_mutex);
3871 mutex_init(&adev->gfx.pipe_reserve_mutex);
3872 mutex_init(&adev->gfx.gfx_off_mutex);
3873 mutex_init(&adev->gfx.partition_mutex);
3874 mutex_init(&adev->grbm_idx_mutex);
3875 mutex_init(&adev->mn_lock);
3876 mutex_init(&adev->virt.vf_errors.lock);
3877 hash_init(adev->mn_hash);
3878 mutex_init(&adev->psp.mutex);
3879 mutex_init(&adev->notifier_lock);
3880 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3881 mutex_init(&adev->benchmark_mutex);
3883 amdgpu_device_init_apu_flags(adev);
3885 r = amdgpu_device_check_arguments(adev);
3889 spin_lock_init(&adev->mmio_idx_lock);
3890 spin_lock_init(&adev->smc_idx_lock);
3891 spin_lock_init(&adev->pcie_idx_lock);
3892 spin_lock_init(&adev->uvd_ctx_idx_lock);
3893 spin_lock_init(&adev->didt_idx_lock);
3894 spin_lock_init(&adev->gc_cac_idx_lock);
3895 spin_lock_init(&adev->se_cac_idx_lock);
3896 spin_lock_init(&adev->audio_endpt_idx_lock);
3897 spin_lock_init(&adev->mm_stats.lock);
3899 INIT_LIST_HEAD(&adev->shadow_list);
3900 mutex_init(&adev->shadow_list_lock);
3902 INIT_LIST_HEAD(&adev->reset_list);
3904 INIT_LIST_HEAD(&adev->ras_list);
3906 INIT_LIST_HEAD(&adev->pm.od_kobj_list);
3908 INIT_DELAYED_WORK(&adev->delayed_init_work,
3909 amdgpu_device_delayed_init_work_handler);
3910 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3911 amdgpu_device_delay_enable_gfx_off);
3913 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3915 adev->gfx.gfx_off_req_count = 1;
3916 adev->gfx.gfx_off_residency = 0;
3917 adev->gfx.gfx_off_entrycount = 0;
3918 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3920 atomic_set(&adev->throttling_logging_enabled, 1);
3922 * If throttling continues, logging will be performed every minute
3923 * to avoid log flooding. "-1" is subtracted since the thermal
3924 * throttling interrupt comes every second. Thus, the total logging
3925 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3926 * for throttling interrupt) = 60 seconds.
3928 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3929 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3931 /* Registers mapping */
3932 /* TODO: block userspace mapping of io register */
3933 if (adev->asic_type >= CHIP_BONAIRE) {
3934 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3935 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3937 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3938 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3941 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
3942 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
3944 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3948 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3949 DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size);
3952 * Reset domain needs to be present early, before XGMI hive discovered
3953 * (if any) and intitialized to use reset sem and in_gpu reset flag
3954 * early on during init and before calling to RREG32.
3956 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
3957 if (!adev->reset_domain)
3960 /* detect hw virtualization here */
3961 amdgpu_detect_virtualization(adev);
3963 amdgpu_device_get_pcie_info(adev);
3965 r = amdgpu_device_get_job_timeout_settings(adev);
3967 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3971 /* early init functions */
3972 r = amdgpu_device_ip_early_init(adev);
3976 amdgpu_device_set_mcbp(adev);
3978 /* Get rid of things like offb */
3979 r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
3983 /* Enable TMZ based on IP_VERSION */
3984 amdgpu_gmc_tmz_set(adev);
3986 amdgpu_gmc_noretry_set(adev);
3987 /* Need to get xgmi info early to decide the reset behavior*/
3988 if (adev->gmc.xgmi.supported) {
3989 r = adev->gfxhub.funcs->get_xgmi_info(adev);
3994 /* enable PCIE atomic ops */
3995 if (amdgpu_sriov_vf(adev)) {
3996 if (adev->virt.fw_reserve.p_pf2vf)
3997 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
3998 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
3999 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4000 /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
4001 * internal path natively support atomics, set have_atomics_support to true.
4003 } else if ((adev->flags & AMD_IS_APU) &&
4004 (amdgpu_ip_version(adev, GC_HWIP, 0) >
4005 IP_VERSION(9, 0, 0))) {
4006 adev->have_atomics_support = true;
4008 adev->have_atomics_support =
4009 !pci_enable_atomic_ops_to_root(adev->pdev,
4010 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
4011 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4014 if (!adev->have_atomics_support)
4015 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
4017 /* doorbell bar mapping and doorbell index init*/
4018 amdgpu_doorbell_init(adev);
4020 if (amdgpu_emu_mode == 1) {
4021 /* post the asic on emulation mode */
4022 emu_soc_asic_init(adev);
4023 goto fence_driver_init;
4026 amdgpu_reset_init(adev);
4028 /* detect if we are with an SRIOV vbios */
4030 amdgpu_device_detect_sriov_bios(adev);
4032 /* check if we need to reset the asic
4033 * E.g., driver was not cleanly unloaded previously, etc.
4035 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
4036 if (adev->gmc.xgmi.num_physical_nodes) {
4037 dev_info(adev->dev, "Pending hive reset.\n");
4038 adev->gmc.xgmi.pending_reset = true;
4039 /* Only need to init necessary block for SMU to handle the reset */
4040 for (i = 0; i < adev->num_ip_blocks; i++) {
4041 if (!adev->ip_blocks[i].status.valid)
4043 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
4044 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
4045 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
4046 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
4047 DRM_DEBUG("IP %s disabled for hw_init.\n",
4048 adev->ip_blocks[i].version->funcs->name);
4049 adev->ip_blocks[i].status.hw = true;
4053 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
4054 case IP_VERSION(13, 0, 0):
4055 case IP_VERSION(13, 0, 7):
4056 case IP_VERSION(13, 0, 10):
4057 r = psp_gpu_reset(adev);
4060 tmp = amdgpu_reset_method;
4061 /* It should do a default reset when loading or reloading the driver,
4062 * regardless of the module parameter reset_method.
4064 amdgpu_reset_method = AMD_RESET_METHOD_NONE;
4065 r = amdgpu_asic_reset(adev);
4066 amdgpu_reset_method = tmp;
4071 dev_err(adev->dev, "asic reset on init failed\n");
4077 /* Post card if necessary */
4078 if (amdgpu_device_need_post(adev)) {
4080 dev_err(adev->dev, "no vBIOS found\n");
4084 DRM_INFO("GPU posting now...\n");
4085 r = amdgpu_device_asic_init(adev);
4087 dev_err(adev->dev, "gpu post error!\n");
4093 if (adev->is_atom_fw) {
4094 /* Initialize clocks */
4095 r = amdgpu_atomfirmware_get_clock_info(adev);
4097 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
4098 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4102 /* Initialize clocks */
4103 r = amdgpu_atombios_get_clock_info(adev);
4105 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
4106 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4109 /* init i2c buses */
4110 if (!amdgpu_device_has_dc_support(adev))
4111 amdgpu_atombios_i2c_init(adev);
4117 r = amdgpu_fence_driver_sw_init(adev);
4119 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
4120 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
4124 /* init the mode config */
4125 drm_mode_config_init(adev_to_drm(adev));
4127 r = amdgpu_device_ip_init(adev);
4129 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
4130 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
4131 goto release_ras_con;
4134 amdgpu_fence_driver_hw_init(adev);
4137 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
4138 adev->gfx.config.max_shader_engines,
4139 adev->gfx.config.max_sh_per_se,
4140 adev->gfx.config.max_cu_per_sh,
4141 adev->gfx.cu_info.number);
4143 adev->accel_working = true;
4145 amdgpu_vm_check_compute_bug(adev);
4147 /* Initialize the buffer migration limit. */
4148 if (amdgpu_moverate >= 0)
4149 max_MBps = amdgpu_moverate;
4151 max_MBps = 8; /* Allow 8 MB/s. */
4152 /* Get a log2 for easy divisions. */
4153 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
4156 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
4157 * Otherwise the mgpu fan boost feature will be skipped due to the
4158 * gpu instance is counted less.
4160 amdgpu_register_gpu_instance(adev);
4162 /* enable clockgating, etc. after ib tests, etc. since some blocks require
4163 * explicit gating rather than handling it automatically.
4165 if (!adev->gmc.xgmi.pending_reset) {
4166 r = amdgpu_device_ip_late_init(adev);
4168 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
4169 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
4170 goto release_ras_con;
4173 amdgpu_ras_resume(adev);
4174 queue_delayed_work(system_wq, &adev->delayed_init_work,
4175 msecs_to_jiffies(AMDGPU_RESUME_MS));
4178 if (amdgpu_sriov_vf(adev)) {
4179 amdgpu_virt_release_full_gpu(adev, true);
4180 flush_delayed_work(&adev->delayed_init_work);
4184 * Place those sysfs registering after `late_init`. As some of those
4185 * operations performed in `late_init` might affect the sysfs
4186 * interfaces creating.
4188 r = amdgpu_atombios_sysfs_init(adev);
4190 drm_err(&adev->ddev,
4191 "registering atombios sysfs failed (%d).\n", r);
4193 r = amdgpu_pm_sysfs_init(adev);
4195 DRM_ERROR("registering pm sysfs failed (%d).\n", r);
4197 r = amdgpu_ucode_sysfs_init(adev);
4199 adev->ucode_sysfs_en = false;
4200 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
4202 adev->ucode_sysfs_en = true;
4204 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
4206 dev_err(adev->dev, "Could not create amdgpu device attr\n");
4208 r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group);
4211 "Could not create amdgpu board attributes\n");
4213 amdgpu_fru_sysfs_init(adev);
4215 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4216 r = amdgpu_pmu_init(adev);
4218 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
4220 /* Have stored pci confspace at hand for restore in sudden PCI error */
4221 if (amdgpu_device_cache_pci_state(adev->pdev))
4222 pci_restore_state(pdev);
4224 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
4225 /* this will fail for cards that aren't VGA class devices, just
4228 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4229 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
4231 px = amdgpu_device_supports_px(ddev);
4233 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4234 apple_gmux_detect(NULL, NULL)))
4235 vga_switcheroo_register_client(adev->pdev,
4236 &amdgpu_switcheroo_ops, px);
4239 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
4241 if (adev->gmc.xgmi.pending_reset)
4242 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
4243 msecs_to_jiffies(AMDGPU_RESUME_MS));
4245 amdgpu_device_check_iommu_direct_map(adev);
4250 if (amdgpu_sriov_vf(adev))
4251 amdgpu_virt_release_full_gpu(adev, true);
4253 /* failed in exclusive mode due to timeout */
4254 if (amdgpu_sriov_vf(adev) &&
4255 !amdgpu_sriov_runtime(adev) &&
4256 amdgpu_virt_mmio_blocked(adev) &&
4257 !amdgpu_virt_wait_reset(adev)) {
4258 dev_err(adev->dev, "VF exclusive mode timeout\n");
4259 /* Don't send request since VF is inactive. */
4260 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
4261 adev->virt.ops = NULL;
4264 amdgpu_release_ras_context(adev);
4267 amdgpu_vf_error_trans_all(adev);
4272 static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
4275 /* Clear all CPU mappings pointing to this device */
4276 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
4278 /* Unmap all mapped bars - Doorbell, registers and VRAM */
4279 amdgpu_doorbell_fini(adev);
4281 iounmap(adev->rmmio);
4283 if (adev->mman.aper_base_kaddr)
4284 iounmap(adev->mman.aper_base_kaddr);
4285 adev->mman.aper_base_kaddr = NULL;
4287 /* Memory manager related */
4288 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
4289 arch_phys_wc_del(adev->gmc.vram_mtrr);
4290 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
4295 * amdgpu_device_fini_hw - tear down the driver
4297 * @adev: amdgpu_device pointer
4299 * Tear down the driver info (all asics).
4300 * Called at driver shutdown.
4302 void amdgpu_device_fini_hw(struct amdgpu_device *adev)
4304 dev_info(adev->dev, "amdgpu: finishing device.\n");
4305 flush_delayed_work(&adev->delayed_init_work);
4306 adev->shutdown = true;
4308 /* make sure IB test finished before entering exclusive mode
4309 * to avoid preemption on IB test
4311 if (amdgpu_sriov_vf(adev)) {
4312 amdgpu_virt_request_full_gpu(adev, false);
4313 amdgpu_virt_fini_data_exchange(adev);
4316 /* disable all interrupts */
4317 amdgpu_irq_disable_all(adev);
4318 if (adev->mode_info.mode_config_initialized) {
4319 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
4320 drm_helper_force_disable_all(adev_to_drm(adev));
4322 drm_atomic_helper_shutdown(adev_to_drm(adev));
4324 amdgpu_fence_driver_hw_fini(adev);
4326 if (adev->mman.initialized)
4327 drain_workqueue(adev->mman.bdev.wq);
4329 if (adev->pm.sysfs_initialized)
4330 amdgpu_pm_sysfs_fini(adev);
4331 if (adev->ucode_sysfs_en)
4332 amdgpu_ucode_sysfs_fini(adev);
4333 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4334 amdgpu_fru_sysfs_fini(adev);
4336 /* disable ras feature must before hw fini */
4337 amdgpu_ras_pre_fini(adev);
4339 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4341 amdgpu_device_ip_fini_early(adev);
4343 amdgpu_irq_fini_hw(adev);
4345 if (adev->mman.initialized)
4346 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4348 amdgpu_gart_dummy_page_fini(adev);
4350 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4351 amdgpu_device_unmap_mmio(adev);
4355 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4360 amdgpu_fence_driver_sw_fini(adev);
4361 amdgpu_device_ip_fini(adev);
4362 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4363 adev->accel_working = false;
4364 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4366 amdgpu_reset_fini(adev);
4368 /* free i2c buses */
4369 if (!amdgpu_device_has_dc_support(adev))
4370 amdgpu_i2c_fini(adev);
4372 if (amdgpu_emu_mode != 1)
4373 amdgpu_atombios_fini(adev);
4378 kfree(adev->fru_info);
4379 adev->fru_info = NULL;
4381 px = amdgpu_device_supports_px(adev_to_drm(adev));
4383 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4384 apple_gmux_detect(NULL, NULL)))
4385 vga_switcheroo_unregister_client(adev->pdev);
4388 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4390 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4391 vga_client_unregister(adev->pdev);
4393 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4395 iounmap(adev->rmmio);
4397 amdgpu_doorbell_fini(adev);
4401 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4402 amdgpu_pmu_fini(adev);
4403 if (adev->mman.discovery_bin)
4404 amdgpu_discovery_fini(adev);
4406 amdgpu_reset_put_reset_domain(adev->reset_domain);
4407 adev->reset_domain = NULL;
4409 kfree(adev->pci_state);
4414 * amdgpu_device_evict_resources - evict device resources
4415 * @adev: amdgpu device object
4417 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4418 * of the vram memory type. Mainly used for evicting device resources
4422 static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4426 /* No need to evict vram on APUs for suspend to ram or s2idle */
4427 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4430 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4432 DRM_WARN("evicting device resources failed\n");
4440 * amdgpu_device_prepare - prepare for device suspend
4442 * @dev: drm dev pointer
4444 * Prepare to put the hw in the suspend state (all asics).
4445 * Returns 0 for success or an error on failure.
4446 * Called at driver suspend.
4448 int amdgpu_device_prepare(struct drm_device *dev)
4450 struct amdgpu_device *adev = drm_to_adev(dev);
4453 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4456 /* Evict the majority of BOs before starting suspend sequence */
4457 r = amdgpu_device_evict_resources(adev);
4461 for (i = 0; i < adev->num_ip_blocks; i++) {
4462 if (!adev->ip_blocks[i].status.valid)
4464 if (!adev->ip_blocks[i].version->funcs->prepare_suspend)
4466 r = adev->ip_blocks[i].version->funcs->prepare_suspend((void *)adev);
4475 * amdgpu_device_suspend - initiate device suspend
4477 * @dev: drm dev pointer
4478 * @fbcon : notify the fbdev of suspend
4480 * Puts the hw in the suspend state (all asics).
4481 * Returns 0 for success or an error on failure.
4482 * Called at driver suspend.
4484 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4486 struct amdgpu_device *adev = drm_to_adev(dev);
4489 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4492 adev->in_suspend = true;
4494 if (amdgpu_sriov_vf(adev)) {
4495 amdgpu_virt_fini_data_exchange(adev);
4496 r = amdgpu_virt_request_full_gpu(adev, false);
4501 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4502 DRM_WARN("smart shift update failed\n");
4505 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4507 cancel_delayed_work_sync(&adev->delayed_init_work);
4508 flush_delayed_work(&adev->gfx.gfx_off_delay_work);
4510 amdgpu_ras_suspend(adev);
4512 amdgpu_device_ip_suspend_phase1(adev);
4515 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4517 r = amdgpu_device_evict_resources(adev);
4521 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4523 amdgpu_fence_driver_hw_fini(adev);
4525 amdgpu_device_ip_suspend_phase2(adev);
4527 if (amdgpu_sriov_vf(adev))
4528 amdgpu_virt_release_full_gpu(adev, false);
4530 r = amdgpu_dpm_notify_rlc_state(adev, false);
4538 * amdgpu_device_resume - initiate device resume
4540 * @dev: drm dev pointer
4541 * @fbcon : notify the fbdev of resume
4543 * Bring the hw back to operating state (all asics).
4544 * Returns 0 for success or an error on failure.
4545 * Called at driver resume.
4547 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4549 struct amdgpu_device *adev = drm_to_adev(dev);
4552 if (amdgpu_sriov_vf(adev)) {
4553 r = amdgpu_virt_request_full_gpu(adev, true);
4558 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4562 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4565 if (amdgpu_device_need_post(adev)) {
4566 r = amdgpu_device_asic_init(adev);
4568 dev_err(adev->dev, "amdgpu asic init failed\n");
4571 r = amdgpu_device_ip_resume(adev);
4574 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4577 amdgpu_fence_driver_hw_init(adev);
4579 if (!adev->in_s0ix) {
4580 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4585 r = amdgpu_device_ip_late_init(adev);
4589 queue_delayed_work(system_wq, &adev->delayed_init_work,
4590 msecs_to_jiffies(AMDGPU_RESUME_MS));
4592 if (amdgpu_sriov_vf(adev)) {
4593 amdgpu_virt_init_data_exchange(adev);
4594 amdgpu_virt_release_full_gpu(adev, true);
4600 /* Make sure IB tests flushed */
4601 flush_delayed_work(&adev->delayed_init_work);
4604 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4606 amdgpu_ras_resume(adev);
4608 if (adev->mode_info.num_crtc) {
4610 * Most of the connector probing functions try to acquire runtime pm
4611 * refs to ensure that the GPU is powered on when connector polling is
4612 * performed. Since we're calling this from a runtime PM callback,
4613 * trying to acquire rpm refs will cause us to deadlock.
4615 * Since we're guaranteed to be holding the rpm lock, it's safe to
4616 * temporarily disable the rpm helpers so this doesn't deadlock us.
4619 dev->dev->power.disable_depth++;
4621 if (!adev->dc_enabled)
4622 drm_helper_hpd_irq_event(dev);
4624 drm_kms_helper_hotplug_event(dev);
4626 dev->dev->power.disable_depth--;
4629 adev->in_suspend = false;
4631 if (adev->enable_mes)
4632 amdgpu_mes_self_test(adev);
4634 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4635 DRM_WARN("smart shift update failed\n");
4641 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4643 * @adev: amdgpu_device pointer
4645 * The list of all the hardware IPs that make up the asic is walked and
4646 * the check_soft_reset callbacks are run. check_soft_reset determines
4647 * if the asic is still hung or not.
4648 * Returns true if any of the IPs are still in a hung state, false if not.
4650 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4653 bool asic_hang = false;
4655 if (amdgpu_sriov_vf(adev))
4658 if (amdgpu_asic_need_full_reset(adev))
4661 for (i = 0; i < adev->num_ip_blocks; i++) {
4662 if (!adev->ip_blocks[i].status.valid)
4664 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4665 adev->ip_blocks[i].status.hang =
4666 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4667 if (adev->ip_blocks[i].status.hang) {
4668 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4676 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4678 * @adev: amdgpu_device pointer
4680 * The list of all the hardware IPs that make up the asic is walked and the
4681 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4682 * handles any IP specific hardware or software state changes that are
4683 * necessary for a soft reset to succeed.
4684 * Returns 0 on success, negative error code on failure.
4686 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4690 for (i = 0; i < adev->num_ip_blocks; i++) {
4691 if (!adev->ip_blocks[i].status.valid)
4693 if (adev->ip_blocks[i].status.hang &&
4694 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4695 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4705 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4707 * @adev: amdgpu_device pointer
4709 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4710 * reset is necessary to recover.
4711 * Returns true if a full asic reset is required, false if not.
4713 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4717 if (amdgpu_asic_need_full_reset(adev))
4720 for (i = 0; i < adev->num_ip_blocks; i++) {
4721 if (!adev->ip_blocks[i].status.valid)
4723 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4724 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4725 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4726 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4727 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4728 if (adev->ip_blocks[i].status.hang) {
4729 dev_info(adev->dev, "Some block need full reset!\n");
4738 * amdgpu_device_ip_soft_reset - do a soft reset
4740 * @adev: amdgpu_device pointer
4742 * The list of all the hardware IPs that make up the asic is walked and the
4743 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4744 * IP specific hardware or software state changes that are necessary to soft
4746 * Returns 0 on success, negative error code on failure.
4748 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4752 for (i = 0; i < adev->num_ip_blocks; i++) {
4753 if (!adev->ip_blocks[i].status.valid)
4755 if (adev->ip_blocks[i].status.hang &&
4756 adev->ip_blocks[i].version->funcs->soft_reset) {
4757 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4767 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4769 * @adev: amdgpu_device pointer
4771 * The list of all the hardware IPs that make up the asic is walked and the
4772 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4773 * handles any IP specific hardware or software state changes that are
4774 * necessary after the IP has been soft reset.
4775 * Returns 0 on success, negative error code on failure.
4777 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4781 for (i = 0; i < adev->num_ip_blocks; i++) {
4782 if (!adev->ip_blocks[i].status.valid)
4784 if (adev->ip_blocks[i].status.hang &&
4785 adev->ip_blocks[i].version->funcs->post_soft_reset)
4786 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4795 * amdgpu_device_recover_vram - Recover some VRAM contents
4797 * @adev: amdgpu_device pointer
4799 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4800 * restore things like GPUVM page tables after a GPU reset where
4801 * the contents of VRAM might be lost.
4804 * 0 on success, negative error code on failure.
4806 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4808 struct dma_fence *fence = NULL, *next = NULL;
4809 struct amdgpu_bo *shadow;
4810 struct amdgpu_bo_vm *vmbo;
4813 if (amdgpu_sriov_runtime(adev))
4814 tmo = msecs_to_jiffies(8000);
4816 tmo = msecs_to_jiffies(100);
4818 dev_info(adev->dev, "recover vram bo from shadow start\n");
4819 mutex_lock(&adev->shadow_list_lock);
4820 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4821 /* If vm is compute context or adev is APU, shadow will be NULL */
4824 shadow = vmbo->shadow;
4826 /* No need to recover an evicted BO */
4827 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4828 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4829 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4832 r = amdgpu_bo_restore_shadow(shadow, &next);
4837 tmo = dma_fence_wait_timeout(fence, false, tmo);
4838 dma_fence_put(fence);
4843 } else if (tmo < 0) {
4851 mutex_unlock(&adev->shadow_list_lock);
4854 tmo = dma_fence_wait_timeout(fence, false, tmo);
4855 dma_fence_put(fence);
4857 if (r < 0 || tmo <= 0) {
4858 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4862 dev_info(adev->dev, "recover vram bo from shadow done\n");
4868 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4870 * @adev: amdgpu_device pointer
4871 * @from_hypervisor: request from hypervisor
4873 * do VF FLR and reinitialize Asic
4874 * return 0 means succeeded otherwise failed
4876 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4877 bool from_hypervisor)
4880 struct amdgpu_hive_info *hive = NULL;
4881 int retry_limit = 0;
4884 amdgpu_amdkfd_pre_reset(adev);
4886 if (from_hypervisor)
4887 r = amdgpu_virt_request_full_gpu(adev, true);
4889 r = amdgpu_virt_reset_gpu(adev);
4892 amdgpu_irq_gpu_reset_resume_helper(adev);
4894 /* some sw clean up VF needs to do before recover */
4895 amdgpu_virt_post_reset(adev);
4897 /* Resume IP prior to SMC */
4898 r = amdgpu_device_ip_reinit_early_sriov(adev);
4902 amdgpu_virt_init_data_exchange(adev);
4904 r = amdgpu_device_fw_loading(adev);
4908 /* now we are okay to resume SMC/CP/SDMA */
4909 r = amdgpu_device_ip_reinit_late_sriov(adev);
4913 hive = amdgpu_get_xgmi_hive(adev);
4914 /* Update PSP FW topology after reset */
4915 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
4916 r = amdgpu_xgmi_update_topology(hive, adev);
4919 amdgpu_put_xgmi_hive(hive);
4922 r = amdgpu_ib_ring_tests(adev);
4924 amdgpu_amdkfd_post_reset(adev);
4928 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4929 amdgpu_inc_vram_lost(adev);
4930 r = amdgpu_device_recover_vram(adev);
4932 amdgpu_virt_release_full_gpu(adev, true);
4934 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
4935 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
4939 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
4946 * amdgpu_device_has_job_running - check if there is any job in mirror list
4948 * @adev: amdgpu_device pointer
4950 * check if there is any job in mirror list
4952 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4955 struct drm_sched_job *job;
4957 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4958 struct amdgpu_ring *ring = adev->rings[i];
4960 if (!ring || !ring->sched.thread)
4963 spin_lock(&ring->sched.job_list_lock);
4964 job = list_first_entry_or_null(&ring->sched.pending_list,
4965 struct drm_sched_job, list);
4966 spin_unlock(&ring->sched.job_list_lock);
4974 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4976 * @adev: amdgpu_device pointer
4978 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4981 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4984 if (amdgpu_gpu_recovery == 0)
4987 /* Skip soft reset check in fatal error mode */
4988 if (!amdgpu_ras_is_poison_mode_supported(adev))
4991 if (amdgpu_sriov_vf(adev))
4994 if (amdgpu_gpu_recovery == -1) {
4995 switch (adev->asic_type) {
4996 #ifdef CONFIG_DRM_AMDGPU_SI
5003 #ifdef CONFIG_DRM_AMDGPU_CIK
5010 case CHIP_CYAN_SKILLFISH:
5020 dev_info(adev->dev, "GPU recovery disabled.\n");
5024 int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
5029 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
5031 dev_info(adev->dev, "GPU mode1 reset\n");
5034 pci_clear_master(adev->pdev);
5036 amdgpu_device_cache_pci_state(adev->pdev);
5038 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
5039 dev_info(adev->dev, "GPU smu mode1 reset\n");
5040 ret = amdgpu_dpm_mode1_reset(adev);
5042 dev_info(adev->dev, "GPU psp mode1 reset\n");
5043 ret = psp_gpu_reset(adev);
5047 goto mode1_reset_failed;
5049 amdgpu_device_load_pci_state(adev->pdev);
5050 ret = amdgpu_psp_wait_for_bootloader(adev);
5052 goto mode1_reset_failed;
5054 /* wait for asic to come out of reset */
5055 for (i = 0; i < adev->usec_timeout; i++) {
5056 u32 memsize = adev->nbio.funcs->get_memsize(adev);
5058 if (memsize != 0xffffffff)
5063 if (i >= adev->usec_timeout) {
5065 goto mode1_reset_failed;
5068 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
5073 dev_err(adev->dev, "GPU mode1 reset failed\n");
5077 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
5078 struct amdgpu_reset_context *reset_context)
5081 struct amdgpu_job *job = NULL;
5082 bool need_full_reset =
5083 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5085 if (reset_context->reset_req_dev == adev)
5086 job = reset_context->job;
5088 if (amdgpu_sriov_vf(adev)) {
5089 /* stop the data exchange thread */
5090 amdgpu_virt_fini_data_exchange(adev);
5093 amdgpu_fence_driver_isr_toggle(adev, true);
5095 /* block all schedulers and reset given job's ring */
5096 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5097 struct amdgpu_ring *ring = adev->rings[i];
5099 if (!ring || !ring->sched.thread)
5102 /* Clear job fence from fence drv to avoid force_completion
5103 * leave NULL and vm flush fence in fence drv
5105 amdgpu_fence_driver_clear_job_fences(ring);
5107 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
5108 amdgpu_fence_driver_force_completion(ring);
5111 amdgpu_fence_driver_isr_toggle(adev, false);
5114 drm_sched_increase_karma(&job->base);
5116 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
5117 /* If reset handler not implemented, continue; otherwise return */
5118 if (r == -EOPNOTSUPP)
5123 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
5124 if (!amdgpu_sriov_vf(adev)) {
5126 if (!need_full_reset)
5127 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
5129 if (!need_full_reset && amdgpu_gpu_recovery &&
5130 amdgpu_device_ip_check_soft_reset(adev)) {
5131 amdgpu_device_ip_pre_soft_reset(adev);
5132 r = amdgpu_device_ip_soft_reset(adev);
5133 amdgpu_device_ip_post_soft_reset(adev);
5134 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
5135 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
5136 need_full_reset = true;
5140 if (need_full_reset)
5141 r = amdgpu_device_ip_suspend(adev);
5142 if (need_full_reset)
5143 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5145 clear_bit(AMDGPU_NEED_FULL_RESET,
5146 &reset_context->flags);
5152 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
5156 lockdep_assert_held(&adev->reset_domain->sem);
5158 for (i = 0; i < adev->reset_info.num_regs; i++) {
5159 adev->reset_info.reset_dump_reg_value[i] =
5160 RREG32(adev->reset_info.reset_dump_reg_list[i]);
5162 trace_amdgpu_reset_reg_dumps(adev->reset_info.reset_dump_reg_list[i],
5163 adev->reset_info.reset_dump_reg_value[i]);
5169 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
5170 struct amdgpu_reset_context *reset_context)
5172 struct amdgpu_device *tmp_adev = NULL;
5173 bool need_full_reset, skip_hw_reset, vram_lost = false;
5175 bool gpu_reset_for_dev_remove = 0;
5177 /* Try reset handler method first */
5178 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5180 amdgpu_reset_reg_dumps(tmp_adev);
5182 reset_context->reset_device_list = device_list_handle;
5183 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
5184 /* If reset handler not implemented, continue; otherwise return */
5185 if (r == -EOPNOTSUPP)
5190 /* Reset handler not implemented, use the default method */
5192 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5193 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
5195 gpu_reset_for_dev_remove =
5196 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5197 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5200 * ASIC reset has to be done on all XGMI hive nodes ASAP
5201 * to allow proper links negotiation in FW (within 1 sec)
5203 if (!skip_hw_reset && need_full_reset) {
5204 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5205 /* For XGMI run all resets in parallel to speed up the process */
5206 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5207 tmp_adev->gmc.xgmi.pending_reset = false;
5208 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
5211 r = amdgpu_asic_reset(tmp_adev);
5214 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
5215 r, adev_to_drm(tmp_adev)->unique);
5220 /* For XGMI wait for all resets to complete before proceed */
5222 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5223 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5224 flush_work(&tmp_adev->xgmi_reset_work);
5225 r = tmp_adev->asic_reset_res;
5233 if (!r && amdgpu_ras_intr_triggered()) {
5234 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5235 amdgpu_ras_reset_error_count(tmp_adev, AMDGPU_RAS_BLOCK__MMHUB);
5238 amdgpu_ras_intr_cleared();
5241 /* Since the mode1 reset affects base ip blocks, the
5242 * phase1 ip blocks need to be resumed. Otherwise there
5243 * will be a BIOS signature error and the psp bootloader
5244 * can't load kdb on the next amdgpu install.
5246 if (gpu_reset_for_dev_remove) {
5247 list_for_each_entry(tmp_adev, device_list_handle, reset_list)
5248 amdgpu_device_ip_resume_phase1(tmp_adev);
5253 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5254 if (need_full_reset) {
5256 r = amdgpu_device_asic_init(tmp_adev);
5258 dev_warn(tmp_adev->dev, "asic atom init failed!");
5260 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
5262 r = amdgpu_device_ip_resume_phase1(tmp_adev);
5266 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
5268 amdgpu_coredump(tmp_adev, vram_lost, reset_context);
5271 DRM_INFO("VRAM is lost due to GPU reset!\n");
5272 amdgpu_inc_vram_lost(tmp_adev);
5275 r = amdgpu_device_fw_loading(tmp_adev);
5279 r = amdgpu_xcp_restore_partition_mode(
5284 r = amdgpu_device_ip_resume_phase2(tmp_adev);
5288 if (tmp_adev->mman.buffer_funcs_ring->sched.ready)
5289 amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);
5292 amdgpu_device_fill_reset_magic(tmp_adev);
5295 * Add this ASIC as tracked as reset was already
5296 * complete successfully.
5298 amdgpu_register_gpu_instance(tmp_adev);
5300 if (!reset_context->hive &&
5301 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5302 amdgpu_xgmi_add_device(tmp_adev);
5304 r = amdgpu_device_ip_late_init(tmp_adev);
5308 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
5311 * The GPU enters bad state once faulty pages
5312 * by ECC has reached the threshold, and ras
5313 * recovery is scheduled next. So add one check
5314 * here to break recovery if it indeed exceeds
5315 * bad page threshold, and remind user to
5316 * retire this GPU or setting one bigger
5317 * bad_page_threshold value to fix this once
5318 * probing driver again.
5320 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
5322 amdgpu_ras_resume(tmp_adev);
5328 /* Update PSP FW topology after reset */
5329 if (reset_context->hive &&
5330 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5331 r = amdgpu_xgmi_update_topology(
5332 reset_context->hive, tmp_adev);
5338 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5339 r = amdgpu_ib_ring_tests(tmp_adev);
5341 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5342 need_full_reset = true;
5349 r = amdgpu_device_recover_vram(tmp_adev);
5351 tmp_adev->asic_reset_res = r;
5355 if (need_full_reset)
5356 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5358 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5362 static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5365 switch (amdgpu_asic_reset_method(adev)) {
5366 case AMD_RESET_METHOD_MODE1:
5367 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5369 case AMD_RESET_METHOD_MODE2:
5370 adev->mp1_state = PP_MP1_STATE_RESET;
5373 adev->mp1_state = PP_MP1_STATE_NONE;
5378 static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5380 amdgpu_vf_error_trans_all(adev);
5381 adev->mp1_state = PP_MP1_STATE_NONE;
5384 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5386 struct pci_dev *p = NULL;
5388 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5389 adev->pdev->bus->number, 1);
5391 pm_runtime_enable(&(p->dev));
5392 pm_runtime_resume(&(p->dev));
5398 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5400 enum amd_reset_method reset_method;
5401 struct pci_dev *p = NULL;
5405 * For now, only BACO and mode1 reset are confirmed
5406 * to suffer the audio issue without proper suspended.
5408 reset_method = amdgpu_asic_reset_method(adev);
5409 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5410 (reset_method != AMD_RESET_METHOD_MODE1))
5413 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5414 adev->pdev->bus->number, 1);
5418 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5421 * If we cannot get the audio device autosuspend delay,
5422 * a fixed 4S interval will be used. Considering 3S is
5423 * the audio controller default autosuspend delay setting.
5424 * 4S used here is guaranteed to cover that.
5426 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5428 while (!pm_runtime_status_suspended(&(p->dev))) {
5429 if (!pm_runtime_suspend(&(p->dev)))
5432 if (expires < ktime_get_mono_fast_ns()) {
5433 dev_warn(adev->dev, "failed to suspend display audio\n");
5435 /* TODO: abort the succeeding gpu reset? */
5440 pm_runtime_disable(&(p->dev));
5446 static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5448 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5450 #if defined(CONFIG_DEBUG_FS)
5451 if (!amdgpu_sriov_vf(adev))
5452 cancel_work(&adev->reset_work);
5456 cancel_work(&adev->kfd.reset_work);
5458 if (amdgpu_sriov_vf(adev))
5459 cancel_work(&adev->virt.flr_work);
5461 if (con && adev->ras_enabled)
5462 cancel_work(&con->recovery_work);
5467 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5469 * @adev: amdgpu_device pointer
5470 * @job: which job trigger hang
5471 * @reset_context: amdgpu reset context pointer
5473 * Attempt to reset the GPU if it has hung (all asics).
5474 * Attempt to do soft-reset or full-reset and reinitialize Asic
5475 * Returns 0 for success or an error on failure.
5478 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5479 struct amdgpu_job *job,
5480 struct amdgpu_reset_context *reset_context)
5482 struct list_head device_list, *device_list_handle = NULL;
5483 bool job_signaled = false;
5484 struct amdgpu_hive_info *hive = NULL;
5485 struct amdgpu_device *tmp_adev = NULL;
5487 bool need_emergency_restart = false;
5488 bool audio_suspended = false;
5489 bool gpu_reset_for_dev_remove = false;
5491 gpu_reset_for_dev_remove =
5492 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5493 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5496 * Special case: RAS triggered and full reset isn't supported
5498 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5501 * Flush RAM to disk so that after reboot
5502 * the user can read log and see why the system rebooted.
5504 if (need_emergency_restart && amdgpu_ras_get_context(adev) &&
5505 amdgpu_ras_get_context(adev)->reboot) {
5506 DRM_WARN("Emergency reboot.");
5509 emergency_restart();
5512 dev_info(adev->dev, "GPU %s begin!\n",
5513 need_emergency_restart ? "jobs stop":"reset");
5515 if (!amdgpu_sriov_vf(adev))
5516 hive = amdgpu_get_xgmi_hive(adev);
5518 mutex_lock(&hive->hive_lock);
5520 reset_context->job = job;
5521 reset_context->hive = hive;
5523 * Build list of devices to reset.
5524 * In case we are in XGMI hive mode, resort the device list
5525 * to put adev in the 1st position.
5527 INIT_LIST_HEAD(&device_list);
5528 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5529 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5530 list_add_tail(&tmp_adev->reset_list, &device_list);
5531 if (gpu_reset_for_dev_remove && adev->shutdown)
5532 tmp_adev->shutdown = true;
5534 if (!list_is_first(&adev->reset_list, &device_list))
5535 list_rotate_to_front(&adev->reset_list, &device_list);
5536 device_list_handle = &device_list;
5538 list_add_tail(&adev->reset_list, &device_list);
5539 device_list_handle = &device_list;
5542 /* We need to lock reset domain only once both for XGMI and single device */
5543 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5545 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5547 /* block all schedulers and reset given job's ring */
5548 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5550 amdgpu_device_set_mp1_state(tmp_adev);
5553 * Try to put the audio codec into suspend state
5554 * before gpu reset started.
5556 * Due to the power domain of the graphics device
5557 * is shared with AZ power domain. Without this,
5558 * we may change the audio hardware from behind
5559 * the audio driver's back. That will trigger
5560 * some audio codec errors.
5562 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5563 audio_suspended = true;
5565 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5567 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5569 if (!amdgpu_sriov_vf(tmp_adev))
5570 amdgpu_amdkfd_pre_reset(tmp_adev);
5573 * Mark these ASICs to be reseted as untracked first
5574 * And add them back after reset completed
5576 amdgpu_unregister_gpu_instance(tmp_adev);
5578 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5580 /* disable ras on ALL IPs */
5581 if (!need_emergency_restart &&
5582 amdgpu_device_ip_need_full_reset(tmp_adev))
5583 amdgpu_ras_suspend(tmp_adev);
5585 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5586 struct amdgpu_ring *ring = tmp_adev->rings[i];
5588 if (!ring || !ring->sched.thread)
5591 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5593 if (need_emergency_restart)
5594 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5596 atomic_inc(&tmp_adev->gpu_reset_counter);
5599 if (need_emergency_restart)
5600 goto skip_sched_resume;
5603 * Must check guilty signal here since after this point all old
5604 * HW fences are force signaled.
5606 * job->base holds a reference to parent fence
5608 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5609 job_signaled = true;
5610 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5614 retry: /* Rest of adevs pre asic reset from XGMI hive. */
5615 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5616 if (gpu_reset_for_dev_remove) {
5617 /* Workaroud for ASICs need to disable SMC first */
5618 amdgpu_device_smu_fini_early(tmp_adev);
5620 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5621 /*TODO Should we stop ?*/
5623 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5624 r, adev_to_drm(tmp_adev)->unique);
5625 tmp_adev->asic_reset_res = r;
5629 * Drop all pending non scheduler resets. Scheduler resets
5630 * were already dropped during drm_sched_stop
5632 amdgpu_device_stop_pending_resets(tmp_adev);
5635 /* Actual ASIC resets if needed.*/
5636 /* Host driver will handle XGMI hive reset for SRIOV */
5637 if (amdgpu_sriov_vf(adev)) {
5638 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5640 adev->asic_reset_res = r;
5642 /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */
5643 if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5644 IP_VERSION(9, 4, 2) ||
5645 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))
5646 amdgpu_ras_resume(adev);
5648 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5649 if (r && r == -EAGAIN)
5652 if (!r && gpu_reset_for_dev_remove)
5658 /* Post ASIC reset for all devs .*/
5659 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5661 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5662 struct amdgpu_ring *ring = tmp_adev->rings[i];
5664 if (!ring || !ring->sched.thread)
5667 drm_sched_start(&ring->sched, true);
5670 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
5671 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5673 if (tmp_adev->asic_reset_res)
5674 r = tmp_adev->asic_reset_res;
5676 tmp_adev->asic_reset_res = 0;
5679 /* bad news, how to tell it to userspace ? */
5680 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5681 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5683 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5684 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5685 DRM_WARN("smart shift update failed\n");
5690 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5691 /* unlock kfd: SRIOV would do it separately */
5692 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5693 amdgpu_amdkfd_post_reset(tmp_adev);
5695 /* kfd_post_reset will do nothing if kfd device is not initialized,
5696 * need to bring up kfd here if it's not be initialized before
5698 if (!adev->kfd.init_complete)
5699 amdgpu_amdkfd_device_init(adev);
5701 if (audio_suspended)
5702 amdgpu_device_resume_display_audio(tmp_adev);
5704 amdgpu_device_unset_mp1_state(tmp_adev);
5706 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5710 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5712 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5715 mutex_unlock(&hive->hive_lock);
5716 amdgpu_put_xgmi_hive(hive);
5720 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5722 atomic_set(&adev->reset_domain->reset_res, r);
5727 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5729 * @adev: amdgpu_device pointer
5731 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5732 * and lanes) of the slot the device is in. Handles APUs and
5733 * virtualized environments where PCIE config space may not be available.
5735 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5737 struct pci_dev *pdev;
5738 enum pci_bus_speed speed_cap, platform_speed_cap;
5739 enum pcie_link_width platform_link_width;
5741 if (amdgpu_pcie_gen_cap)
5742 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5744 if (amdgpu_pcie_lane_cap)
5745 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5747 /* covers APUs as well */
5748 if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) {
5749 if (adev->pm.pcie_gen_mask == 0)
5750 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5751 if (adev->pm.pcie_mlw_mask == 0)
5752 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5756 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5759 pcie_bandwidth_available(adev->pdev, NULL,
5760 &platform_speed_cap, &platform_link_width);
5762 if (adev->pm.pcie_gen_mask == 0) {
5765 speed_cap = pcie_get_speed_cap(pdev);
5766 if (speed_cap == PCI_SPEED_UNKNOWN) {
5767 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5768 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5769 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5771 if (speed_cap == PCIE_SPEED_32_0GT)
5772 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5773 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5774 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5775 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5776 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5777 else if (speed_cap == PCIE_SPEED_16_0GT)
5778 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5779 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5780 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5781 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5782 else if (speed_cap == PCIE_SPEED_8_0GT)
5783 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5784 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5785 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5786 else if (speed_cap == PCIE_SPEED_5_0GT)
5787 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5788 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5790 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5793 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5794 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5795 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5797 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5798 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5799 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5800 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5801 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5802 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5803 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5804 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5805 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5806 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5807 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5808 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5809 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5810 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5811 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5812 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5813 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5814 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5816 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5820 if (adev->pm.pcie_mlw_mask == 0) {
5821 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5822 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5824 switch (platform_link_width) {
5826 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5827 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5828 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5829 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5830 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5831 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5832 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5835 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5836 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5837 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5838 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5839 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5840 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5843 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5844 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5845 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5846 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5847 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5850 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5851 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5852 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5853 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5856 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5857 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5858 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5861 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5862 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5865 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5875 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5877 * @adev: amdgpu_device pointer
5878 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5880 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5881 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5884 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5885 struct amdgpu_device *peer_adev)
5887 #ifdef CONFIG_HSA_AMD_P2P
5888 uint64_t address_mask = peer_adev->dev->dma_mask ?
5889 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5890 resource_size_t aper_limit =
5891 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5893 !adev->gmc.xgmi.connected_to_cpu &&
5894 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
5896 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
5897 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
5898 !(adev->gmc.aper_base & address_mask ||
5899 aper_limit & address_mask));
5905 int amdgpu_device_baco_enter(struct drm_device *dev)
5907 struct amdgpu_device *adev = drm_to_adev(dev);
5908 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5910 if (!amdgpu_device_supports_baco(dev))
5913 if (ras && adev->ras_enabled &&
5914 adev->nbio.funcs->enable_doorbell_interrupt)
5915 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5917 return amdgpu_dpm_baco_enter(adev);
5920 int amdgpu_device_baco_exit(struct drm_device *dev)
5922 struct amdgpu_device *adev = drm_to_adev(dev);
5923 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5926 if (!amdgpu_device_supports_baco(dev))
5929 ret = amdgpu_dpm_baco_exit(adev);
5933 if (ras && adev->ras_enabled &&
5934 adev->nbio.funcs->enable_doorbell_interrupt)
5935 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
5937 if (amdgpu_passthrough(adev) &&
5938 adev->nbio.funcs->clear_doorbell_interrupt)
5939 adev->nbio.funcs->clear_doorbell_interrupt(adev);
5945 * amdgpu_pci_error_detected - Called when a PCI error is detected.
5946 * @pdev: PCI device struct
5947 * @state: PCI channel state
5949 * Description: Called when a PCI error is detected.
5951 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
5953 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5955 struct drm_device *dev = pci_get_drvdata(pdev);
5956 struct amdgpu_device *adev = drm_to_adev(dev);
5959 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
5961 if (adev->gmc.xgmi.num_physical_nodes > 1) {
5962 DRM_WARN("No support for XGMI hive yet...");
5963 return PCI_ERS_RESULT_DISCONNECT;
5966 adev->pci_channel_state = state;
5969 case pci_channel_io_normal:
5970 return PCI_ERS_RESULT_CAN_RECOVER;
5971 /* Fatal error, prepare for slot reset */
5972 case pci_channel_io_frozen:
5974 * Locking adev->reset_domain->sem will prevent any external access
5975 * to GPU during PCI error recovery
5977 amdgpu_device_lock_reset_domain(adev->reset_domain);
5978 amdgpu_device_set_mp1_state(adev);
5981 * Block any work scheduling as we do for regular GPU reset
5982 * for the duration of the recovery
5984 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5985 struct amdgpu_ring *ring = adev->rings[i];
5987 if (!ring || !ring->sched.thread)
5990 drm_sched_stop(&ring->sched, NULL);
5992 atomic_inc(&adev->gpu_reset_counter);
5993 return PCI_ERS_RESULT_NEED_RESET;
5994 case pci_channel_io_perm_failure:
5995 /* Permanent error, prepare for device removal */
5996 return PCI_ERS_RESULT_DISCONNECT;
5999 return PCI_ERS_RESULT_NEED_RESET;
6003 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
6004 * @pdev: pointer to PCI device
6006 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
6009 DRM_INFO("PCI error: mmio enabled callback!!\n");
6011 /* TODO - dump whatever for debugging purposes */
6013 /* This called only if amdgpu_pci_error_detected returns
6014 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
6015 * works, no need to reset slot.
6018 return PCI_ERS_RESULT_RECOVERED;
6022 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
6023 * @pdev: PCI device struct
6025 * Description: This routine is called by the pci error recovery
6026 * code after the PCI slot has been reset, just before we
6027 * should resume normal operations.
6029 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
6031 struct drm_device *dev = pci_get_drvdata(pdev);
6032 struct amdgpu_device *adev = drm_to_adev(dev);
6034 struct amdgpu_reset_context reset_context;
6036 struct list_head device_list;
6038 DRM_INFO("PCI error: slot reset callback!!\n");
6040 memset(&reset_context, 0, sizeof(reset_context));
6042 INIT_LIST_HEAD(&device_list);
6043 list_add_tail(&adev->reset_list, &device_list);
6045 /* wait for asic to come out of reset */
6048 /* Restore PCI confspace */
6049 amdgpu_device_load_pci_state(pdev);
6051 /* confirm ASIC came out of reset */
6052 for (i = 0; i < adev->usec_timeout; i++) {
6053 memsize = amdgpu_asic_get_config_memsize(adev);
6055 if (memsize != 0xffffffff)
6059 if (memsize == 0xffffffff) {
6064 reset_context.method = AMD_RESET_METHOD_NONE;
6065 reset_context.reset_req_dev = adev;
6066 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
6067 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
6069 adev->no_hw_access = true;
6070 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
6071 adev->no_hw_access = false;
6075 r = amdgpu_do_asic_reset(&device_list, &reset_context);
6079 if (amdgpu_device_cache_pci_state(adev->pdev))
6080 pci_restore_state(adev->pdev);
6082 DRM_INFO("PCIe error recovery succeeded\n");
6084 DRM_ERROR("PCIe error recovery failed, err:%d", r);
6085 amdgpu_device_unset_mp1_state(adev);
6086 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6089 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
6093 * amdgpu_pci_resume() - resume normal ops after PCI reset
6094 * @pdev: pointer to PCI device
6096 * Called when the error recovery driver tells us that its
6097 * OK to resume normal operation.
6099 void amdgpu_pci_resume(struct pci_dev *pdev)
6101 struct drm_device *dev = pci_get_drvdata(pdev);
6102 struct amdgpu_device *adev = drm_to_adev(dev);
6106 DRM_INFO("PCI error: resume callback!!\n");
6108 /* Only continue execution for the case of pci_channel_io_frozen */
6109 if (adev->pci_channel_state != pci_channel_io_frozen)
6112 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6113 struct amdgpu_ring *ring = adev->rings[i];
6115 if (!ring || !ring->sched.thread)
6118 drm_sched_start(&ring->sched, true);
6121 amdgpu_device_unset_mp1_state(adev);
6122 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6125 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
6127 struct drm_device *dev = pci_get_drvdata(pdev);
6128 struct amdgpu_device *adev = drm_to_adev(dev);
6131 r = pci_save_state(pdev);
6133 kfree(adev->pci_state);
6135 adev->pci_state = pci_store_saved_state(pdev);
6137 if (!adev->pci_state) {
6138 DRM_ERROR("Failed to store PCI saved state");
6142 DRM_WARN("Failed to save PCI state, err:%d\n", r);
6149 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
6151 struct drm_device *dev = pci_get_drvdata(pdev);
6152 struct amdgpu_device *adev = drm_to_adev(dev);
6155 if (!adev->pci_state)
6158 r = pci_load_saved_state(pdev, adev->pci_state);
6161 pci_restore_state(pdev);
6163 DRM_WARN("Failed to load PCI state, err:%d\n", r);
6170 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
6171 struct amdgpu_ring *ring)
6173 #ifdef CONFIG_X86_64
6174 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6177 if (adev->gmc.xgmi.connected_to_cpu)
6180 if (ring && ring->funcs->emit_hdp_flush)
6181 amdgpu_ring_emit_hdp_flush(ring);
6183 amdgpu_asic_flush_hdp(adev, ring);
6186 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
6187 struct amdgpu_ring *ring)
6189 #ifdef CONFIG_X86_64
6190 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6193 if (adev->gmc.xgmi.connected_to_cpu)
6196 amdgpu_asic_invalidate_hdp(adev, ring);
6199 int amdgpu_in_reset(struct amdgpu_device *adev)
6201 return atomic_read(&adev->reset_domain->in_gpu_reset);
6205 * amdgpu_device_halt() - bring hardware to some kind of halt state
6207 * @adev: amdgpu_device pointer
6209 * Bring hardware to some kind of halt state so that no one can touch it
6210 * any more. It will help to maintain error context when error occurred.
6211 * Compare to a simple hang, the system will keep stable at least for SSH
6212 * access. Then it should be trivial to inspect the hardware state and
6213 * see what's going on. Implemented as following:
6215 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
6216 * clears all CPU mappings to device, disallows remappings through page faults
6217 * 2. amdgpu_irq_disable_all() disables all interrupts
6218 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
6219 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
6220 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
6221 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
6222 * flush any in flight DMA operations
6224 void amdgpu_device_halt(struct amdgpu_device *adev)
6226 struct pci_dev *pdev = adev->pdev;
6227 struct drm_device *ddev = adev_to_drm(adev);
6229 amdgpu_xcp_dev_unplug(adev);
6230 drm_dev_unplug(ddev);
6232 amdgpu_irq_disable_all(adev);
6234 amdgpu_fence_driver_hw_fini(adev);
6236 adev->no_hw_access = true;
6238 amdgpu_device_unmap_mmio(adev);
6240 pci_disable_device(pdev);
6241 pci_wait_for_pending_transaction(pdev);
6244 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
6247 unsigned long flags, address, data;
6250 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6251 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6253 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6254 WREG32(address, reg * 4);
6255 (void)RREG32(address);
6257 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6261 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
6264 unsigned long flags, address, data;
6266 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6267 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6269 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6270 WREG32(address, reg * 4);
6271 (void)RREG32(address);
6274 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6278 * amdgpu_device_switch_gang - switch to a new gang
6279 * @adev: amdgpu_device pointer
6280 * @gang: the gang to switch to
6282 * Try to switch to a new gang.
6283 * Returns: NULL if we switched to the new gang or a reference to the current
6286 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
6287 struct dma_fence *gang)
6289 struct dma_fence *old = NULL;
6294 old = dma_fence_get_rcu_safe(&adev->gang_submit);
6300 if (!dma_fence_is_signaled(old))
6303 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
6310 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
6312 switch (adev->asic_type) {
6313 #ifdef CONFIG_DRM_AMDGPU_SI
6317 /* chips with no display hardware */
6319 #ifdef CONFIG_DRM_AMDGPU_SI
6325 #ifdef CONFIG_DRM_AMDGPU_CIK
6334 case CHIP_POLARIS10:
6335 case CHIP_POLARIS11:
6336 case CHIP_POLARIS12:
6340 /* chips with display hardware */
6344 if (!amdgpu_ip_version(adev, DCE_HWIP, 0) ||
6345 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6351 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
6352 uint32_t inst, uint32_t reg_addr, char reg_name[],
6353 uint32_t expected_value, uint32_t mask)
6357 uint32_t tmp_ = RREG32(reg_addr);
6358 uint32_t loop = adev->usec_timeout;
6360 while ((tmp_ & (mask)) != (expected_value)) {
6362 loop = adev->usec_timeout;
6366 tmp_ = RREG32(reg_addr);
6369 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",
6370 inst, reg_name, (uint32_t)expected_value,
6371 (uint32_t)(tmp_ & (mask)));