drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/power_supply.h>
  29 #include <linux/kthread.h>
  30 #include <linux/module.h>
  31 #include <linux/console.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_probe_helper.h>
  36 #include <drm/amdgpu_drm.h>
  37 #include <linux/vgaarb.h>
  38 #include <linux/vga_switcheroo.h>
  39 #include <linux/efi.h>
  40 #include "amdgpu.h"
  41 #include "amdgpu_trace.h"
  42 #include "amdgpu_i2c.h"
  43 #include "atom.h"
  44 #include "amdgpu_atombios.h"
  45 #include "amdgpu_atomfirmware.h"
  46 #include "amd_pcie.h"
  47 #ifdef CONFIG_DRM_AMDGPU_SI
  48 #include "si.h"
  49 #endif
  50 #ifdef CONFIG_DRM_AMDGPU_CIK
  51 #include "cik.h"
  52 #endif
  53 #include "vi.h"
  54 #include "soc15.h"
  55 #include "nv.h"
  56 #include "bif/bif_4_1_d.h"
  57 #include <linux/pci.h>
  58 #include <linux/firmware.h>
  59 #include "amdgpu_vf_error.h"
  60
  61 #include "amdgpu_amdkfd.h"
  62 #include "amdgpu_pm.h"
  63
  64 #include "amdgpu_xgmi.h"
  65 #include "amdgpu_ras.h"
  66 #include "amdgpu_pmu.h"
  67
  68 #include <linux/suspend.h>
  69
  70 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  71 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
  72 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  73 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
  74 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
  75 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
  76 MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
  77 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
  78 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
  79 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
  80
  81 #define AMDGPU_RESUME_MS                2000
  82
  83 const char *amdgpu_asic_name[] = {
  84         "TAHITI",
  85         "PITCAIRN",
  86         "VERDE",
  87         "OLAND",
  88         "HAINAN",
  89         "BONAIRE",
  90         "KAVERI",
  91         "KABINI",
  92         "HAWAII",
  93         "MULLINS",
  94         "TOPAZ",
  95         "TONGA",
  96         "FIJI",
  97         "CARRIZO",
  98         "STONEY",
  99         "POLARIS10",
 100         "POLARIS11",
 101         "POLARIS12",
 102         "VEGAM",
 103         "VEGA10",
 104         "VEGA12",
 105         "VEGA20",
 106         "RAVEN",
 107         "ARCTURUS",
 108         "RENOIR",
 109         "NAVI10",
 110         "NAVI14",
 111         "NAVI12",
 112         "LAST",
 113 };
 114
 115 /**
 116  * DOC: pcie_replay_count
 117  *
 118  * The amdgpu driver provides a sysfs API for reporting the total number
 119  * of PCIe replays (NAKs)
 120  * The file pcie_replay_count is used for this and returns the total
 121  * number of replays as a sum of the NAKs generated and NAKs received
 122  */
 123
 124 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
 125                 struct device_attribute *attr, char *buf)
 126 {
 127         struct drm_device *ddev = dev_get_drvdata(dev);
 128         struct amdgpu_device *adev = ddev->dev_private;
 129         uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
 130
 131         return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
 132 }
 133
 134 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
 135                 amdgpu_device_get_pcie_replay_count, NULL);
 136
 137 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 138
 139 /**
 140  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
 141  *
 142  * @dev: drm_device pointer
 143  *
 144  * Returns true if the device is a dGPU with HG/PX power control,
 145  * otherwise return false.
 146  */
 147 bool amdgpu_device_is_px(struct drm_device *dev)
 148 {
 149         struct amdgpu_device *adev = dev->dev_private;
 150
 151         if (adev->flags & AMD_IS_PX)
 152                 return true;
 153         return false;
 154 }
 155
 156 /*
 157  * MMIO register access helper functions.
 158  */
 159 /**
 160  * amdgpu_mm_rreg - read a memory mapped IO register
 161  *
 162  * @adev: amdgpu_device pointer
 163  * @reg: dword aligned register offset
 164  * @acc_flags: access flags which require special behavior
 165  *
 166  * Returns the 32 bit value from the offset specified.
 167  */
 168 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 169                         uint32_t acc_flags)
 170 {
 171         uint32_t ret;
 172
 173         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 174                 return amdgpu_virt_kiq_rreg(adev, reg);
 175
 176         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 177                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 178         else {
 179                 unsigned long flags;
 180
 181                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 182                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 183                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 184                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 185         }
 186         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 187         return ret;
 188 }
 189
 190 /*
 191  * MMIO register read with bytes helper functions
 192  * @offset:bytes offset from MMIO start
 193  *
 194 */
 195
 196 /**
 197  * amdgpu_mm_rreg8 - read a memory mapped IO register
 198  *
 199  * @adev: amdgpu_device pointer
 200  * @offset: byte aligned register offset
 201  *
 202  * Returns the 8 bit value from the offset specified.
 203  */
 204 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 205         if (offset < adev->rmmio_size)
 206                 return (readb(adev->rmmio + offset));
 207         BUG();
 208 }
 209
 210 /*
 211  * MMIO register write with bytes helper functions
 212  * @offset:bytes offset from MMIO start
 213  * @value: the value want to be written to the register
 214  *
 215 */
 216 /**
 217  * amdgpu_mm_wreg8 - read a memory mapped IO register
 218  *
 219  * @adev: amdgpu_device pointer
 220  * @offset: byte aligned register offset
 221  * @value: 8 bit value to write
 222  *
 223  * Writes the value specified to the offset specified.
 224  */
 225 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 226         if (offset < adev->rmmio_size)
 227                 writeb(value, adev->rmmio + offset);
 228         else
 229                 BUG();
 230 }
 231
 232 /**
 233  * amdgpu_mm_wreg - write to a memory mapped IO register
 234  *
 235  * @adev: amdgpu_device pointer
 236  * @reg: dword aligned register offset
 237  * @v: 32 bit value to write to the register
 238  * @acc_flags: access flags which require special behavior
 239  *
 240  * Writes the value specified to the offset specified.
 241  */
 242 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 243                     uint32_t acc_flags)
 244 {
 245         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 246
 247         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 248                 adev->last_mm_index = v;
 249         }
 250
 251         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 252                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 253
 254         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 255                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 256         else {
 257                 unsigned long flags;
 258
 259                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 260                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 261                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 262                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 263         }
 264
 265         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 266                 udelay(500);
 267         }
 268 }
 269
 270 /**
 271  * amdgpu_io_rreg - read an IO register
 272  *
 273  * @adev: amdgpu_device pointer
 274  * @reg: dword aligned register offset
 275  *
 276  * Returns the 32 bit value from the offset specified.
 277  */
 278 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 279 {
 280         if ((reg * 4) < adev->rio_mem_size)
 281                 return ioread32(adev->rio_mem + (reg * 4));
 282         else {
 283                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 284                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 285         }
 286 }
 287
 288 /**
 289  * amdgpu_io_wreg - write to an IO register
 290  *
 291  * @adev: amdgpu_device pointer
 292  * @reg: dword aligned register offset
 293  * @v: 32 bit value to write to the register
 294  *
 295  * Writes the value specified to the offset specified.
 296  */
 297 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 298 {
 299         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 300                 adev->last_mm_index = v;
 301         }
 302
 303         if ((reg * 4) < adev->rio_mem_size)
 304                 iowrite32(v, adev->rio_mem + (reg * 4));
 305         else {
 306                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 307                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 308         }
 309
 310         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 311                 udelay(500);
 312         }
 313 }
 314
 315 /**
 316  * amdgpu_mm_rdoorbell - read a doorbell dword
 317  *
 318  * @adev: amdgpu_device pointer
 319  * @index: doorbell index
 320  *
 321  * Returns the value in the doorbell aperture at the
 322  * requested doorbell index (CIK).
 323  */
 324 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 325 {
 326         if (index < adev->doorbell.num_doorbells) {
 327                 return readl(adev->doorbell.ptr + index);
 328         } else {
 329                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 330                 return 0;
 331         }
 332 }
 333
 334 /**
 335  * amdgpu_mm_wdoorbell - write a doorbell dword
 336  *
 337  * @adev: amdgpu_device pointer
 338  * @index: doorbell index
 339  * @v: value to write
 340  *
 341  * Writes @v to the doorbell aperture at the
 342  * requested doorbell index (CIK).
 343  */
 344 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 345 {
 346         if (index < adev->doorbell.num_doorbells) {
 347                 writel(v, adev->doorbell.ptr + index);
 348         } else {
 349                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 350         }
 351 }
 352
 353 /**
 354  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 355  *
 356  * @adev: amdgpu_device pointer
 357  * @index: doorbell index
 358  *
 359  * Returns the value in the doorbell aperture at the
 360  * requested doorbell index (VEGA10+).
 361  */
 362 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 363 {
 364         if (index < adev->doorbell.num_doorbells) {
 365                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 366         } else {
 367                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 368                 return 0;
 369         }
 370 }
 371
 372 /**
 373  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 374  *
 375  * @adev: amdgpu_device pointer
 376  * @index: doorbell index
 377  * @v: value to write
 378  *
 379  * Writes @v to the doorbell aperture at the
 380  * requested doorbell index (VEGA10+).
 381  */
 382 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 383 {
 384         if (index < adev->doorbell.num_doorbells) {
 385                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 386         } else {
 387                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 388         }
 389 }
 390
 391 /**
 392  * amdgpu_invalid_rreg - dummy reg read function
 393  *
 394  * @adev: amdgpu device pointer
 395  * @reg: offset of register
 396  *
 397  * Dummy register read function.  Used for register blocks
 398  * that certain asics don't have (all asics).
 399  * Returns the value in the register.
 400  */
 401 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 402 {
 403         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 404         BUG();
 405         return 0;
 406 }
 407
 408 /**
 409  * amdgpu_invalid_wreg - dummy reg write function
 410  *
 411  * @adev: amdgpu device pointer
 412  * @reg: offset of register
 413  * @v: value to write to the register
 414  *
 415  * Dummy register read function.  Used for register blocks
 416  * that certain asics don't have (all asics).
 417  */
 418 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 419 {
 420         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 421                   reg, v);
 422         BUG();
 423 }
 424
 425 /**
 426  * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
 427  *
 428  * @adev: amdgpu device pointer
 429  * @reg: offset of register
 430  *
 431  * Dummy register read function.  Used for register blocks
 432  * that certain asics don't have (all asics).
 433  * Returns the value in the register.
 434  */
 435 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
 436 {
 437         DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
 438         BUG();
 439         return 0;
 440 }
 441
 442 /**
 443  * amdgpu_invalid_wreg64 - dummy reg write function
 444  *
 445  * @adev: amdgpu device pointer
 446  * @reg: offset of register
 447  * @v: value to write to the register
 448  *
 449  * Dummy register read function.  Used for register blocks
 450  * that certain asics don't have (all asics).
 451  */
 452 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
 453 {
 454         DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
 455                   reg, v);
 456         BUG();
 457 }
 458
 459 /**
 460  * amdgpu_block_invalid_rreg - dummy reg read function
 461  *
 462  * @adev: amdgpu device pointer
 463  * @block: offset of instance
 464  * @reg: offset of register
 465  *
 466  * Dummy register read function.  Used for register blocks
 467  * that certain asics don't have (all asics).
 468  * Returns the value in the register.
 469  */
 470 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 471                                           uint32_t block, uint32_t reg)
 472 {
 473         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 474                   reg, block);
 475         BUG();
 476         return 0;
 477 }
 478
 479 /**
 480  * amdgpu_block_invalid_wreg - dummy reg write function
 481  *
 482  * @adev: amdgpu device pointer
 483  * @block: offset of instance
 484  * @reg: offset of register
 485  * @v: value to write to the register
 486  *
 487  * Dummy register read function.  Used for register blocks
 488  * that certain asics don't have (all asics).
 489  */
 490 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 491                                       uint32_t block,
 492                                       uint32_t reg, uint32_t v)
 493 {
 494         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 495                   reg, block, v);
 496         BUG();
 497 }
 498
 499 /**
 500  * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
 501  *
 502  * @adev: amdgpu device pointer
 503  *
 504  * Allocates a scratch page of VRAM for use by various things in the
 505  * driver.
 506  */
 507 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 508 {
 509         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 510                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 511                                        &adev->vram_scratch.robj,
 512                                        &adev->vram_scratch.gpu_addr,
 513                                        (void **)&adev->vram_scratch.ptr);
 514 }
 515
 516 /**
 517  * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
 518  *
 519  * @adev: amdgpu device pointer
 520  *
 521  * Frees the VRAM scratch page.
 522  */
 523 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 524 {
 525         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 526 }
 527
 528 /**
 529  * amdgpu_device_program_register_sequence - program an array of registers.
 530  *
 531  * @adev: amdgpu_device pointer
 532  * @registers: pointer to the register array
 533  * @array_size: size of the register array
 534  *
 535  * Programs an array or registers with and and or masks.
 536  * This is a helper for setting golden registers.
 537  */
 538 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 539                                              const u32 *registers,
 540                                              const u32 array_size)
 541 {
 542         u32 tmp, reg, and_mask, or_mask;
 543         int i;
 544
 545         if (array_size % 3)
 546                 return;
 547
 548         for (i = 0; i < array_size; i +=3) {
 549                 reg = registers[i + 0];
 550                 and_mask = registers[i + 1];
 551                 or_mask = registers[i + 2];
 552
 553                 if (and_mask == 0xffffffff) {
 554                         tmp = or_mask;
 555                 } else {
 556                         tmp = RREG32(reg);
 557                         tmp &= ~and_mask;
 558                         if (adev->family >= AMDGPU_FAMILY_AI)
 559                                 tmp |= (or_mask & and_mask);
 560                         else
 561                                 tmp |= or_mask;
 562                 }
 563                 WREG32(reg, tmp);
 564         }
 565 }
 566
 567 /**
 568  * amdgpu_device_pci_config_reset - reset the GPU
 569  *
 570  * @adev: amdgpu_device pointer
 571  *
 572  * Resets the GPU using the pci config reset sequence.
 573  * Only applicable to asics prior to vega10.
 574  */
 575 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 576 {
 577         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 578 }
 579
 580 /*
 581  * GPU doorbell aperture helpers function.
 582  */
 583 /**
 584  * amdgpu_device_doorbell_init - Init doorbell driver information.
 585  *
 586  * @adev: amdgpu_device pointer
 587  *
 588  * Init doorbell driver information (CIK)
 589  * Returns 0 on success, error on failure.
 590  */
 591 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 592 {
 593
 594         /* No doorbell on SI hardware generation */
 595         if (adev->asic_type < CHIP_BONAIRE) {
 596                 adev->doorbell.base = 0;
 597                 adev->doorbell.size = 0;
 598                 adev->doorbell.num_doorbells = 0;
 599                 adev->doorbell.ptr = NULL;
 600                 return 0;
 601         }
 602
 603         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 604                 return -EINVAL;
 605
 606         amdgpu_asic_init_doorbell_index(adev);
 607
 608         /* doorbell bar mapping */
 609         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 610         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 611
 612         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 613                                              adev->doorbell_index.max_assignment+1);
 614         if (adev->doorbell.num_doorbells == 0)
 615                 return -EINVAL;
 616
 617         /* For Vega, reserve and map two pages on doorbell BAR since SDMA
 618          * paging queue doorbell use the second page. The
 619          * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
 620          * doorbells are in the first page. So with paging queue enabled,
 621          * the max num_doorbells should + 1 page (0x400 in dword)
 622          */
 623         if (adev->asic_type >= CHIP_VEGA10)
 624                 adev->doorbell.num_doorbells += 0x400;
 625
 626         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 627                                      adev->doorbell.num_doorbells *
 628                                      sizeof(u32));
 629         if (adev->doorbell.ptr == NULL)
 630                 return -ENOMEM;
 631
 632         return 0;
 633 }
 634
 635 /**
 636  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 637  *
 638  * @adev: amdgpu_device pointer
 639  *
 640  * Tear down doorbell driver information (CIK)
 641  */
 642 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 643 {
 644         iounmap(adev->doorbell.ptr);
 645         adev->doorbell.ptr = NULL;
 646 }
 647
 648
 649
 650 /*
 651  * amdgpu_device_wb_*()
 652  * Writeback is the method by which the GPU updates special pages in memory
 653  * with the status of certain GPU events (fences, ring pointers,etc.).
 654  */
 655
 656 /**
 657  * amdgpu_device_wb_fini - Disable Writeback and free memory
 658  *
 659  * @adev: amdgpu_device pointer
 660  *
 661  * Disables Writeback and frees the Writeback memory (all asics).
 662  * Used at driver shutdown.
 663  */
 664 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 665 {
 666         if (adev->wb.wb_obj) {
 667                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 668                                       &adev->wb.gpu_addr,
 669                                       (void **)&adev->wb.wb);
 670                 adev->wb.wb_obj = NULL;
 671         }
 672 }
 673
 674 /**
 675  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 676  *
 677  * @adev: amdgpu_device pointer
 678  *
 679  * Initializes writeback and allocates writeback memory (all asics).
 680  * Used at driver startup.
 681  * Returns 0 on success or an -error on failure.
 682  */
 683 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 684 {
 685         int r;
 686
 687         if (adev->wb.wb_obj == NULL) {
 688                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 689                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 690                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 691                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 692                                             (void **)&adev->wb.wb);
 693                 if (r) {
 694                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 695                         return r;
 696                 }
 697
 698                 adev->wb.num_wb = AMDGPU_MAX_WB;
 699                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 700
 701                 /* clear wb memory */
 702                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
 703         }
 704
 705         return 0;
 706 }
 707
 708 /**
 709  * amdgpu_device_wb_get - Allocate a wb entry
 710  *
 711  * @adev: amdgpu_device pointer
 712  * @wb: wb index
 713  *
 714  * Allocate a wb slot for use by the driver (all asics).
 715  * Returns 0 on success or -EINVAL on failure.
 716  */
 717 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 718 {
 719         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 720
 721         if (offset < adev->wb.num_wb) {
 722                 __set_bit(offset, adev->wb.used);
 723                 *wb = offset << 3; /* convert to dw offset */
 724                 return 0;
 725         } else {
 726                 return -EINVAL;
 727         }
 728 }
 729
 730 /**
 731  * amdgpu_device_wb_free - Free a wb entry
 732  *
 733  * @adev: amdgpu_device pointer
 734  * @wb: wb index
 735  *
 736  * Free a wb slot allocated for use by the driver (all asics)
 737  */
 738 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 739 {
 740         wb >>= 3;
 741         if (wb < adev->wb.num_wb)
 742                 __clear_bit(wb, adev->wb.used);
 743 }
 744
 745 /**
 746  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 747  *
 748  * @adev: amdgpu_device pointer
 749  *
 750  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 751  * to fail, but if any of the BARs is not accessible after the size we abort
 752  * driver loading by returning -ENODEV.
 753  */
 754 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 755 {
 756         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 757         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 758         struct pci_bus *root;
 759         struct resource *res;
 760         unsigned i;
 761         u16 cmd;
 762         int r;
 763
 764         /* Bypass for VF */
 765         if (amdgpu_sriov_vf(adev))
 766                 return 0;
 767
 768         /* Check if the root BUS has 64bit memory resources */
 769         root = adev->pdev->bus;
 770         while (root->parent)
 771                 root = root->parent;
 772
 773         pci_bus_for_each_resource(root, res, i) {
 774                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 775                     res->start > 0x100000000ull)
 776                         break;
 777         }
 778
 779         /* Trying to resize is pointless without a root hub window above 4GB */
 780         if (!res)
 781                 return 0;
 782
 783         /* Disable memory decoding while we change the BAR addresses and size */
 784         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 785         pci_write_config_word(adev->pdev, PCI_COMMAND,
 786                               cmd & ~PCI_COMMAND_MEMORY);
 787
 788         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 789         amdgpu_device_doorbell_fini(adev);
 790         if (adev->asic_type >= CHIP_BONAIRE)
 791                 pci_release_resource(adev->pdev, 2);
 792
 793         pci_release_resource(adev->pdev, 0);
 794
 795         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 796         if (r == -ENOSPC)
 797                 DRM_INFO("Not enough PCI address space for a large BAR.");
 798         else if (r && r != -ENOTSUPP)
 799                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 800
 801         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 802
 803         /* When the doorbell or fb BAR isn't available we have no chance of
 804          * using the device.
 805          */
 806         r = amdgpu_device_doorbell_init(adev);
 807         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 808                 return -ENODEV;
 809
 810         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 811
 812         return 0;
 813 }
 814
 815 /*
 816  * GPU helpers function.
 817  */
 818 /**
 819  * amdgpu_device_need_post - check if the hw need post or not
 820  *
 821  * @adev: amdgpu_device pointer
 822  *
 823  * Check if the asic has been initialized (all asics) at driver startup
 824  * or post is needed if  hw reset is performed.
 825  * Returns true if need or false if not.
 826  */
 827 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 828 {
 829         uint32_t reg;
 830
 831         if (amdgpu_sriov_vf(adev))
 832                 return false;
 833
 834         if (amdgpu_passthrough(adev)) {
 835                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 836                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 837                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 838                  * vpost executed for smc version below 22.15
 839                  */
 840                 if (adev->asic_type == CHIP_FIJI) {
 841                         int err;
 842                         uint32_t fw_ver;
 843                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 844                         /* force vPost if error occured */
 845                         if (err)
 846                                 return true;
 847
 848                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 849                         if (fw_ver < 0x00160e00)
 850                                 return true;
 851                 }
 852         }
 853
 854         if (adev->has_hw_reset) {
 855                 adev->has_hw_reset = false;
 856                 return true;
 857         }
 858
 859         /* bios scratch used on CIK+ */
 860         if (adev->asic_type >= CHIP_BONAIRE)
 861                 return amdgpu_atombios_scratch_need_asic_init(adev);
 862
 863         /* check MEM_SIZE for older asics */
 864         reg = amdgpu_asic_get_config_memsize(adev);
 865
 866         if ((reg != 0) && (reg != 0xffffffff))
 867                 return false;
 868
 869         return true;
 870 }
 871
 872 /* if we get transitioned to only one device, take VGA back */
 873 /**
 874  * amdgpu_device_vga_set_decode - enable/disable vga decode
 875  *
 876  * @cookie: amdgpu_device pointer
 877  * @state: enable/disable vga decode
 878  *
 879  * Enable/disable vga decode (all asics).
 880  * Returns VGA resource flags.
 881  */
 882 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 883 {
 884         struct amdgpu_device *adev = cookie;
 885         amdgpu_asic_set_vga_state(adev, state);
 886         if (state)
 887                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 888                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 889         else
 890                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 891 }
 892
 893 /**
 894  * amdgpu_device_check_block_size - validate the vm block size
 895  *
 896  * @adev: amdgpu_device pointer
 897  *
 898  * Validates the vm block size specified via module parameter.
 899  * The vm block size defines number of bits in page table versus page directory,
 900  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 901  * page table and the remaining bits are in the page directory.
 902  */
 903 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 904 {
 905         /* defines number of bits in page table versus page directory,
 906          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 907          * page table and the remaining bits are in the page directory */
 908         if (amdgpu_vm_block_size == -1)
 909                 return;
 910
 911         if (amdgpu_vm_block_size < 9) {
 912                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 913                          amdgpu_vm_block_size);
 914                 amdgpu_vm_block_size = -1;
 915         }
 916 }
 917
 918 /**
 919  * amdgpu_device_check_vm_size - validate the vm size
 920  *
 921  * @adev: amdgpu_device pointer
 922  *
 923  * Validates the vm size in GB specified via module parameter.
 924  * The VM size is the size of the GPU virtual memory space in GB.
 925  */
 926 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 927 {
 928         /* no need to check the default value */
 929         if (amdgpu_vm_size == -1)
 930                 return;
 931
 932         if (amdgpu_vm_size < 1) {
 933                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 934                          amdgpu_vm_size);
 935                 amdgpu_vm_size = -1;
 936         }
 937 }
 938
 939 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
 940 {
 941         struct sysinfo si;
 942         bool is_os_64 = (sizeof(void *) == 8) ? true : false;
 943         uint64_t total_memory;
 944         uint64_t dram_size_seven_GB = 0x1B8000000;
 945         uint64_t dram_size_three_GB = 0xB8000000;
 946
 947         if (amdgpu_smu_memory_pool_size == 0)
 948                 return;
 949
 950         if (!is_os_64) {
 951                 DRM_WARN("Not 64-bit OS, feature not supported\n");
 952                 goto def_value;
 953         }
 954         si_meminfo(&si);
 955         total_memory = (uint64_t)si.totalram * si.mem_unit;
 956
 957         if ((amdgpu_smu_memory_pool_size == 1) ||
 958                 (amdgpu_smu_memory_pool_size == 2)) {
 959                 if (total_memory < dram_size_three_GB)
 960                         goto def_value1;
 961         } else if ((amdgpu_smu_memory_pool_size == 4) ||
 962                 (amdgpu_smu_memory_pool_size == 8)) {
 963                 if (total_memory < dram_size_seven_GB)
 964                         goto def_value1;
 965         } else {
 966                 DRM_WARN("Smu memory pool size not supported\n");
 967                 goto def_value;
 968         }
 969         adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
 970
 971         return;
 972
 973 def_value1:
 974         DRM_WARN("No enough system memory\n");
 975 def_value:
 976         adev->pm.smu_prv_buffer_size = 0;
 977 }
 978
 979 /**
 980  * amdgpu_device_check_arguments - validate module params
 981  *
 982  * @adev: amdgpu_device pointer
 983  *
 984  * Validates certain module parameters and updates
 985  * the associated values used by the driver (all asics).
 986  */
 987 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
 988 {
 989         int ret = 0;
 990
 991         if (amdgpu_sched_jobs < 4) {
 992                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 993                          amdgpu_sched_jobs);
 994                 amdgpu_sched_jobs = 4;
 995         } else if (!is_power_of_2(amdgpu_sched_jobs)){
 996                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 997                          amdgpu_sched_jobs);
 998                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 999         }
1000
1001         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1002                 /* gart size must be greater or equal to 32M */
1003                 dev_warn(adev->dev, "gart size (%d) too small\n",
1004                          amdgpu_gart_size);
1005                 amdgpu_gart_size = -1;
1006         }
1007
1008         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1009                 /* gtt size must be greater or equal to 32M */
1010                 dev_warn(adev->dev, "gtt size (%d) too small\n",
1011                                  amdgpu_gtt_size);
1012                 amdgpu_gtt_size = -1;
1013         }
1014
1015         /* valid range is between 4 and 9 inclusive */
1016         if (amdgpu_vm_fragment_size != -1 &&
1017             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1018                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1019                 amdgpu_vm_fragment_size = -1;
1020         }
1021
1022         amdgpu_device_check_smu_prv_buffer_size(adev);
1023
1024         amdgpu_device_check_vm_size(adev);
1025
1026         amdgpu_device_check_block_size(adev);
1027
1028         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1029
1030         return ret;
1031 }
1032
1033 /**
1034  * amdgpu_switcheroo_set_state - set switcheroo state
1035  *
1036  * @pdev: pci dev pointer
1037  * @state: vga_switcheroo state
1038  *
1039  * Callback for the switcheroo driver.  Suspends or resumes the
1040  * the asics before or after it is powered up using ACPI methods.
1041  */
1042 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1043 {
1044         struct drm_device *dev = pci_get_drvdata(pdev);
1045
1046         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1047                 return;
1048
1049         if (state == VGA_SWITCHEROO_ON) {
1050                 pr_info("amdgpu: switched on\n");
1051                 /* don't suspend or resume card normally */
1052                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1053
1054                 amdgpu_device_resume(dev, true, true);
1055
1056                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1057                 drm_kms_helper_poll_enable(dev);
1058         } else {
1059                 pr_info("amdgpu: switched off\n");
1060                 drm_kms_helper_poll_disable(dev);
1061                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1062                 amdgpu_device_suspend(dev, true, true);
1063                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1064         }
1065 }
1066
1067 /**
1068  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1069  *
1070  * @pdev: pci dev pointer
1071  *
1072  * Callback for the switcheroo driver.  Check of the switcheroo
1073  * state can be changed.
1074  * Returns true if the state can be changed, false if not.
1075  */
1076 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1077 {
1078         struct drm_device *dev = pci_get_drvdata(pdev);
1079
1080         /*
1081         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1082         * locking inversion with the driver load path. And the access here is
1083         * completely racy anyway. So don't bother with locking for now.
1084         */
1085         return dev->open_count == 0;
1086 }
1087
1088 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1089         .set_gpu_state = amdgpu_switcheroo_set_state,
1090         .reprobe = NULL,
1091         .can_switch = amdgpu_switcheroo_can_switch,
1092 };
1093
1094 /**
1095  * amdgpu_device_ip_set_clockgating_state - set the CG state
1096  *
1097  * @dev: amdgpu_device pointer
1098  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1099  * @state: clockgating state (gate or ungate)
1100  *
1101  * Sets the requested clockgating state for all instances of
1102  * the hardware IP specified.
1103  * Returns the error code from the last instance.
1104  */
1105 int amdgpu_device_ip_set_clockgating_state(void *dev,
1106                                            enum amd_ip_block_type block_type,
1107                                            enum amd_clockgating_state state)
1108 {
1109         struct amdgpu_device *adev = dev;
1110         int i, r = 0;
1111
1112         for (i = 0; i < adev->num_ip_blocks; i++) {
1113                 if (!adev->ip_blocks[i].status.valid)
1114                         continue;
1115                 if (adev->ip_blocks[i].version->type != block_type)
1116                         continue;
1117                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1118                         continue;
1119                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1120                         (void *)adev, state);
1121                 if (r)
1122                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1123                                   adev->ip_blocks[i].version->funcs->name, r);
1124         }
1125         return r;
1126 }
1127
1128 /**
1129  * amdgpu_device_ip_set_powergating_state - set the PG state
1130  *
1131  * @dev: amdgpu_device pointer
1132  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1133  * @state: powergating state (gate or ungate)
1134  *
1135  * Sets the requested powergating state for all instances of
1136  * the hardware IP specified.
1137  * Returns the error code from the last instance.
1138  */
1139 int amdgpu_device_ip_set_powergating_state(void *dev,
1140                                            enum amd_ip_block_type block_type,
1141                                            enum amd_powergating_state state)
1142 {
1143         struct amdgpu_device *adev = dev;
1144         int i, r = 0;
1145
1146         for (i = 0; i < adev->num_ip_blocks; i++) {
1147                 if (!adev->ip_blocks[i].status.valid)
1148                         continue;
1149                 if (adev->ip_blocks[i].version->type != block_type)
1150                         continue;
1151                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1152                         continue;
1153                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1154                         (void *)adev, state);
1155                 if (r)
1156                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1157                                   adev->ip_blocks[i].version->funcs->name, r);
1158         }
1159         return r;
1160 }
1161
1162 /**
1163  * amdgpu_device_ip_get_clockgating_state - get the CG state
1164  *
1165  * @adev: amdgpu_device pointer
1166  * @flags: clockgating feature flags
1167  *
1168  * Walks the list of IPs on the device and updates the clockgating
1169  * flags for each IP.
1170  * Updates @flags with the feature flags for each hardware IP where
1171  * clockgating is enabled.
1172  */
1173 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1174                                             u32 *flags)
1175 {
1176         int i;
1177
1178         for (i = 0; i < adev->num_ip_blocks; i++) {
1179                 if (!adev->ip_blocks[i].status.valid)
1180                         continue;
1181                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1182                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1183         }
1184 }
1185
1186 /**
1187  * amdgpu_device_ip_wait_for_idle - wait for idle
1188  *
1189  * @adev: amdgpu_device pointer
1190  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1191  *
1192  * Waits for the request hardware IP to be idle.
1193  * Returns 0 for success or a negative error code on failure.
1194  */
1195 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1196                                    enum amd_ip_block_type block_type)
1197 {
1198         int i, r;
1199
1200         for (i = 0; i < adev->num_ip_blocks; i++) {
1201                 if (!adev->ip_blocks[i].status.valid)
1202                         continue;
1203                 if (adev->ip_blocks[i].version->type == block_type) {
1204                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1205                         if (r)
1206                                 return r;
1207                         break;
1208                 }
1209         }
1210         return 0;
1211
1212 }
1213
1214 /**
1215  * amdgpu_device_ip_is_idle - is the hardware IP idle
1216  *
1217  * @adev: amdgpu_device pointer
1218  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1219  *
1220  * Check if the hardware IP is idle or not.
1221  * Returns true if it the IP is idle, false if not.
1222  */
1223 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1224                               enum amd_ip_block_type block_type)
1225 {
1226         int i;
1227
1228         for (i = 0; i < adev->num_ip_blocks; i++) {
1229                 if (!adev->ip_blocks[i].status.valid)
1230                         continue;
1231                 if (adev->ip_blocks[i].version->type == block_type)
1232                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1233         }
1234         return true;
1235
1236 }
1237
1238 /**
1239  * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1240  *
1241  * @adev: amdgpu_device pointer
1242  * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1243  *
1244  * Returns a pointer to the hardware IP block structure
1245  * if it exists for the asic, otherwise NULL.
1246  */
1247 struct amdgpu_ip_block *
1248 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1249                               enum amd_ip_block_type type)
1250 {
1251         int i;
1252
1253         for (i = 0; i < adev->num_ip_blocks; i++)
1254                 if (adev->ip_blocks[i].version->type == type)
1255                         return &adev->ip_blocks[i];
1256
1257         return NULL;
1258 }
1259
1260 /**
1261  * amdgpu_device_ip_block_version_cmp
1262  *
1263  * @adev: amdgpu_device pointer
1264  * @type: enum amd_ip_block_type
1265  * @major: major version
1266  * @minor: minor version
1267  *
1268  * return 0 if equal or greater
1269  * return 1 if smaller or the ip_block doesn't exist
1270  */
1271 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1272                                        enum amd_ip_block_type type,
1273                                        u32 major, u32 minor)
1274 {
1275         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1276
1277         if (ip_block && ((ip_block->version->major > major) ||
1278                         ((ip_block->version->major == major) &&
1279                         (ip_block->version->minor >= minor))))
1280                 return 0;
1281
1282         return 1;
1283 }
1284
1285 /**
1286  * amdgpu_device_ip_block_add
1287  *
1288  * @adev: amdgpu_device pointer
1289  * @ip_block_version: pointer to the IP to add
1290  *
1291  * Adds the IP block driver information to the collection of IPs
1292  * on the asic.
1293  */
1294 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1295                                const struct amdgpu_ip_block_version *ip_block_version)
1296 {
1297         if (!ip_block_version)
1298                 return -EINVAL;
1299
1300         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1301                   ip_block_version->funcs->name);
1302
1303         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1304
1305         return 0;
1306 }
1307
1308 /**
1309  * amdgpu_device_enable_virtual_display - enable virtual display feature
1310  *
1311  * @adev: amdgpu_device pointer
1312  *
1313  * Enabled the virtual display feature if the user has enabled it via
1314  * the module parameter virtual_display.  This feature provides a virtual
1315  * display hardware on headless boards or in virtualized environments.
1316  * This function parses and validates the configuration string specified by
1317  * the user and configues the virtual display configuration (number of
1318  * virtual connectors, crtcs, etc.) specified.
1319  */
1320 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1321 {
1322         adev->enable_virtual_display = false;
1323
1324         if (amdgpu_virtual_display) {
1325                 struct drm_device *ddev = adev->ddev;
1326                 const char *pci_address_name = pci_name(ddev->pdev);
1327                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1328
1329                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1330                 pciaddstr_tmp = pciaddstr;
1331                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1332                         pciaddname = strsep(&pciaddname_tmp, ",");
1333                         if (!strcmp("all", pciaddname)
1334                             || !strcmp(pci_address_name, pciaddname)) {
1335                                 long num_crtc;
1336                                 int res = -1;
1337
1338                                 adev->enable_virtual_display = true;
1339
1340                                 if (pciaddname_tmp)
1341                                         res = kstrtol(pciaddname_tmp, 10,
1342                                                       &num_crtc);
1343
1344                                 if (!res) {
1345                                         if (num_crtc < 1)
1346                                                 num_crtc = 1;
1347                                         if (num_crtc > 6)
1348                                                 num_crtc = 6;
1349                                         adev->mode_info.num_crtc = num_crtc;
1350                                 } else {
1351                                         adev->mode_info.num_crtc = 1;
1352                                 }
1353                                 break;
1354                         }
1355                 }
1356
1357                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1358                          amdgpu_virtual_display, pci_address_name,
1359                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1360
1361                 kfree(pciaddstr);
1362         }
1363 }
1364
1365 /**
1366  * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1367  *
1368  * @adev: amdgpu_device pointer
1369  *
1370  * Parses the asic configuration parameters specified in the gpu info
1371  * firmware and makes them availale to the driver for use in configuring
1372  * the asic.
1373  * Returns 0 on success, -EINVAL on failure.
1374  */
1375 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1376 {
1377         const char *chip_name;
1378         char fw_name[30];
1379         int err;
1380         const struct gpu_info_firmware_header_v1_0 *hdr;
1381
1382         adev->firmware.gpu_info_fw = NULL;
1383
1384         switch (adev->asic_type) {
1385         case CHIP_TOPAZ:
1386         case CHIP_TONGA:
1387         case CHIP_FIJI:
1388         case CHIP_POLARIS10:
1389         case CHIP_POLARIS11:
1390         case CHIP_POLARIS12:
1391         case CHIP_VEGAM:
1392         case CHIP_CARRIZO:
1393         case CHIP_STONEY:
1394 #ifdef CONFIG_DRM_AMDGPU_SI
1395         case CHIP_VERDE:
1396         case CHIP_TAHITI:
1397         case CHIP_PITCAIRN:
1398         case CHIP_OLAND:
1399         case CHIP_HAINAN:
1400 #endif
1401 #ifdef CONFIG_DRM_AMDGPU_CIK
1402         case CHIP_BONAIRE:
1403         case CHIP_HAWAII:
1404         case CHIP_KAVERI:
1405         case CHIP_KABINI:
1406         case CHIP_MULLINS:
1407 #endif
1408         case CHIP_VEGA20:
1409         default:
1410                 return 0;
1411         case CHIP_VEGA10:
1412                 chip_name = "vega10";
1413                 break;
1414         case CHIP_VEGA12:
1415                 chip_name = "vega12";
1416                 break;
1417         case CHIP_RAVEN:
1418                 if (adev->rev_id >= 8)
1419                         chip_name = "raven2";
1420                 else if (adev->pdev->device == 0x15d8)
1421                         chip_name = "picasso";
1422                 else
1423                         chip_name = "raven";
1424                 break;
1425         case CHIP_ARCTURUS:
1426                 chip_name = "arcturus";
1427                 break;
1428         case CHIP_RENOIR:
1429                 chip_name = "renoir";
1430                 break;
1431         case CHIP_NAVI10:
1432                 chip_name = "navi10";
1433                 break;
1434         case CHIP_NAVI14:
1435                 chip_name = "navi14";
1436                 break;
1437         case CHIP_NAVI12:
1438                 chip_name = "navi12";
1439                 break;
1440         }
1441
1442         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1443         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1444         if (err) {
1445                 dev_err(adev->dev,
1446                         "Failed to load gpu_info firmware \"%s\"\n",
1447                         fw_name);
1448                 goto out;
1449         }
1450         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1451         if (err) {
1452                 dev_err(adev->dev,
1453                         "Failed to validate gpu_info firmware \"%s\"\n",
1454                         fw_name);
1455                 goto out;
1456         }
1457
1458         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1459         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1460
1461         switch (hdr->version_major) {
1462         case 1:
1463         {
1464                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1465                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1466                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1467
1468                 if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
1469                         goto parse_soc_bounding_box;
1470
1471                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1472                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1473                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1474                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1475                 adev->gfx.config.max_texture_channel_caches =
1476                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1477                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1478                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1479                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1480                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1481                 adev->gfx.config.double_offchip_lds_buf =
1482                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1483                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1484                 adev->gfx.cu_info.max_waves_per_simd =
1485                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1486                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1487                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1488                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1489                 if (hdr->version_minor >= 1) {
1490                         const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1491                                 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1492                                                                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1493                         adev->gfx.config.num_sc_per_sh =
1494                                 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1495                         adev->gfx.config.num_packer_per_sc =
1496                                 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1497                 }
1498
1499 parse_soc_bounding_box:
1500 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
1501                 /*
1502                  * soc bounding box info is not integrated in disocovery table,
1503                  * we always need to parse it from gpu info firmware.
1504                  */
1505                 if (hdr->version_minor == 2) {
1506                         const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1507                                 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1508                                                                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1509                         adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1510                 }
1511 #endif
1512                 break;
1513         }
1514         default:
1515                 dev_err(adev->dev,
1516                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1517                 err = -EINVAL;
1518                 goto out;
1519         }
1520 out:
1521         return err;
1522 }
1523
1524 /**
1525  * amdgpu_device_ip_early_init - run early init for hardware IPs
1526  *
1527  * @adev: amdgpu_device pointer
1528  *
1529  * Early initialization pass for hardware IPs.  The hardware IPs that make
1530  * up each asic are discovered each IP's early_init callback is run.  This
1531  * is the first stage in initializing the asic.
1532  * Returns 0 on success, negative error code on failure.
1533  */
1534 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1535 {
1536         int i, r;
1537
1538         amdgpu_device_enable_virtual_display(adev);
1539
1540         switch (adev->asic_type) {
1541         case CHIP_TOPAZ:
1542         case CHIP_TONGA:
1543         case CHIP_FIJI:
1544         case CHIP_POLARIS10:
1545         case CHIP_POLARIS11:
1546         case CHIP_POLARIS12:
1547         case CHIP_VEGAM:
1548         case CHIP_CARRIZO:
1549         case CHIP_STONEY:
1550                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1551                         adev->family = AMDGPU_FAMILY_CZ;
1552                 else
1553                         adev->family = AMDGPU_FAMILY_VI;
1554
1555                 r = vi_set_ip_blocks(adev);
1556                 if (r)
1557                         return r;
1558                 break;
1559 #ifdef CONFIG_DRM_AMDGPU_SI
1560         case CHIP_VERDE:
1561         case CHIP_TAHITI:
1562         case CHIP_PITCAIRN:
1563         case CHIP_OLAND:
1564         case CHIP_HAINAN:
1565                 adev->family = AMDGPU_FAMILY_SI;
1566                 r = si_set_ip_blocks(adev);
1567                 if (r)
1568                         return r;
1569                 break;
1570 #endif
1571 #ifdef CONFIG_DRM_AMDGPU_CIK
1572         case CHIP_BONAIRE:
1573         case CHIP_HAWAII:
1574         case CHIP_KAVERI:
1575         case CHIP_KABINI:
1576         case CHIP_MULLINS:
1577                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1578                         adev->family = AMDGPU_FAMILY_CI;
1579                 else
1580                         adev->family = AMDGPU_FAMILY_KV;
1581
1582                 r = cik_set_ip_blocks(adev);
1583                 if (r)
1584                         return r;
1585                 break;
1586 #endif
1587         case CHIP_VEGA10:
1588         case CHIP_VEGA12:
1589         case CHIP_VEGA20:
1590         case CHIP_RAVEN:
1591         case CHIP_ARCTURUS:
1592         case CHIP_RENOIR:
1593                 if (adev->asic_type == CHIP_RAVEN ||
1594                     adev->asic_type == CHIP_RENOIR)
1595                         adev->family = AMDGPU_FAMILY_RV;
1596                 else
1597                         adev->family = AMDGPU_FAMILY_AI;
1598
1599                 r = soc15_set_ip_blocks(adev);
1600                 if (r)
1601                         return r;
1602                 break;
1603         case  CHIP_NAVI10:
1604         case  CHIP_NAVI14:
1605         case  CHIP_NAVI12:
1606                 adev->family = AMDGPU_FAMILY_NV;
1607
1608                 r = nv_set_ip_blocks(adev);
1609                 if (r)
1610                         return r;
1611                 break;
1612         default:
1613                 /* FIXME: not supported yet */
1614                 return -EINVAL;
1615         }
1616
1617         r = amdgpu_device_parse_gpu_info_fw(adev);
1618         if (r)
1619                 return r;
1620
1621         if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
1622                 amdgpu_discovery_get_gfx_info(adev);
1623
1624         amdgpu_amdkfd_device_probe(adev);
1625
1626         if (amdgpu_sriov_vf(adev)) {
1627                 r = amdgpu_virt_request_full_gpu(adev, true);
1628                 if (r)
1629                         return -EAGAIN;
1630         }
1631
1632         adev->pm.pp_feature = amdgpu_pp_feature_mask;
1633         if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
1634                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1635
1636         for (i = 0; i < adev->num_ip_blocks; i++) {
1637                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1638                         DRM_ERROR("disabled ip block: %d <%s>\n",
1639                                   i, adev->ip_blocks[i].version->funcs->name);
1640                         adev->ip_blocks[i].status.valid = false;
1641                 } else {
1642                         if (adev->ip_blocks[i].version->funcs->early_init) {
1643                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1644                                 if (r == -ENOENT) {
1645                                         adev->ip_blocks[i].status.valid = false;
1646                                 } else if (r) {
1647                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1648                                                   adev->ip_blocks[i].version->funcs->name, r);
1649                                         return r;
1650                                 } else {
1651                                         adev->ip_blocks[i].status.valid = true;
1652                                 }
1653                         } else {
1654                                 adev->ip_blocks[i].status.valid = true;
1655                         }
1656                 }
1657                 /* get the vbios after the asic_funcs are set up */
1658                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
1659                         /* Read BIOS */
1660                         if (!amdgpu_get_bios(adev))
1661                                 return -EINVAL;
1662
1663                         r = amdgpu_atombios_init(adev);
1664                         if (r) {
1665                                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1666                                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1667                                 return r;
1668                         }
1669                 }
1670         }
1671
1672         adev->cg_flags &= amdgpu_cg_mask;
1673         adev->pg_flags &= amdgpu_pg_mask;
1674
1675         return 0;
1676 }
1677
1678 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1679 {
1680         int i, r;
1681
1682         for (i = 0; i < adev->num_ip_blocks; i++) {
1683                 if (!adev->ip_blocks[i].status.sw)
1684                         continue;
1685                 if (adev->ip_blocks[i].status.hw)
1686                         continue;
1687                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1688                     (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
1689                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1690                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1691                         if (r) {
1692                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1693                                           adev->ip_blocks[i].version->funcs->name, r);
1694                                 return r;
1695                         }
1696                         adev->ip_blocks[i].status.hw = true;
1697                 }
1698         }
1699
1700         return 0;
1701 }
1702
1703 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1704 {
1705         int i, r;
1706
1707         for (i = 0; i < adev->num_ip_blocks; i++) {
1708                 if (!adev->ip_blocks[i].status.sw)
1709                         continue;
1710                 if (adev->ip_blocks[i].status.hw)
1711                         continue;
1712                 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1713                 if (r) {
1714                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1715                                   adev->ip_blocks[i].version->funcs->name, r);
1716                         return r;
1717                 }
1718                 adev->ip_blocks[i].status.hw = true;
1719         }
1720
1721         return 0;
1722 }
1723
1724 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1725 {
1726         int r = 0;
1727         int i;
1728         uint32_t smu_version;
1729
1730         if (adev->asic_type >= CHIP_VEGA10) {
1731                 for (i = 0; i < adev->num_ip_blocks; i++) {
1732                         if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
1733                                 continue;
1734
1735                         /* no need to do the fw loading again if already done*/
1736                         if (adev->ip_blocks[i].status.hw == true)
1737                                 break;
1738
1739                         if (adev->in_gpu_reset || adev->in_suspend) {
1740                                 r = adev->ip_blocks[i].version->funcs->resume(adev);
1741                                 if (r) {
1742                                         DRM_ERROR("resume of IP block <%s> failed %d\n",
1743                                                           adev->ip_blocks[i].version->funcs->name, r);
1744                                         return r;
1745                                 }
1746                         } else {
1747                                 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1748                                 if (r) {
1749                                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1750                                                           adev->ip_blocks[i].version->funcs->name, r);
1751                                         return r;
1752                                 }
1753                         }
1754
1755                         adev->ip_blocks[i].status.hw = true;
1756                         break;
1757                 }
1758         }
1759
1760         r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
1761
1762         return r;
1763 }
1764
1765 /**
1766  * amdgpu_device_ip_init - run init for hardware IPs
1767  *
1768  * @adev: amdgpu_device pointer
1769  *
1770  * Main initialization pass for hardware IPs.  The list of all the hardware
1771  * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1772  * are run.  sw_init initializes the software state associated with each IP
1773  * and hw_init initializes the hardware associated with each IP.
1774  * Returns 0 on success, negative error code on failure.
1775  */
1776 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1777 {
1778         int i, r;
1779
1780         r = amdgpu_ras_init(adev);
1781         if (r)
1782                 return r;
1783
1784         for (i = 0; i < adev->num_ip_blocks; i++) {
1785                 if (!adev->ip_blocks[i].status.valid)
1786                         continue;
1787                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1788                 if (r) {
1789                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1790                                   adev->ip_blocks[i].version->funcs->name, r);
1791                         goto init_failed;
1792                 }
1793                 adev->ip_blocks[i].status.sw = true;
1794
1795                 /* need to do gmc hw init early so we can allocate gpu mem */
1796                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1797                         r = amdgpu_device_vram_scratch_init(adev);
1798                         if (r) {
1799                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1800                                 goto init_failed;
1801                         }
1802                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1803                         if (r) {
1804                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1805                                 goto init_failed;
1806                         }
1807                         r = amdgpu_device_wb_init(adev);
1808                         if (r) {
1809                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1810                                 goto init_failed;
1811                         }
1812                         adev->ip_blocks[i].status.hw = true;
1813
1814                         /* right after GMC hw init, we create CSA */
1815                         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1816                                 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1817                                                                 AMDGPU_GEM_DOMAIN_VRAM,
1818                                                                 AMDGPU_CSA_SIZE);
1819                                 if (r) {
1820                                         DRM_ERROR("allocate CSA failed %d\n", r);
1821                                         goto init_failed;
1822                                 }
1823                         }
1824                 }
1825         }
1826
1827         r = amdgpu_ib_pool_init(adev);
1828         if (r) {
1829                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1830                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
1831                 goto init_failed;
1832         }
1833
1834         r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1835         if (r)
1836                 goto init_failed;
1837
1838         r = amdgpu_device_ip_hw_init_phase1(adev);
1839         if (r)
1840                 goto init_failed;
1841
1842         r = amdgpu_device_fw_loading(adev);
1843         if (r)
1844                 goto init_failed;
1845
1846         r = amdgpu_device_ip_hw_init_phase2(adev);
1847         if (r)
1848                 goto init_failed;
1849
1850         if (adev->gmc.xgmi.num_physical_nodes > 1)
1851                 amdgpu_xgmi_add_device(adev);
1852         amdgpu_amdkfd_device_init(adev);
1853
1854 init_failed:
1855         if (amdgpu_sriov_vf(adev)) {
1856                 if (!r)
1857                         amdgpu_virt_init_data_exchange(adev);
1858                 amdgpu_virt_release_full_gpu(adev, true);
1859         }
1860
1861         return r;
1862 }
1863
1864 /**
1865  * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1866  *
1867  * @adev: amdgpu_device pointer
1868  *
1869  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
1870  * this function before a GPU reset.  If the value is retained after a
1871  * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.
1872  */
1873 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1874 {
1875         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1876 }
1877
1878 /**
1879  * amdgpu_device_check_vram_lost - check if vram is valid
1880  *
1881  * @adev: amdgpu_device pointer
1882  *
1883  * Checks the reset magic value written to the gart pointer in VRAM.
1884  * The driver calls this after a GPU reset to see if the contents of
1885  * VRAM is lost or now.
1886  * returns true if vram is lost, false if not.
1887  */
1888 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1889 {
1890         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1891                         AMDGPU_RESET_MAGIC_NUM);
1892 }
1893
1894 /**
1895  * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1896  *
1897  * @adev: amdgpu_device pointer
1898  *
1899  * The list of all the hardware IPs that make up the asic is walked and the
1900  * set_clockgating_state callbacks are run.
1901  * Late initialization pass enabling clockgating for hardware IPs.
1902  * Fini or suspend, pass disabling clockgating for hardware IPs.
1903  * Returns 0 on success, negative error code on failure.
1904  */
1905
1906 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1907                                                 enum amd_clockgating_state state)
1908 {
1909         int i, j, r;
1910
1911         if (amdgpu_emu_mode == 1)
1912                 return 0;
1913
1914         for (j = 0; j < adev->num_ip_blocks; j++) {
1915                 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1916                 if (!adev->ip_blocks[i].status.late_initialized)
1917                         continue;
1918                 /* skip CG for VCE/UVD, it's handled specially */
1919                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1920                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1921                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1922                     adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1923                         /* enable clockgating to save power */
1924                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1925                                                                                      state);
1926                         if (r) {
1927                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1928                                           adev->ip_blocks[i].version->funcs->name, r);
1929                                 return r;
1930                         }
1931                 }
1932         }
1933
1934         return 0;
1935 }
1936
1937 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1938 {
1939         int i, j, r;
1940
1941         if (amdgpu_emu_mode == 1)
1942                 return 0;
1943
1944         for (j = 0; j < adev->num_ip_blocks; j++) {
1945                 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1946                 if (!adev->ip_blocks[i].status.late_initialized)
1947                         continue;
1948                 /* skip CG for VCE/UVD, it's handled specially */
1949                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1950                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1951                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1952                     adev->ip_blocks[i].version->funcs->set_powergating_state) {
1953                         /* enable powergating to save power */
1954                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1955                                                                                         state);
1956                         if (r) {
1957                                 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1958                                           adev->ip_blocks[i].version->funcs->name, r);
1959                                 return r;
1960                         }
1961                 }
1962         }
1963         return 0;
1964 }
1965
1966 static int amdgpu_device_enable_mgpu_fan_boost(void)
1967 {
1968         struct amdgpu_gpu_instance *gpu_ins;
1969         struct amdgpu_device *adev;
1970         int i, ret = 0;
1971
1972         mutex_lock(&mgpu_info.mutex);
1973
1974         /*
1975          * MGPU fan boost feature should be enabled
1976          * only when there are two or more dGPUs in
1977          * the system
1978          */
1979         if (mgpu_info.num_dgpu < 2)
1980                 goto out;
1981
1982         for (i = 0; i < mgpu_info.num_dgpu; i++) {
1983                 gpu_ins = &(mgpu_info.gpu_ins[i]);
1984                 adev = gpu_ins->adev;
1985                 if (!(adev->flags & AMD_IS_APU) &&
1986                     !gpu_ins->mgpu_fan_enabled &&
1987                     adev->powerplay.pp_funcs &&
1988                     adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
1989                         ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
1990                         if (ret)
1991                                 break;
1992
1993                         gpu_ins->mgpu_fan_enabled = 1;
1994                 }
1995         }
1996
1997 out:
1998         mutex_unlock(&mgpu_info.mutex);
1999
2000         return ret;
2001 }
2002
2003 /**
2004  * amdgpu_device_ip_late_init - run late init for hardware IPs
2005  *
2006  * @adev: amdgpu_device pointer
2007  *
2008  * Late initialization pass for hardware IPs.  The list of all the hardware
2009  * IPs that make up the asic is walked and the late_init callbacks are run.
2010  * late_init covers any special initialization that an IP requires
2011  * after all of the have been initialized or something that needs to happen
2012  * late in the init process.
2013  * Returns 0 on success, negative error code on failure.
2014  */
2015 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2016 {
2017         int i = 0, r;
2018
2019         for (i = 0; i < adev->num_ip_blocks; i++) {
2020                 if (!adev->ip_blocks[i].status.hw)
2021                         continue;
2022                 if (adev->ip_blocks[i].version->funcs->late_init) {
2023                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2024                         if (r) {
2025                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2026                                           adev->ip_blocks[i].version->funcs->name, r);
2027                                 return r;
2028                         }
2029                 }
2030                 adev->ip_blocks[i].status.late_initialized = true;
2031         }
2032
2033         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2034         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2035
2036         amdgpu_device_fill_reset_magic(adev);
2037
2038         r = amdgpu_device_enable_mgpu_fan_boost();
2039         if (r)
2040                 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2041
2042         /* set to low pstate by default */
2043         amdgpu_xgmi_set_pstate(adev, 0);
2044
2045         return 0;
2046 }
2047
2048 /**
2049  * amdgpu_device_ip_fini - run fini for hardware IPs
2050  *
2051  * @adev: amdgpu_device pointer
2052  *
2053  * Main teardown pass for hardware IPs.  The list of all the hardware
2054  * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2055  * are run.  hw_fini tears down the hardware associated with each IP
2056  * and sw_fini tears down any software state associated with each IP.
2057  * Returns 0 on success, negative error code on failure.
2058  */
2059 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2060 {
2061         int i, r;
2062
2063         amdgpu_ras_pre_fini(adev);
2064
2065         if (adev->gmc.xgmi.num_physical_nodes > 1)
2066                 amdgpu_xgmi_remove_device(adev);
2067
2068         amdgpu_amdkfd_device_fini(adev);
2069
2070         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2071         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2072
2073         /* need to disable SMC first */
2074         for (i = 0; i < adev->num_ip_blocks; i++) {
2075                 if (!adev->ip_blocks[i].status.hw)
2076                         continue;
2077                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2078                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2079                         /* XXX handle errors */
2080                         if (r) {
2081                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2082                                           adev->ip_blocks[i].version->funcs->name, r);
2083                         }
2084                         adev->ip_blocks[i].status.hw = false;
2085                         break;
2086                 }
2087         }
2088
2089         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2090                 if (!adev->ip_blocks[i].status.hw)
2091                         continue;
2092
2093                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2094                 /* XXX handle errors */
2095                 if (r) {
2096                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2097                                   adev->ip_blocks[i].version->funcs->name, r);
2098                 }
2099
2100                 adev->ip_blocks[i].status.hw = false;
2101         }
2102
2103
2104         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2105                 if (!adev->ip_blocks[i].status.sw)
2106                         continue;
2107
2108                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2109                         amdgpu_ucode_free_bo(adev);
2110                         amdgpu_free_static_csa(&adev->virt.csa_obj);
2111                         amdgpu_device_wb_fini(adev);
2112                         amdgpu_device_vram_scratch_fini(adev);
2113                         amdgpu_ib_pool_fini(adev);
2114                 }
2115
2116                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2117                 /* XXX handle errors */
2118                 if (r) {
2119                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2120                                   adev->ip_blocks[i].version->funcs->name, r);
2121                 }
2122                 adev->ip_blocks[i].status.sw = false;
2123                 adev->ip_blocks[i].status.valid = false;
2124         }
2125
2126         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2127                 if (!adev->ip_blocks[i].status.late_initialized)
2128                         continue;
2129                 if (adev->ip_blocks[i].version->funcs->late_fini)
2130                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2131                 adev->ip_blocks[i].status.late_initialized = false;
2132         }
2133
2134         amdgpu_ras_fini(adev);
2135
2136         if (amdgpu_sriov_vf(adev))
2137                 if (amdgpu_virt_release_full_gpu(adev, false))
2138                         DRM_ERROR("failed to release exclusive mode on fini\n");
2139
2140         return 0;
2141 }
2142
2143 /**
2144  * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2145  *
2146  * @work: work_struct.
2147  */
2148 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2149 {
2150         struct amdgpu_device *adev =
2151                 container_of(work, struct amdgpu_device, delayed_init_work.work);
2152         int r;
2153
2154         r = amdgpu_ib_ring_tests(adev);
2155         if (r)
2156                 DRM_ERROR("ib ring test failed (%d).\n", r);
2157 }
2158
2159 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2160 {
2161         struct amdgpu_device *adev =
2162                 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2163
2164         mutex_lock(&adev->gfx.gfx_off_mutex);
2165         if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2166                 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2167                         adev->gfx.gfx_off_state = true;
2168         }
2169         mutex_unlock(&adev->gfx.gfx_off_mutex);
2170 }
2171
2172 /**
2173  * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2174  *
2175  * @adev: amdgpu_device pointer
2176  *
2177  * Main suspend function for hardware IPs.  The list of all the hardware
2178  * IPs that make up the asic is walked, clockgating is disabled and the
2179  * suspend callbacks are run.  suspend puts the hardware and software state
2180  * in each IP into a state suitable for suspend.
2181  * Returns 0 on success, negative error code on failure.
2182  */
2183 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2184 {
2185         int i, r;
2186
2187         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2188         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2189
2190         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2191                 if (!adev->ip_blocks[i].status.valid)
2192                         continue;
2193                 /* displays are handled separately */
2194                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2195                         /* XXX handle errors */
2196                         r = adev->ip_blocks[i].version->funcs->suspend(adev);
2197                         /* XXX handle errors */
2198                         if (r) {
2199                                 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2200                                           adev->ip_blocks[i].version->funcs->name, r);
2201                                 return r;
2202                         }
2203                         adev->ip_blocks[i].status.hw = false;
2204                 }
2205         }
2206
2207         return 0;
2208 }
2209
2210 /**
2211  * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2212  *
2213  * @adev: amdgpu_device pointer
2214  *
2215  * Main suspend function for hardware IPs.  The list of all the hardware
2216  * IPs that make up the asic is walked, clockgating is disabled and the
2217  * suspend callbacks are run.  suspend puts the hardware and software state
2218  * in each IP into a state suitable for suspend.
2219  * Returns 0 on success, negative error code on failure.
2220  */
2221 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2222 {
2223         int i, r;
2224
2225         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2226                 if (!adev->ip_blocks[i].status.valid)
2227                         continue;
2228                 /* displays are handled in phase1 */
2229                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2230                         continue;
2231                 /* XXX handle errors */
2232                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2233                 /* XXX handle errors */
2234                 if (r) {
2235                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
2236                                   adev->ip_blocks[i].version->funcs->name, r);
2237                 }
2238                 adev->ip_blocks[i].status.hw = false;
2239                 /* handle putting the SMC in the appropriate state */
2240                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2241                         if (is_support_sw_smu(adev)) {
2242                                 r = smu_set_mp1_state(&adev->smu, adev->mp1_state);
2243                         } else if (adev->powerplay.pp_funcs &&
2244                                            adev->powerplay.pp_funcs->set_mp1_state) {
2245                                 r = adev->powerplay.pp_funcs->set_mp1_state(
2246                                         adev->powerplay.pp_handle,
2247                                         adev->mp1_state);
2248                         }
2249                         if (r) {
2250                                 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2251                                           adev->mp1_state, r);
2252                                 return r;
2253                         }
2254                 }
2255
2256                 adev->ip_blocks[i].status.hw = false;
2257         }
2258
2259         return 0;
2260 }
2261
2262 /**
2263  * amdgpu_device_ip_suspend - run suspend for hardware IPs
2264  *
2265  * @adev: amdgpu_device pointer
2266  *
2267  * Main suspend function for hardware IPs.  The list of all the hardware
2268  * IPs that make up the asic is walked, clockgating is disabled and the
2269  * suspend callbacks are run.  suspend puts the hardware and software state
2270  * in each IP into a state suitable for suspend.
2271  * Returns 0 on success, negative error code on failure.
2272  */
2273 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2274 {
2275         int r;
2276
2277         if (amdgpu_sriov_vf(adev))
2278                 amdgpu_virt_request_full_gpu(adev, false);
2279
2280         r = amdgpu_device_ip_suspend_phase1(adev);
2281         if (r)
2282                 return r;
2283         r = amdgpu_device_ip_suspend_phase2(adev);
2284
2285         if (amdgpu_sriov_vf(adev))
2286                 amdgpu_virt_release_full_gpu(adev, false);
2287
2288         return r;
2289 }
2290
2291 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2292 {
2293         int i, r;
2294
2295         static enum amd_ip_block_type ip_order[] = {
2296                 AMD_IP_BLOCK_TYPE_GMC,
2297                 AMD_IP_BLOCK_TYPE_COMMON,
2298                 AMD_IP_BLOCK_TYPE_PSP,
2299                 AMD_IP_BLOCK_TYPE_IH,
2300         };
2301
2302         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2303                 int j;
2304                 struct amdgpu_ip_block *block;
2305
2306                 for (j = 0; j < adev->num_ip_blocks; j++) {
2307                         block = &adev->ip_blocks[j];
2308
2309                         block->status.hw = false;
2310                         if (block->version->type != ip_order[i] ||
2311                                 !block->status.valid)
2312                                 continue;
2313
2314                         r = block->version->funcs->hw_init(adev);
2315                         DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2316                         if (r)
2317                                 return r;
2318                         block->status.hw = true;
2319                 }
2320         }
2321
2322         return 0;
2323 }
2324
2325 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2326 {
2327         int i, r;
2328
2329         static enum amd_ip_block_type ip_order[] = {
2330                 AMD_IP_BLOCK_TYPE_SMC,
2331                 AMD_IP_BLOCK_TYPE_DCE,
2332                 AMD_IP_BLOCK_TYPE_GFX,
2333                 AMD_IP_BLOCK_TYPE_SDMA,
2334                 AMD_IP_BLOCK_TYPE_UVD,
2335                 AMD_IP_BLOCK_TYPE_VCE
2336         };
2337
2338         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2339                 int j;
2340                 struct amdgpu_ip_block *block;
2341
2342                 for (j = 0; j < adev->num_ip_blocks; j++) {
2343                         block = &adev->ip_blocks[j];
2344
2345                         if (block->version->type != ip_order[i] ||
2346                                 !block->status.valid ||
2347                                 block->status.hw)
2348                                 continue;
2349
2350                         r = block->version->funcs->hw_init(adev);
2351                         DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2352                         if (r)
2353                                 return r;
2354                         block->status.hw = true;
2355                 }
2356         }
2357
2358         return 0;
2359 }
2360
2361 /**
2362  * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2363  *
2364  * @adev: amdgpu_device pointer
2365  *
2366  * First resume function for hardware IPs.  The list of all the hardware
2367  * IPs that make up the asic is walked and the resume callbacks are run for
2368  * COMMON, GMC, and IH.  resume puts the hardware into a functional state
2369  * after a suspend and updates the software state as necessary.  This
2370  * function is also used for restoring the GPU after a GPU reset.
2371  * Returns 0 on success, negative error code on failure.
2372  */
2373 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2374 {
2375         int i, r;
2376
2377         for (i = 0; i < adev->num_ip_blocks; i++) {
2378                 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2379                         continue;
2380                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2381                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2382                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2383
2384                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2385                         if (r) {
2386                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2387                                           adev->ip_blocks[i].version->funcs->name, r);
2388                                 return r;
2389                         }
2390                         adev->ip_blocks[i].status.hw = true;
2391                 }
2392         }
2393
2394         return 0;
2395 }
2396
2397 /**
2398  * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2399  *
2400  * @adev: amdgpu_device pointer
2401  *
2402  * First resume function for hardware IPs.  The list of all the hardware
2403  * IPs that make up the asic is walked and the resume callbacks are run for
2404  * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a
2405  * functional state after a suspend and updates the software state as
2406  * necessary.  This function is also used for restoring the GPU after a GPU
2407  * reset.
2408  * Returns 0 on success, negative error code on failure.
2409  */
2410 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2411 {
2412         int i, r;
2413
2414         for (i = 0; i < adev->num_ip_blocks; i++) {
2415                 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2416                         continue;
2417                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2418                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2419                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2420                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2421                         continue;
2422                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2423                 if (r) {
2424                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2425                                   adev->ip_blocks[i].version->funcs->name, r);
2426                         return r;
2427                 }
2428                 adev->ip_blocks[i].status.hw = true;
2429         }
2430
2431         return 0;
2432 }
2433
2434 /**
2435  * amdgpu_device_ip_resume - run resume for hardware IPs
2436  *
2437  * @adev: amdgpu_device pointer
2438  *
2439  * Main resume function for hardware IPs.  The hardware IPs
2440  * are split into two resume functions because they are
2441  * are also used in in recovering from a GPU reset and some additional
2442  * steps need to be take between them.  In this case (S3/S4) they are
2443  * run sequentially.
2444  * Returns 0 on success, negative error code on failure.
2445  */
2446 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2447 {
2448         int r;
2449
2450         r = amdgpu_device_ip_resume_phase1(adev);
2451         if (r)
2452                 return r;
2453
2454         r = amdgpu_device_fw_loading(adev);
2455         if (r)
2456                 return r;
2457
2458         r = amdgpu_device_ip_resume_phase2(adev);
2459
2460         return r;
2461 }
2462
2463 /**
2464  * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2465  *
2466  * @adev: amdgpu_device pointer
2467  *
2468  * Query the VBIOS data tables to determine if the board supports SR-IOV.
2469  */
2470 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2471 {
2472         if (amdgpu_sriov_vf(adev)) {
2473                 if (adev->is_atom_fw) {
2474                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2475                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2476                 } else {
2477                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2478                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2479                 }
2480
2481                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2482                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2483         }
2484 }
2485
2486 /**
2487  * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2488  *
2489  * @asic_type: AMD asic type
2490  *
2491  * Check if there is DC (new modesetting infrastructre) support for an asic.
2492  * returns true if DC has support, false if not.
2493  */
2494 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2495 {
2496         switch (asic_type) {
2497 #if defined(CONFIG_DRM_AMD_DC)
2498         case CHIP_BONAIRE:
2499         case CHIP_KAVERI:
2500         case CHIP_KABINI:
2501         case CHIP_MULLINS:
2502                 /*
2503                  * We have systems in the wild with these ASICs that require
2504                  * LVDS and VGA support which is not supported with DC.
2505                  *
2506                  * Fallback to the non-DC driver here by default so as not to
2507                  * cause regressions.
2508                  */
2509                 return amdgpu_dc > 0;
2510         case CHIP_HAWAII:
2511         case CHIP_CARRIZO:
2512         case CHIP_STONEY:
2513         case CHIP_POLARIS10:
2514         case CHIP_POLARIS11:
2515         case CHIP_POLARIS12:
2516         case CHIP_VEGAM:
2517         case CHIP_TONGA:
2518         case CHIP_FIJI:
2519         case CHIP_VEGA10:
2520         case CHIP_VEGA12:
2521         case CHIP_VEGA20:
2522 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2523         case CHIP_RAVEN:
2524 #endif
2525 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2526         case CHIP_NAVI10:
2527         case CHIP_NAVI14:
2528         case CHIP_NAVI12:
2529 #endif
2530 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2531         case CHIP_RENOIR:
2532 #endif
2533                 return amdgpu_dc != 0;
2534 #endif
2535         default:
2536                 return false;
2537         }
2538 }
2539
2540 /**
2541  * amdgpu_device_has_dc_support - check if dc is supported
2542  *
2543  * @adev: amdgpu_device_pointer
2544  *
2545  * Returns true for supported, false for not supported
2546  */
2547 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2548 {
2549         if (amdgpu_sriov_vf(adev))
2550                 return false;
2551
2552         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2553 }
2554
2555
2556 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2557 {
2558         struct amdgpu_device *adev =
2559                 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2560
2561         adev->asic_reset_res =  amdgpu_asic_reset(adev);
2562         if (adev->asic_reset_res)
2563                 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
2564                          adev->asic_reset_res, adev->ddev->unique);
2565 }
2566
2567
2568 /**
2569  * amdgpu_device_init - initialize the driver
2570  *
2571  * @adev: amdgpu_device pointer
2572  * @ddev: drm dev pointer
2573  * @pdev: pci dev pointer
2574  * @flags: driver flags
2575  *
2576  * Initializes the driver info and hw (all asics).
2577  * Returns 0 for success or an error on failure.
2578  * Called at driver startup.
2579  */
2580 int amdgpu_device_init(struct amdgpu_device *adev,
2581                        struct drm_device *ddev,
2582                        struct pci_dev *pdev,
2583                        uint32_t flags)
2584 {
2585         int r, i;
2586         bool runtime = false;
2587         u32 max_MBps;
2588
2589         adev->shutdown = false;
2590         adev->dev = &pdev->dev;
2591         adev->ddev = ddev;
2592         adev->pdev = pdev;
2593         adev->flags = flags;
2594
2595         if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
2596                 adev->asic_type = amdgpu_force_asic_type;
2597         else
2598                 adev->asic_type = flags & AMD_ASIC_MASK;
2599
2600         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2601         if (amdgpu_emu_mode == 1)
2602                 adev->usec_timeout *= 2;
2603         adev->gmc.gart_size = 512 * 1024 * 1024;
2604         adev->accel_working = false;
2605         adev->num_rings = 0;
2606         adev->mman.buffer_funcs = NULL;
2607         adev->mman.buffer_funcs_ring = NULL;
2608         adev->vm_manager.vm_pte_funcs = NULL;
2609         adev->vm_manager.vm_pte_num_rqs = 0;
2610         adev->gmc.gmc_funcs = NULL;
2611         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2612         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2613
2614         adev->smc_rreg = &amdgpu_invalid_rreg;
2615         adev->smc_wreg = &amdgpu_invalid_wreg;
2616         adev->pcie_rreg = &amdgpu_invalid_rreg;
2617         adev->pcie_wreg = &amdgpu_invalid_wreg;
2618         adev->pciep_rreg = &amdgpu_invalid_rreg;
2619         adev->pciep_wreg = &amdgpu_invalid_wreg;
2620         adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
2621         adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
2622         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2623         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2624         adev->didt_rreg = &amdgpu_invalid_rreg;
2625         adev->didt_wreg = &amdgpu_invalid_wreg;
2626         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2627         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2628         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2629         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2630
2631         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2632                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2633                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2634
2635         /* mutex initialization are all done here so we
2636          * can recall function without having locking issues */
2637         atomic_set(&adev->irq.ih.lock, 0);
2638         mutex_init(&adev->firmware.mutex);
2639         mutex_init(&adev->pm.mutex);
2640         mutex_init(&adev->gfx.gpu_clock_mutex);
2641         mutex_init(&adev->srbm_mutex);
2642         mutex_init(&adev->gfx.pipe_reserve_mutex);
2643         mutex_init(&adev->gfx.gfx_off_mutex);
2644         mutex_init(&adev->grbm_idx_mutex);
2645         mutex_init(&adev->mn_lock);
2646         mutex_init(&adev->virt.vf_errors.lock);
2647         hash_init(adev->mn_hash);
2648         mutex_init(&adev->lock_reset);
2649         mutex_init(&adev->virt.dpm_mutex);
2650         mutex_init(&adev->psp.mutex);
2651
2652         r = amdgpu_device_check_arguments(adev);
2653         if (r)
2654                 return r;
2655
2656         spin_lock_init(&adev->mmio_idx_lock);
2657         spin_lock_init(&adev->smc_idx_lock);
2658         spin_lock_init(&adev->pcie_idx_lock);
2659         spin_lock_init(&adev->uvd_ctx_idx_lock);
2660         spin_lock_init(&adev->didt_idx_lock);
2661         spin_lock_init(&adev->gc_cac_idx_lock);
2662         spin_lock_init(&adev->se_cac_idx_lock);
2663         spin_lock_init(&adev->audio_endpt_idx_lock);
2664         spin_lock_init(&adev->mm_stats.lock);
2665
2666         INIT_LIST_HEAD(&adev->shadow_list);
2667         mutex_init(&adev->shadow_list_lock);
2668
2669         INIT_LIST_HEAD(&adev->ring_lru_list);
2670         spin_lock_init(&adev->ring_lru_list_lock);
2671
2672         INIT_DELAYED_WORK(&adev->delayed_init_work,
2673                           amdgpu_device_delayed_init_work_handler);
2674         INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2675                           amdgpu_device_delay_enable_gfx_off);
2676
2677         INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2678
2679         adev->gfx.gfx_off_req_count = 1;
2680         adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2681
2682         /* Registers mapping */
2683         /* TODO: block userspace mapping of io register */
2684         if (adev->asic_type >= CHIP_BONAIRE) {
2685                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2686                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2687         } else {
2688                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2689                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2690         }
2691
2692         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2693         if (adev->rmmio == NULL) {
2694                 return -ENOMEM;
2695         }
2696         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2697         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2698
2699         /* io port mapping */
2700         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2701                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2702                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2703                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2704                         break;
2705                 }
2706         }
2707         if (adev->rio_mem == NULL)
2708                 DRM_INFO("PCI I/O BAR is not found.\n");
2709
2710         /* enable PCIE atomic ops */
2711         r = pci_enable_atomic_ops_to_root(adev->pdev,
2712                                           PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
2713                                           PCI_EXP_DEVCAP2_ATOMIC_COMP64);
2714         if (r) {
2715                 adev->have_atomics_support = false;
2716                 DRM_INFO("PCIE atomic ops is not supported\n");
2717         } else {
2718                 adev->have_atomics_support = true;
2719         }
2720
2721         amdgpu_device_get_pcie_info(adev);
2722
2723         if (amdgpu_mcbp)
2724                 DRM_INFO("MCBP is enabled\n");
2725
2726         if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
2727                 adev->enable_mes = true;
2728
2729         if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) {
2730                 r = amdgpu_discovery_init(adev);
2731                 if (r) {
2732                         dev_err(adev->dev, "amdgpu_discovery_init failed\n");
2733                         return r;
2734                 }
2735         }
2736
2737         /* early init functions */
2738         r = amdgpu_device_ip_early_init(adev);
2739         if (r)
2740                 return r;
2741
2742         r = amdgpu_device_get_job_timeout_settings(adev);
2743         if (r) {
2744                 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
2745                 return r;
2746         }
2747
2748         /* doorbell bar mapping and doorbell index init*/
2749         amdgpu_device_doorbell_init(adev);
2750
2751         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2752         /* this will fail for cards that aren't VGA class devices, just
2753          * ignore it */
2754         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2755
2756         if (amdgpu_device_is_px(ddev))
2757                 runtime = true;
2758         if (!pci_is_thunderbolt_attached(adev->pdev))
2759                 vga_switcheroo_register_client(adev->pdev,
2760                                                &amdgpu_switcheroo_ops, runtime);
2761         if (runtime)
2762                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2763
2764         if (amdgpu_emu_mode == 1) {
2765                 /* post the asic on emulation mode */
2766                 emu_soc_asic_init(adev);
2767                 goto fence_driver_init;
2768         }
2769
2770         /* detect if we are with an SRIOV vbios */
2771         amdgpu_device_detect_sriov_bios(adev);
2772
2773         /* check if we need to reset the asic
2774          *  E.g., driver was not cleanly unloaded previously, etc.
2775          */
2776         if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
2777                 r = amdgpu_asic_reset(adev);
2778                 if (r) {
2779                         dev_err(adev->dev, "asic reset on init failed\n");
2780                         goto failed;
2781                 }
2782         }
2783
2784         /* Post card if necessary */
2785         if (amdgpu_device_need_post(adev)) {
2786                 if (!adev->bios) {
2787                         dev_err(adev->dev, "no vBIOS found\n");
2788                         r = -EINVAL;
2789                         goto failed;
2790                 }
2791                 DRM_INFO("GPU posting now...\n");
2792                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2793                 if (r) {
2794                         dev_err(adev->dev, "gpu post error!\n");
2795                         goto failed;
2796                 }
2797         }
2798
2799         if (adev->is_atom_fw) {
2800                 /* Initialize clocks */
2801                 r = amdgpu_atomfirmware_get_clock_info(adev);
2802                 if (r) {
2803                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2804                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2805                         goto failed;
2806                 }
2807         } else {
2808                 /* Initialize clocks */
2809                 r = amdgpu_atombios_get_clock_info(adev);
2810                 if (r) {
2811                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2812                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2813                         goto failed;
2814                 }
2815                 /* init i2c buses */
2816                 if (!amdgpu_device_has_dc_support(adev))
2817                         amdgpu_atombios_i2c_init(adev);
2818         }
2819
2820 fence_driver_init:
2821         /* Fence driver */
2822         r = amdgpu_fence_driver_init(adev);
2823         if (r) {
2824                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2825                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2826                 goto failed;
2827         }
2828
2829         /* init the mode config */
2830         drm_mode_config_init(adev->ddev);
2831
2832         r = amdgpu_device_ip_init(adev);
2833         if (r) {
2834                 /* failed in exclusive mode due to timeout */
2835                 if (amdgpu_sriov_vf(adev) &&
2836                     !amdgpu_sriov_runtime(adev) &&
2837                     amdgpu_virt_mmio_blocked(adev) &&
2838                     !amdgpu_virt_wait_reset(adev)) {
2839                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2840                         /* Don't send request since VF is inactive. */
2841                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2842                         adev->virt.ops = NULL;
2843                         r = -EAGAIN;
2844                         goto failed;
2845                 }
2846                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2847                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2848                 if (amdgpu_virt_request_full_gpu(adev, false))
2849                         amdgpu_virt_release_full_gpu(adev, false);
2850                 goto failed;
2851         }
2852
2853         adev->accel_working = true;
2854
2855         amdgpu_vm_check_compute_bug(adev);
2856
2857         /* Initialize the buffer migration limit. */
2858         if (amdgpu_moverate >= 0)
2859                 max_MBps = amdgpu_moverate;
2860         else
2861                 max_MBps = 8; /* Allow 8 MB/s. */
2862         /* Get a log2 for easy divisions. */
2863         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2864
2865         amdgpu_fbdev_init(adev);
2866
2867         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
2868                 amdgpu_pm_virt_sysfs_init(adev);
2869
2870         r = amdgpu_pm_sysfs_init(adev);
2871         if (r)
2872                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2873
2874         r = amdgpu_ucode_sysfs_init(adev);
2875         if (r)
2876                 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
2877
2878         r = amdgpu_debugfs_gem_init(adev);
2879         if (r)
2880                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2881
2882         r = amdgpu_debugfs_regs_init(adev);
2883         if (r)
2884                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2885
2886         r = amdgpu_debugfs_firmware_init(adev);
2887         if (r)
2888                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2889
2890         r = amdgpu_debugfs_init(adev);
2891         if (r)
2892                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2893
2894         if ((amdgpu_testing & 1)) {
2895                 if (adev->accel_working)
2896                         amdgpu_test_moves(adev);
2897                 else
2898                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2899         }
2900         if (amdgpu_benchmarking) {
2901                 if (adev->accel_working)
2902                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2903                 else
2904                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2905         }
2906
2907         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2908          * explicit gating rather than handling it automatically.
2909          */
2910         r = amdgpu_device_ip_late_init(adev);
2911         if (r) {
2912                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2913                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2914                 goto failed;
2915         }
2916
2917         /* must succeed. */
2918         amdgpu_ras_resume(adev);
2919
2920         queue_delayed_work(system_wq, &adev->delayed_init_work,
2921                            msecs_to_jiffies(AMDGPU_RESUME_MS));
2922
2923         r = device_create_file(adev->dev, &dev_attr_pcie_replay_count);
2924         if (r) {
2925                 dev_err(adev->dev, "Could not create pcie_replay_count");
2926                 return r;
2927         }
2928
2929         if (IS_ENABLED(CONFIG_PERF_EVENTS))
2930                 r = amdgpu_pmu_init(adev);
2931         if (r)
2932                 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
2933
2934         return 0;
2935
2936 failed:
2937         amdgpu_vf_error_trans_all(adev);
2938         if (runtime)
2939                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2940
2941         return r;
2942 }
2943
2944 /**
2945  * amdgpu_device_fini - tear down the driver
2946  *
2947  * @adev: amdgpu_device pointer
2948  *
2949  * Tear down the driver info (all asics).
2950  * Called at driver shutdown.
2951  */
2952 void amdgpu_device_fini(struct amdgpu_device *adev)
2953 {
2954         int r;
2955
2956         DRM_INFO("amdgpu: finishing device.\n");
2957         adev->shutdown = true;
2958         /* disable all interrupts */
2959         amdgpu_irq_disable_all(adev);
2960         if (adev->mode_info.mode_config_initialized){
2961                 if (!amdgpu_device_has_dc_support(adev))
2962                         drm_helper_force_disable_all(adev->ddev);
2963                 else
2964                         drm_atomic_helper_shutdown(adev->ddev);
2965         }
2966         amdgpu_fence_driver_fini(adev);
2967         amdgpu_pm_sysfs_fini(adev);
2968         amdgpu_fbdev_fini(adev);
2969         r = amdgpu_device_ip_fini(adev);
2970         if (adev->firmware.gpu_info_fw) {
2971                 release_firmware(adev->firmware.gpu_info_fw);
2972                 adev->firmware.gpu_info_fw = NULL;
2973         }
2974         adev->accel_working = false;
2975         cancel_delayed_work_sync(&adev->delayed_init_work);
2976         /* free i2c buses */
2977         if (!amdgpu_device_has_dc_support(adev))
2978                 amdgpu_i2c_fini(adev);
2979
2980         if (amdgpu_emu_mode != 1)
2981                 amdgpu_atombios_fini(adev);
2982
2983         kfree(adev->bios);
2984         adev->bios = NULL;
2985         if (!pci_is_thunderbolt_attached(adev->pdev))
2986                 vga_switcheroo_unregister_client(adev->pdev);
2987         if (adev->flags & AMD_IS_PX)
2988                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2989         vga_client_register(adev->pdev, NULL, NULL, NULL);
2990         if (adev->rio_mem)
2991                 pci_iounmap(adev->pdev, adev->rio_mem);
2992         adev->rio_mem = NULL;
2993         iounmap(adev->rmmio);
2994         adev->rmmio = NULL;
2995         amdgpu_device_doorbell_fini(adev);
2996         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
2997                 amdgpu_pm_virt_sysfs_fini(adev);
2998
2999         amdgpu_debugfs_regs_cleanup(adev);
3000         device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
3001         amdgpu_ucode_sysfs_fini(adev);
3002         if (IS_ENABLED(CONFIG_PERF_EVENTS))
3003                 amdgpu_pmu_fini(adev);
3004         amdgpu_debugfs_preempt_cleanup(adev);
3005         if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
3006                 amdgpu_discovery_fini(adev);
3007 }
3008
3009
3010 /*
3011  * Suspend & resume.
3012  */
3013 /**
3014  * amdgpu_device_suspend - initiate device suspend
3015  *
3016  * @dev: drm dev pointer
3017  * @suspend: suspend state
3018  * @fbcon : notify the fbdev of suspend
3019  *
3020  * Puts the hw in the suspend state (all asics).
3021  * Returns 0 for success or an error on failure.
3022  * Called at driver suspend.
3023  */
3024 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
3025 {
3026         struct amdgpu_device *adev;
3027         struct drm_crtc *crtc;
3028         struct drm_connector *connector;
3029         struct drm_connector_list_iter iter;
3030         int r;
3031
3032         if (dev == NULL || dev->dev_private == NULL) {
3033                 return -ENODEV;
3034         }
3035
3036         adev = dev->dev_private;
3037
3038         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3039                 return 0;
3040
3041         adev->in_suspend = true;
3042         drm_kms_helper_poll_disable(dev);
3043
3044         if (fbcon)
3045                 amdgpu_fbdev_set_suspend(adev, 1);
3046
3047         cancel_delayed_work_sync(&adev->delayed_init_work);
3048
3049         if (!amdgpu_device_has_dc_support(adev)) {
3050                 /* turn off display hw */
3051                 drm_modeset_lock_all(dev);
3052                 drm_connector_list_iter_begin(dev, &iter);
3053                 drm_for_each_connector_iter(connector, &iter)
3054                         drm_helper_connector_dpms(connector,
3055                                                   DRM_MODE_DPMS_OFF);
3056                 drm_connector_list_iter_end(&iter);
3057                 drm_modeset_unlock_all(dev);
3058                         /* unpin the front buffers and cursors */
3059                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3060                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3061                         struct drm_framebuffer *fb = crtc->primary->fb;
3062                         struct amdgpu_bo *robj;
3063
3064                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3065                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3066                                 r = amdgpu_bo_reserve(aobj, true);
3067                                 if (r == 0) {
3068                                         amdgpu_bo_unpin(aobj);
3069                                         amdgpu_bo_unreserve(aobj);
3070                                 }
3071                         }
3072
3073                         if (fb == NULL || fb->obj[0] == NULL) {
3074                                 continue;
3075                         }
3076                         robj = gem_to_amdgpu_bo(fb->obj[0]);
3077                         /* don't unpin kernel fb objects */
3078                         if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
3079                                 r = amdgpu_bo_reserve(robj, true);
3080                                 if (r == 0) {
3081                                         amdgpu_bo_unpin(robj);
3082                                         amdgpu_bo_unreserve(robj);
3083                                 }
3084                         }
3085                 }
3086         }
3087
3088         amdgpu_amdkfd_suspend(adev);
3089
3090         amdgpu_ras_suspend(adev);
3091
3092         r = amdgpu_device_ip_suspend_phase1(adev);
3093
3094         /* evict vram memory */
3095         amdgpu_bo_evict_vram(adev);
3096
3097         amdgpu_fence_driver_suspend(adev);
3098
3099         r = amdgpu_device_ip_suspend_phase2(adev);
3100
3101         /* evict remaining vram memory
3102          * This second call to evict vram is to evict the gart page table
3103          * using the CPU.
3104          */
3105         amdgpu_bo_evict_vram(adev);
3106
3107         pci_save_state(dev->pdev);
3108         if (suspend) {
3109                 /* Shut down the device */
3110                 pci_disable_device(dev->pdev);
3111                 pci_set_power_state(dev->pdev, PCI_D3hot);
3112         } else {
3113                 r = amdgpu_asic_reset(adev);
3114                 if (r)
3115                         DRM_ERROR("amdgpu asic reset failed\n");
3116         }
3117
3118         return 0;
3119 }
3120
3121 /**
3122  * amdgpu_device_resume - initiate device resume
3123  *
3124  * @dev: drm dev pointer
3125  * @resume: resume state
3126  * @fbcon : notify the fbdev of resume
3127  *
3128  * Bring the hw back to operating state (all asics).
3129  * Returns 0 for success or an error on failure.
3130  * Called at driver resume.
3131  */
3132 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
3133 {
3134         struct drm_connector *connector;
3135         struct drm_connector_list_iter iter;
3136         struct amdgpu_device *adev = dev->dev_private;
3137         struct drm_crtc *crtc;
3138         int r = 0;
3139
3140         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3141                 return 0;
3142
3143         if (resume) {
3144                 pci_set_power_state(dev->pdev, PCI_D0);
3145                 pci_restore_state(dev->pdev);
3146                 r = pci_enable_device(dev->pdev);
3147                 if (r)
3148                         return r;
3149         }
3150
3151         /* post card */
3152         if (amdgpu_device_need_post(adev)) {
3153                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
3154                 if (r)
3155                         DRM_ERROR("amdgpu asic init failed\n");
3156         }
3157
3158         r = amdgpu_device_ip_resume(adev);
3159         if (r) {
3160                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
3161                 return r;
3162         }
3163         amdgpu_fence_driver_resume(adev);
3164
3165
3166         r = amdgpu_device_ip_late_init(adev);
3167         if (r)
3168                 return r;
3169
3170         queue_delayed_work(system_wq, &adev->delayed_init_work,
3171                            msecs_to_jiffies(AMDGPU_RESUME_MS));
3172
3173         if (!amdgpu_device_has_dc_support(adev)) {
3174                 /* pin cursors */
3175                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3176                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3177
3178                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3179                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3180                                 r = amdgpu_bo_reserve(aobj, true);
3181                                 if (r == 0) {
3182                                         r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3183                                         if (r != 0)
3184                                                 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
3185                                         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3186                                         amdgpu_bo_unreserve(aobj);
3187                                 }
3188                         }
3189                 }
3190         }
3191         r = amdgpu_amdkfd_resume(adev);
3192         if (r)
3193                 return r;
3194
3195         /* Make sure IB tests flushed */
3196         flush_delayed_work(&adev->delayed_init_work);
3197
3198         /* blat the mode back in */
3199         if (fbcon) {
3200                 if (!amdgpu_device_has_dc_support(adev)) {
3201                         /* pre DCE11 */
3202                         drm_helper_resume_force_mode(dev);
3203
3204                         /* turn on display hw */
3205                         drm_modeset_lock_all(dev);
3206
3207                         drm_connector_list_iter_begin(dev, &iter);
3208                         drm_for_each_connector_iter(connector, &iter)
3209                                 drm_helper_connector_dpms(connector,
3210                                                           DRM_MODE_DPMS_ON);
3211                         drm_connector_list_iter_end(&iter);
3212
3213                         drm_modeset_unlock_all(dev);
3214                 }
3215                 amdgpu_fbdev_set_suspend(adev, 0);
3216         }
3217
3218         drm_kms_helper_poll_enable(dev);
3219
3220         amdgpu_ras_resume(adev);
3221
3222         /*
3223          * Most of the connector probing functions try to acquire runtime pm
3224          * refs to ensure that the GPU is powered on when connector polling is
3225          * performed. Since we're calling this from a runtime PM callback,
3226          * trying to acquire rpm refs will cause us to deadlock.
3227          *
3228          * Since we're guaranteed to be holding the rpm lock, it's safe to
3229          * temporarily disable the rpm helpers so this doesn't deadlock us.
3230          */
3231 #ifdef CONFIG_PM
3232         dev->dev->power.disable_depth++;
3233 #endif
3234         if (!amdgpu_device_has_dc_support(adev))
3235                 drm_helper_hpd_irq_event(dev);
3236         else
3237                 drm_kms_helper_hotplug_event(dev);
3238 #ifdef CONFIG_PM
3239         dev->dev->power.disable_depth--;
3240 #endif
3241         adev->in_suspend = false;
3242
3243         return 0;
3244 }
3245
3246 /**
3247  * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3248  *
3249  * @adev: amdgpu_device pointer
3250  *
3251  * The list of all the hardware IPs that make up the asic is walked and
3252  * the check_soft_reset callbacks are run.  check_soft_reset determines
3253  * if the asic is still hung or not.
3254  * Returns true if any of the IPs are still in a hung state, false if not.
3255  */
3256 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3257 {
3258         int i;
3259         bool asic_hang = false;
3260
3261         if (amdgpu_sriov_vf(adev))
3262                 return true;
3263
3264         if (amdgpu_asic_need_full_reset(adev))
3265                 return true;
3266
3267         for (i = 0; i < adev->num_ip_blocks; i++) {
3268                 if (!adev->ip_blocks[i].status.valid)
3269                         continue;
3270                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3271                         adev->ip_blocks[i].status.hang =
3272                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3273                 if (adev->ip_blocks[i].status.hang) {
3274                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3275                         asic_hang = true;
3276                 }
3277         }
3278         return asic_hang;
3279 }
3280
3281 /**
3282  * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3283  *
3284  * @adev: amdgpu_device pointer
3285  *
3286  * The list of all the hardware IPs that make up the asic is walked and the
3287  * pre_soft_reset callbacks are run if the block is hung.  pre_soft_reset
3288  * handles any IP specific hardware or software state changes that are
3289  * necessary for a soft reset to succeed.
3290  * Returns 0 on success, negative error code on failure.
3291  */
3292 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3293 {
3294         int i, r = 0;
3295
3296         for (i = 0; i < adev->num_ip_blocks; i++) {
3297                 if (!adev->ip_blocks[i].status.valid)
3298                         continue;
3299                 if (adev->ip_blocks[i].status.hang &&
3300                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3301                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3302                         if (r)
3303                                 return r;
3304                 }
3305         }
3306
3307         return 0;
3308 }
3309
3310 /**
3311  * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3312  *
3313  * @adev: amdgpu_device pointer
3314  *
3315  * Some hardware IPs cannot be soft reset.  If they are hung, a full gpu
3316  * reset is necessary to recover.
3317  * Returns true if a full asic reset is required, false if not.
3318  */
3319 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3320 {
3321         int i;
3322
3323         if (amdgpu_asic_need_full_reset(adev))
3324                 return true;
3325
3326         for (i = 0; i < adev->num_ip_blocks; i++) {
3327                 if (!adev->ip_blocks[i].status.valid)
3328                         continue;
3329                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3330                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3331                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3332                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3333                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3334                         if (adev->ip_blocks[i].status.hang) {
3335                                 DRM_INFO("Some block need full reset!\n");
3336                                 return true;
3337                         }
3338                 }
3339         }
3340         return false;
3341 }
3342
3343 /**
3344  * amdgpu_device_ip_soft_reset - do a soft reset
3345  *
3346  * @adev: amdgpu_device pointer
3347  *
3348  * The list of all the hardware IPs that make up the asic is walked and the
3349  * soft_reset callbacks are run if the block is hung.  soft_reset handles any
3350  * IP specific hardware or software state changes that are necessary to soft
3351  * reset the IP.
3352  * Returns 0 on success, negative error code on failure.
3353  */
3354 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3355 {
3356         int i, r = 0;
3357
3358         for (i = 0; i < adev->num_ip_blocks; i++) {
3359                 if (!adev->ip_blocks[i].status.valid)
3360                         continue;
3361                 if (adev->ip_blocks[i].status.hang &&
3362                     adev->ip_blocks[i].version->funcs->soft_reset) {
3363                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3364                         if (r)
3365                                 return r;
3366                 }
3367         }
3368
3369         return 0;
3370 }
3371
3372 /**
3373  * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3374  *
3375  * @adev: amdgpu_device pointer
3376  *
3377  * The list of all the hardware IPs that make up the asic is walked and the
3378  * post_soft_reset callbacks are run if the asic was hung.  post_soft_reset
3379  * handles any IP specific hardware or software state changes that are
3380  * necessary after the IP has been soft reset.
3381  * Returns 0 on success, negative error code on failure.
3382  */
3383 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3384 {
3385         int i, r = 0;
3386
3387         for (i = 0; i < adev->num_ip_blocks; i++) {
3388                 if (!adev->ip_blocks[i].status.valid)
3389                         continue;
3390                 if (adev->ip_blocks[i].status.hang &&
3391                     adev->ip_blocks[i].version->funcs->post_soft_reset)
3392                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3393                 if (r)
3394                         return r;
3395         }
3396
3397         return 0;
3398 }
3399
3400 /**
3401  * amdgpu_device_recover_vram - Recover some VRAM contents
3402  *
3403  * @adev: amdgpu_device pointer
3404  *
3405  * Restores the contents of VRAM buffers from the shadows in GTT.  Used to
3406  * restore things like GPUVM page tables after a GPU reset where
3407  * the contents of VRAM might be lost.
3408  *
3409  * Returns:
3410  * 0 on success, negative error code on failure.
3411  */
3412 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3413 {
3414         struct dma_fence *fence = NULL, *next = NULL;
3415         struct amdgpu_bo *shadow;
3416         long r = 1, tmo;
3417
3418         if (amdgpu_sriov_runtime(adev))
3419                 tmo = msecs_to_jiffies(8000);
3420         else
3421                 tmo = msecs_to_jiffies(100);
3422
3423         DRM_INFO("recover vram bo from shadow start\n");
3424         mutex_lock(&adev->shadow_list_lock);
3425         list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3426
3427                 /* No need to recover an evicted BO */
3428                 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3429                     shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
3430                     shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3431                         continue;
3432
3433                 r = amdgpu_bo_restore_shadow(shadow, &next);
3434                 if (r)
3435                         break;
3436
3437                 if (fence) {
3438                         tmo = dma_fence_wait_timeout(fence, false, tmo);
3439                         dma_fence_put(fence);
3440                         fence = next;
3441                         if (tmo == 0) {
3442                                 r = -ETIMEDOUT;
3443                                 break;
3444                         } else if (tmo < 0) {
3445                                 r = tmo;
3446                                 break;
3447                         }
3448                 } else {
3449                         fence = next;
3450                 }
3451         }
3452         mutex_unlock(&adev->shadow_list_lock);
3453
3454         if (fence)
3455                 tmo = dma_fence_wait_timeout(fence, false, tmo);
3456         dma_fence_put(fence);
3457
3458         if (r < 0 || tmo <= 0) {
3459                 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
3460                 return -EIO;
3461         }
3462
3463         DRM_INFO("recover vram bo from shadow done\n");
3464         return 0;
3465 }
3466
3467
3468 /**
3469  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3470  *
3471  * @adev: amdgpu device pointer
3472  * @from_hypervisor: request from hypervisor
3473  *
3474  * do VF FLR and reinitialize Asic
3475  * return 0 means succeeded otherwise failed
3476  */
3477 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3478                                      bool from_hypervisor)
3479 {
3480         int r;
3481
3482         if (from_hypervisor)
3483                 r = amdgpu_virt_request_full_gpu(adev, true);
3484         else
3485                 r = amdgpu_virt_reset_gpu(adev);
3486         if (r)
3487                 return r;
3488
3489         amdgpu_amdkfd_pre_reset(adev);
3490
3491         /* Resume IP prior to SMC */
3492         r = amdgpu_device_ip_reinit_early_sriov(adev);
3493         if (r)
3494                 goto error;
3495
3496         /* we need recover gart prior to run SMC/CP/SDMA resume */
3497         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3498
3499         r = amdgpu_device_fw_loading(adev);
3500         if (r)
3501                 return r;
3502
3503         /* now we are okay to resume SMC/CP/SDMA */
3504         r = amdgpu_device_ip_reinit_late_sriov(adev);
3505         if (r)
3506                 goto error;
3507
3508         amdgpu_irq_gpu_reset_resume_helper(adev);
3509         r = amdgpu_ib_ring_tests(adev);
3510         amdgpu_amdkfd_post_reset(adev);
3511
3512 error:
3513         amdgpu_virt_init_data_exchange(adev);
3514         amdgpu_virt_release_full_gpu(adev, true);
3515         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3516                 amdgpu_inc_vram_lost(adev);
3517                 r = amdgpu_device_recover_vram(adev);
3518         }
3519
3520         return r;
3521 }
3522
3523 /**
3524  * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3525  *
3526  * @adev: amdgpu device pointer
3527  *
3528  * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3529  * a hung GPU.
3530  */
3531 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3532 {
3533         if (!amdgpu_device_ip_check_soft_reset(adev)) {
3534                 DRM_INFO("Timeout, but no hardware hang detected.\n");
3535                 return false;
3536         }
3537
3538         if (amdgpu_gpu_recovery == 0)
3539                 goto disabled;
3540
3541         if (amdgpu_sriov_vf(adev))
3542                 return true;
3543
3544         if (amdgpu_gpu_recovery == -1) {
3545                 switch (adev->asic_type) {
3546                 case CHIP_BONAIRE:
3547                 case CHIP_HAWAII:
3548                 case CHIP_TOPAZ:
3549                 case CHIP_TONGA:
3550                 case CHIP_FIJI:
3551                 case CHIP_POLARIS10:
3552                 case CHIP_POLARIS11:
3553                 case CHIP_POLARIS12:
3554                 case CHIP_VEGAM:
3555                 case CHIP_VEGA20:
3556                 case CHIP_VEGA10:
3557                 case CHIP_VEGA12:
3558                 case CHIP_RAVEN:
3559                         break;
3560                 default:
3561                         goto disabled;
3562                 }
3563         }
3564
3565         return true;
3566
3567 disabled:
3568                 DRM_INFO("GPU recovery disabled.\n");
3569                 return false;
3570 }
3571
3572
3573 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3574                                         struct amdgpu_job *job,
3575                                         bool *need_full_reset_arg)
3576 {
3577         int i, r = 0;
3578         bool need_full_reset  = *need_full_reset_arg;
3579
3580         /* block all schedulers and reset given job's ring */
3581         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3582                 struct amdgpu_ring *ring = adev->rings[i];
3583
3584                 if (!ring || !ring->sched.thread)
3585                         continue;
3586
3587                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3588                 amdgpu_fence_driver_force_completion(ring);
3589         }
3590
3591         if(job)
3592                 drm_sched_increase_karma(&job->base);
3593
3594         /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
3595         if (!amdgpu_sriov_vf(adev)) {
3596
3597                 if (!need_full_reset)
3598                         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3599
3600                 if (!need_full_reset) {
3601                         amdgpu_device_ip_pre_soft_reset(adev);
3602                         r = amdgpu_device_ip_soft_reset(adev);
3603                         amdgpu_device_ip_post_soft_reset(adev);
3604                         if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3605                                 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3606                                 need_full_reset = true;
3607                         }
3608                 }
3609
3610                 if (need_full_reset)
3611                         r = amdgpu_device_ip_suspend(adev);
3612
3613                 *need_full_reset_arg = need_full_reset;
3614         }
3615
3616         return r;
3617 }
3618
3619 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3620                                struct list_head *device_list_handle,
3621                                bool *need_full_reset_arg)
3622 {
3623         struct amdgpu_device *tmp_adev = NULL;
3624         bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3625         int r = 0;
3626
3627         /*
3628          * ASIC reset has to be done on all HGMI hive nodes ASAP
3629          * to allow proper links negotiation in FW (within 1 sec)
3630          */
3631         if (need_full_reset) {
3632                 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3633                         /* For XGMI run all resets in parallel to speed up the process */
3634                         if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3635                                 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3636                                         r = -EALREADY;
3637                         } else
3638                                 r = amdgpu_asic_reset(tmp_adev);
3639
3640                         if (r) {
3641                                 DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
3642                                          r, tmp_adev->ddev->unique);
3643                                 break;
3644                         }
3645                 }
3646
3647                 /* For XGMI wait for all PSP resets to complete before proceed */
3648                 if (!r) {
3649                         list_for_each_entry(tmp_adev, device_list_handle,
3650                                             gmc.xgmi.head) {
3651                                 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3652                                         flush_work(&tmp_adev->xgmi_reset_work);
3653                                         r = tmp_adev->asic_reset_res;
3654                                         if (r)
3655                                                 break;
3656                                 }
3657                         }
3658                 }
3659         }
3660
3661
3662         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3663                 if (need_full_reset) {
3664                         /* post card */
3665                         if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3666                                 DRM_WARN("asic atom init failed!");
3667
3668                         if (!r) {
3669                                 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3670                                 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3671                                 if (r)
3672                                         goto out;
3673
3674                                 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3675                                 if (vram_lost) {
3676                                         DRM_INFO("VRAM is lost due to GPU reset!\n");
3677                                         amdgpu_inc_vram_lost(tmp_adev);
3678                                 }
3679
3680                                 r = amdgpu_gtt_mgr_recover(
3681                                         &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3682                                 if (r)
3683                                         goto out;
3684
3685                                 r = amdgpu_device_fw_loading(tmp_adev);
3686                                 if (r)
3687                                         return r;
3688
3689                                 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3690                                 if (r)
3691                                         goto out;
3692
3693                                 if (vram_lost)
3694                                         amdgpu_device_fill_reset_magic(tmp_adev);
3695
3696                                 /*
3697                                  * Add this ASIC as tracked as reset was already
3698                                  * complete successfully.
3699                                  */
3700                                 amdgpu_register_gpu_instance(tmp_adev);
3701
3702                                 r = amdgpu_device_ip_late_init(tmp_adev);
3703                                 if (r)
3704                                         goto out;
3705
3706                                 /* must succeed. */
3707                                 amdgpu_ras_resume(tmp_adev);
3708
3709                                 /* Update PSP FW topology after reset */
3710                                 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3711                                         r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3712                         }
3713                 }
3714
3715
3716 out:
3717                 if (!r) {
3718                         amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3719                         r = amdgpu_ib_ring_tests(tmp_adev);
3720                         if (r) {
3721                                 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3722                                 r = amdgpu_device_ip_suspend(tmp_adev);
3723                                 need_full_reset = true;
3724                                 r = -EAGAIN;
3725                                 goto end;
3726                         }
3727                 }
3728
3729                 if (!r)
3730                         r = amdgpu_device_recover_vram(tmp_adev);
3731                 else
3732                         tmp_adev->asic_reset_res = r;
3733         }
3734
3735 end:
3736         *need_full_reset_arg = need_full_reset;
3737         return r;
3738 }
3739
3740 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
3741 {
3742         if (trylock) {
3743                 if (!mutex_trylock(&adev->lock_reset))
3744                         return false;
3745         } else
3746                 mutex_lock(&adev->lock_reset);
3747
3748         atomic_inc(&adev->gpu_reset_counter);
3749         adev->in_gpu_reset = 1;
3750         switch (amdgpu_asic_reset_method(adev)) {
3751         case AMD_RESET_METHOD_MODE1:
3752                 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
3753                 break;
3754         case AMD_RESET_METHOD_MODE2:
3755                 adev->mp1_state = PP_MP1_STATE_RESET;
3756                 break;
3757         default:
3758                 adev->mp1_state = PP_MP1_STATE_NONE;
3759                 break;
3760         }
3761
3762         return true;
3763 }
3764
3765 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3766 {
3767         amdgpu_vf_error_trans_all(adev);
3768         adev->mp1_state = PP_MP1_STATE_NONE;
3769         adev->in_gpu_reset = 0;
3770         mutex_unlock(&adev->lock_reset);
3771 }
3772
3773 /**
3774  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3775  *
3776  * @adev: amdgpu device pointer
3777  * @job: which job trigger hang
3778  *
3779  * Attempt to reset the GPU if it has hung (all asics).
3780  * Attempt to do soft-reset or full-reset and reinitialize Asic
3781  * Returns 0 for success or an error on failure.
3782  */
3783
3784 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3785                               struct amdgpu_job *job)
3786 {
3787         struct list_head device_list, *device_list_handle =  NULL;
3788         bool need_full_reset, job_signaled;
3789         struct amdgpu_hive_info *hive = NULL;
3790         struct amdgpu_device *tmp_adev = NULL;
3791         int i, r = 0;
3792         bool in_ras_intr = amdgpu_ras_intr_triggered();
3793
3794         /*
3795          * Flush RAM to disk so that after reboot
3796          * the user can read log and see why the system rebooted.
3797          */
3798         if (in_ras_intr && amdgpu_ras_get_context(adev)->reboot) {
3799
3800                 DRM_WARN("Emergency reboot.");
3801
3802                 ksys_sync_helper();
3803                 emergency_restart();
3804         }
3805
3806         need_full_reset = job_signaled = false;
3807         INIT_LIST_HEAD(&device_list);
3808
3809         dev_info(adev->dev, "GPU %s begin!\n", in_ras_intr ? "jobs stop":"reset");
3810
3811         cancel_delayed_work_sync(&adev->delayed_init_work);
3812
3813         hive = amdgpu_get_xgmi_hive(adev, false);
3814
3815         /*
3816          * Here we trylock to avoid chain of resets executing from
3817          * either trigger by jobs on different adevs in XGMI hive or jobs on
3818          * different schedulers for same device while this TO handler is running.
3819          * We always reset all schedulers for device and all devices for XGMI
3820          * hive so that should take care of them too.
3821          */
3822
3823         if (hive && !mutex_trylock(&hive->reset_lock)) {
3824                 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
3825                           job ? job->base.id : -1, hive->hive_id);
3826                 return 0;
3827         }
3828
3829         /* Start with adev pre asic reset first for soft reset check.*/
3830         if (!amdgpu_device_lock_adev(adev, !hive)) {
3831                 DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
3832                           job ? job->base.id : -1);
3833                 return 0;
3834         }
3835
3836         /* Block kfd: SRIOV would do it separately */
3837         if (!amdgpu_sriov_vf(adev))
3838                 amdgpu_amdkfd_pre_reset(adev);
3839
3840         /* Build list of devices to reset */
3841         if  (adev->gmc.xgmi.num_physical_nodes > 1) {
3842                 if (!hive) {
3843                         /*unlock kfd: SRIOV would do it separately */
3844                         if (!amdgpu_sriov_vf(adev))
3845                                 amdgpu_amdkfd_post_reset(adev);
3846                         amdgpu_device_unlock_adev(adev);
3847                         return -ENODEV;
3848                 }
3849
3850                 /*
3851                  * In case we are in XGMI hive mode device reset is done for all the
3852                  * nodes in the hive to retrain all XGMI links and hence the reset
3853                  * sequence is executed in loop on all nodes.
3854                  */
3855                 device_list_handle = &hive->device_list;
3856         } else {
3857                 list_add_tail(&adev->gmc.xgmi.head, &device_list);
3858                 device_list_handle = &device_list;
3859         }
3860
3861         /* block all schedulers and reset given job's ring */
3862         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3863                 if (tmp_adev != adev) {
3864                         amdgpu_device_lock_adev(tmp_adev, false);
3865                         if (!amdgpu_sriov_vf(tmp_adev))
3866                                         amdgpu_amdkfd_pre_reset(tmp_adev);
3867                 }
3868
3869                 /*
3870                  * Mark these ASICs to be reseted as untracked first
3871                  * And add them back after reset completed
3872                  */
3873                 amdgpu_unregister_gpu_instance(tmp_adev);
3874
3875                 /* disable ras on ALL IPs */
3876                 if (!in_ras_intr && amdgpu_device_ip_need_full_reset(tmp_adev))
3877                         amdgpu_ras_suspend(tmp_adev);
3878
3879                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3880                         struct amdgpu_ring *ring = tmp_adev->rings[i];
3881
3882                         if (!ring || !ring->sched.thread)
3883                                 continue;
3884
3885                         drm_sched_stop(&ring->sched, job ? &job->base : NULL);
3886
3887                         if (in_ras_intr)
3888                                 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
3889                 }
3890         }
3891
3892
3893         if (in_ras_intr)
3894                 goto skip_sched_resume;
3895
3896         /*
3897          * Must check guilty signal here since after this point all old
3898          * HW fences are force signaled.
3899          *
3900          * job->base holds a reference to parent fence
3901          */
3902         if (job && job->base.s_fence->parent &&
3903             dma_fence_is_signaled(job->base.s_fence->parent))
3904                 job_signaled = true;
3905
3906         if (job_signaled) {
3907                 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
3908                 goto skip_hw_reset;
3909         }
3910
3911
3912         /* Guilty job will be freed after this*/
3913         r = amdgpu_device_pre_asic_reset(adev, job, &need_full_reset);
3914         if (r) {
3915                 /*TODO Should we stop ?*/
3916                 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3917                           r, adev->ddev->unique);
3918                 adev->asic_reset_res = r;
3919         }
3920
3921 retry:  /* Rest of adevs pre asic reset from XGMI hive. */
3922         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3923
3924                 if (tmp_adev == adev)
3925                         continue;
3926
3927                 r = amdgpu_device_pre_asic_reset(tmp_adev,
3928                                                  NULL,
3929                                                  &need_full_reset);
3930                 /*TODO Should we stop ?*/
3931                 if (r) {
3932                         DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3933                                   r, tmp_adev->ddev->unique);
3934                         tmp_adev->asic_reset_res = r;
3935                 }
3936         }
3937
3938         /* Actual ASIC resets if needed.*/
3939         /* TODO Implement XGMI hive reset logic for SRIOV */
3940         if (amdgpu_sriov_vf(adev)) {
3941                 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3942                 if (r)
3943                         adev->asic_reset_res = r;
3944         } else {
3945                 r  = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
3946                 if (r && r == -EAGAIN)
3947                         goto retry;
3948         }
3949
3950 skip_hw_reset:
3951
3952         /* Post ASIC reset for all devs .*/
3953         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3954
3955                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3956                         struct amdgpu_ring *ring = tmp_adev->rings[i];
3957
3958                         if (!ring || !ring->sched.thread)
3959                                 continue;
3960
3961                         /* No point to resubmit jobs if we didn't HW reset*/
3962                         if (!tmp_adev->asic_reset_res && !job_signaled)
3963                                 drm_sched_resubmit_jobs(&ring->sched);
3964
3965                         drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
3966                 }
3967
3968                 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
3969                         drm_helper_resume_force_mode(tmp_adev->ddev);
3970                 }
3971
3972                 tmp_adev->asic_reset_res = 0;
3973
3974                 if (r) {
3975                         /* bad news, how to tell it to userspace ? */
3976                         dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
3977                         amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3978                 } else {
3979                         dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
3980                 }
3981         }
3982
3983 skip_sched_resume:
3984         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3985                 /*unlock kfd: SRIOV would do it separately */
3986                 if (!in_ras_intr && !amdgpu_sriov_vf(tmp_adev))
3987                         amdgpu_amdkfd_post_reset(tmp_adev);
3988                 amdgpu_device_unlock_adev(tmp_adev);
3989         }
3990
3991         if (hive)
3992                 mutex_unlock(&hive->reset_lock);
3993
3994         if (r)
3995                 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
3996         return r;
3997 }
3998
3999 /**
4000  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
4001  *
4002  * @adev: amdgpu_device pointer
4003  *
4004  * Fetchs and stores in the driver the PCIE capabilities (gen speed
4005  * and lanes) of the slot the device is in. Handles APUs and
4006  * virtualized environments where PCIE config space may not be available.
4007  */
4008 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
4009 {
4010         struct pci_dev *pdev;
4011         enum pci_bus_speed speed_cap, platform_speed_cap;
4012         enum pcie_link_width platform_link_width;
4013
4014         if (amdgpu_pcie_gen_cap)
4015                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
4016
4017         if (amdgpu_pcie_lane_cap)
4018                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
4019
4020         /* covers APUs as well */
4021         if (pci_is_root_bus(adev->pdev->bus)) {
4022                 if (adev->pm.pcie_gen_mask == 0)
4023                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
4024                 if (adev->pm.pcie_mlw_mask == 0)
4025                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4026                 return;
4027         }
4028
4029         if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
4030                 return;
4031
4032         pcie_bandwidth_available(adev->pdev, NULL,
4033                                  &platform_speed_cap, &platform_link_width);
4034
4035         if (adev->pm.pcie_gen_mask == 0) {
4036                 /* asic caps */
4037                 pdev = adev->pdev;
4038                 speed_cap = pcie_get_speed_cap(pdev);
4039                 if (speed_cap == PCI_SPEED_UNKNOWN) {
4040                         adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4041                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4042                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4043                 } else {
4044                         if (speed_cap == PCIE_SPEED_16_0GT)
4045                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4046                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4047                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4048                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
4049                         else if (speed_cap == PCIE_SPEED_8_0GT)
4050                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4051                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4052                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4053                         else if (speed_cap == PCIE_SPEED_5_0GT)
4054                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4055                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
4056                         else
4057                                 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
4058                 }
4059                 /* platform caps */
4060                 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
4061                         adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4062                                                    CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4063                 } else {
4064                         if (platform_speed_cap == PCIE_SPEED_16_0GT)
4065                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4066                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4067                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4068                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
4069                         else if (platform_speed_cap == PCIE_SPEED_8_0GT)
4070                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4071                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4072                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
4073                         else if (platform_speed_cap == PCIE_SPEED_5_0GT)
4074                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4075                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4076                         else
4077                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
4078
4079                 }
4080         }
4081         if (adev->pm.pcie_mlw_mask == 0) {
4082                 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
4083                         adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
4084                 } else {
4085                         switch (platform_link_width) {
4086                         case PCIE_LNK_X32:
4087                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
4088                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4089                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4090                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4091                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4092                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4093                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4094                                 break;
4095                         case PCIE_LNK_X16:
4096                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4097                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4098                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4099                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4100                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4101                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4102                                 break;
4103                         case PCIE_LNK_X12:
4104                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4105                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4106                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4107                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4108                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4109                                 break;
4110                         case PCIE_LNK_X8:
4111                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4112                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4113                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4114                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4115                                 break;
4116                         case PCIE_LNK_X4:
4117                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4118                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4119                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4120                                 break;
4121                         case PCIE_LNK_X2:
4122                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4123                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4124                                 break;
4125                         case PCIE_LNK_X1:
4126                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
4127                                 break;
4128                         default:
4129                                 break;
4130                         }
4131                 }
4132         }
4133 }
4134