2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
33 #include <linux/iommu.h>
34 #include <linux/pci.h>
35 #include <linux/pci-p2pdma.h>
36 #include <linux/apple-gmux.h>
38 #include <drm/drm_aperture.h>
39 #include <drm/drm_atomic_helper.h>
40 #include <drm/drm_crtc_helper.h>
41 #include <drm/drm_fb_helper.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/amdgpu_drm.h>
44 #include <linux/device.h>
45 #include <linux/vgaarb.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/efi.h>
49 #include "amdgpu_trace.h"
50 #include "amdgpu_i2c.h"
52 #include "amdgpu_atombios.h"
53 #include "amdgpu_atomfirmware.h"
55 #ifdef CONFIG_DRM_AMDGPU_SI
58 #ifdef CONFIG_DRM_AMDGPU_CIK
64 #include "bif/bif_4_1_d.h"
65 #include <linux/firmware.h>
66 #include "amdgpu_vf_error.h"
68 #include "amdgpu_amdkfd.h"
69 #include "amdgpu_pm.h"
71 #include "amdgpu_xgmi.h"
72 #include "amdgpu_ras.h"
73 #include "amdgpu_pmu.h"
74 #include "amdgpu_fru_eeprom.h"
75 #include "amdgpu_reset.h"
76 #include "amdgpu_virt.h"
78 #include <linux/suspend.h>
79 #include <drm/task_barrier.h>
80 #include <linux/pm_runtime.h>
82 #include <drm/drm_drv.h>
84 #if IS_ENABLED(CONFIG_X86)
85 #include <asm/intel-family.h>
88 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
89 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
90 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
91 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
92 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
93 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
94 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
96 #define AMDGPU_RESUME_MS 2000
97 #define AMDGPU_MAX_RETRY_LIMIT 2
98 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
100 static const struct drm_driver amdgpu_kms_driver;
102 const char *amdgpu_asic_name[] = {
144 * DOC: pcie_replay_count
146 * The amdgpu driver provides a sysfs API for reporting the total number
147 * of PCIe replays (NAKs)
148 * The file pcie_replay_count is used for this and returns the total
149 * number of replays as a sum of the NAKs generated and NAKs received
152 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
153 struct device_attribute *attr, char *buf)
155 struct drm_device *ddev = dev_get_drvdata(dev);
156 struct amdgpu_device *adev = drm_to_adev(ddev);
157 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
159 return sysfs_emit(buf, "%llu\n", cnt);
162 static DEVICE_ATTR(pcie_replay_count, 0444,
163 amdgpu_device_get_pcie_replay_count, NULL);
165 static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj,
166 struct bin_attribute *attr, char *buf,
167 loff_t ppos, size_t count)
169 struct device *dev = kobj_to_dev(kobj);
170 struct drm_device *ddev = dev_get_drvdata(dev);
171 struct amdgpu_device *adev = drm_to_adev(ddev);
175 case AMDGPU_SYS_REG_STATE_XGMI:
176 bytes_read = amdgpu_asic_get_reg_state(
177 adev, AMDGPU_REG_STATE_TYPE_XGMI, buf, count);
179 case AMDGPU_SYS_REG_STATE_WAFL:
180 bytes_read = amdgpu_asic_get_reg_state(
181 adev, AMDGPU_REG_STATE_TYPE_WAFL, buf, count);
183 case AMDGPU_SYS_REG_STATE_PCIE:
184 bytes_read = amdgpu_asic_get_reg_state(
185 adev, AMDGPU_REG_STATE_TYPE_PCIE, buf, count);
187 case AMDGPU_SYS_REG_STATE_USR:
188 bytes_read = amdgpu_asic_get_reg_state(
189 adev, AMDGPU_REG_STATE_TYPE_USR, buf, count);
191 case AMDGPU_SYS_REG_STATE_USR_1:
192 bytes_read = amdgpu_asic_get_reg_state(
193 adev, AMDGPU_REG_STATE_TYPE_USR_1, buf, count);
202 BIN_ATTR(reg_state, 0444, amdgpu_sysfs_reg_state_get, NULL,
203 AMDGPU_SYS_REG_STATE_END);
205 int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev)
209 if (!amdgpu_asic_get_reg_state_supported(adev))
212 ret = sysfs_create_bin_file(&adev->dev->kobj, &bin_attr_reg_state);
217 void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev)
219 if (!amdgpu_asic_get_reg_state_supported(adev))
221 sysfs_remove_bin_file(&adev->dev->kobj, &bin_attr_reg_state);
227 * The amdgpu driver provides a sysfs API for giving board related information.
228 * It provides the form factor information in the format
232 * Possible form factor values
234 * - "cem" - PCIE CEM card
235 * - "oam" - Open Compute Accelerator Module
236 * - "unknown" - Not known
240 static ssize_t amdgpu_device_get_board_info(struct device *dev,
241 struct device_attribute *attr,
244 struct drm_device *ddev = dev_get_drvdata(dev);
245 struct amdgpu_device *adev = drm_to_adev(ddev);
246 enum amdgpu_pkg_type pkg_type = AMDGPU_PKG_TYPE_CEM;
249 if (adev->smuio.funcs && adev->smuio.funcs->get_pkg_type)
250 pkg_type = adev->smuio.funcs->get_pkg_type(adev);
253 case AMDGPU_PKG_TYPE_CEM:
256 case AMDGPU_PKG_TYPE_OAM:
264 return sysfs_emit(buf, "%s : %s\n", "type", pkg);
267 static DEVICE_ATTR(board_info, 0444, amdgpu_device_get_board_info, NULL);
269 static struct attribute *amdgpu_board_attrs[] = {
270 &dev_attr_board_info.attr,
274 static umode_t amdgpu_board_attrs_is_visible(struct kobject *kobj,
275 struct attribute *attr, int n)
277 struct device *dev = kobj_to_dev(kobj);
278 struct drm_device *ddev = dev_get_drvdata(dev);
279 struct amdgpu_device *adev = drm_to_adev(ddev);
281 if (adev->flags & AMD_IS_APU)
287 static const struct attribute_group amdgpu_board_attrs_group = {
288 .attrs = amdgpu_board_attrs,
289 .is_visible = amdgpu_board_attrs_is_visible
292 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
296 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
298 * @dev: drm_device pointer
300 * Returns true if the device is a dGPU with ATPX power control,
301 * otherwise return false.
303 bool amdgpu_device_supports_px(struct drm_device *dev)
305 struct amdgpu_device *adev = drm_to_adev(dev);
307 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
313 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
315 * @dev: drm_device pointer
317 * Returns true if the device is a dGPU with ACPI power control,
318 * otherwise return false.
320 bool amdgpu_device_supports_boco(struct drm_device *dev)
322 struct amdgpu_device *adev = drm_to_adev(dev);
325 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
331 * amdgpu_device_supports_baco - Does the device support BACO
333 * @dev: drm_device pointer
335 * Returns true if the device supporte BACO,
336 * otherwise return false.
338 bool amdgpu_device_supports_baco(struct drm_device *dev)
340 struct amdgpu_device *adev = drm_to_adev(dev);
342 return amdgpu_asic_supports_baco(adev);
346 * amdgpu_device_supports_smart_shift - Is the device dGPU with
347 * smart shift support
349 * @dev: drm_device pointer
351 * Returns true if the device is a dGPU with Smart Shift support,
352 * otherwise returns false.
354 bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
356 return (amdgpu_device_supports_boco(dev) &&
357 amdgpu_acpi_is_power_shift_control_supported());
361 * VRAM access helper functions
365 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
367 * @adev: amdgpu_device pointer
368 * @pos: offset of the buffer in vram
369 * @buf: virtual address of the buffer in system memory
370 * @size: read/write size, sizeof(@buf) must > @size
371 * @write: true - write to vram, otherwise - read from vram
373 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
374 void *buf, size_t size, bool write)
377 uint32_t hi = ~0, tmp = 0;
378 uint32_t *data = buf;
382 if (!drm_dev_enter(adev_to_drm(adev), &idx))
385 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
387 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
388 for (last = pos + size; pos < last; pos += 4) {
391 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
393 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
397 WREG32_NO_KIQ(mmMM_DATA, *data++);
399 *data++ = RREG32_NO_KIQ(mmMM_DATA);
402 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
407 * amdgpu_device_aper_access - access vram by vram aperature
409 * @adev: amdgpu_device pointer
410 * @pos: offset of the buffer in vram
411 * @buf: virtual address of the buffer in system memory
412 * @size: read/write size, sizeof(@buf) must > @size
413 * @write: true - write to vram, otherwise - read from vram
415 * The return value means how many bytes have been transferred.
417 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
418 void *buf, size_t size, bool write)
425 if (!adev->mman.aper_base_kaddr)
428 last = min(pos + size, adev->gmc.visible_vram_size);
430 addr = adev->mman.aper_base_kaddr + pos;
434 memcpy_toio(addr, buf, count);
435 /* Make sure HDP write cache flush happens without any reordering
436 * after the system memory contents are sent over PCIe device
439 amdgpu_device_flush_hdp(adev, NULL);
441 amdgpu_device_invalidate_hdp(adev, NULL);
442 /* Make sure HDP read cache is invalidated before issuing a read
446 memcpy_fromio(buf, addr, count);
458 * amdgpu_device_vram_access - read/write a buffer in vram
460 * @adev: amdgpu_device pointer
461 * @pos: offset of the buffer in vram
462 * @buf: virtual address of the buffer in system memory
463 * @size: read/write size, sizeof(@buf) must > @size
464 * @write: true - write to vram, otherwise - read from vram
466 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
467 void *buf, size_t size, bool write)
471 /* try to using vram apreature to access vram first */
472 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
475 /* using MM to access rest vram */
478 amdgpu_device_mm_access(adev, pos, buf, size, write);
483 * register access helper functions.
486 /* Check if hw access should be skipped because of hotplug or device error */
487 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
489 if (adev->no_hw_access)
492 #ifdef CONFIG_LOCKDEP
494 * This is a bit complicated to understand, so worth a comment. What we assert
495 * here is that the GPU reset is not running on another thread in parallel.
497 * For this we trylock the read side of the reset semaphore, if that succeeds
498 * we know that the reset is not running in paralell.
500 * If the trylock fails we assert that we are either already holding the read
501 * side of the lock or are the reset thread itself and hold the write side of
505 if (down_read_trylock(&adev->reset_domain->sem))
506 up_read(&adev->reset_domain->sem);
508 lockdep_assert_held(&adev->reset_domain->sem);
515 * amdgpu_device_rreg - read a memory mapped IO or indirect register
517 * @adev: amdgpu_device pointer
518 * @reg: dword aligned register offset
519 * @acc_flags: access flags which require special behavior
521 * Returns the 32 bit value from the offset specified.
523 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
524 uint32_t reg, uint32_t acc_flags)
528 if (amdgpu_device_skip_hw_access(adev))
531 if ((reg * 4) < adev->rmmio_size) {
532 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
533 amdgpu_sriov_runtime(adev) &&
534 down_read_trylock(&adev->reset_domain->sem)) {
535 ret = amdgpu_kiq_rreg(adev, reg, 0);
536 up_read(&adev->reset_domain->sem);
538 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
541 ret = adev->pcie_rreg(adev, reg * 4);
544 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
550 * MMIO register read with bytes helper functions
551 * @offset:bytes offset from MMIO start
555 * amdgpu_mm_rreg8 - read a memory mapped IO register
557 * @adev: amdgpu_device pointer
558 * @offset: byte aligned register offset
560 * Returns the 8 bit value from the offset specified.
562 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
564 if (amdgpu_device_skip_hw_access(adev))
567 if (offset < adev->rmmio_size)
568 return (readb(adev->rmmio + offset));
574 * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC
576 * @adev: amdgpu_device pointer
577 * @reg: dword aligned register offset
578 * @acc_flags: access flags which require special behavior
579 * @xcc_id: xcc accelerated compute core id
581 * Returns the 32 bit value from the offset specified.
583 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
584 uint32_t reg, uint32_t acc_flags,
587 uint32_t ret, rlcg_flag;
589 if (amdgpu_device_skip_hw_access(adev))
592 if ((reg * 4) < adev->rmmio_size) {
593 if (amdgpu_sriov_vf(adev) &&
594 !amdgpu_sriov_runtime(adev) &&
595 adev->gfx.rlc.rlcg_reg_access_supported &&
596 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
599 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, xcc_id);
600 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
601 amdgpu_sriov_runtime(adev) &&
602 down_read_trylock(&adev->reset_domain->sem)) {
603 ret = amdgpu_kiq_rreg(adev, reg, xcc_id);
604 up_read(&adev->reset_domain->sem);
606 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
609 ret = adev->pcie_rreg(adev, reg * 4);
616 * MMIO register write with bytes helper functions
617 * @offset:bytes offset from MMIO start
618 * @value: the value want to be written to the register
622 * amdgpu_mm_wreg8 - read a memory mapped IO register
624 * @adev: amdgpu_device pointer
625 * @offset: byte aligned register offset
626 * @value: 8 bit value to write
628 * Writes the value specified to the offset specified.
630 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
632 if (amdgpu_device_skip_hw_access(adev))
635 if (offset < adev->rmmio_size)
636 writeb(value, adev->rmmio + offset);
642 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
644 * @adev: amdgpu_device pointer
645 * @reg: dword aligned register offset
646 * @v: 32 bit value to write to the register
647 * @acc_flags: access flags which require special behavior
649 * Writes the value specified to the offset specified.
651 void amdgpu_device_wreg(struct amdgpu_device *adev,
652 uint32_t reg, uint32_t v,
655 if (amdgpu_device_skip_hw_access(adev))
658 if ((reg * 4) < adev->rmmio_size) {
659 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
660 amdgpu_sriov_runtime(adev) &&
661 down_read_trylock(&adev->reset_domain->sem)) {
662 amdgpu_kiq_wreg(adev, reg, v, 0);
663 up_read(&adev->reset_domain->sem);
665 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
668 adev->pcie_wreg(adev, reg * 4, v);
671 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
675 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
677 * @adev: amdgpu_device pointer
678 * @reg: mmio/rlc register
680 * @xcc_id: xcc accelerated compute core id
682 * this function is invoked only for the debugfs register access
684 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
685 uint32_t reg, uint32_t v,
688 if (amdgpu_device_skip_hw_access(adev))
691 if (amdgpu_sriov_fullaccess(adev) &&
692 adev->gfx.rlc.funcs &&
693 adev->gfx.rlc.funcs->is_rlcg_access_range) {
694 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
695 return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
696 } else if ((reg * 4) >= adev->rmmio_size) {
697 adev->pcie_wreg(adev, reg * 4, v);
699 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
704 * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC
706 * @adev: amdgpu_device pointer
707 * @reg: dword aligned register offset
708 * @v: 32 bit value to write to the register
709 * @acc_flags: access flags which require special behavior
710 * @xcc_id: xcc accelerated compute core id
712 * Writes the value specified to the offset specified.
714 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
715 uint32_t reg, uint32_t v,
716 uint32_t acc_flags, uint32_t xcc_id)
720 if (amdgpu_device_skip_hw_access(adev))
723 if ((reg * 4) < adev->rmmio_size) {
724 if (amdgpu_sriov_vf(adev) &&
725 !amdgpu_sriov_runtime(adev) &&
726 adev->gfx.rlc.rlcg_reg_access_supported &&
727 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
730 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, xcc_id);
731 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
732 amdgpu_sriov_runtime(adev) &&
733 down_read_trylock(&adev->reset_domain->sem)) {
734 amdgpu_kiq_wreg(adev, reg, v, xcc_id);
735 up_read(&adev->reset_domain->sem);
737 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
740 adev->pcie_wreg(adev, reg * 4, v);
745 * amdgpu_device_indirect_rreg - read an indirect register
747 * @adev: amdgpu_device pointer
748 * @reg_addr: indirect register address to read from
750 * Returns the value of indirect register @reg_addr
752 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
755 unsigned long flags, pcie_index, pcie_data;
756 void __iomem *pcie_index_offset;
757 void __iomem *pcie_data_offset;
760 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
761 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
763 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
764 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
765 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
767 writel(reg_addr, pcie_index_offset);
768 readl(pcie_index_offset);
769 r = readl(pcie_data_offset);
770 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
775 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
778 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
780 void __iomem *pcie_index_offset;
781 void __iomem *pcie_index_hi_offset;
782 void __iomem *pcie_data_offset;
784 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
785 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
786 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
787 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
791 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
792 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
793 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
794 if (pcie_index_hi != 0)
795 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
798 writel(reg_addr, pcie_index_offset);
799 readl(pcie_index_offset);
800 if (pcie_index_hi != 0) {
801 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
802 readl(pcie_index_hi_offset);
804 r = readl(pcie_data_offset);
806 /* clear the high bits */
807 if (pcie_index_hi != 0) {
808 writel(0, pcie_index_hi_offset);
809 readl(pcie_index_hi_offset);
812 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
818 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
820 * @adev: amdgpu_device pointer
821 * @reg_addr: indirect register address to read from
823 * Returns the value of indirect register @reg_addr
825 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
828 unsigned long flags, pcie_index, pcie_data;
829 void __iomem *pcie_index_offset;
830 void __iomem *pcie_data_offset;
833 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
834 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
836 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
837 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
838 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
840 /* read low 32 bits */
841 writel(reg_addr, pcie_index_offset);
842 readl(pcie_index_offset);
843 r = readl(pcie_data_offset);
844 /* read high 32 bits */
845 writel(reg_addr + 4, pcie_index_offset);
846 readl(pcie_index_offset);
847 r |= ((u64)readl(pcie_data_offset) << 32);
848 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
853 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
856 unsigned long flags, pcie_index, pcie_data;
857 unsigned long pcie_index_hi = 0;
858 void __iomem *pcie_index_offset;
859 void __iomem *pcie_index_hi_offset;
860 void __iomem *pcie_data_offset;
863 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
864 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
865 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
866 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
868 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
869 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
870 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
871 if (pcie_index_hi != 0)
872 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
875 /* read low 32 bits */
876 writel(reg_addr, pcie_index_offset);
877 readl(pcie_index_offset);
878 if (pcie_index_hi != 0) {
879 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
880 readl(pcie_index_hi_offset);
882 r = readl(pcie_data_offset);
883 /* read high 32 bits */
884 writel(reg_addr + 4, pcie_index_offset);
885 readl(pcie_index_offset);
886 if (pcie_index_hi != 0) {
887 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
888 readl(pcie_index_hi_offset);
890 r |= ((u64)readl(pcie_data_offset) << 32);
892 /* clear the high bits */
893 if (pcie_index_hi != 0) {
894 writel(0, pcie_index_hi_offset);
895 readl(pcie_index_hi_offset);
898 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
904 * amdgpu_device_indirect_wreg - write an indirect register address
906 * @adev: amdgpu_device pointer
907 * @reg_addr: indirect register offset
908 * @reg_data: indirect register data
911 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
912 u32 reg_addr, u32 reg_data)
914 unsigned long flags, pcie_index, pcie_data;
915 void __iomem *pcie_index_offset;
916 void __iomem *pcie_data_offset;
918 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
919 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
921 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
922 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
923 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
925 writel(reg_addr, pcie_index_offset);
926 readl(pcie_index_offset);
927 writel(reg_data, pcie_data_offset);
928 readl(pcie_data_offset);
929 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
932 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
933 u64 reg_addr, u32 reg_data)
935 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
936 void __iomem *pcie_index_offset;
937 void __iomem *pcie_index_hi_offset;
938 void __iomem *pcie_data_offset;
940 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
941 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
942 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
943 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
947 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
948 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
949 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
950 if (pcie_index_hi != 0)
951 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
954 writel(reg_addr, pcie_index_offset);
955 readl(pcie_index_offset);
956 if (pcie_index_hi != 0) {
957 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
958 readl(pcie_index_hi_offset);
960 writel(reg_data, pcie_data_offset);
961 readl(pcie_data_offset);
963 /* clear the high bits */
964 if (pcie_index_hi != 0) {
965 writel(0, pcie_index_hi_offset);
966 readl(pcie_index_hi_offset);
969 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
973 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
975 * @adev: amdgpu_device pointer
976 * @reg_addr: indirect register offset
977 * @reg_data: indirect register data
980 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
981 u32 reg_addr, u64 reg_data)
983 unsigned long flags, pcie_index, pcie_data;
984 void __iomem *pcie_index_offset;
985 void __iomem *pcie_data_offset;
987 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
988 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
990 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
991 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
992 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
994 /* write low 32 bits */
995 writel(reg_addr, pcie_index_offset);
996 readl(pcie_index_offset);
997 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
998 readl(pcie_data_offset);
999 /* write high 32 bits */
1000 writel(reg_addr + 4, pcie_index_offset);
1001 readl(pcie_index_offset);
1002 writel((u32)(reg_data >> 32), pcie_data_offset);
1003 readl(pcie_data_offset);
1004 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1007 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1008 u64 reg_addr, u64 reg_data)
1010 unsigned long flags, pcie_index, pcie_data;
1011 unsigned long pcie_index_hi = 0;
1012 void __iomem *pcie_index_offset;
1013 void __iomem *pcie_index_hi_offset;
1014 void __iomem *pcie_data_offset;
1016 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1017 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1018 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
1019 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
1021 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1022 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1023 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1024 if (pcie_index_hi != 0)
1025 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
1028 /* write low 32 bits */
1029 writel(reg_addr, pcie_index_offset);
1030 readl(pcie_index_offset);
1031 if (pcie_index_hi != 0) {
1032 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1033 readl(pcie_index_hi_offset);
1035 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
1036 readl(pcie_data_offset);
1037 /* write high 32 bits */
1038 writel(reg_addr + 4, pcie_index_offset);
1039 readl(pcie_index_offset);
1040 if (pcie_index_hi != 0) {
1041 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1042 readl(pcie_index_hi_offset);
1044 writel((u32)(reg_data >> 32), pcie_data_offset);
1045 readl(pcie_data_offset);
1047 /* clear the high bits */
1048 if (pcie_index_hi != 0) {
1049 writel(0, pcie_index_hi_offset);
1050 readl(pcie_index_hi_offset);
1053 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1057 * amdgpu_device_get_rev_id - query device rev_id
1059 * @adev: amdgpu_device pointer
1061 * Return device rev_id
1063 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)
1065 return adev->nbio.funcs->get_rev_id(adev);
1069 * amdgpu_invalid_rreg - dummy reg read function
1071 * @adev: amdgpu_device pointer
1072 * @reg: offset of register
1074 * Dummy register read function. Used for register blocks
1075 * that certain asics don't have (all asics).
1076 * Returns the value in the register.
1078 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
1080 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
1085 static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
1087 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1093 * amdgpu_invalid_wreg - dummy reg write function
1095 * @adev: amdgpu_device pointer
1096 * @reg: offset of register
1097 * @v: value to write to the register
1099 * Dummy register read function. Used for register blocks
1100 * that certain asics don't have (all asics).
1102 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
1104 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
1109 static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
1111 DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",
1117 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
1119 * @adev: amdgpu_device pointer
1120 * @reg: offset of register
1122 * Dummy register read function. Used for register blocks
1123 * that certain asics don't have (all asics).
1124 * Returns the value in the register.
1126 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
1128 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
1133 static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)
1135 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1141 * amdgpu_invalid_wreg64 - dummy reg write function
1143 * @adev: amdgpu_device pointer
1144 * @reg: offset of register
1145 * @v: value to write to the register
1147 * Dummy register read function. Used for register blocks
1148 * that certain asics don't have (all asics).
1150 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
1152 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
1157 static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)
1159 DRM_ERROR("Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",
1165 * amdgpu_block_invalid_rreg - dummy reg read function
1167 * @adev: amdgpu_device pointer
1168 * @block: offset of instance
1169 * @reg: offset of register
1171 * Dummy register read function. Used for register blocks
1172 * that certain asics don't have (all asics).
1173 * Returns the value in the register.
1175 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
1176 uint32_t block, uint32_t reg)
1178 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
1185 * amdgpu_block_invalid_wreg - dummy reg write function
1187 * @adev: amdgpu_device pointer
1188 * @block: offset of instance
1189 * @reg: offset of register
1190 * @v: value to write to the register
1192 * Dummy register read function. Used for register blocks
1193 * that certain asics don't have (all asics).
1195 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
1197 uint32_t reg, uint32_t v)
1199 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
1205 * amdgpu_device_asic_init - Wrapper for atom asic_init
1207 * @adev: amdgpu_device pointer
1209 * Does any asic specific work and then calls atom asic init.
1211 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
1215 amdgpu_asic_pre_asic_init(adev);
1217 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1218 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) {
1219 amdgpu_psp_wait_for_bootloader(adev);
1220 ret = amdgpu_atomfirmware_asic_init(adev, true);
1221 /* TODO: check the return val and stop device initialization if boot fails */
1222 amdgpu_psp_query_boot_status(adev);
1225 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
1232 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
1234 * @adev: amdgpu_device pointer
1236 * Allocates a scratch page of VRAM for use by various things in the
1239 static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
1241 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
1242 AMDGPU_GEM_DOMAIN_VRAM |
1243 AMDGPU_GEM_DOMAIN_GTT,
1244 &adev->mem_scratch.robj,
1245 &adev->mem_scratch.gpu_addr,
1246 (void **)&adev->mem_scratch.ptr);
1250 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
1252 * @adev: amdgpu_device pointer
1254 * Frees the VRAM scratch page.
1256 static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
1258 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
1262 * amdgpu_device_program_register_sequence - program an array of registers.
1264 * @adev: amdgpu_device pointer
1265 * @registers: pointer to the register array
1266 * @array_size: size of the register array
1268 * Programs an array or registers with and or masks.
1269 * This is a helper for setting golden registers.
1271 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1272 const u32 *registers,
1273 const u32 array_size)
1275 u32 tmp, reg, and_mask, or_mask;
1281 for (i = 0; i < array_size; i += 3) {
1282 reg = registers[i + 0];
1283 and_mask = registers[i + 1];
1284 or_mask = registers[i + 2];
1286 if (and_mask == 0xffffffff) {
1291 if (adev->family >= AMDGPU_FAMILY_AI)
1292 tmp |= (or_mask & and_mask);
1301 * amdgpu_device_pci_config_reset - reset the GPU
1303 * @adev: amdgpu_device pointer
1305 * Resets the GPU using the pci config reset sequence.
1306 * Only applicable to asics prior to vega10.
1308 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1310 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1314 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1316 * @adev: amdgpu_device pointer
1318 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1320 int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1322 return pci_reset_function(adev->pdev);
1326 * amdgpu_device_wb_*()
1327 * Writeback is the method by which the GPU updates special pages in memory
1328 * with the status of certain GPU events (fences, ring pointers,etc.).
1332 * amdgpu_device_wb_fini - Disable Writeback and free memory
1334 * @adev: amdgpu_device pointer
1336 * Disables Writeback and frees the Writeback memory (all asics).
1337 * Used at driver shutdown.
1339 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1341 if (adev->wb.wb_obj) {
1342 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1344 (void **)&adev->wb.wb);
1345 adev->wb.wb_obj = NULL;
1350 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1352 * @adev: amdgpu_device pointer
1354 * Initializes writeback and allocates writeback memory (all asics).
1355 * Used at driver startup.
1356 * Returns 0 on success or an -error on failure.
1358 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1362 if (adev->wb.wb_obj == NULL) {
1363 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1364 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1365 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1366 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1367 (void **)&adev->wb.wb);
1369 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1373 adev->wb.num_wb = AMDGPU_MAX_WB;
1374 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1376 /* clear wb memory */
1377 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1384 * amdgpu_device_wb_get - Allocate a wb entry
1386 * @adev: amdgpu_device pointer
1389 * Allocate a wb slot for use by the driver (all asics).
1390 * Returns 0 on success or -EINVAL on failure.
1392 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1394 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1396 if (offset < adev->wb.num_wb) {
1397 __set_bit(offset, adev->wb.used);
1398 *wb = offset << 3; /* convert to dw offset */
1406 * amdgpu_device_wb_free - Free a wb entry
1408 * @adev: amdgpu_device pointer
1411 * Free a wb slot allocated for use by the driver (all asics)
1413 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1416 if (wb < adev->wb.num_wb)
1417 __clear_bit(wb, adev->wb.used);
1421 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1423 * @adev: amdgpu_device pointer
1425 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1426 * to fail, but if any of the BARs is not accessible after the size we abort
1427 * driver loading by returning -ENODEV.
1429 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1431 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1432 struct pci_bus *root;
1433 struct resource *res;
1438 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
1442 if (amdgpu_sriov_vf(adev))
1445 /* skip if the bios has already enabled large BAR */
1446 if (adev->gmc.real_vram_size &&
1447 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1450 /* Check if the root BUS has 64bit memory resources */
1451 root = adev->pdev->bus;
1452 while (root->parent)
1453 root = root->parent;
1455 pci_bus_for_each_resource(root, res, i) {
1456 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1457 res->start > 0x100000000ull)
1461 /* Trying to resize is pointless without a root hub window above 4GB */
1465 /* Limit the BAR size to what is available */
1466 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1469 /* Disable memory decoding while we change the BAR addresses and size */
1470 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1471 pci_write_config_word(adev->pdev, PCI_COMMAND,
1472 cmd & ~PCI_COMMAND_MEMORY);
1474 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1475 amdgpu_doorbell_fini(adev);
1476 if (adev->asic_type >= CHIP_BONAIRE)
1477 pci_release_resource(adev->pdev, 2);
1479 pci_release_resource(adev->pdev, 0);
1481 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1483 DRM_INFO("Not enough PCI address space for a large BAR.");
1484 else if (r && r != -ENOTSUPP)
1485 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1487 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1489 /* When the doorbell or fb BAR isn't available we have no chance of
1492 r = amdgpu_doorbell_init(adev);
1493 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1496 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1501 static bool amdgpu_device_read_bios(struct amdgpu_device *adev)
1503 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
1510 * GPU helpers function.
1513 * amdgpu_device_need_post - check if the hw need post or not
1515 * @adev: amdgpu_device pointer
1517 * Check if the asic has been initialized (all asics) at driver startup
1518 * or post is needed if hw reset is performed.
1519 * Returns true if need or false if not.
1521 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1525 if (amdgpu_sriov_vf(adev))
1528 if (!amdgpu_device_read_bios(adev))
1531 if (amdgpu_passthrough(adev)) {
1532 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1533 * some old smc fw still need driver do vPost otherwise gpu hang, while
1534 * those smc fw version above 22.15 doesn't have this flaw, so we force
1535 * vpost executed for smc version below 22.15
1537 if (adev->asic_type == CHIP_FIJI) {
1541 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1542 /* force vPost if error occured */
1546 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1547 if (fw_ver < 0x00160e00)
1552 /* Don't post if we need to reset whole hive on init */
1553 if (adev->gmc.xgmi.pending_reset)
1556 if (adev->has_hw_reset) {
1557 adev->has_hw_reset = false;
1561 /* bios scratch used on CIK+ */
1562 if (adev->asic_type >= CHIP_BONAIRE)
1563 return amdgpu_atombios_scratch_need_asic_init(adev);
1565 /* check MEM_SIZE for older asics */
1566 reg = amdgpu_asic_get_config_memsize(adev);
1568 if ((reg != 0) && (reg != 0xffffffff))
1575 * Check whether seamless boot is supported.
1577 * So far we only support seamless boot on DCE 3.0 or later.
1578 * If users report that it works on older ASICS as well, we may
1581 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)
1583 switch (amdgpu_seamless) {
1591 DRM_ERROR("Invalid value for amdgpu.seamless: %d\n",
1596 if (!(adev->flags & AMD_IS_APU))
1599 if (adev->mman.keep_stolen_vga_memory)
1602 return amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0);
1606 * Intel hosts such as Rocket Lake, Alder Lake, Raptor Lake and Sapphire Rapids
1607 * don't support dynamic speed switching. Until we have confirmation from Intel
1608 * that a specific host supports it, it's safer that we keep it disabled for all.
1610 * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
1611 * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
1613 static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev)
1615 #if IS_ENABLED(CONFIG_X86)
1616 struct cpuinfo_x86 *c = &cpu_data(0);
1618 /* eGPU change speeds based on USB4 fabric conditions */
1619 if (dev_is_removable(adev->dev))
1622 if (c->x86_vendor == X86_VENDOR_INTEL)
1629 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1631 * @adev: amdgpu_device pointer
1633 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1634 * be set for this device.
1636 * Returns true if it should be used or false if not.
1638 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1640 switch (amdgpu_aspm) {
1650 if (adev->flags & AMD_IS_APU)
1652 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK))
1654 return pcie_aspm_enabled(adev->pdev);
1657 /* if we get transitioned to only one device, take VGA back */
1659 * amdgpu_device_vga_set_decode - enable/disable vga decode
1661 * @pdev: PCI device pointer
1662 * @state: enable/disable vga decode
1664 * Enable/disable vga decode (all asics).
1665 * Returns VGA resource flags.
1667 static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1670 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1672 amdgpu_asic_set_vga_state(adev, state);
1674 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1675 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1677 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1681 * amdgpu_device_check_block_size - validate the vm block size
1683 * @adev: amdgpu_device pointer
1685 * Validates the vm block size specified via module parameter.
1686 * The vm block size defines number of bits in page table versus page directory,
1687 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1688 * page table and the remaining bits are in the page directory.
1690 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1692 /* defines number of bits in page table versus page directory,
1693 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1694 * page table and the remaining bits are in the page directory
1696 if (amdgpu_vm_block_size == -1)
1699 if (amdgpu_vm_block_size < 9) {
1700 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1701 amdgpu_vm_block_size);
1702 amdgpu_vm_block_size = -1;
1707 * amdgpu_device_check_vm_size - validate the vm size
1709 * @adev: amdgpu_device pointer
1711 * Validates the vm size in GB specified via module parameter.
1712 * The VM size is the size of the GPU virtual memory space in GB.
1714 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1716 /* no need to check the default value */
1717 if (amdgpu_vm_size == -1)
1720 if (amdgpu_vm_size < 1) {
1721 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1723 amdgpu_vm_size = -1;
1727 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1730 bool is_os_64 = (sizeof(void *) == 8);
1731 uint64_t total_memory;
1732 uint64_t dram_size_seven_GB = 0x1B8000000;
1733 uint64_t dram_size_three_GB = 0xB8000000;
1735 if (amdgpu_smu_memory_pool_size == 0)
1739 DRM_WARN("Not 64-bit OS, feature not supported\n");
1743 total_memory = (uint64_t)si.totalram * si.mem_unit;
1745 if ((amdgpu_smu_memory_pool_size == 1) ||
1746 (amdgpu_smu_memory_pool_size == 2)) {
1747 if (total_memory < dram_size_three_GB)
1749 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1750 (amdgpu_smu_memory_pool_size == 8)) {
1751 if (total_memory < dram_size_seven_GB)
1754 DRM_WARN("Smu memory pool size not supported\n");
1757 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1762 DRM_WARN("No enough system memory\n");
1764 adev->pm.smu_prv_buffer_size = 0;
1767 static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1769 if (!(adev->flags & AMD_IS_APU) ||
1770 adev->asic_type < CHIP_RAVEN)
1773 switch (adev->asic_type) {
1775 if (adev->pdev->device == 0x15dd)
1776 adev->apu_flags |= AMD_APU_IS_RAVEN;
1777 if (adev->pdev->device == 0x15d8)
1778 adev->apu_flags |= AMD_APU_IS_PICASSO;
1781 if ((adev->pdev->device == 0x1636) ||
1782 (adev->pdev->device == 0x164c))
1783 adev->apu_flags |= AMD_APU_IS_RENOIR;
1785 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1788 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1790 case CHIP_YELLOW_CARP:
1792 case CHIP_CYAN_SKILLFISH:
1793 if ((adev->pdev->device == 0x13FE) ||
1794 (adev->pdev->device == 0x143F))
1795 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1805 * amdgpu_device_check_arguments - validate module params
1807 * @adev: amdgpu_device pointer
1809 * Validates certain module parameters and updates
1810 * the associated values used by the driver (all asics).
1812 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1814 if (amdgpu_sched_jobs < 4) {
1815 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1817 amdgpu_sched_jobs = 4;
1818 } else if (!is_power_of_2(amdgpu_sched_jobs)) {
1819 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1821 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1824 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1825 /* gart size must be greater or equal to 32M */
1826 dev_warn(adev->dev, "gart size (%d) too small\n",
1828 amdgpu_gart_size = -1;
1831 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1832 /* gtt size must be greater or equal to 32M */
1833 dev_warn(adev->dev, "gtt size (%d) too small\n",
1835 amdgpu_gtt_size = -1;
1838 /* valid range is between 4 and 9 inclusive */
1839 if (amdgpu_vm_fragment_size != -1 &&
1840 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1841 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1842 amdgpu_vm_fragment_size = -1;
1845 if (amdgpu_sched_hw_submission < 2) {
1846 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1847 amdgpu_sched_hw_submission);
1848 amdgpu_sched_hw_submission = 2;
1849 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1850 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1851 amdgpu_sched_hw_submission);
1852 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1855 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1856 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1857 amdgpu_reset_method = -1;
1860 amdgpu_device_check_smu_prv_buffer_size(adev);
1862 amdgpu_device_check_vm_size(adev);
1864 amdgpu_device_check_block_size(adev);
1866 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1872 * amdgpu_switcheroo_set_state - set switcheroo state
1874 * @pdev: pci dev pointer
1875 * @state: vga_switcheroo state
1877 * Callback for the switcheroo driver. Suspends or resumes
1878 * the asics before or after it is powered up using ACPI methods.
1880 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1881 enum vga_switcheroo_state state)
1883 struct drm_device *dev = pci_get_drvdata(pdev);
1886 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1889 if (state == VGA_SWITCHEROO_ON) {
1890 pr_info("switched on\n");
1891 /* don't suspend or resume card normally */
1892 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1894 pci_set_power_state(pdev, PCI_D0);
1895 amdgpu_device_load_pci_state(pdev);
1896 r = pci_enable_device(pdev);
1898 DRM_WARN("pci_enable_device failed (%d)\n", r);
1899 amdgpu_device_resume(dev, true);
1901 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1903 pr_info("switched off\n");
1904 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1905 amdgpu_device_prepare(dev);
1906 amdgpu_device_suspend(dev, true);
1907 amdgpu_device_cache_pci_state(pdev);
1908 /* Shut down the device */
1909 pci_disable_device(pdev);
1910 pci_set_power_state(pdev, PCI_D3cold);
1911 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1916 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1918 * @pdev: pci dev pointer
1920 * Callback for the switcheroo driver. Check of the switcheroo
1921 * state can be changed.
1922 * Returns true if the state can be changed, false if not.
1924 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1926 struct drm_device *dev = pci_get_drvdata(pdev);
1929 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1930 * locking inversion with the driver load path. And the access here is
1931 * completely racy anyway. So don't bother with locking for now.
1933 return atomic_read(&dev->open_count) == 0;
1936 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1937 .set_gpu_state = amdgpu_switcheroo_set_state,
1939 .can_switch = amdgpu_switcheroo_can_switch,
1943 * amdgpu_device_ip_set_clockgating_state - set the CG state
1945 * @dev: amdgpu_device pointer
1946 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1947 * @state: clockgating state (gate or ungate)
1949 * Sets the requested clockgating state for all instances of
1950 * the hardware IP specified.
1951 * Returns the error code from the last instance.
1953 int amdgpu_device_ip_set_clockgating_state(void *dev,
1954 enum amd_ip_block_type block_type,
1955 enum amd_clockgating_state state)
1957 struct amdgpu_device *adev = dev;
1960 for (i = 0; i < adev->num_ip_blocks; i++) {
1961 if (!adev->ip_blocks[i].status.valid)
1963 if (adev->ip_blocks[i].version->type != block_type)
1965 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1967 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1968 (void *)adev, state);
1970 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1971 adev->ip_blocks[i].version->funcs->name, r);
1977 * amdgpu_device_ip_set_powergating_state - set the PG state
1979 * @dev: amdgpu_device pointer
1980 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1981 * @state: powergating state (gate or ungate)
1983 * Sets the requested powergating state for all instances of
1984 * the hardware IP specified.
1985 * Returns the error code from the last instance.
1987 int amdgpu_device_ip_set_powergating_state(void *dev,
1988 enum amd_ip_block_type block_type,
1989 enum amd_powergating_state state)
1991 struct amdgpu_device *adev = dev;
1994 for (i = 0; i < adev->num_ip_blocks; i++) {
1995 if (!adev->ip_blocks[i].status.valid)
1997 if (adev->ip_blocks[i].version->type != block_type)
1999 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
2001 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
2002 (void *)adev, state);
2004 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
2005 adev->ip_blocks[i].version->funcs->name, r);
2011 * amdgpu_device_ip_get_clockgating_state - get the CG state
2013 * @adev: amdgpu_device pointer
2014 * @flags: clockgating feature flags
2016 * Walks the list of IPs on the device and updates the clockgating
2017 * flags for each IP.
2018 * Updates @flags with the feature flags for each hardware IP where
2019 * clockgating is enabled.
2021 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
2026 for (i = 0; i < adev->num_ip_blocks; i++) {
2027 if (!adev->ip_blocks[i].status.valid)
2029 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
2030 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
2035 * amdgpu_device_ip_wait_for_idle - wait for idle
2037 * @adev: amdgpu_device pointer
2038 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2040 * Waits for the request hardware IP to be idle.
2041 * Returns 0 for success or a negative error code on failure.
2043 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
2044 enum amd_ip_block_type block_type)
2048 for (i = 0; i < adev->num_ip_blocks; i++) {
2049 if (!adev->ip_blocks[i].status.valid)
2051 if (adev->ip_blocks[i].version->type == block_type) {
2052 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
2063 * amdgpu_device_ip_is_idle - is the hardware IP idle
2065 * @adev: amdgpu_device pointer
2066 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2068 * Check if the hardware IP is idle or not.
2069 * Returns true if it the IP is idle, false if not.
2071 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
2072 enum amd_ip_block_type block_type)
2076 for (i = 0; i < adev->num_ip_blocks; i++) {
2077 if (!adev->ip_blocks[i].status.valid)
2079 if (adev->ip_blocks[i].version->type == block_type)
2080 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
2087 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
2089 * @adev: amdgpu_device pointer
2090 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
2092 * Returns a pointer to the hardware IP block structure
2093 * if it exists for the asic, otherwise NULL.
2095 struct amdgpu_ip_block *
2096 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
2097 enum amd_ip_block_type type)
2101 for (i = 0; i < adev->num_ip_blocks; i++)
2102 if (adev->ip_blocks[i].version->type == type)
2103 return &adev->ip_blocks[i];
2109 * amdgpu_device_ip_block_version_cmp
2111 * @adev: amdgpu_device pointer
2112 * @type: enum amd_ip_block_type
2113 * @major: major version
2114 * @minor: minor version
2116 * return 0 if equal or greater
2117 * return 1 if smaller or the ip_block doesn't exist
2119 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
2120 enum amd_ip_block_type type,
2121 u32 major, u32 minor)
2123 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
2125 if (ip_block && ((ip_block->version->major > major) ||
2126 ((ip_block->version->major == major) &&
2127 (ip_block->version->minor >= minor))))
2134 * amdgpu_device_ip_block_add
2136 * @adev: amdgpu_device pointer
2137 * @ip_block_version: pointer to the IP to add
2139 * Adds the IP block driver information to the collection of IPs
2142 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
2143 const struct amdgpu_ip_block_version *ip_block_version)
2145 if (!ip_block_version)
2148 switch (ip_block_version->type) {
2149 case AMD_IP_BLOCK_TYPE_VCN:
2150 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
2153 case AMD_IP_BLOCK_TYPE_JPEG:
2154 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
2161 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
2162 ip_block_version->funcs->name);
2164 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
2170 * amdgpu_device_enable_virtual_display - enable virtual display feature
2172 * @adev: amdgpu_device pointer
2174 * Enabled the virtual display feature if the user has enabled it via
2175 * the module parameter virtual_display. This feature provides a virtual
2176 * display hardware on headless boards or in virtualized environments.
2177 * This function parses and validates the configuration string specified by
2178 * the user and configues the virtual display configuration (number of
2179 * virtual connectors, crtcs, etc.) specified.
2181 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
2183 adev->enable_virtual_display = false;
2185 if (amdgpu_virtual_display) {
2186 const char *pci_address_name = pci_name(adev->pdev);
2187 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
2189 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
2190 pciaddstr_tmp = pciaddstr;
2191 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
2192 pciaddname = strsep(&pciaddname_tmp, ",");
2193 if (!strcmp("all", pciaddname)
2194 || !strcmp(pci_address_name, pciaddname)) {
2198 adev->enable_virtual_display = true;
2201 res = kstrtol(pciaddname_tmp, 10,
2209 adev->mode_info.num_crtc = num_crtc;
2211 adev->mode_info.num_crtc = 1;
2217 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
2218 amdgpu_virtual_display, pci_address_name,
2219 adev->enable_virtual_display, adev->mode_info.num_crtc);
2225 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
2227 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
2228 adev->mode_info.num_crtc = 1;
2229 adev->enable_virtual_display = true;
2230 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
2231 adev->enable_virtual_display, adev->mode_info.num_crtc);
2236 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
2238 * @adev: amdgpu_device pointer
2240 * Parses the asic configuration parameters specified in the gpu info
2241 * firmware and makes them availale to the driver for use in configuring
2243 * Returns 0 on success, -EINVAL on failure.
2245 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
2247 const char *chip_name;
2250 const struct gpu_info_firmware_header_v1_0 *hdr;
2252 adev->firmware.gpu_info_fw = NULL;
2254 if (adev->mman.discovery_bin)
2257 switch (adev->asic_type) {
2261 chip_name = "vega10";
2264 chip_name = "vega12";
2267 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
2268 chip_name = "raven2";
2269 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
2270 chip_name = "picasso";
2272 chip_name = "raven";
2275 chip_name = "arcturus";
2278 chip_name = "navi12";
2282 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
2283 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name);
2286 "Failed to get gpu_info firmware \"%s\"\n",
2291 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2292 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2294 switch (hdr->version_major) {
2297 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2298 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2299 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2302 * Should be droped when DAL no longer needs it.
2304 if (adev->asic_type == CHIP_NAVI12)
2305 goto parse_soc_bounding_box;
2307 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2308 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2309 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2310 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2311 adev->gfx.config.max_texture_channel_caches =
2312 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2313 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2314 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2315 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2316 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2317 adev->gfx.config.double_offchip_lds_buf =
2318 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2319 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2320 adev->gfx.cu_info.max_waves_per_simd =
2321 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2322 adev->gfx.cu_info.max_scratch_slots_per_cu =
2323 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2324 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2325 if (hdr->version_minor >= 1) {
2326 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2327 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2328 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2329 adev->gfx.config.num_sc_per_sh =
2330 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2331 adev->gfx.config.num_packer_per_sc =
2332 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2335 parse_soc_bounding_box:
2337 * soc bounding box info is not integrated in disocovery table,
2338 * we always need to parse it from gpu info firmware if needed.
2340 if (hdr->version_minor == 2) {
2341 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2342 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2343 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2344 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2350 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2359 * amdgpu_device_ip_early_init - run early init for hardware IPs
2361 * @adev: amdgpu_device pointer
2363 * Early initialization pass for hardware IPs. The hardware IPs that make
2364 * up each asic are discovered each IP's early_init callback is run. This
2365 * is the first stage in initializing the asic.
2366 * Returns 0 on success, negative error code on failure.
2368 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2370 struct pci_dev *parent;
2374 amdgpu_device_enable_virtual_display(adev);
2376 if (amdgpu_sriov_vf(adev)) {
2377 r = amdgpu_virt_request_full_gpu(adev, true);
2382 switch (adev->asic_type) {
2383 #ifdef CONFIG_DRM_AMDGPU_SI
2389 adev->family = AMDGPU_FAMILY_SI;
2390 r = si_set_ip_blocks(adev);
2395 #ifdef CONFIG_DRM_AMDGPU_CIK
2401 if (adev->flags & AMD_IS_APU)
2402 adev->family = AMDGPU_FAMILY_KV;
2404 adev->family = AMDGPU_FAMILY_CI;
2406 r = cik_set_ip_blocks(adev);
2414 case CHIP_POLARIS10:
2415 case CHIP_POLARIS11:
2416 case CHIP_POLARIS12:
2420 if (adev->flags & AMD_IS_APU)
2421 adev->family = AMDGPU_FAMILY_CZ;
2423 adev->family = AMDGPU_FAMILY_VI;
2425 r = vi_set_ip_blocks(adev);
2430 r = amdgpu_discovery_set_ip_blocks(adev);
2436 if (amdgpu_has_atpx() &&
2437 (amdgpu_is_atpx_hybrid() ||
2438 amdgpu_has_atpx_dgpu_power_cntl()) &&
2439 ((adev->flags & AMD_IS_APU) == 0) &&
2440 !dev_is_removable(&adev->pdev->dev))
2441 adev->flags |= AMD_IS_PX;
2443 if (!(adev->flags & AMD_IS_APU)) {
2444 parent = pcie_find_root_port(adev->pdev);
2445 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2449 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2450 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2451 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2452 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2453 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2454 if (!amdgpu_device_pcie_dynamic_switching_supported(adev))
2455 adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;
2458 for (i = 0; i < adev->num_ip_blocks; i++) {
2459 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2460 DRM_WARN("disabled ip block: %d <%s>\n",
2461 i, adev->ip_blocks[i].version->funcs->name);
2462 adev->ip_blocks[i].status.valid = false;
2464 if (adev->ip_blocks[i].version->funcs->early_init) {
2465 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2467 adev->ip_blocks[i].status.valid = false;
2469 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2470 adev->ip_blocks[i].version->funcs->name, r);
2473 adev->ip_blocks[i].status.valid = true;
2476 adev->ip_blocks[i].status.valid = true;
2479 /* get the vbios after the asic_funcs are set up */
2480 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2481 r = amdgpu_device_parse_gpu_info_fw(adev);
2486 if (amdgpu_device_read_bios(adev)) {
2487 if (!amdgpu_get_bios(adev))
2490 r = amdgpu_atombios_init(adev);
2492 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2493 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2498 /*get pf2vf msg info at it's earliest time*/
2499 if (amdgpu_sriov_vf(adev))
2500 amdgpu_virt_init_data_exchange(adev);
2507 amdgpu_amdkfd_device_probe(adev);
2508 adev->cg_flags &= amdgpu_cg_mask;
2509 adev->pg_flags &= amdgpu_pg_mask;
2514 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2518 for (i = 0; i < adev->num_ip_blocks; i++) {
2519 if (!adev->ip_blocks[i].status.sw)
2521 if (adev->ip_blocks[i].status.hw)
2523 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2524 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2525 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2526 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2528 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2529 adev->ip_blocks[i].version->funcs->name, r);
2532 adev->ip_blocks[i].status.hw = true;
2539 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2543 for (i = 0; i < adev->num_ip_blocks; i++) {
2544 if (!adev->ip_blocks[i].status.sw)
2546 if (adev->ip_blocks[i].status.hw)
2548 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2550 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2551 adev->ip_blocks[i].version->funcs->name, r);
2554 adev->ip_blocks[i].status.hw = true;
2560 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2564 uint32_t smu_version;
2566 if (adev->asic_type >= CHIP_VEGA10) {
2567 for (i = 0; i < adev->num_ip_blocks; i++) {
2568 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2571 if (!adev->ip_blocks[i].status.sw)
2574 /* no need to do the fw loading again if already done*/
2575 if (adev->ip_blocks[i].status.hw == true)
2578 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2579 r = adev->ip_blocks[i].version->funcs->resume(adev);
2581 DRM_ERROR("resume of IP block <%s> failed %d\n",
2582 adev->ip_blocks[i].version->funcs->name, r);
2586 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2588 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2589 adev->ip_blocks[i].version->funcs->name, r);
2594 adev->ip_blocks[i].status.hw = true;
2599 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2600 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2605 static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2610 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2611 struct amdgpu_ring *ring = adev->rings[i];
2613 /* No need to setup the GPU scheduler for rings that don't need it */
2614 if (!ring || ring->no_scheduler)
2617 switch (ring->funcs->type) {
2618 case AMDGPU_RING_TYPE_GFX:
2619 timeout = adev->gfx_timeout;
2621 case AMDGPU_RING_TYPE_COMPUTE:
2622 timeout = adev->compute_timeout;
2624 case AMDGPU_RING_TYPE_SDMA:
2625 timeout = adev->sdma_timeout;
2628 timeout = adev->video_timeout;
2632 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, NULL,
2633 DRM_SCHED_PRIORITY_COUNT,
2634 ring->num_hw_submission, 0,
2635 timeout, adev->reset_domain->wq,
2636 ring->sched_score, ring->name,
2639 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2643 r = amdgpu_uvd_entity_init(adev, ring);
2645 DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n",
2649 r = amdgpu_vce_entity_init(adev, ring);
2651 DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n",
2657 amdgpu_xcp_update_partition_sched_list(adev);
2664 * amdgpu_device_ip_init - run init for hardware IPs
2666 * @adev: amdgpu_device pointer
2668 * Main initialization pass for hardware IPs. The list of all the hardware
2669 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2670 * are run. sw_init initializes the software state associated with each IP
2671 * and hw_init initializes the hardware associated with each IP.
2672 * Returns 0 on success, negative error code on failure.
2674 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2678 r = amdgpu_ras_init(adev);
2682 for (i = 0; i < adev->num_ip_blocks; i++) {
2683 if (!adev->ip_blocks[i].status.valid)
2685 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2687 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2688 adev->ip_blocks[i].version->funcs->name, r);
2691 adev->ip_blocks[i].status.sw = true;
2693 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2694 /* need to do common hw init early so everything is set up for gmc */
2695 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2697 DRM_ERROR("hw_init %d failed %d\n", i, r);
2700 adev->ip_blocks[i].status.hw = true;
2701 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2702 /* need to do gmc hw init early so we can allocate gpu mem */
2703 /* Try to reserve bad pages early */
2704 if (amdgpu_sriov_vf(adev))
2705 amdgpu_virt_exchange_data(adev);
2707 r = amdgpu_device_mem_scratch_init(adev);
2709 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2712 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2714 DRM_ERROR("hw_init %d failed %d\n", i, r);
2717 r = amdgpu_device_wb_init(adev);
2719 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2722 adev->ip_blocks[i].status.hw = true;
2724 /* right after GMC hw init, we create CSA */
2725 if (adev->gfx.mcbp) {
2726 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2727 AMDGPU_GEM_DOMAIN_VRAM |
2728 AMDGPU_GEM_DOMAIN_GTT,
2731 DRM_ERROR("allocate CSA failed %d\n", r);
2736 r = amdgpu_seq64_init(adev);
2738 DRM_ERROR("allocate seq64 failed %d\n", r);
2744 if (amdgpu_sriov_vf(adev))
2745 amdgpu_virt_init_data_exchange(adev);
2747 r = amdgpu_ib_pool_init(adev);
2749 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2750 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2754 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2758 r = amdgpu_device_ip_hw_init_phase1(adev);
2762 r = amdgpu_device_fw_loading(adev);
2766 r = amdgpu_device_ip_hw_init_phase2(adev);
2771 * retired pages will be loaded from eeprom and reserved here,
2772 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2773 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2774 * for I2C communication which only true at this point.
2776 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2777 * failure from bad gpu situation and stop amdgpu init process
2778 * accordingly. For other failed cases, it will still release all
2779 * the resource and print error message, rather than returning one
2780 * negative value to upper level.
2782 * Note: theoretically, this should be called before all vram allocations
2783 * to protect retired page from abusing
2785 r = amdgpu_ras_recovery_init(adev);
2790 * In case of XGMI grab extra reference for reset domain for this device
2792 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2793 if (amdgpu_xgmi_add_device(adev) == 0) {
2794 if (!amdgpu_sriov_vf(adev)) {
2795 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2797 if (WARN_ON(!hive)) {
2802 if (!hive->reset_domain ||
2803 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2805 amdgpu_put_xgmi_hive(hive);
2809 /* Drop the early temporary reset domain we created for device */
2810 amdgpu_reset_put_reset_domain(adev->reset_domain);
2811 adev->reset_domain = hive->reset_domain;
2812 amdgpu_put_xgmi_hive(hive);
2817 r = amdgpu_device_init_schedulers(adev);
2821 if (adev->mman.buffer_funcs_ring->sched.ready)
2822 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2824 /* Don't init kfd if whole hive need to be reset during init */
2825 if (!adev->gmc.xgmi.pending_reset) {
2826 kgd2kfd_init_zone_device(adev);
2827 amdgpu_amdkfd_device_init(adev);
2830 amdgpu_fru_get_product_info(adev);
2838 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2840 * @adev: amdgpu_device pointer
2842 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2843 * this function before a GPU reset. If the value is retained after a
2844 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2846 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2848 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2852 * amdgpu_device_check_vram_lost - check if vram is valid
2854 * @adev: amdgpu_device pointer
2856 * Checks the reset magic value written to the gart pointer in VRAM.
2857 * The driver calls this after a GPU reset to see if the contents of
2858 * VRAM is lost or now.
2859 * returns true if vram is lost, false if not.
2861 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2863 if (memcmp(adev->gart.ptr, adev->reset_magic,
2864 AMDGPU_RESET_MAGIC_NUM))
2867 if (!amdgpu_in_reset(adev))
2871 * For all ASICs with baco/mode1 reset, the VRAM is
2872 * always assumed to be lost.
2874 switch (amdgpu_asic_reset_method(adev)) {
2875 case AMD_RESET_METHOD_BACO:
2876 case AMD_RESET_METHOD_MODE1:
2884 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2886 * @adev: amdgpu_device pointer
2887 * @state: clockgating state (gate or ungate)
2889 * The list of all the hardware IPs that make up the asic is walked and the
2890 * set_clockgating_state callbacks are run.
2891 * Late initialization pass enabling clockgating for hardware IPs.
2892 * Fini or suspend, pass disabling clockgating for hardware IPs.
2893 * Returns 0 on success, negative error code on failure.
2896 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2897 enum amd_clockgating_state state)
2901 if (amdgpu_emu_mode == 1)
2904 for (j = 0; j < adev->num_ip_blocks; j++) {
2905 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2906 if (!adev->ip_blocks[i].status.late_initialized)
2908 /* skip CG for GFX, SDMA on S0ix */
2909 if (adev->in_s0ix &&
2910 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2911 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2913 /* skip CG for VCE/UVD, it's handled specially */
2914 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2915 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2916 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2917 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2918 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2919 /* enable clockgating to save power */
2920 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2923 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2924 adev->ip_blocks[i].version->funcs->name, r);
2933 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2934 enum amd_powergating_state state)
2938 if (amdgpu_emu_mode == 1)
2941 for (j = 0; j < adev->num_ip_blocks; j++) {
2942 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2943 if (!adev->ip_blocks[i].status.late_initialized)
2945 /* skip PG for GFX, SDMA on S0ix */
2946 if (adev->in_s0ix &&
2947 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2948 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2950 /* skip CG for VCE/UVD, it's handled specially */
2951 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2952 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2953 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2954 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2955 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2956 /* enable powergating to save power */
2957 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2960 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2961 adev->ip_blocks[i].version->funcs->name, r);
2969 static int amdgpu_device_enable_mgpu_fan_boost(void)
2971 struct amdgpu_gpu_instance *gpu_ins;
2972 struct amdgpu_device *adev;
2975 mutex_lock(&mgpu_info.mutex);
2978 * MGPU fan boost feature should be enabled
2979 * only when there are two or more dGPUs in
2982 if (mgpu_info.num_dgpu < 2)
2985 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2986 gpu_ins = &(mgpu_info.gpu_ins[i]);
2987 adev = gpu_ins->adev;
2988 if (!(adev->flags & AMD_IS_APU) &&
2989 !gpu_ins->mgpu_fan_enabled) {
2990 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2994 gpu_ins->mgpu_fan_enabled = 1;
2999 mutex_unlock(&mgpu_info.mutex);
3005 * amdgpu_device_ip_late_init - run late init for hardware IPs
3007 * @adev: amdgpu_device pointer
3009 * Late initialization pass for hardware IPs. The list of all the hardware
3010 * IPs that make up the asic is walked and the late_init callbacks are run.
3011 * late_init covers any special initialization that an IP requires
3012 * after all of the have been initialized or something that needs to happen
3013 * late in the init process.
3014 * Returns 0 on success, negative error code on failure.
3016 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
3018 struct amdgpu_gpu_instance *gpu_instance;
3021 for (i = 0; i < adev->num_ip_blocks; i++) {
3022 if (!adev->ip_blocks[i].status.hw)
3024 if (adev->ip_blocks[i].version->funcs->late_init) {
3025 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
3027 DRM_ERROR("late_init of IP block <%s> failed %d\n",
3028 adev->ip_blocks[i].version->funcs->name, r);
3032 adev->ip_blocks[i].status.late_initialized = true;
3035 r = amdgpu_ras_late_init(adev);
3037 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
3041 amdgpu_ras_set_error_query_ready(adev, true);
3043 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
3044 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
3046 amdgpu_device_fill_reset_magic(adev);
3048 r = amdgpu_device_enable_mgpu_fan_boost();
3050 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
3052 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
3053 if (amdgpu_passthrough(adev) &&
3054 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
3055 adev->asic_type == CHIP_ALDEBARAN))
3056 amdgpu_dpm_handle_passthrough_sbr(adev, true);
3058 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3059 mutex_lock(&mgpu_info.mutex);
3062 * Reset device p-state to low as this was booted with high.
3064 * This should be performed only after all devices from the same
3065 * hive get initialized.
3067 * However, it's unknown how many device in the hive in advance.
3068 * As this is counted one by one during devices initializations.
3070 * So, we wait for all XGMI interlinked devices initialized.
3071 * This may bring some delays as those devices may come from
3072 * different hives. But that should be OK.
3074 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
3075 for (i = 0; i < mgpu_info.num_gpu; i++) {
3076 gpu_instance = &(mgpu_info.gpu_ins[i]);
3077 if (gpu_instance->adev->flags & AMD_IS_APU)
3080 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
3081 AMDGPU_XGMI_PSTATE_MIN);
3083 DRM_ERROR("pstate setting failed (%d).\n", r);
3089 mutex_unlock(&mgpu_info.mutex);
3096 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
3098 * @adev: amdgpu_device pointer
3100 * For ASICs need to disable SMC first
3102 static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
3106 if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0))
3109 for (i = 0; i < adev->num_ip_blocks; i++) {
3110 if (!adev->ip_blocks[i].status.hw)
3112 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3113 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
3114 /* XXX handle errors */
3116 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3117 adev->ip_blocks[i].version->funcs->name, r);
3119 adev->ip_blocks[i].status.hw = false;
3125 static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
3129 for (i = 0; i < adev->num_ip_blocks; i++) {
3130 if (!adev->ip_blocks[i].version->funcs->early_fini)
3133 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
3135 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
3136 adev->ip_blocks[i].version->funcs->name, r);
3140 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3141 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3143 amdgpu_amdkfd_suspend(adev, false);
3145 /* Workaroud for ASICs need to disable SMC first */
3146 amdgpu_device_smu_fini_early(adev);
3148 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3149 if (!adev->ip_blocks[i].status.hw)
3152 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
3153 /* XXX handle errors */
3155 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3156 adev->ip_blocks[i].version->funcs->name, r);
3159 adev->ip_blocks[i].status.hw = false;
3162 if (amdgpu_sriov_vf(adev)) {
3163 if (amdgpu_virt_release_full_gpu(adev, false))
3164 DRM_ERROR("failed to release exclusive mode on fini\n");
3171 * amdgpu_device_ip_fini - run fini for hardware IPs
3173 * @adev: amdgpu_device pointer
3175 * Main teardown pass for hardware IPs. The list of all the hardware
3176 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
3177 * are run. hw_fini tears down the hardware associated with each IP
3178 * and sw_fini tears down any software state associated with each IP.
3179 * Returns 0 on success, negative error code on failure.
3181 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
3185 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
3186 amdgpu_virt_release_ras_err_handler_data(adev);
3188 if (adev->gmc.xgmi.num_physical_nodes > 1)
3189 amdgpu_xgmi_remove_device(adev);
3191 amdgpu_amdkfd_device_fini_sw(adev);
3193 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3194 if (!adev->ip_blocks[i].status.sw)
3197 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
3198 amdgpu_ucode_free_bo(adev);
3199 amdgpu_free_static_csa(&adev->virt.csa_obj);
3200 amdgpu_device_wb_fini(adev);
3201 amdgpu_device_mem_scratch_fini(adev);
3202 amdgpu_ib_pool_fini(adev);
3203 amdgpu_seq64_fini(adev);
3206 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
3207 /* XXX handle errors */
3209 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
3210 adev->ip_blocks[i].version->funcs->name, r);
3212 adev->ip_blocks[i].status.sw = false;
3213 adev->ip_blocks[i].status.valid = false;
3216 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3217 if (!adev->ip_blocks[i].status.late_initialized)
3219 if (adev->ip_blocks[i].version->funcs->late_fini)
3220 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
3221 adev->ip_blocks[i].status.late_initialized = false;
3224 amdgpu_ras_fini(adev);
3230 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
3232 * @work: work_struct.
3234 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
3236 struct amdgpu_device *adev =
3237 container_of(work, struct amdgpu_device, delayed_init_work.work);
3240 r = amdgpu_ib_ring_tests(adev);
3242 DRM_ERROR("ib ring test failed (%d).\n", r);
3245 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
3247 struct amdgpu_device *adev =
3248 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
3250 WARN_ON_ONCE(adev->gfx.gfx_off_state);
3251 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
3253 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
3254 adev->gfx.gfx_off_state = true;
3258 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
3260 * @adev: amdgpu_device pointer
3262 * Main suspend function for hardware IPs. The list of all the hardware
3263 * IPs that make up the asic is walked, clockgating is disabled and the
3264 * suspend callbacks are run. suspend puts the hardware and software state
3265 * in each IP into a state suitable for suspend.
3266 * Returns 0 on success, negative error code on failure.
3268 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
3272 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3273 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3276 * Per PMFW team's suggestion, driver needs to handle gfxoff
3277 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
3278 * scenario. Add the missing df cstate disablement here.
3280 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
3281 dev_warn(adev->dev, "Failed to disallow df cstate");
3283 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3284 if (!adev->ip_blocks[i].status.valid)
3287 /* displays are handled separately */
3288 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
3291 /* XXX handle errors */
3292 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3293 /* XXX handle errors */
3295 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3296 adev->ip_blocks[i].version->funcs->name, r);
3300 adev->ip_blocks[i].status.hw = false;
3307 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
3309 * @adev: amdgpu_device pointer
3311 * Main suspend function for hardware IPs. The list of all the hardware
3312 * IPs that make up the asic is walked, clockgating is disabled and the
3313 * suspend callbacks are run. suspend puts the hardware and software state
3314 * in each IP into a state suitable for suspend.
3315 * Returns 0 on success, negative error code on failure.
3317 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
3322 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
3324 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3325 if (!adev->ip_blocks[i].status.valid)
3327 /* displays are handled in phase1 */
3328 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3330 /* PSP lost connection when err_event_athub occurs */
3331 if (amdgpu_ras_intr_triggered() &&
3332 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3333 adev->ip_blocks[i].status.hw = false;
3337 /* skip unnecessary suspend if we do not initialize them yet */
3338 if (adev->gmc.xgmi.pending_reset &&
3339 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3340 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
3341 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3342 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
3343 adev->ip_blocks[i].status.hw = false;
3347 /* skip suspend of gfx/mes and psp for S0ix
3348 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3349 * like at runtime. PSP is also part of the always on hardware
3350 * so no need to suspend it.
3352 if (adev->in_s0ix &&
3353 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3354 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3355 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3358 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
3359 if (adev->in_s0ix &&
3360 (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >=
3361 IP_VERSION(5, 0, 0)) &&
3362 (adev->ip_blocks[i].version->type ==
3363 AMD_IP_BLOCK_TYPE_SDMA))
3366 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
3367 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
3368 * from this location and RLC Autoload automatically also gets loaded
3369 * from here based on PMFW -> PSP message during re-init sequence.
3370 * Therefore, the psp suspend & resume should be skipped to avoid destroy
3371 * the TMR and reload FWs again for IMU enabled APU ASICs.
3373 if (amdgpu_in_reset(adev) &&
3374 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3375 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3378 /* XXX handle errors */
3379 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3380 /* XXX handle errors */
3382 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3383 adev->ip_blocks[i].version->funcs->name, r);
3385 adev->ip_blocks[i].status.hw = false;
3386 /* handle putting the SMC in the appropriate state */
3387 if (!amdgpu_sriov_vf(adev)) {
3388 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3389 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3391 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3392 adev->mp1_state, r);
3403 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3405 * @adev: amdgpu_device pointer
3407 * Main suspend function for hardware IPs. The list of all the hardware
3408 * IPs that make up the asic is walked, clockgating is disabled and the
3409 * suspend callbacks are run. suspend puts the hardware and software state
3410 * in each IP into a state suitable for suspend.
3411 * Returns 0 on success, negative error code on failure.
3413 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3417 if (amdgpu_sriov_vf(adev)) {
3418 amdgpu_virt_fini_data_exchange(adev);
3419 amdgpu_virt_request_full_gpu(adev, false);
3422 amdgpu_ttm_set_buffer_funcs_status(adev, false);
3424 r = amdgpu_device_ip_suspend_phase1(adev);
3427 r = amdgpu_device_ip_suspend_phase2(adev);
3429 if (amdgpu_sriov_vf(adev))
3430 amdgpu_virt_release_full_gpu(adev, false);
3435 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3439 static enum amd_ip_block_type ip_order[] = {
3440 AMD_IP_BLOCK_TYPE_COMMON,
3441 AMD_IP_BLOCK_TYPE_GMC,
3442 AMD_IP_BLOCK_TYPE_PSP,
3443 AMD_IP_BLOCK_TYPE_IH,
3446 for (i = 0; i < adev->num_ip_blocks; i++) {
3448 struct amdgpu_ip_block *block;
3450 block = &adev->ip_blocks[i];
3451 block->status.hw = false;
3453 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3455 if (block->version->type != ip_order[j] ||
3456 !block->status.valid)
3459 r = block->version->funcs->hw_init(adev);
3460 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3463 block->status.hw = true;
3470 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3474 static enum amd_ip_block_type ip_order[] = {
3475 AMD_IP_BLOCK_TYPE_SMC,
3476 AMD_IP_BLOCK_TYPE_DCE,
3477 AMD_IP_BLOCK_TYPE_GFX,
3478 AMD_IP_BLOCK_TYPE_SDMA,
3479 AMD_IP_BLOCK_TYPE_MES,
3480 AMD_IP_BLOCK_TYPE_UVD,
3481 AMD_IP_BLOCK_TYPE_VCE,
3482 AMD_IP_BLOCK_TYPE_VCN,
3483 AMD_IP_BLOCK_TYPE_JPEG
3486 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3488 struct amdgpu_ip_block *block;
3490 for (j = 0; j < adev->num_ip_blocks; j++) {
3491 block = &adev->ip_blocks[j];
3493 if (block->version->type != ip_order[i] ||
3494 !block->status.valid ||
3498 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3499 r = block->version->funcs->resume(adev);
3501 r = block->version->funcs->hw_init(adev);
3503 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3506 block->status.hw = true;
3514 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3516 * @adev: amdgpu_device pointer
3518 * First resume function for hardware IPs. The list of all the hardware
3519 * IPs that make up the asic is walked and the resume callbacks are run for
3520 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3521 * after a suspend and updates the software state as necessary. This
3522 * function is also used for restoring the GPU after a GPU reset.
3523 * Returns 0 on success, negative error code on failure.
3525 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3529 for (i = 0; i < adev->num_ip_blocks; i++) {
3530 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3532 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3533 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3534 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3535 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3537 r = adev->ip_blocks[i].version->funcs->resume(adev);
3539 DRM_ERROR("resume of IP block <%s> failed %d\n",
3540 adev->ip_blocks[i].version->funcs->name, r);
3543 adev->ip_blocks[i].status.hw = true;
3551 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3553 * @adev: amdgpu_device pointer
3555 * First resume function for hardware IPs. The list of all the hardware
3556 * IPs that make up the asic is walked and the resume callbacks are run for
3557 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3558 * functional state after a suspend and updates the software state as
3559 * necessary. This function is also used for restoring the GPU after a GPU
3561 * Returns 0 on success, negative error code on failure.
3563 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3567 for (i = 0; i < adev->num_ip_blocks; i++) {
3568 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3570 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3571 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3572 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3573 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3575 r = adev->ip_blocks[i].version->funcs->resume(adev);
3577 DRM_ERROR("resume of IP block <%s> failed %d\n",
3578 adev->ip_blocks[i].version->funcs->name, r);
3581 adev->ip_blocks[i].status.hw = true;
3588 * amdgpu_device_ip_resume - run resume for hardware IPs
3590 * @adev: amdgpu_device pointer
3592 * Main resume function for hardware IPs. The hardware IPs
3593 * are split into two resume functions because they are
3594 * also used in recovering from a GPU reset and some additional
3595 * steps need to be take between them. In this case (S3/S4) they are
3597 * Returns 0 on success, negative error code on failure.
3599 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3603 r = amdgpu_device_ip_resume_phase1(adev);
3607 r = amdgpu_device_fw_loading(adev);
3611 r = amdgpu_device_ip_resume_phase2(adev);
3613 if (adev->mman.buffer_funcs_ring->sched.ready)
3614 amdgpu_ttm_set_buffer_funcs_status(adev, true);
3620 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3622 * @adev: amdgpu_device pointer
3624 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3626 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3628 if (amdgpu_sriov_vf(adev)) {
3629 if (adev->is_atom_fw) {
3630 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3631 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3633 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3634 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3637 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3638 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3643 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3645 * @asic_type: AMD asic type
3647 * Check if there is DC (new modesetting infrastructre) support for an asic.
3648 * returns true if DC has support, false if not.
3650 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3652 switch (asic_type) {
3653 #ifdef CONFIG_DRM_AMDGPU_SI
3657 /* chips with no display hardware */
3659 #if defined(CONFIG_DRM_AMD_DC)
3665 * We have systems in the wild with these ASICs that require
3666 * LVDS and VGA support which is not supported with DC.
3668 * Fallback to the non-DC driver here by default so as not to
3669 * cause regressions.
3671 #if defined(CONFIG_DRM_AMD_DC_SI)
3672 return amdgpu_dc > 0;
3681 * We have systems in the wild with these ASICs that require
3682 * VGA support which is not supported with DC.
3684 * Fallback to the non-DC driver here by default so as not to
3685 * cause regressions.
3687 return amdgpu_dc > 0;
3689 return amdgpu_dc != 0;
3693 DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");
3700 * amdgpu_device_has_dc_support - check if dc is supported
3702 * @adev: amdgpu_device pointer
3704 * Returns true for supported, false for not supported
3706 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3708 if (adev->enable_virtual_display ||
3709 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3712 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3715 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3717 struct amdgpu_device *adev =
3718 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3719 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3721 /* It's a bug to not have a hive within this function */
3726 * Use task barrier to synchronize all xgmi reset works across the
3727 * hive. task_barrier_enter and task_barrier_exit will block
3728 * until all the threads running the xgmi reset works reach
3729 * those points. task_barrier_full will do both blocks.
3731 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3733 task_barrier_enter(&hive->tb);
3734 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3736 if (adev->asic_reset_res)
3739 task_barrier_exit(&hive->tb);
3740 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3742 if (adev->asic_reset_res)
3745 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
3748 task_barrier_full(&hive->tb);
3749 adev->asic_reset_res = amdgpu_asic_reset(adev);
3753 if (adev->asic_reset_res)
3754 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3755 adev->asic_reset_res, adev_to_drm(adev)->unique);
3756 amdgpu_put_xgmi_hive(hive);
3759 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3761 char *input = amdgpu_lockup_timeout;
3762 char *timeout_setting = NULL;
3768 * By default timeout for non compute jobs is 10000
3769 * and 60000 for compute jobs.
3770 * In SR-IOV or passthrough mode, timeout for compute
3771 * jobs are 60000 by default.
3773 adev->gfx_timeout = msecs_to_jiffies(10000);
3774 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3775 if (amdgpu_sriov_vf(adev))
3776 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3777 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3779 adev->compute_timeout = msecs_to_jiffies(60000);
3781 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3782 while ((timeout_setting = strsep(&input, ",")) &&
3783 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3784 ret = kstrtol(timeout_setting, 0, &timeout);
3791 } else if (timeout < 0) {
3792 timeout = MAX_SCHEDULE_TIMEOUT;
3793 dev_warn(adev->dev, "lockup timeout disabled");
3794 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3796 timeout = msecs_to_jiffies(timeout);
3801 adev->gfx_timeout = timeout;
3804 adev->compute_timeout = timeout;
3807 adev->sdma_timeout = timeout;
3810 adev->video_timeout = timeout;
3817 * There is only one value specified and
3818 * it should apply to all non-compute jobs.
3821 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3822 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3823 adev->compute_timeout = adev->gfx_timeout;
3831 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3833 * @adev: amdgpu_device pointer
3835 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3837 static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3839 struct iommu_domain *domain;
3841 domain = iommu_get_domain_for_dev(adev->dev);
3842 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3843 adev->ram_is_direct_mapped = true;
3846 static const struct attribute *amdgpu_dev_attributes[] = {
3847 &dev_attr_pcie_replay_count.attr,
3851 static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
3853 if (amdgpu_mcbp == 1)
3854 adev->gfx.mcbp = true;
3855 else if (amdgpu_mcbp == 0)
3856 adev->gfx.mcbp = false;
3858 if (amdgpu_sriov_vf(adev))
3859 adev->gfx.mcbp = true;
3862 DRM_INFO("MCBP is enabled\n");
3866 * amdgpu_device_init - initialize the driver
3868 * @adev: amdgpu_device pointer
3869 * @flags: driver flags
3871 * Initializes the driver info and hw (all asics).
3872 * Returns 0 for success or an error on failure.
3873 * Called at driver startup.
3875 int amdgpu_device_init(struct amdgpu_device *adev,
3878 struct drm_device *ddev = adev_to_drm(adev);
3879 struct pci_dev *pdev = adev->pdev;
3885 adev->shutdown = false;
3886 adev->flags = flags;
3888 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3889 adev->asic_type = amdgpu_force_asic_type;
3891 adev->asic_type = flags & AMD_ASIC_MASK;
3893 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3894 if (amdgpu_emu_mode == 1)
3895 adev->usec_timeout *= 10;
3896 adev->gmc.gart_size = 512 * 1024 * 1024;
3897 adev->accel_working = false;
3898 adev->num_rings = 0;
3899 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3900 adev->mman.buffer_funcs = NULL;
3901 adev->mman.buffer_funcs_ring = NULL;
3902 adev->vm_manager.vm_pte_funcs = NULL;
3903 adev->vm_manager.vm_pte_num_scheds = 0;
3904 adev->gmc.gmc_funcs = NULL;
3905 adev->harvest_ip_mask = 0x0;
3906 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3907 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3909 adev->smc_rreg = &amdgpu_invalid_rreg;
3910 adev->smc_wreg = &amdgpu_invalid_wreg;
3911 adev->pcie_rreg = &amdgpu_invalid_rreg;
3912 adev->pcie_wreg = &amdgpu_invalid_wreg;
3913 adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext;
3914 adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext;
3915 adev->pciep_rreg = &amdgpu_invalid_rreg;
3916 adev->pciep_wreg = &amdgpu_invalid_wreg;
3917 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3918 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3919 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext;
3920 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext;
3921 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3922 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3923 adev->didt_rreg = &amdgpu_invalid_rreg;
3924 adev->didt_wreg = &amdgpu_invalid_wreg;
3925 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3926 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3927 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3928 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3930 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3931 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3932 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3934 /* mutex initialization are all done here so we
3935 * can recall function without having locking issues
3937 mutex_init(&adev->firmware.mutex);
3938 mutex_init(&adev->pm.mutex);
3939 mutex_init(&adev->gfx.gpu_clock_mutex);
3940 mutex_init(&adev->srbm_mutex);
3941 mutex_init(&adev->gfx.pipe_reserve_mutex);
3942 mutex_init(&adev->gfx.gfx_off_mutex);
3943 mutex_init(&adev->gfx.partition_mutex);
3944 mutex_init(&adev->grbm_idx_mutex);
3945 mutex_init(&adev->mn_lock);
3946 mutex_init(&adev->virt.vf_errors.lock);
3947 hash_init(adev->mn_hash);
3948 mutex_init(&adev->psp.mutex);
3949 mutex_init(&adev->notifier_lock);
3950 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3951 mutex_init(&adev->benchmark_mutex);
3953 amdgpu_device_init_apu_flags(adev);
3955 r = amdgpu_device_check_arguments(adev);
3959 spin_lock_init(&adev->mmio_idx_lock);
3960 spin_lock_init(&adev->smc_idx_lock);
3961 spin_lock_init(&adev->pcie_idx_lock);
3962 spin_lock_init(&adev->uvd_ctx_idx_lock);
3963 spin_lock_init(&adev->didt_idx_lock);
3964 spin_lock_init(&adev->gc_cac_idx_lock);
3965 spin_lock_init(&adev->se_cac_idx_lock);
3966 spin_lock_init(&adev->audio_endpt_idx_lock);
3967 spin_lock_init(&adev->mm_stats.lock);
3969 INIT_LIST_HEAD(&adev->shadow_list);
3970 mutex_init(&adev->shadow_list_lock);
3972 INIT_LIST_HEAD(&adev->reset_list);
3974 INIT_LIST_HEAD(&adev->ras_list);
3976 INIT_LIST_HEAD(&adev->pm.od_kobj_list);
3978 INIT_DELAYED_WORK(&adev->delayed_init_work,
3979 amdgpu_device_delayed_init_work_handler);
3980 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3981 amdgpu_device_delay_enable_gfx_off);
3983 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3985 adev->gfx.gfx_off_req_count = 1;
3986 adev->gfx.gfx_off_residency = 0;
3987 adev->gfx.gfx_off_entrycount = 0;
3988 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3990 atomic_set(&adev->throttling_logging_enabled, 1);
3992 * If throttling continues, logging will be performed every minute
3993 * to avoid log flooding. "-1" is subtracted since the thermal
3994 * throttling interrupt comes every second. Thus, the total logging
3995 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3996 * for throttling interrupt) = 60 seconds.
3998 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3999 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
4001 /* Registers mapping */
4002 /* TODO: block userspace mapping of io register */
4003 if (adev->asic_type >= CHIP_BONAIRE) {
4004 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
4005 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
4007 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
4008 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
4011 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
4012 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
4014 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
4018 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
4019 DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size);
4022 * Reset domain needs to be present early, before XGMI hive discovered
4023 * (if any) and intitialized to use reset sem and in_gpu reset flag
4024 * early on during init and before calling to RREG32.
4026 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
4027 if (!adev->reset_domain)
4030 /* detect hw virtualization here */
4031 amdgpu_detect_virtualization(adev);
4033 amdgpu_device_get_pcie_info(adev);
4035 r = amdgpu_device_get_job_timeout_settings(adev);
4037 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
4041 /* early init functions */
4042 r = amdgpu_device_ip_early_init(adev);
4046 amdgpu_device_set_mcbp(adev);
4048 /* Get rid of things like offb */
4049 r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
4053 /* Enable TMZ based on IP_VERSION */
4054 amdgpu_gmc_tmz_set(adev);
4056 amdgpu_gmc_noretry_set(adev);
4057 /* Need to get xgmi info early to decide the reset behavior*/
4058 if (adev->gmc.xgmi.supported) {
4059 r = adev->gfxhub.funcs->get_xgmi_info(adev);
4064 /* enable PCIE atomic ops */
4065 if (amdgpu_sriov_vf(adev)) {
4066 if (adev->virt.fw_reserve.p_pf2vf)
4067 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
4068 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
4069 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4070 /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
4071 * internal path natively support atomics, set have_atomics_support to true.
4073 } else if ((adev->flags & AMD_IS_APU) &&
4074 (amdgpu_ip_version(adev, GC_HWIP, 0) >
4075 IP_VERSION(9, 0, 0))) {
4076 adev->have_atomics_support = true;
4078 adev->have_atomics_support =
4079 !pci_enable_atomic_ops_to_root(adev->pdev,
4080 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
4081 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4084 if (!adev->have_atomics_support)
4085 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
4087 /* doorbell bar mapping and doorbell index init*/
4088 amdgpu_doorbell_init(adev);
4090 if (amdgpu_emu_mode == 1) {
4091 /* post the asic on emulation mode */
4092 emu_soc_asic_init(adev);
4093 goto fence_driver_init;
4096 amdgpu_reset_init(adev);
4098 /* detect if we are with an SRIOV vbios */
4100 amdgpu_device_detect_sriov_bios(adev);
4102 /* check if we need to reset the asic
4103 * E.g., driver was not cleanly unloaded previously, etc.
4105 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
4106 if (adev->gmc.xgmi.num_physical_nodes) {
4107 dev_info(adev->dev, "Pending hive reset.\n");
4108 adev->gmc.xgmi.pending_reset = true;
4109 /* Only need to init necessary block for SMU to handle the reset */
4110 for (i = 0; i < adev->num_ip_blocks; i++) {
4111 if (!adev->ip_blocks[i].status.valid)
4113 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
4114 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
4115 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
4116 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
4117 DRM_DEBUG("IP %s disabled for hw_init.\n",
4118 adev->ip_blocks[i].version->funcs->name);
4119 adev->ip_blocks[i].status.hw = true;
4123 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
4124 case IP_VERSION(13, 0, 0):
4125 case IP_VERSION(13, 0, 7):
4126 case IP_VERSION(13, 0, 10):
4127 r = psp_gpu_reset(adev);
4130 tmp = amdgpu_reset_method;
4131 /* It should do a default reset when loading or reloading the driver,
4132 * regardless of the module parameter reset_method.
4134 amdgpu_reset_method = AMD_RESET_METHOD_NONE;
4135 r = amdgpu_asic_reset(adev);
4136 amdgpu_reset_method = tmp;
4141 dev_err(adev->dev, "asic reset on init failed\n");
4147 /* Post card if necessary */
4148 if (amdgpu_device_need_post(adev)) {
4150 dev_err(adev->dev, "no vBIOS found\n");
4154 DRM_INFO("GPU posting now...\n");
4155 r = amdgpu_device_asic_init(adev);
4157 dev_err(adev->dev, "gpu post error!\n");
4163 if (adev->is_atom_fw) {
4164 /* Initialize clocks */
4165 r = amdgpu_atomfirmware_get_clock_info(adev);
4167 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
4168 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4172 /* Initialize clocks */
4173 r = amdgpu_atombios_get_clock_info(adev);
4175 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
4176 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4179 /* init i2c buses */
4180 if (!amdgpu_device_has_dc_support(adev))
4181 amdgpu_atombios_i2c_init(adev);
4187 r = amdgpu_fence_driver_sw_init(adev);
4189 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
4190 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
4194 /* init the mode config */
4195 drm_mode_config_init(adev_to_drm(adev));
4197 r = amdgpu_device_ip_init(adev);
4199 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
4200 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
4201 goto release_ras_con;
4204 amdgpu_fence_driver_hw_init(adev);
4207 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
4208 adev->gfx.config.max_shader_engines,
4209 adev->gfx.config.max_sh_per_se,
4210 adev->gfx.config.max_cu_per_sh,
4211 adev->gfx.cu_info.number);
4213 adev->accel_working = true;
4215 amdgpu_vm_check_compute_bug(adev);
4217 /* Initialize the buffer migration limit. */
4218 if (amdgpu_moverate >= 0)
4219 max_MBps = amdgpu_moverate;
4221 max_MBps = 8; /* Allow 8 MB/s. */
4222 /* Get a log2 for easy divisions. */
4223 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
4226 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
4227 * Otherwise the mgpu fan boost feature will be skipped due to the
4228 * gpu instance is counted less.
4230 amdgpu_register_gpu_instance(adev);
4232 /* enable clockgating, etc. after ib tests, etc. since some blocks require
4233 * explicit gating rather than handling it automatically.
4235 if (!adev->gmc.xgmi.pending_reset) {
4236 r = amdgpu_device_ip_late_init(adev);
4238 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
4239 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
4240 goto release_ras_con;
4243 amdgpu_ras_resume(adev);
4244 queue_delayed_work(system_wq, &adev->delayed_init_work,
4245 msecs_to_jiffies(AMDGPU_RESUME_MS));
4248 if (amdgpu_sriov_vf(adev)) {
4249 amdgpu_virt_release_full_gpu(adev, true);
4250 flush_delayed_work(&adev->delayed_init_work);
4254 * Place those sysfs registering after `late_init`. As some of those
4255 * operations performed in `late_init` might affect the sysfs
4256 * interfaces creating.
4258 r = amdgpu_atombios_sysfs_init(adev);
4260 drm_err(&adev->ddev,
4261 "registering atombios sysfs failed (%d).\n", r);
4263 r = amdgpu_pm_sysfs_init(adev);
4265 DRM_ERROR("registering pm sysfs failed (%d).\n", r);
4267 r = amdgpu_ucode_sysfs_init(adev);
4269 adev->ucode_sysfs_en = false;
4270 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
4272 adev->ucode_sysfs_en = true;
4274 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
4276 dev_err(adev->dev, "Could not create amdgpu device attr\n");
4278 r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group);
4281 "Could not create amdgpu board attributes\n");
4283 amdgpu_fru_sysfs_init(adev);
4284 amdgpu_reg_state_sysfs_init(adev);
4286 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4287 r = amdgpu_pmu_init(adev);
4289 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
4291 /* Have stored pci confspace at hand for restore in sudden PCI error */
4292 if (amdgpu_device_cache_pci_state(adev->pdev))
4293 pci_restore_state(pdev);
4295 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
4296 /* this will fail for cards that aren't VGA class devices, just
4299 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4300 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
4302 px = amdgpu_device_supports_px(ddev);
4304 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4305 apple_gmux_detect(NULL, NULL)))
4306 vga_switcheroo_register_client(adev->pdev,
4307 &amdgpu_switcheroo_ops, px);
4310 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
4312 if (adev->gmc.xgmi.pending_reset)
4313 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
4314 msecs_to_jiffies(AMDGPU_RESUME_MS));
4316 amdgpu_device_check_iommu_direct_map(adev);
4321 if (amdgpu_sriov_vf(adev))
4322 amdgpu_virt_release_full_gpu(adev, true);
4324 /* failed in exclusive mode due to timeout */
4325 if (amdgpu_sriov_vf(adev) &&
4326 !amdgpu_sriov_runtime(adev) &&
4327 amdgpu_virt_mmio_blocked(adev) &&
4328 !amdgpu_virt_wait_reset(adev)) {
4329 dev_err(adev->dev, "VF exclusive mode timeout\n");
4330 /* Don't send request since VF is inactive. */
4331 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
4332 adev->virt.ops = NULL;
4335 amdgpu_release_ras_context(adev);
4338 amdgpu_vf_error_trans_all(adev);
4343 static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
4346 /* Clear all CPU mappings pointing to this device */
4347 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
4349 /* Unmap all mapped bars - Doorbell, registers and VRAM */
4350 amdgpu_doorbell_fini(adev);
4352 iounmap(adev->rmmio);
4354 if (adev->mman.aper_base_kaddr)
4355 iounmap(adev->mman.aper_base_kaddr);
4356 adev->mman.aper_base_kaddr = NULL;
4358 /* Memory manager related */
4359 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
4360 arch_phys_wc_del(adev->gmc.vram_mtrr);
4361 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
4366 * amdgpu_device_fini_hw - tear down the driver
4368 * @adev: amdgpu_device pointer
4370 * Tear down the driver info (all asics).
4371 * Called at driver shutdown.
4373 void amdgpu_device_fini_hw(struct amdgpu_device *adev)
4375 dev_info(adev->dev, "amdgpu: finishing device.\n");
4376 flush_delayed_work(&adev->delayed_init_work);
4377 adev->shutdown = true;
4379 /* make sure IB test finished before entering exclusive mode
4380 * to avoid preemption on IB test
4382 if (amdgpu_sriov_vf(adev)) {
4383 amdgpu_virt_request_full_gpu(adev, false);
4384 amdgpu_virt_fini_data_exchange(adev);
4387 /* disable all interrupts */
4388 amdgpu_irq_disable_all(adev);
4389 if (adev->mode_info.mode_config_initialized) {
4390 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
4391 drm_helper_force_disable_all(adev_to_drm(adev));
4393 drm_atomic_helper_shutdown(adev_to_drm(adev));
4395 amdgpu_fence_driver_hw_fini(adev);
4397 if (adev->mman.initialized)
4398 drain_workqueue(adev->mman.bdev.wq);
4400 if (adev->pm.sysfs_initialized)
4401 amdgpu_pm_sysfs_fini(adev);
4402 if (adev->ucode_sysfs_en)
4403 amdgpu_ucode_sysfs_fini(adev);
4404 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4405 amdgpu_fru_sysfs_fini(adev);
4407 amdgpu_reg_state_sysfs_fini(adev);
4409 /* disable ras feature must before hw fini */
4410 amdgpu_ras_pre_fini(adev);
4412 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4414 amdgpu_device_ip_fini_early(adev);
4416 amdgpu_irq_fini_hw(adev);
4418 if (adev->mman.initialized)
4419 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4421 amdgpu_gart_dummy_page_fini(adev);
4423 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4424 amdgpu_device_unmap_mmio(adev);
4428 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4433 amdgpu_fence_driver_sw_fini(adev);
4434 amdgpu_device_ip_fini(adev);
4435 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4436 adev->accel_working = false;
4437 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4439 amdgpu_reset_fini(adev);
4441 /* free i2c buses */
4442 if (!amdgpu_device_has_dc_support(adev))
4443 amdgpu_i2c_fini(adev);
4445 if (amdgpu_emu_mode != 1)
4446 amdgpu_atombios_fini(adev);
4451 kfree(adev->fru_info);
4452 adev->fru_info = NULL;
4454 px = amdgpu_device_supports_px(adev_to_drm(adev));
4456 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4457 apple_gmux_detect(NULL, NULL)))
4458 vga_switcheroo_unregister_client(adev->pdev);
4461 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4463 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4464 vga_client_unregister(adev->pdev);
4466 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4468 iounmap(adev->rmmio);
4470 amdgpu_doorbell_fini(adev);
4474 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4475 amdgpu_pmu_fini(adev);
4476 if (adev->mman.discovery_bin)
4477 amdgpu_discovery_fini(adev);
4479 amdgpu_reset_put_reset_domain(adev->reset_domain);
4480 adev->reset_domain = NULL;
4482 kfree(adev->pci_state);
4487 * amdgpu_device_evict_resources - evict device resources
4488 * @adev: amdgpu device object
4490 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4491 * of the vram memory type. Mainly used for evicting device resources
4495 static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4499 /* No need to evict vram on APUs for suspend to ram or s2idle */
4500 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4503 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4505 DRM_WARN("evicting device resources failed\n");
4513 * amdgpu_device_prepare - prepare for device suspend
4515 * @dev: drm dev pointer
4517 * Prepare to put the hw in the suspend state (all asics).
4518 * Returns 0 for success or an error on failure.
4519 * Called at driver suspend.
4521 int amdgpu_device_prepare(struct drm_device *dev)
4523 struct amdgpu_device *adev = drm_to_adev(dev);
4526 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4529 /* Evict the majority of BOs before starting suspend sequence */
4530 r = amdgpu_device_evict_resources(adev);
4534 for (i = 0; i < adev->num_ip_blocks; i++) {
4535 if (!adev->ip_blocks[i].status.valid)
4537 if (!adev->ip_blocks[i].version->funcs->prepare_suspend)
4539 r = adev->ip_blocks[i].version->funcs->prepare_suspend((void *)adev);
4548 * amdgpu_device_suspend - initiate device suspend
4550 * @dev: drm dev pointer
4551 * @fbcon : notify the fbdev of suspend
4553 * Puts the hw in the suspend state (all asics).
4554 * Returns 0 for success or an error on failure.
4555 * Called at driver suspend.
4557 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4559 struct amdgpu_device *adev = drm_to_adev(dev);
4562 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4565 adev->in_suspend = true;
4567 if (amdgpu_sriov_vf(adev)) {
4568 amdgpu_virt_fini_data_exchange(adev);
4569 r = amdgpu_virt_request_full_gpu(adev, false);
4574 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4575 DRM_WARN("smart shift update failed\n");
4578 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4580 cancel_delayed_work_sync(&adev->delayed_init_work);
4581 flush_delayed_work(&adev->gfx.gfx_off_delay_work);
4583 amdgpu_ras_suspend(adev);
4585 amdgpu_device_ip_suspend_phase1(adev);
4588 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4590 r = amdgpu_device_evict_resources(adev);
4594 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4596 amdgpu_fence_driver_hw_fini(adev);
4598 amdgpu_device_ip_suspend_phase2(adev);
4600 if (amdgpu_sriov_vf(adev))
4601 amdgpu_virt_release_full_gpu(adev, false);
4603 r = amdgpu_dpm_notify_rlc_state(adev, false);
4611 * amdgpu_device_resume - initiate device resume
4613 * @dev: drm dev pointer
4614 * @fbcon : notify the fbdev of resume
4616 * Bring the hw back to operating state (all asics).
4617 * Returns 0 for success or an error on failure.
4618 * Called at driver resume.
4620 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4622 struct amdgpu_device *adev = drm_to_adev(dev);
4625 if (amdgpu_sriov_vf(adev)) {
4626 r = amdgpu_virt_request_full_gpu(adev, true);
4631 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4635 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4638 if (amdgpu_device_need_post(adev)) {
4639 r = amdgpu_device_asic_init(adev);
4641 dev_err(adev->dev, "amdgpu asic init failed\n");
4644 r = amdgpu_device_ip_resume(adev);
4647 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4650 amdgpu_fence_driver_hw_init(adev);
4652 if (!adev->in_s0ix) {
4653 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4658 r = amdgpu_device_ip_late_init(adev);
4662 queue_delayed_work(system_wq, &adev->delayed_init_work,
4663 msecs_to_jiffies(AMDGPU_RESUME_MS));
4665 if (amdgpu_sriov_vf(adev)) {
4666 amdgpu_virt_init_data_exchange(adev);
4667 amdgpu_virt_release_full_gpu(adev, true);
4673 /* Make sure IB tests flushed */
4674 flush_delayed_work(&adev->delayed_init_work);
4677 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4679 amdgpu_ras_resume(adev);
4681 if (adev->mode_info.num_crtc) {
4683 * Most of the connector probing functions try to acquire runtime pm
4684 * refs to ensure that the GPU is powered on when connector polling is
4685 * performed. Since we're calling this from a runtime PM callback,
4686 * trying to acquire rpm refs will cause us to deadlock.
4688 * Since we're guaranteed to be holding the rpm lock, it's safe to
4689 * temporarily disable the rpm helpers so this doesn't deadlock us.
4692 dev->dev->power.disable_depth++;
4694 if (!adev->dc_enabled)
4695 drm_helper_hpd_irq_event(dev);
4697 drm_kms_helper_hotplug_event(dev);
4699 dev->dev->power.disable_depth--;
4702 adev->in_suspend = false;
4704 if (adev->enable_mes)
4705 amdgpu_mes_self_test(adev);
4707 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4708 DRM_WARN("smart shift update failed\n");
4714 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4716 * @adev: amdgpu_device pointer
4718 * The list of all the hardware IPs that make up the asic is walked and
4719 * the check_soft_reset callbacks are run. check_soft_reset determines
4720 * if the asic is still hung or not.
4721 * Returns true if any of the IPs are still in a hung state, false if not.
4723 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4726 bool asic_hang = false;
4728 if (amdgpu_sriov_vf(adev))
4731 if (amdgpu_asic_need_full_reset(adev))
4734 for (i = 0; i < adev->num_ip_blocks; i++) {
4735 if (!adev->ip_blocks[i].status.valid)
4737 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4738 adev->ip_blocks[i].status.hang =
4739 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4740 if (adev->ip_blocks[i].status.hang) {
4741 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4749 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4751 * @adev: amdgpu_device pointer
4753 * The list of all the hardware IPs that make up the asic is walked and the
4754 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4755 * handles any IP specific hardware or software state changes that are
4756 * necessary for a soft reset to succeed.
4757 * Returns 0 on success, negative error code on failure.
4759 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4763 for (i = 0; i < adev->num_ip_blocks; i++) {
4764 if (!adev->ip_blocks[i].status.valid)
4766 if (adev->ip_blocks[i].status.hang &&
4767 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4768 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4778 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4780 * @adev: amdgpu_device pointer
4782 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4783 * reset is necessary to recover.
4784 * Returns true if a full asic reset is required, false if not.
4786 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4790 if (amdgpu_asic_need_full_reset(adev))
4793 for (i = 0; i < adev->num_ip_blocks; i++) {
4794 if (!adev->ip_blocks[i].status.valid)
4796 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4797 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4798 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4799 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4800 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4801 if (adev->ip_blocks[i].status.hang) {
4802 dev_info(adev->dev, "Some block need full reset!\n");
4811 * amdgpu_device_ip_soft_reset - do a soft reset
4813 * @adev: amdgpu_device pointer
4815 * The list of all the hardware IPs that make up the asic is walked and the
4816 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4817 * IP specific hardware or software state changes that are necessary to soft
4819 * Returns 0 on success, negative error code on failure.
4821 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4825 for (i = 0; i < adev->num_ip_blocks; i++) {
4826 if (!adev->ip_blocks[i].status.valid)
4828 if (adev->ip_blocks[i].status.hang &&
4829 adev->ip_blocks[i].version->funcs->soft_reset) {
4830 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4840 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4842 * @adev: amdgpu_device pointer
4844 * The list of all the hardware IPs that make up the asic is walked and the
4845 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4846 * handles any IP specific hardware or software state changes that are
4847 * necessary after the IP has been soft reset.
4848 * Returns 0 on success, negative error code on failure.
4850 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4854 for (i = 0; i < adev->num_ip_blocks; i++) {
4855 if (!adev->ip_blocks[i].status.valid)
4857 if (adev->ip_blocks[i].status.hang &&
4858 adev->ip_blocks[i].version->funcs->post_soft_reset)
4859 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4868 * amdgpu_device_recover_vram - Recover some VRAM contents
4870 * @adev: amdgpu_device pointer
4872 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4873 * restore things like GPUVM page tables after a GPU reset where
4874 * the contents of VRAM might be lost.
4877 * 0 on success, negative error code on failure.
4879 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4881 struct dma_fence *fence = NULL, *next = NULL;
4882 struct amdgpu_bo *shadow;
4883 struct amdgpu_bo_vm *vmbo;
4886 if (amdgpu_sriov_runtime(adev))
4887 tmo = msecs_to_jiffies(8000);
4889 tmo = msecs_to_jiffies(100);
4891 dev_info(adev->dev, "recover vram bo from shadow start\n");
4892 mutex_lock(&adev->shadow_list_lock);
4893 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4894 /* If vm is compute context or adev is APU, shadow will be NULL */
4897 shadow = vmbo->shadow;
4899 /* No need to recover an evicted BO */
4900 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4901 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4902 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4905 r = amdgpu_bo_restore_shadow(shadow, &next);
4910 tmo = dma_fence_wait_timeout(fence, false, tmo);
4911 dma_fence_put(fence);
4916 } else if (tmo < 0) {
4924 mutex_unlock(&adev->shadow_list_lock);
4927 tmo = dma_fence_wait_timeout(fence, false, tmo);
4928 dma_fence_put(fence);
4930 if (r < 0 || tmo <= 0) {
4931 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4935 dev_info(adev->dev, "recover vram bo from shadow done\n");
4941 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4943 * @adev: amdgpu_device pointer
4944 * @from_hypervisor: request from hypervisor
4946 * do VF FLR and reinitialize Asic
4947 * return 0 means succeeded otherwise failed
4949 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4950 bool from_hypervisor)
4953 struct amdgpu_hive_info *hive = NULL;
4954 int retry_limit = 0;
4957 amdgpu_amdkfd_pre_reset(adev);
4959 if (from_hypervisor)
4960 r = amdgpu_virt_request_full_gpu(adev, true);
4962 r = amdgpu_virt_reset_gpu(adev);
4965 amdgpu_irq_gpu_reset_resume_helper(adev);
4967 /* some sw clean up VF needs to do before recover */
4968 amdgpu_virt_post_reset(adev);
4970 /* Resume IP prior to SMC */
4971 r = amdgpu_device_ip_reinit_early_sriov(adev);
4975 amdgpu_virt_init_data_exchange(adev);
4977 r = amdgpu_device_fw_loading(adev);
4981 /* now we are okay to resume SMC/CP/SDMA */
4982 r = amdgpu_device_ip_reinit_late_sriov(adev);
4986 hive = amdgpu_get_xgmi_hive(adev);
4987 /* Update PSP FW topology after reset */
4988 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
4989 r = amdgpu_xgmi_update_topology(hive, adev);
4992 amdgpu_put_xgmi_hive(hive);
4995 r = amdgpu_ib_ring_tests(adev);
4997 amdgpu_amdkfd_post_reset(adev);
5001 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
5002 amdgpu_inc_vram_lost(adev);
5003 r = amdgpu_device_recover_vram(adev);
5005 amdgpu_virt_release_full_gpu(adev, true);
5007 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
5008 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
5012 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
5019 * amdgpu_device_has_job_running - check if there is any job in mirror list
5021 * @adev: amdgpu_device pointer
5023 * check if there is any job in mirror list
5025 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
5028 struct drm_sched_job *job;
5030 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5031 struct amdgpu_ring *ring = adev->rings[i];
5033 if (!ring || !drm_sched_wqueue_ready(&ring->sched))
5036 spin_lock(&ring->sched.job_list_lock);
5037 job = list_first_entry_or_null(&ring->sched.pending_list,
5038 struct drm_sched_job, list);
5039 spin_unlock(&ring->sched.job_list_lock);
5047 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
5049 * @adev: amdgpu_device pointer
5051 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
5054 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
5057 if (amdgpu_gpu_recovery == 0)
5060 /* Skip soft reset check in fatal error mode */
5061 if (!amdgpu_ras_is_poison_mode_supported(adev))
5064 if (amdgpu_sriov_vf(adev))
5067 if (amdgpu_gpu_recovery == -1) {
5068 switch (adev->asic_type) {
5069 #ifdef CONFIG_DRM_AMDGPU_SI
5076 #ifdef CONFIG_DRM_AMDGPU_CIK
5083 case CHIP_CYAN_SKILLFISH:
5093 dev_info(adev->dev, "GPU recovery disabled.\n");
5097 int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
5102 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
5104 dev_info(adev->dev, "GPU mode1 reset\n");
5107 pci_clear_master(adev->pdev);
5109 amdgpu_device_cache_pci_state(adev->pdev);
5111 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
5112 dev_info(adev->dev, "GPU smu mode1 reset\n");
5113 ret = amdgpu_dpm_mode1_reset(adev);
5115 dev_info(adev->dev, "GPU psp mode1 reset\n");
5116 ret = psp_gpu_reset(adev);
5120 goto mode1_reset_failed;
5122 amdgpu_device_load_pci_state(adev->pdev);
5123 ret = amdgpu_psp_wait_for_bootloader(adev);
5125 goto mode1_reset_failed;
5127 /* wait for asic to come out of reset */
5128 for (i = 0; i < adev->usec_timeout; i++) {
5129 u32 memsize = adev->nbio.funcs->get_memsize(adev);
5131 if (memsize != 0xffffffff)
5136 if (i >= adev->usec_timeout) {
5138 goto mode1_reset_failed;
5141 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
5146 dev_err(adev->dev, "GPU mode1 reset failed\n");
5150 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
5151 struct amdgpu_reset_context *reset_context)
5154 struct amdgpu_job *job = NULL;
5155 bool need_full_reset =
5156 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5158 if (reset_context->reset_req_dev == adev)
5159 job = reset_context->job;
5161 if (amdgpu_sriov_vf(adev)) {
5162 /* stop the data exchange thread */
5163 amdgpu_virt_fini_data_exchange(adev);
5166 amdgpu_fence_driver_isr_toggle(adev, true);
5168 /* block all schedulers and reset given job's ring */
5169 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5170 struct amdgpu_ring *ring = adev->rings[i];
5172 if (!ring || !drm_sched_wqueue_ready(&ring->sched))
5175 /* Clear job fence from fence drv to avoid force_completion
5176 * leave NULL and vm flush fence in fence drv
5178 amdgpu_fence_driver_clear_job_fences(ring);
5180 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
5181 amdgpu_fence_driver_force_completion(ring);
5184 amdgpu_fence_driver_isr_toggle(adev, false);
5187 drm_sched_increase_karma(&job->base);
5189 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
5190 /* If reset handler not implemented, continue; otherwise return */
5191 if (r == -EOPNOTSUPP)
5196 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
5197 if (!amdgpu_sriov_vf(adev)) {
5199 if (!need_full_reset)
5200 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
5202 if (!need_full_reset && amdgpu_gpu_recovery &&
5203 amdgpu_device_ip_check_soft_reset(adev)) {
5204 amdgpu_device_ip_pre_soft_reset(adev);
5205 r = amdgpu_device_ip_soft_reset(adev);
5206 amdgpu_device_ip_post_soft_reset(adev);
5207 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
5208 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
5209 need_full_reset = true;
5213 if (need_full_reset)
5214 r = amdgpu_device_ip_suspend(adev);
5215 if (need_full_reset)
5216 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5218 clear_bit(AMDGPU_NEED_FULL_RESET,
5219 &reset_context->flags);
5225 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
5229 lockdep_assert_held(&adev->reset_domain->sem);
5231 for (i = 0; i < adev->reset_info.num_regs; i++) {
5232 adev->reset_info.reset_dump_reg_value[i] =
5233 RREG32(adev->reset_info.reset_dump_reg_list[i]);
5235 trace_amdgpu_reset_reg_dumps(adev->reset_info.reset_dump_reg_list[i],
5236 adev->reset_info.reset_dump_reg_value[i]);
5242 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
5243 struct amdgpu_reset_context *reset_context)
5245 struct amdgpu_device *tmp_adev = NULL;
5246 bool need_full_reset, skip_hw_reset, vram_lost = false;
5248 bool gpu_reset_for_dev_remove = 0;
5250 /* Try reset handler method first */
5251 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5253 amdgpu_reset_reg_dumps(tmp_adev);
5255 reset_context->reset_device_list = device_list_handle;
5256 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
5257 /* If reset handler not implemented, continue; otherwise return */
5258 if (r == -EOPNOTSUPP)
5263 /* Reset handler not implemented, use the default method */
5265 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5266 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
5268 gpu_reset_for_dev_remove =
5269 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5270 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5273 * ASIC reset has to be done on all XGMI hive nodes ASAP
5274 * to allow proper links negotiation in FW (within 1 sec)
5276 if (!skip_hw_reset && need_full_reset) {
5277 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5278 /* For XGMI run all resets in parallel to speed up the process */
5279 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5280 tmp_adev->gmc.xgmi.pending_reset = false;
5281 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
5284 r = amdgpu_asic_reset(tmp_adev);
5287 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
5288 r, adev_to_drm(tmp_adev)->unique);
5293 /* For XGMI wait for all resets to complete before proceed */
5295 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5296 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5297 flush_work(&tmp_adev->xgmi_reset_work);
5298 r = tmp_adev->asic_reset_res;
5306 if (!r && amdgpu_ras_intr_triggered()) {
5307 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5308 amdgpu_ras_reset_error_count(tmp_adev, AMDGPU_RAS_BLOCK__MMHUB);
5311 amdgpu_ras_intr_cleared();
5314 /* Since the mode1 reset affects base ip blocks, the
5315 * phase1 ip blocks need to be resumed. Otherwise there
5316 * will be a BIOS signature error and the psp bootloader
5317 * can't load kdb on the next amdgpu install.
5319 if (gpu_reset_for_dev_remove) {
5320 list_for_each_entry(tmp_adev, device_list_handle, reset_list)
5321 amdgpu_device_ip_resume_phase1(tmp_adev);
5326 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5327 if (need_full_reset) {
5329 r = amdgpu_device_asic_init(tmp_adev);
5331 dev_warn(tmp_adev->dev, "asic atom init failed!");
5333 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
5335 r = amdgpu_device_ip_resume_phase1(tmp_adev);
5339 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
5341 amdgpu_coredump(tmp_adev, vram_lost, reset_context);
5344 DRM_INFO("VRAM is lost due to GPU reset!\n");
5345 amdgpu_inc_vram_lost(tmp_adev);
5348 r = amdgpu_device_fw_loading(tmp_adev);
5352 r = amdgpu_xcp_restore_partition_mode(
5357 r = amdgpu_device_ip_resume_phase2(tmp_adev);
5361 if (tmp_adev->mman.buffer_funcs_ring->sched.ready)
5362 amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);
5365 amdgpu_device_fill_reset_magic(tmp_adev);
5368 * Add this ASIC as tracked as reset was already
5369 * complete successfully.
5371 amdgpu_register_gpu_instance(tmp_adev);
5373 if (!reset_context->hive &&
5374 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5375 amdgpu_xgmi_add_device(tmp_adev);
5377 r = amdgpu_device_ip_late_init(tmp_adev);
5381 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
5384 * The GPU enters bad state once faulty pages
5385 * by ECC has reached the threshold, and ras
5386 * recovery is scheduled next. So add one check
5387 * here to break recovery if it indeed exceeds
5388 * bad page threshold, and remind user to
5389 * retire this GPU or setting one bigger
5390 * bad_page_threshold value to fix this once
5391 * probing driver again.
5393 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
5395 amdgpu_ras_resume(tmp_adev);
5401 /* Update PSP FW topology after reset */
5402 if (reset_context->hive &&
5403 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5404 r = amdgpu_xgmi_update_topology(
5405 reset_context->hive, tmp_adev);
5411 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5412 r = amdgpu_ib_ring_tests(tmp_adev);
5414 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5415 need_full_reset = true;
5422 r = amdgpu_device_recover_vram(tmp_adev);
5424 tmp_adev->asic_reset_res = r;
5428 if (need_full_reset)
5429 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5431 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5435 static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5438 switch (amdgpu_asic_reset_method(adev)) {
5439 case AMD_RESET_METHOD_MODE1:
5440 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5442 case AMD_RESET_METHOD_MODE2:
5443 adev->mp1_state = PP_MP1_STATE_RESET;
5446 adev->mp1_state = PP_MP1_STATE_NONE;
5451 static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5453 amdgpu_vf_error_trans_all(adev);
5454 adev->mp1_state = PP_MP1_STATE_NONE;
5457 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5459 struct pci_dev *p = NULL;
5461 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5462 adev->pdev->bus->number, 1);
5464 pm_runtime_enable(&(p->dev));
5465 pm_runtime_resume(&(p->dev));
5471 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5473 enum amd_reset_method reset_method;
5474 struct pci_dev *p = NULL;
5478 * For now, only BACO and mode1 reset are confirmed
5479 * to suffer the audio issue without proper suspended.
5481 reset_method = amdgpu_asic_reset_method(adev);
5482 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5483 (reset_method != AMD_RESET_METHOD_MODE1))
5486 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5487 adev->pdev->bus->number, 1);
5491 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5494 * If we cannot get the audio device autosuspend delay,
5495 * a fixed 4S interval will be used. Considering 3S is
5496 * the audio controller default autosuspend delay setting.
5497 * 4S used here is guaranteed to cover that.
5499 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5501 while (!pm_runtime_status_suspended(&(p->dev))) {
5502 if (!pm_runtime_suspend(&(p->dev)))
5505 if (expires < ktime_get_mono_fast_ns()) {
5506 dev_warn(adev->dev, "failed to suspend display audio\n");
5508 /* TODO: abort the succeeding gpu reset? */
5513 pm_runtime_disable(&(p->dev));
5519 static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5521 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5523 #if defined(CONFIG_DEBUG_FS)
5524 if (!amdgpu_sriov_vf(adev))
5525 cancel_work(&adev->reset_work);
5529 cancel_work(&adev->kfd.reset_work);
5531 if (amdgpu_sriov_vf(adev))
5532 cancel_work(&adev->virt.flr_work);
5534 if (con && adev->ras_enabled)
5535 cancel_work(&con->recovery_work);
5540 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5542 * @adev: amdgpu_device pointer
5543 * @job: which job trigger hang
5544 * @reset_context: amdgpu reset context pointer
5546 * Attempt to reset the GPU if it has hung (all asics).
5547 * Attempt to do soft-reset or full-reset and reinitialize Asic
5548 * Returns 0 for success or an error on failure.
5551 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5552 struct amdgpu_job *job,
5553 struct amdgpu_reset_context *reset_context)
5555 struct list_head device_list, *device_list_handle = NULL;
5556 bool job_signaled = false;
5557 struct amdgpu_hive_info *hive = NULL;
5558 struct amdgpu_device *tmp_adev = NULL;
5560 bool need_emergency_restart = false;
5561 bool audio_suspended = false;
5562 bool gpu_reset_for_dev_remove = false;
5564 gpu_reset_for_dev_remove =
5565 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5566 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5569 * Special case: RAS triggered and full reset isn't supported
5571 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5574 * Flush RAM to disk so that after reboot
5575 * the user can read log and see why the system rebooted.
5577 if (need_emergency_restart && amdgpu_ras_get_context(adev) &&
5578 amdgpu_ras_get_context(adev)->reboot) {
5579 DRM_WARN("Emergency reboot.");
5582 emergency_restart();
5585 dev_info(adev->dev, "GPU %s begin!\n",
5586 need_emergency_restart ? "jobs stop":"reset");
5588 if (!amdgpu_sriov_vf(adev))
5589 hive = amdgpu_get_xgmi_hive(adev);
5591 mutex_lock(&hive->hive_lock);
5593 reset_context->job = job;
5594 reset_context->hive = hive;
5596 * Build list of devices to reset.
5597 * In case we are in XGMI hive mode, resort the device list
5598 * to put adev in the 1st position.
5600 INIT_LIST_HEAD(&device_list);
5601 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5602 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5603 list_add_tail(&tmp_adev->reset_list, &device_list);
5604 if (gpu_reset_for_dev_remove && adev->shutdown)
5605 tmp_adev->shutdown = true;
5607 if (!list_is_first(&adev->reset_list, &device_list))
5608 list_rotate_to_front(&adev->reset_list, &device_list);
5609 device_list_handle = &device_list;
5611 list_add_tail(&adev->reset_list, &device_list);
5612 device_list_handle = &device_list;
5615 /* We need to lock reset domain only once both for XGMI and single device */
5616 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5618 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5620 /* block all schedulers and reset given job's ring */
5621 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5623 amdgpu_device_set_mp1_state(tmp_adev);
5626 * Try to put the audio codec into suspend state
5627 * before gpu reset started.
5629 * Due to the power domain of the graphics device
5630 * is shared with AZ power domain. Without this,
5631 * we may change the audio hardware from behind
5632 * the audio driver's back. That will trigger
5633 * some audio codec errors.
5635 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5636 audio_suspended = true;
5638 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5640 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5642 if (!amdgpu_sriov_vf(tmp_adev))
5643 amdgpu_amdkfd_pre_reset(tmp_adev);
5646 * Mark these ASICs to be reseted as untracked first
5647 * And add them back after reset completed
5649 amdgpu_unregister_gpu_instance(tmp_adev);
5651 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5653 /* disable ras on ALL IPs */
5654 if (!need_emergency_restart &&
5655 amdgpu_device_ip_need_full_reset(tmp_adev))
5656 amdgpu_ras_suspend(tmp_adev);
5658 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5659 struct amdgpu_ring *ring = tmp_adev->rings[i];
5661 if (!ring || !drm_sched_wqueue_ready(&ring->sched))
5664 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5666 if (need_emergency_restart)
5667 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5669 atomic_inc(&tmp_adev->gpu_reset_counter);
5672 if (need_emergency_restart)
5673 goto skip_sched_resume;
5676 * Must check guilty signal here since after this point all old
5677 * HW fences are force signaled.
5679 * job->base holds a reference to parent fence
5681 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5682 job_signaled = true;
5683 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5687 retry: /* Rest of adevs pre asic reset from XGMI hive. */
5688 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5689 if (gpu_reset_for_dev_remove) {
5690 /* Workaroud for ASICs need to disable SMC first */
5691 amdgpu_device_smu_fini_early(tmp_adev);
5693 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5694 /*TODO Should we stop ?*/
5696 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5697 r, adev_to_drm(tmp_adev)->unique);
5698 tmp_adev->asic_reset_res = r;
5702 * Drop all pending non scheduler resets. Scheduler resets
5703 * were already dropped during drm_sched_stop
5705 amdgpu_device_stop_pending_resets(tmp_adev);
5708 /* Actual ASIC resets if needed.*/
5709 /* Host driver will handle XGMI hive reset for SRIOV */
5710 if (amdgpu_sriov_vf(adev)) {
5711 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5713 adev->asic_reset_res = r;
5715 /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */
5716 if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5717 IP_VERSION(9, 4, 2) ||
5718 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))
5719 amdgpu_ras_resume(adev);
5721 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5722 if (r && r == -EAGAIN)
5725 if (!r && gpu_reset_for_dev_remove)
5731 /* Post ASIC reset for all devs .*/
5732 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5734 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5735 struct amdgpu_ring *ring = tmp_adev->rings[i];
5737 if (!ring || !drm_sched_wqueue_ready(&ring->sched))
5740 drm_sched_start(&ring->sched, true);
5743 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
5744 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5746 if (tmp_adev->asic_reset_res)
5747 r = tmp_adev->asic_reset_res;
5749 tmp_adev->asic_reset_res = 0;
5752 /* bad news, how to tell it to userspace ? */
5753 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5754 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5756 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5757 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5758 DRM_WARN("smart shift update failed\n");
5763 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5764 /* unlock kfd: SRIOV would do it separately */
5765 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5766 amdgpu_amdkfd_post_reset(tmp_adev);
5768 /* kfd_post_reset will do nothing if kfd device is not initialized,
5769 * need to bring up kfd here if it's not be initialized before
5771 if (!adev->kfd.init_complete)
5772 amdgpu_amdkfd_device_init(adev);
5774 if (audio_suspended)
5775 amdgpu_device_resume_display_audio(tmp_adev);
5777 amdgpu_device_unset_mp1_state(tmp_adev);
5779 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5783 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5785 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5788 mutex_unlock(&hive->hive_lock);
5789 amdgpu_put_xgmi_hive(hive);
5793 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5795 atomic_set(&adev->reset_domain->reset_res, r);
5800 * amdgpu_device_partner_bandwidth - find the bandwidth of appropriate partner
5802 * @adev: amdgpu_device pointer
5803 * @speed: pointer to the speed of the link
5804 * @width: pointer to the width of the link
5806 * Evaluate the hierarchy to find the speed and bandwidth capabilities of the
5807 * first physical partner to an AMD dGPU.
5808 * This will exclude any virtual switches and links.
5810 static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,
5811 enum pci_bus_speed *speed,
5812 enum pcie_link_width *width)
5814 struct pci_dev *parent = adev->pdev;
5816 if (!speed || !width)
5819 *speed = PCI_SPEED_UNKNOWN;
5820 *width = PCIE_LNK_WIDTH_UNKNOWN;
5822 while ((parent = pci_upstream_bridge(parent))) {
5823 /* skip upstream/downstream switches internal to dGPU*/
5824 if (parent->vendor == PCI_VENDOR_ID_ATI)
5826 *speed = pcie_get_speed_cap(parent);
5827 *width = pcie_get_width_cap(parent);
5833 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5835 * @adev: amdgpu_device pointer
5837 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5838 * and lanes) of the slot the device is in. Handles APUs and
5839 * virtualized environments where PCIE config space may not be available.
5841 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5843 struct pci_dev *pdev;
5844 enum pci_bus_speed speed_cap, platform_speed_cap;
5845 enum pcie_link_width platform_link_width;
5847 if (amdgpu_pcie_gen_cap)
5848 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5850 if (amdgpu_pcie_lane_cap)
5851 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5853 /* covers APUs as well */
5854 if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) {
5855 if (adev->pm.pcie_gen_mask == 0)
5856 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5857 if (adev->pm.pcie_mlw_mask == 0)
5858 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5862 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5865 amdgpu_device_partner_bandwidth(adev, &platform_speed_cap,
5866 &platform_link_width);
5868 if (adev->pm.pcie_gen_mask == 0) {
5871 speed_cap = pcie_get_speed_cap(pdev);
5872 if (speed_cap == PCI_SPEED_UNKNOWN) {
5873 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5874 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5875 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5877 if (speed_cap == PCIE_SPEED_32_0GT)
5878 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5879 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5880 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5881 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5882 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5883 else if (speed_cap == PCIE_SPEED_16_0GT)
5884 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5885 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5886 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5887 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5888 else if (speed_cap == PCIE_SPEED_8_0GT)
5889 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5890 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5891 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5892 else if (speed_cap == PCIE_SPEED_5_0GT)
5893 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5894 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5896 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5899 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5900 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5901 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5903 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5904 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5905 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5906 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5907 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5908 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5909 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5910 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5911 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5912 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5913 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5914 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5915 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5916 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5917 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5918 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5919 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5920 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5922 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5926 if (adev->pm.pcie_mlw_mask == 0) {
5927 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5928 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5930 switch (platform_link_width) {
5932 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5933 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5934 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5935 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5936 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5937 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5938 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5941 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5942 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5943 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5944 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5945 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5946 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5949 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5950 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5951 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5952 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5953 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5956 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5957 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5958 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5959 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5962 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5963 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5964 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5967 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5968 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5971 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5981 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5983 * @adev: amdgpu_device pointer
5984 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5986 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5987 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5990 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5991 struct amdgpu_device *peer_adev)
5993 #ifdef CONFIG_HSA_AMD_P2P
5994 uint64_t address_mask = peer_adev->dev->dma_mask ?
5995 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5996 resource_size_t aper_limit =
5997 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5999 !adev->gmc.xgmi.connected_to_cpu &&
6000 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
6002 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
6003 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
6004 !(adev->gmc.aper_base & address_mask ||
6005 aper_limit & address_mask));
6011 int amdgpu_device_baco_enter(struct drm_device *dev)
6013 struct amdgpu_device *adev = drm_to_adev(dev);
6014 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
6016 if (!amdgpu_device_supports_baco(dev))
6019 if (ras && adev->ras_enabled &&
6020 adev->nbio.funcs->enable_doorbell_interrupt)
6021 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
6023 return amdgpu_dpm_baco_enter(adev);
6026 int amdgpu_device_baco_exit(struct drm_device *dev)
6028 struct amdgpu_device *adev = drm_to_adev(dev);
6029 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
6032 if (!amdgpu_device_supports_baco(dev))
6035 ret = amdgpu_dpm_baco_exit(adev);
6039 if (ras && adev->ras_enabled &&
6040 adev->nbio.funcs->enable_doorbell_interrupt)
6041 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
6043 if (amdgpu_passthrough(adev) &&
6044 adev->nbio.funcs->clear_doorbell_interrupt)
6045 adev->nbio.funcs->clear_doorbell_interrupt(adev);
6051 * amdgpu_pci_error_detected - Called when a PCI error is detected.
6052 * @pdev: PCI device struct
6053 * @state: PCI channel state
6055 * Description: Called when a PCI error is detected.
6057 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
6059 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6061 struct drm_device *dev = pci_get_drvdata(pdev);
6062 struct amdgpu_device *adev = drm_to_adev(dev);
6065 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
6067 if (adev->gmc.xgmi.num_physical_nodes > 1) {
6068 DRM_WARN("No support for XGMI hive yet...");
6069 return PCI_ERS_RESULT_DISCONNECT;
6072 adev->pci_channel_state = state;
6075 case pci_channel_io_normal:
6076 return PCI_ERS_RESULT_CAN_RECOVER;
6077 /* Fatal error, prepare for slot reset */
6078 case pci_channel_io_frozen:
6080 * Locking adev->reset_domain->sem will prevent any external access
6081 * to GPU during PCI error recovery
6083 amdgpu_device_lock_reset_domain(adev->reset_domain);
6084 amdgpu_device_set_mp1_state(adev);
6087 * Block any work scheduling as we do for regular GPU reset
6088 * for the duration of the recovery
6090 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6091 struct amdgpu_ring *ring = adev->rings[i];
6093 if (!ring || !drm_sched_wqueue_ready(&ring->sched))
6096 drm_sched_stop(&ring->sched, NULL);
6098 atomic_inc(&adev->gpu_reset_counter);
6099 return PCI_ERS_RESULT_NEED_RESET;
6100 case pci_channel_io_perm_failure:
6101 /* Permanent error, prepare for device removal */
6102 return PCI_ERS_RESULT_DISCONNECT;
6105 return PCI_ERS_RESULT_NEED_RESET;
6109 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
6110 * @pdev: pointer to PCI device
6112 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
6115 DRM_INFO("PCI error: mmio enabled callback!!\n");
6117 /* TODO - dump whatever for debugging purposes */
6119 /* This called only if amdgpu_pci_error_detected returns
6120 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
6121 * works, no need to reset slot.
6124 return PCI_ERS_RESULT_RECOVERED;
6128 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
6129 * @pdev: PCI device struct
6131 * Description: This routine is called by the pci error recovery
6132 * code after the PCI slot has been reset, just before we
6133 * should resume normal operations.
6135 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
6137 struct drm_device *dev = pci_get_drvdata(pdev);
6138 struct amdgpu_device *adev = drm_to_adev(dev);
6140 struct amdgpu_reset_context reset_context;
6142 struct list_head device_list;
6144 DRM_INFO("PCI error: slot reset callback!!\n");
6146 memset(&reset_context, 0, sizeof(reset_context));
6148 INIT_LIST_HEAD(&device_list);
6149 list_add_tail(&adev->reset_list, &device_list);
6151 /* wait for asic to come out of reset */
6154 /* Restore PCI confspace */
6155 amdgpu_device_load_pci_state(pdev);
6157 /* confirm ASIC came out of reset */
6158 for (i = 0; i < adev->usec_timeout; i++) {
6159 memsize = amdgpu_asic_get_config_memsize(adev);
6161 if (memsize != 0xffffffff)
6165 if (memsize == 0xffffffff) {
6170 reset_context.method = AMD_RESET_METHOD_NONE;
6171 reset_context.reset_req_dev = adev;
6172 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
6173 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
6175 adev->no_hw_access = true;
6176 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
6177 adev->no_hw_access = false;
6181 r = amdgpu_do_asic_reset(&device_list, &reset_context);
6185 if (amdgpu_device_cache_pci_state(adev->pdev))
6186 pci_restore_state(adev->pdev);
6188 DRM_INFO("PCIe error recovery succeeded\n");
6190 DRM_ERROR("PCIe error recovery failed, err:%d", r);
6191 amdgpu_device_unset_mp1_state(adev);
6192 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6195 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
6199 * amdgpu_pci_resume() - resume normal ops after PCI reset
6200 * @pdev: pointer to PCI device
6202 * Called when the error recovery driver tells us that its
6203 * OK to resume normal operation.
6205 void amdgpu_pci_resume(struct pci_dev *pdev)
6207 struct drm_device *dev = pci_get_drvdata(pdev);
6208 struct amdgpu_device *adev = drm_to_adev(dev);
6212 DRM_INFO("PCI error: resume callback!!\n");
6214 /* Only continue execution for the case of pci_channel_io_frozen */
6215 if (adev->pci_channel_state != pci_channel_io_frozen)
6218 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6219 struct amdgpu_ring *ring = adev->rings[i];
6221 if (!ring || !drm_sched_wqueue_ready(&ring->sched))
6224 drm_sched_start(&ring->sched, true);
6227 amdgpu_device_unset_mp1_state(adev);
6228 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6231 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
6233 struct drm_device *dev = pci_get_drvdata(pdev);
6234 struct amdgpu_device *adev = drm_to_adev(dev);
6237 r = pci_save_state(pdev);
6239 kfree(adev->pci_state);
6241 adev->pci_state = pci_store_saved_state(pdev);
6243 if (!adev->pci_state) {
6244 DRM_ERROR("Failed to store PCI saved state");
6248 DRM_WARN("Failed to save PCI state, err:%d\n", r);
6255 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
6257 struct drm_device *dev = pci_get_drvdata(pdev);
6258 struct amdgpu_device *adev = drm_to_adev(dev);
6261 if (!adev->pci_state)
6264 r = pci_load_saved_state(pdev, adev->pci_state);
6267 pci_restore_state(pdev);
6269 DRM_WARN("Failed to load PCI state, err:%d\n", r);
6276 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
6277 struct amdgpu_ring *ring)
6279 #ifdef CONFIG_X86_64
6280 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6283 if (adev->gmc.xgmi.connected_to_cpu)
6286 if (ring && ring->funcs->emit_hdp_flush)
6287 amdgpu_ring_emit_hdp_flush(ring);
6289 amdgpu_asic_flush_hdp(adev, ring);
6292 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
6293 struct amdgpu_ring *ring)
6295 #ifdef CONFIG_X86_64
6296 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6299 if (adev->gmc.xgmi.connected_to_cpu)
6302 amdgpu_asic_invalidate_hdp(adev, ring);
6305 int amdgpu_in_reset(struct amdgpu_device *adev)
6307 return atomic_read(&adev->reset_domain->in_gpu_reset);
6311 * amdgpu_device_halt() - bring hardware to some kind of halt state
6313 * @adev: amdgpu_device pointer
6315 * Bring hardware to some kind of halt state so that no one can touch it
6316 * any more. It will help to maintain error context when error occurred.
6317 * Compare to a simple hang, the system will keep stable at least for SSH
6318 * access. Then it should be trivial to inspect the hardware state and
6319 * see what's going on. Implemented as following:
6321 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
6322 * clears all CPU mappings to device, disallows remappings through page faults
6323 * 2. amdgpu_irq_disable_all() disables all interrupts
6324 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
6325 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
6326 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
6327 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
6328 * flush any in flight DMA operations
6330 void amdgpu_device_halt(struct amdgpu_device *adev)
6332 struct pci_dev *pdev = adev->pdev;
6333 struct drm_device *ddev = adev_to_drm(adev);
6335 amdgpu_xcp_dev_unplug(adev);
6336 drm_dev_unplug(ddev);
6338 amdgpu_irq_disable_all(adev);
6340 amdgpu_fence_driver_hw_fini(adev);
6342 adev->no_hw_access = true;
6344 amdgpu_device_unmap_mmio(adev);
6346 pci_disable_device(pdev);
6347 pci_wait_for_pending_transaction(pdev);
6350 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
6353 unsigned long flags, address, data;
6356 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6357 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6359 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6360 WREG32(address, reg * 4);
6361 (void)RREG32(address);
6363 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6367 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
6370 unsigned long flags, address, data;
6372 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6373 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6375 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6376 WREG32(address, reg * 4);
6377 (void)RREG32(address);
6380 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6384 * amdgpu_device_switch_gang - switch to a new gang
6385 * @adev: amdgpu_device pointer
6386 * @gang: the gang to switch to
6388 * Try to switch to a new gang.
6389 * Returns: NULL if we switched to the new gang or a reference to the current
6392 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
6393 struct dma_fence *gang)
6395 struct dma_fence *old = NULL;
6400 old = dma_fence_get_rcu_safe(&adev->gang_submit);
6406 if (!dma_fence_is_signaled(old))
6409 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
6416 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
6418 switch (adev->asic_type) {
6419 #ifdef CONFIG_DRM_AMDGPU_SI
6423 /* chips with no display hardware */
6425 #ifdef CONFIG_DRM_AMDGPU_SI
6431 #ifdef CONFIG_DRM_AMDGPU_CIK
6440 case CHIP_POLARIS10:
6441 case CHIP_POLARIS11:
6442 case CHIP_POLARIS12:
6446 /* chips with display hardware */
6450 if (!amdgpu_ip_version(adev, DCE_HWIP, 0) ||
6451 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6457 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
6458 uint32_t inst, uint32_t reg_addr, char reg_name[],
6459 uint32_t expected_value, uint32_t mask)
6463 uint32_t tmp_ = RREG32(reg_addr);
6464 uint32_t loop = adev->usec_timeout;
6466 while ((tmp_ & (mask)) != (expected_value)) {
6468 loop = adev->usec_timeout;
6472 tmp_ = RREG32(reg_addr);
6475 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",
6476 inst, reg_name, (uint32_t)expected_value,
6477 (uint32_t)(tmp_ & (mask)));