drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/power_supply.h>
  29 #include <linux/kthread.h>
  30 #include <linux/module.h>
  31 #include <linux/console.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_probe_helper.h>
  36 #include <drm/amdgpu_drm.h>
  37 #include <linux/vgaarb.h>
  38 #include <linux/vga_switcheroo.h>
  39 #include <linux/efi.h>
  40 #include "amdgpu.h"
  41 #include "amdgpu_trace.h"
  42 #include "amdgpu_i2c.h"
  43 #include "atom.h"
  44 #include "amdgpu_atombios.h"
  45 #include "amdgpu_atomfirmware.h"
  46 #include "amd_pcie.h"
  47 #ifdef CONFIG_DRM_AMDGPU_SI
  48 #include "si.h"
  49 #endif
  50 #ifdef CONFIG_DRM_AMDGPU_CIK
  51 #include "cik.h"
  52 #endif
  53 #include "vi.h"
  54 #include "soc15.h"
  55 #include "nv.h"
  56 #include "bif/bif_4_1_d.h"
  57 #include <linux/pci.h>
  58 #include <linux/firmware.h>
  59 #include "amdgpu_vf_error.h"
  60
  61 #include "amdgpu_amdkfd.h"
  62 #include "amdgpu_pm.h"
  63
  64 #include "amdgpu_xgmi.h"
  65 #include "amdgpu_ras.h"
  66 #include "amdgpu_pmu.h"
  67
  68 #include <linux/suspend.h>
  69
  70 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  71 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
  72 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  73 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
  74 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
  75 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
  76 MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
  77 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
  78 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
  79 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
  80
  81 #define AMDGPU_RESUME_MS                2000
  82
  83 const char *amdgpu_asic_name[] = {
  84         "TAHITI",
  85         "PITCAIRN",
  86         "VERDE",
  87         "OLAND",
  88         "HAINAN",
  89         "BONAIRE",
  90         "KAVERI",
  91         "KABINI",
  92         "HAWAII",
  93         "MULLINS",
  94         "TOPAZ",
  95         "TONGA",
  96         "FIJI",
  97         "CARRIZO",
  98         "STONEY",
  99         "POLARIS10",
 100         "POLARIS11",
 101         "POLARIS12",
 102         "VEGAM",
 103         "VEGA10",
 104         "VEGA12",
 105         "VEGA20",
 106         "RAVEN",
 107         "ARCTURUS",
 108         "RENOIR",
 109         "NAVI10",
 110         "NAVI14",
 111         "NAVI12",
 112         "LAST",
 113 };
 114
 115 /**
 116  * DOC: pcie_replay_count
 117  *
 118  * The amdgpu driver provides a sysfs API for reporting the total number
 119  * of PCIe replays (NAKs)
 120  * The file pcie_replay_count is used for this and returns the total
 121  * number of replays as a sum of the NAKs generated and NAKs received
 122  */
 123
 124 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
 125                 struct device_attribute *attr, char *buf)
 126 {
 127         struct drm_device *ddev = dev_get_drvdata(dev);
 128         struct amdgpu_device *adev = ddev->dev_private;
 129         uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
 130
 131         return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
 132 }
 133
 134 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
 135                 amdgpu_device_get_pcie_replay_count, NULL);
 136
 137 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 138
 139 /**
 140  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
 141  *
 142  * @dev: drm_device pointer
 143  *
 144  * Returns true if the device is a dGPU with HG/PX power control,
 145  * otherwise return false.
 146  */
 147 bool amdgpu_device_is_px(struct drm_device *dev)
 148 {
 149         struct amdgpu_device *adev = dev->dev_private;
 150
 151         if (adev->flags & AMD_IS_PX)
 152                 return true;
 153         return false;
 154 }
 155
 156 /**
 157  * VRAM access helper functions.
 158  *
 159  * amdgpu_device_vram_access - read/write a buffer in vram
 160  *
 161  * @adev: amdgpu_device pointer
 162  * @pos: offset of the buffer in vram
 163  * @buf: virtual address of the buffer in system memory
 164  * @size: read/write size, sizeof(@buf) must > @size
 165  * @write: true - write to vram, otherwise - read from vram
 166  */
 167 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
 168                                uint32_t *buf, size_t size, bool write)
 169 {
 170         uint64_t last;
 171         unsigned long flags;
 172
 173         last = size - 4;
 174         for (last += pos; pos <= last; pos += 4) {
 175                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 176                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
 177                 WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
 178                 if (write)
 179                         WREG32_NO_KIQ(mmMM_DATA, *buf++);
 180                 else
 181                         *buf++ = RREG32_NO_KIQ(mmMM_DATA);
 182                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 183         }
 184 }
 185
 186 /*
 187  * MMIO register access helper functions.
 188  */
 189 /**
 190  * amdgpu_mm_rreg - read a memory mapped IO register
 191  *
 192  * @adev: amdgpu_device pointer
 193  * @reg: dword aligned register offset
 194  * @acc_flags: access flags which require special behavior
 195  *
 196  * Returns the 32 bit value from the offset specified.
 197  */
 198 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 199                         uint32_t acc_flags)
 200 {
 201         uint32_t ret;
 202
 203         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 204                 return amdgpu_virt_kiq_rreg(adev, reg);
 205
 206         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 207                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 208         else {
 209                 unsigned long flags;
 210
 211                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 212                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 213                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 214                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 215         }
 216         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 217         return ret;
 218 }
 219
 220 /*
 221  * MMIO register read with bytes helper functions
 222  * @offset:bytes offset from MMIO start
 223  *
 224 */
 225
 226 /**
 227  * amdgpu_mm_rreg8 - read a memory mapped IO register
 228  *
 229  * @adev: amdgpu_device pointer
 230  * @offset: byte aligned register offset
 231  *
 232  * Returns the 8 bit value from the offset specified.
 233  */
 234 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 235         if (offset < adev->rmmio_size)
 236                 return (readb(adev->rmmio + offset));
 237         BUG();
 238 }
 239
 240 /*
 241  * MMIO register write with bytes helper functions
 242  * @offset:bytes offset from MMIO start
 243  * @value: the value want to be written to the register
 244  *
 245 */
 246 /**
 247  * amdgpu_mm_wreg8 - read a memory mapped IO register
 248  *
 249  * @adev: amdgpu_device pointer
 250  * @offset: byte aligned register offset
 251  * @value: 8 bit value to write
 252  *
 253  * Writes the value specified to the offset specified.
 254  */
 255 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 256         if (offset < adev->rmmio_size)
 257                 writeb(value, adev->rmmio + offset);
 258         else
 259                 BUG();
 260 }
 261
 262 /**
 263  * amdgpu_mm_wreg - write to a memory mapped IO register
 264  *
 265  * @adev: amdgpu_device pointer
 266  * @reg: dword aligned register offset
 267  * @v: 32 bit value to write to the register
 268  * @acc_flags: access flags which require special behavior
 269  *
 270  * Writes the value specified to the offset specified.
 271  */
 272 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 273                     uint32_t acc_flags)
 274 {
 275         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 276
 277         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 278                 adev->last_mm_index = v;
 279         }
 280
 281         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 282                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 283
 284         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 285                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 286         else {
 287                 unsigned long flags;
 288
 289                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 290                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 291                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 292                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 293         }
 294
 295         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 296                 udelay(500);
 297         }
 298 }
 299
 300 /**
 301  * amdgpu_io_rreg - read an IO register
 302  *
 303  * @adev: amdgpu_device pointer
 304  * @reg: dword aligned register offset
 305  *
 306  * Returns the 32 bit value from the offset specified.
 307  */
 308 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 309 {
 310         if ((reg * 4) < adev->rio_mem_size)
 311                 return ioread32(adev->rio_mem + (reg * 4));
 312         else {
 313                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 314                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 315         }
 316 }
 317
 318 /**
 319  * amdgpu_io_wreg - write to an IO register
 320  *
 321  * @adev: amdgpu_device pointer
 322  * @reg: dword aligned register offset
 323  * @v: 32 bit value to write to the register
 324  *
 325  * Writes the value specified to the offset specified.
 326  */
 327 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 328 {
 329         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 330                 adev->last_mm_index = v;
 331         }
 332
 333         if ((reg * 4) < adev->rio_mem_size)
 334                 iowrite32(v, adev->rio_mem + (reg * 4));
 335         else {
 336                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 337                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 338         }
 339
 340         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 341                 udelay(500);
 342         }
 343 }
 344
 345 /**
 346  * amdgpu_mm_rdoorbell - read a doorbell dword
 347  *
 348  * @adev: amdgpu_device pointer
 349  * @index: doorbell index
 350  *
 351  * Returns the value in the doorbell aperture at the
 352  * requested doorbell index (CIK).
 353  */
 354 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 355 {
 356         if (index < adev->doorbell.num_doorbells) {
 357                 return readl(adev->doorbell.ptr + index);
 358         } else {
 359                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 360                 return 0;
 361         }
 362 }
 363
 364 /**
 365  * amdgpu_mm_wdoorbell - write a doorbell dword
 366  *
 367  * @adev: amdgpu_device pointer
 368  * @index: doorbell index
 369  * @v: value to write
 370  *
 371  * Writes @v to the doorbell aperture at the
 372  * requested doorbell index (CIK).
 373  */
 374 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 375 {
 376         if (index < adev->doorbell.num_doorbells) {
 377                 writel(v, adev->doorbell.ptr + index);
 378         } else {
 379                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 380         }
 381 }
 382
 383 /**
 384  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 385  *
 386  * @adev: amdgpu_device pointer
 387  * @index: doorbell index
 388  *
 389  * Returns the value in the doorbell aperture at the
 390  * requested doorbell index (VEGA10+).
 391  */
 392 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 393 {
 394         if (index < adev->doorbell.num_doorbells) {
 395                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 396         } else {
 397                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 398                 return 0;
 399         }
 400 }
 401
 402 /**
 403  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 404  *
 405  * @adev: amdgpu_device pointer
 406  * @index: doorbell index
 407  * @v: value to write
 408  *
 409  * Writes @v to the doorbell aperture at the
 410  * requested doorbell index (VEGA10+).
 411  */
 412 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 413 {
 414         if (index < adev->doorbell.num_doorbells) {
 415                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 416         } else {
 417                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 418         }
 419 }
 420
 421 /**
 422  * amdgpu_invalid_rreg - dummy reg read function
 423  *
 424  * @adev: amdgpu device pointer
 425  * @reg: offset of register
 426  *
 427  * Dummy register read function.  Used for register blocks
 428  * that certain asics don't have (all asics).
 429  * Returns the value in the register.
 430  */
 431 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 432 {
 433         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 434         BUG();
 435         return 0;
 436 }
 437
 438 /**
 439  * amdgpu_invalid_wreg - dummy reg write function
 440  *
 441  * @adev: amdgpu device pointer
 442  * @reg: offset of register
 443  * @v: value to write to the register
 444  *
 445  * Dummy register read function.  Used for register blocks
 446  * that certain asics don't have (all asics).
 447  */
 448 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 449 {
 450         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 451                   reg, v);
 452         BUG();
 453 }
 454
 455 /**
 456  * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
 457  *
 458  * @adev: amdgpu device pointer
 459  * @reg: offset of register
 460  *
 461  * Dummy register read function.  Used for register blocks
 462  * that certain asics don't have (all asics).
 463  * Returns the value in the register.
 464  */
 465 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
 466 {
 467         DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
 468         BUG();
 469         return 0;
 470 }
 471
 472 /**
 473  * amdgpu_invalid_wreg64 - dummy reg write function
 474  *
 475  * @adev: amdgpu device pointer
 476  * @reg: offset of register
 477  * @v: value to write to the register
 478  *
 479  * Dummy register read function.  Used for register blocks
 480  * that certain asics don't have (all asics).
 481  */
 482 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
 483 {
 484         DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
 485                   reg, v);
 486         BUG();
 487 }
 488
 489 /**
 490  * amdgpu_block_invalid_rreg - dummy reg read function
 491  *
 492  * @adev: amdgpu device pointer
 493  * @block: offset of instance
 494  * @reg: offset of register
 495  *
 496  * Dummy register read function.  Used for register blocks
 497  * that certain asics don't have (all asics).
 498  * Returns the value in the register.
 499  */
 500 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 501                                           uint32_t block, uint32_t reg)
 502 {
 503         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 504                   reg, block);
 505         BUG();
 506         return 0;
 507 }
 508
 509 /**
 510  * amdgpu_block_invalid_wreg - dummy reg write function
 511  *
 512  * @adev: amdgpu device pointer
 513  * @block: offset of instance
 514  * @reg: offset of register
 515  * @v: value to write to the register
 516  *
 517  * Dummy register read function.  Used for register blocks
 518  * that certain asics don't have (all asics).
 519  */
 520 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 521                                       uint32_t block,
 522                                       uint32_t reg, uint32_t v)
 523 {
 524         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 525                   reg, block, v);
 526         BUG();
 527 }
 528
 529 /**
 530  * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
 531  *
 532  * @adev: amdgpu device pointer
 533  *
 534  * Allocates a scratch page of VRAM for use by various things in the
 535  * driver.
 536  */
 537 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 538 {
 539         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 540                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 541                                        &adev->vram_scratch.robj,
 542                                        &adev->vram_scratch.gpu_addr,
 543                                        (void **)&adev->vram_scratch.ptr);
 544 }
 545
 546 /**
 547  * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
 548  *
 549  * @adev: amdgpu device pointer
 550  *
 551  * Frees the VRAM scratch page.
 552  */
 553 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 554 {
 555         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 556 }
 557
 558 /**
 559  * amdgpu_device_program_register_sequence - program an array of registers.
 560  *
 561  * @adev: amdgpu_device pointer
 562  * @registers: pointer to the register array
 563  * @array_size: size of the register array
 564  *
 565  * Programs an array or registers with and and or masks.
 566  * This is a helper for setting golden registers.
 567  */
 568 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 569                                              const u32 *registers,
 570                                              const u32 array_size)
 571 {
 572         u32 tmp, reg, and_mask, or_mask;
 573         int i;
 574
 575         if (array_size % 3)
 576                 return;
 577
 578         for (i = 0; i < array_size; i +=3) {
 579                 reg = registers[i + 0];
 580                 and_mask = registers[i + 1];
 581                 or_mask = registers[i + 2];
 582
 583                 if (and_mask == 0xffffffff) {
 584                         tmp = or_mask;
 585                 } else {
 586                         tmp = RREG32(reg);
 587                         tmp &= ~and_mask;
 588                         if (adev->family >= AMDGPU_FAMILY_AI)
 589                                 tmp |= (or_mask & and_mask);
 590                         else
 591                                 tmp |= or_mask;
 592                 }
 593                 WREG32(reg, tmp);
 594         }
 595 }
 596
 597 /**
 598  * amdgpu_device_pci_config_reset - reset the GPU
 599  *
 600  * @adev: amdgpu_device pointer
 601  *
 602  * Resets the GPU using the pci config reset sequence.
 603  * Only applicable to asics prior to vega10.
 604  */
 605 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 606 {
 607         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 608 }
 609
 610 /*
 611  * GPU doorbell aperture helpers function.
 612  */
 613 /**
 614  * amdgpu_device_doorbell_init - Init doorbell driver information.
 615  *
 616  * @adev: amdgpu_device pointer
 617  *
 618  * Init doorbell driver information (CIK)
 619  * Returns 0 on success, error on failure.
 620  */
 621 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 622 {
 623
 624         /* No doorbell on SI hardware generation */
 625         if (adev->asic_type < CHIP_BONAIRE) {
 626                 adev->doorbell.base = 0;
 627                 adev->doorbell.size = 0;
 628                 adev->doorbell.num_doorbells = 0;
 629                 adev->doorbell.ptr = NULL;
 630                 return 0;
 631         }
 632
 633         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 634                 return -EINVAL;
 635
 636         amdgpu_asic_init_doorbell_index(adev);
 637
 638         /* doorbell bar mapping */
 639         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 640         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 641
 642         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 643                                              adev->doorbell_index.max_assignment+1);
 644         if (adev->doorbell.num_doorbells == 0)
 645                 return -EINVAL;
 646
 647         /* For Vega, reserve and map two pages on doorbell BAR since SDMA
 648          * paging queue doorbell use the second page. The
 649          * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
 650          * doorbells are in the first page. So with paging queue enabled,
 651          * the max num_doorbells should + 1 page (0x400 in dword)
 652          */
 653         if (adev->asic_type >= CHIP_VEGA10)
 654                 adev->doorbell.num_doorbells += 0x400;
 655
 656         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 657                                      adev->doorbell.num_doorbells *
 658                                      sizeof(u32));
 659         if (adev->doorbell.ptr == NULL)
 660                 return -ENOMEM;
 661
 662         return 0;
 663 }
 664
 665 /**
 666  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 667  *
 668  * @adev: amdgpu_device pointer
 669  *
 670  * Tear down doorbell driver information (CIK)
 671  */
 672 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 673 {
 674         iounmap(adev->doorbell.ptr);
 675         adev->doorbell.ptr = NULL;
 676 }
 677
 678
 679
 680 /*
 681  * amdgpu_device_wb_*()
 682  * Writeback is the method by which the GPU updates special pages in memory
 683  * with the status of certain GPU events (fences, ring pointers,etc.).
 684  */
 685
 686 /**
 687  * amdgpu_device_wb_fini - Disable Writeback and free memory
 688  *
 689  * @adev: amdgpu_device pointer
 690  *
 691  * Disables Writeback and frees the Writeback memory (all asics).
 692  * Used at driver shutdown.
 693  */
 694 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 695 {
 696         if (adev->wb.wb_obj) {
 697                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 698                                       &adev->wb.gpu_addr,
 699                                       (void **)&adev->wb.wb);
 700                 adev->wb.wb_obj = NULL;
 701         }
 702 }
 703
 704 /**
 705  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 706  *
 707  * @adev: amdgpu_device pointer
 708  *
 709  * Initializes writeback and allocates writeback memory (all asics).
 710  * Used at driver startup.
 711  * Returns 0 on success or an -error on failure.
 712  */
 713 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 714 {
 715         int r;
 716
 717         if (adev->wb.wb_obj == NULL) {
 718                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 719                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 720                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 721                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 722                                             (void **)&adev->wb.wb);
 723                 if (r) {
 724                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 725                         return r;
 726                 }
 727
 728                 adev->wb.num_wb = AMDGPU_MAX_WB;
 729                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 730
 731                 /* clear wb memory */
 732                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
 733         }
 734
 735         return 0;
 736 }
 737
 738 /**
 739  * amdgpu_device_wb_get - Allocate a wb entry
 740  *
 741  * @adev: amdgpu_device pointer
 742  * @wb: wb index
 743  *
 744  * Allocate a wb slot for use by the driver (all asics).
 745  * Returns 0 on success or -EINVAL on failure.
 746  */
 747 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 748 {
 749         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 750
 751         if (offset < adev->wb.num_wb) {
 752                 __set_bit(offset, adev->wb.used);
 753                 *wb = offset << 3; /* convert to dw offset */
 754                 return 0;
 755         } else {
 756                 return -EINVAL;
 757         }
 758 }
 759
 760 /**
 761  * amdgpu_device_wb_free - Free a wb entry
 762  *
 763  * @adev: amdgpu_device pointer
 764  * @wb: wb index
 765  *
 766  * Free a wb slot allocated for use by the driver (all asics)
 767  */
 768 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 769 {
 770         wb >>= 3;
 771         if (wb < adev->wb.num_wb)
 772                 __clear_bit(wb, adev->wb.used);
 773 }
 774
 775 /**
 776  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 777  *
 778  * @adev: amdgpu_device pointer
 779  *
 780  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 781  * to fail, but if any of the BARs is not accessible after the size we abort
 782  * driver loading by returning -ENODEV.
 783  */
 784 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 785 {
 786         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 787         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 788         struct pci_bus *root;
 789         struct resource *res;
 790         unsigned i;
 791         u16 cmd;
 792         int r;
 793
 794         /* Bypass for VF */
 795         if (amdgpu_sriov_vf(adev))
 796                 return 0;
 797
 798         /* Check if the root BUS has 64bit memory resources */
 799         root = adev->pdev->bus;
 800         while (root->parent)
 801                 root = root->parent;
 802
 803         pci_bus_for_each_resource(root, res, i) {
 804                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 805                     res->start > 0x100000000ull)
 806                         break;
 807         }
 808
 809         /* Trying to resize is pointless without a root hub window above 4GB */
 810         if (!res)
 811                 return 0;
 812
 813         /* Disable memory decoding while we change the BAR addresses and size */
 814         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 815         pci_write_config_word(adev->pdev, PCI_COMMAND,
 816                               cmd & ~PCI_COMMAND_MEMORY);
 817
 818         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 819         amdgpu_device_doorbell_fini(adev);
 820         if (adev->asic_type >= CHIP_BONAIRE)
 821                 pci_release_resource(adev->pdev, 2);
 822
 823         pci_release_resource(adev->pdev, 0);
 824
 825         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 826         if (r == -ENOSPC)
 827                 DRM_INFO("Not enough PCI address space for a large BAR.");
 828         else if (r && r != -ENOTSUPP)
 829                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 830
 831         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 832
 833         /* When the doorbell or fb BAR isn't available we have no chance of
 834          * using the device.
 835          */
 836         r = amdgpu_device_doorbell_init(adev);
 837         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 838                 return -ENODEV;
 839
 840         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 841
 842         return 0;
 843 }
 844
 845 /*
 846  * GPU helpers function.
 847  */
 848 /**
 849  * amdgpu_device_need_post - check if the hw need post or not
 850  *
 851  * @adev: amdgpu_device pointer
 852  *
 853  * Check if the asic has been initialized (all asics) at driver startup
 854  * or post is needed if  hw reset is performed.
 855  * Returns true if need or false if not.
 856  */
 857 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 858 {
 859         uint32_t reg;
 860
 861         if (amdgpu_sriov_vf(adev))
 862                 return false;
 863
 864         if (amdgpu_passthrough(adev)) {
 865                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 866                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 867                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 868                  * vpost executed for smc version below 22.15
 869                  */
 870                 if (adev->asic_type == CHIP_FIJI) {
 871                         int err;
 872                         uint32_t fw_ver;
 873                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 874                         /* force vPost if error occured */
 875                         if (err)
 876                                 return true;
 877
 878                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 879                         if (fw_ver < 0x00160e00)
 880                                 return true;
 881                 }
 882         }
 883
 884         if (adev->has_hw_reset) {
 885                 adev->has_hw_reset = false;
 886                 return true;
 887         }
 888
 889         /* bios scratch used on CIK+ */
 890         if (adev->asic_type >= CHIP_BONAIRE)
 891                 return amdgpu_atombios_scratch_need_asic_init(adev);
 892
 893         /* check MEM_SIZE for older asics */
 894         reg = amdgpu_asic_get_config_memsize(adev);
 895
 896         if ((reg != 0) && (reg != 0xffffffff))
 897                 return false;
 898
 899         return true;
 900 }
 901
 902 /* if we get transitioned to only one device, take VGA back */
 903 /**
 904  * amdgpu_device_vga_set_decode - enable/disable vga decode
 905  *
 906  * @cookie: amdgpu_device pointer
 907  * @state: enable/disable vga decode
 908  *
 909  * Enable/disable vga decode (all asics).
 910  * Returns VGA resource flags.
 911  */
 912 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 913 {
 914         struct amdgpu_device *adev = cookie;
 915         amdgpu_asic_set_vga_state(adev, state);
 916         if (state)
 917                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 918                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 919         else
 920                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 921 }
 922
 923 /**
 924  * amdgpu_device_check_block_size - validate the vm block size
 925  *
 926  * @adev: amdgpu_device pointer
 927  *
 928  * Validates the vm block size specified via module parameter.
 929  * The vm block size defines number of bits in page table versus page directory,
 930  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 931  * page table and the remaining bits are in the page directory.
 932  */
 933 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 934 {
 935         /* defines number of bits in page table versus page directory,
 936          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 937          * page table and the remaining bits are in the page directory */
 938         if (amdgpu_vm_block_size == -1)
 939                 return;
 940
 941         if (amdgpu_vm_block_size < 9) {
 942                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 943                          amdgpu_vm_block_size);
 944                 amdgpu_vm_block_size = -1;
 945         }
 946 }
 947
 948 /**
 949  * amdgpu_device_check_vm_size - validate the vm size
 950  *
 951  * @adev: amdgpu_device pointer
 952  *
 953  * Validates the vm size in GB specified via module parameter.
 954  * The VM size is the size of the GPU virtual memory space in GB.
 955  */
 956 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 957 {
 958         /* no need to check the default value */
 959         if (amdgpu_vm_size == -1)
 960                 return;
 961
 962         if (amdgpu_vm_size < 1) {
 963                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 964                          amdgpu_vm_size);
 965                 amdgpu_vm_size = -1;
 966         }
 967 }
 968
 969 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
 970 {
 971         struct sysinfo si;
 972         bool is_os_64 = (sizeof(void *) == 8) ? true : false;
 973         uint64_t total_memory;
 974         uint64_t dram_size_seven_GB = 0x1B8000000;
 975         uint64_t dram_size_three_GB = 0xB8000000;
 976
 977         if (amdgpu_smu_memory_pool_size == 0)
 978                 return;
 979
 980         if (!is_os_64) {
 981                 DRM_WARN("Not 64-bit OS, feature not supported\n");
 982                 goto def_value;
 983         }
 984         si_meminfo(&si);
 985         total_memory = (uint64_t)si.totalram * si.mem_unit;
 986
 987         if ((amdgpu_smu_memory_pool_size == 1) ||
 988                 (amdgpu_smu_memory_pool_size == 2)) {
 989                 if (total_memory < dram_size_three_GB)
 990                         goto def_value1;
 991         } else if ((amdgpu_smu_memory_pool_size == 4) ||
 992                 (amdgpu_smu_memory_pool_size == 8)) {
 993                 if (total_memory < dram_size_seven_GB)
 994                         goto def_value1;
 995         } else {
 996                 DRM_WARN("Smu memory pool size not supported\n");
 997                 goto def_value;
 998         }
 999         adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1000
1001         return;
1002
1003 def_value1:
1004         DRM_WARN("No enough system memory\n");
1005 def_value:
1006         adev->pm.smu_prv_buffer_size = 0;
1007 }
1008
1009 /**
1010  * amdgpu_device_check_arguments - validate module params
1011  *
1012  * @adev: amdgpu_device pointer
1013  *
1014  * Validates certain module parameters and updates
1015  * the associated values used by the driver (all asics).
1016  */
1017 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1018 {
1019         int ret = 0;
1020
1021         if (amdgpu_sched_jobs < 4) {
1022                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1023                          amdgpu_sched_jobs);
1024                 amdgpu_sched_jobs = 4;
1025         } else if (!is_power_of_2(amdgpu_sched_jobs)){
1026                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1027                          amdgpu_sched_jobs);
1028                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1029         }
1030
1031         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1032                 /* gart size must be greater or equal to 32M */
1033                 dev_warn(adev->dev, "gart size (%d) too small\n",
1034                          amdgpu_gart_size);
1035                 amdgpu_gart_size = -1;
1036         }
1037
1038         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1039                 /* gtt size must be greater or equal to 32M */
1040                 dev_warn(adev->dev, "gtt size (%d) too small\n",
1041                                  amdgpu_gtt_size);
1042                 amdgpu_gtt_size = -1;
1043         }
1044
1045         /* valid range is between 4 and 9 inclusive */
1046         if (amdgpu_vm_fragment_size != -1 &&
1047             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1048                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1049                 amdgpu_vm_fragment_size = -1;
1050         }
1051
1052         amdgpu_device_check_smu_prv_buffer_size(adev);
1053
1054         amdgpu_device_check_vm_size(adev);
1055
1056         amdgpu_device_check_block_size(adev);
1057
1058         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1059
1060         return ret;
1061 }
1062
1063 /**
1064  * amdgpu_switcheroo_set_state - set switcheroo state
1065  *
1066  * @pdev: pci dev pointer
1067  * @state: vga_switcheroo state
1068  *
1069  * Callback for the switcheroo driver.  Suspends or resumes the
1070  * the asics before or after it is powered up using ACPI methods.
1071  */
1072 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1073 {
1074         struct drm_device *dev = pci_get_drvdata(pdev);
1075
1076         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1077                 return;
1078
1079         if (state == VGA_SWITCHEROO_ON) {
1080                 pr_info("amdgpu: switched on\n");
1081                 /* don't suspend or resume card normally */
1082                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1083
1084                 amdgpu_device_resume(dev, true, true);
1085
1086                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1087                 drm_kms_helper_poll_enable(dev);
1088         } else {
1089                 pr_info("amdgpu: switched off\n");
1090                 drm_kms_helper_poll_disable(dev);
1091                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1092                 amdgpu_device_suspend(dev, true, true);
1093                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1094         }
1095 }
1096
1097 /**
1098  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1099  *
1100  * @pdev: pci dev pointer
1101  *
1102  * Callback for the switcheroo driver.  Check of the switcheroo
1103  * state can be changed.
1104  * Returns true if the state can be changed, false if not.
1105  */
1106 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1107 {
1108         struct drm_device *dev = pci_get_drvdata(pdev);
1109
1110         /*
1111         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1112         * locking inversion with the driver load path. And the access here is
1113         * completely racy anyway. So don't bother with locking for now.
1114         */
1115         return dev->open_count == 0;
1116 }
1117
1118 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1119         .set_gpu_state = amdgpu_switcheroo_set_state,
1120         .reprobe = NULL,
1121         .can_switch = amdgpu_switcheroo_can_switch,
1122 };
1123
1124 /**
1125  * amdgpu_device_ip_set_clockgating_state - set the CG state
1126  *
1127  * @dev: amdgpu_device pointer
1128  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1129  * @state: clockgating state (gate or ungate)
1130  *
1131  * Sets the requested clockgating state for all instances of
1132  * the hardware IP specified.
1133  * Returns the error code from the last instance.
1134  */
1135 int amdgpu_device_ip_set_clockgating_state(void *dev,
1136                                            enum amd_ip_block_type block_type,
1137                                            enum amd_clockgating_state state)
1138 {
1139         struct amdgpu_device *adev = dev;
1140         int i, r = 0;
1141
1142         for (i = 0; i < adev->num_ip_blocks; i++) {
1143                 if (!adev->ip_blocks[i].status.valid)
1144                         continue;
1145                 if (adev->ip_blocks[i].version->type != block_type)
1146                         continue;
1147                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1148                         continue;
1149                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1150                         (void *)adev, state);
1151                 if (r)
1152                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1153                                   adev->ip_blocks[i].version->funcs->name, r);
1154         }
1155         return r;
1156 }
1157
1158 /**
1159  * amdgpu_device_ip_set_powergating_state - set the PG state
1160  *
1161  * @dev: amdgpu_device pointer
1162  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1163  * @state: powergating state (gate or ungate)
1164  *
1165  * Sets the requested powergating state for all instances of
1166  * the hardware IP specified.
1167  * Returns the error code from the last instance.
1168  */
1169 int amdgpu_device_ip_set_powergating_state(void *dev,
1170                                            enum amd_ip_block_type block_type,
1171                                            enum amd_powergating_state state)
1172 {
1173         struct amdgpu_device *adev = dev;
1174         int i, r = 0;
1175
1176         for (i = 0; i < adev->num_ip_blocks; i++) {
1177                 if (!adev->ip_blocks[i].status.valid)
1178                         continue;
1179                 if (adev->ip_blocks[i].version->type != block_type)
1180                         continue;
1181                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1182                         continue;
1183                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1184                         (void *)adev, state);
1185                 if (r)
1186                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1187                                   adev->ip_blocks[i].version->funcs->name, r);
1188         }
1189         return r;
1190 }
1191
1192 /**
1193  * amdgpu_device_ip_get_clockgating_state - get the CG state
1194  *
1195  * @adev: amdgpu_device pointer
1196  * @flags: clockgating feature flags
1197  *
1198  * Walks the list of IPs on the device and updates the clockgating
1199  * flags for each IP.
1200  * Updates @flags with the feature flags for each hardware IP where
1201  * clockgating is enabled.
1202  */
1203 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1204                                             u32 *flags)
1205 {
1206         int i;
1207
1208         for (i = 0; i < adev->num_ip_blocks; i++) {
1209                 if (!adev->ip_blocks[i].status.valid)
1210                         continue;
1211                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1212                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1213         }
1214 }
1215
1216 /**
1217  * amdgpu_device_ip_wait_for_idle - wait for idle
1218  *
1219  * @adev: amdgpu_device pointer
1220  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1221  *
1222  * Waits for the request hardware IP to be idle.
1223  * Returns 0 for success or a negative error code on failure.
1224  */
1225 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1226                                    enum amd_ip_block_type block_type)
1227 {
1228         int i, r;
1229
1230         for (i = 0; i < adev->num_ip_blocks; i++) {
1231                 if (!adev->ip_blocks[i].status.valid)
1232                         continue;
1233                 if (adev->ip_blocks[i].version->type == block_type) {
1234                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1235                         if (r)
1236                                 return r;
1237                         break;
1238                 }
1239         }
1240         return 0;
1241
1242 }
1243
1244 /**
1245  * amdgpu_device_ip_is_idle - is the hardware IP idle
1246  *
1247  * @adev: amdgpu_device pointer
1248  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1249  *
1250  * Check if the hardware IP is idle or not.
1251  * Returns true if it the IP is idle, false if not.
1252  */
1253 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1254                               enum amd_ip_block_type block_type)
1255 {
1256         int i;
1257
1258         for (i = 0; i < adev->num_ip_blocks; i++) {
1259                 if (!adev->ip_blocks[i].status.valid)
1260                         continue;
1261                 if (adev->ip_blocks[i].version->type == block_type)
1262                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1263         }
1264         return true;
1265
1266 }
1267
1268 /**
1269  * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1270  *
1271  * @adev: amdgpu_device pointer
1272  * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1273  *
1274  * Returns a pointer to the hardware IP block structure
1275  * if it exists for the asic, otherwise NULL.
1276  */
1277 struct amdgpu_ip_block *
1278 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1279                               enum amd_ip_block_type type)
1280 {
1281         int i;
1282
1283         for (i = 0; i < adev->num_ip_blocks; i++)
1284                 if (adev->ip_blocks[i].version->type == type)
1285                         return &adev->ip_blocks[i];
1286
1287         return NULL;
1288 }
1289
1290 /**
1291  * amdgpu_device_ip_block_version_cmp
1292  *
1293  * @adev: amdgpu_device pointer
1294  * @type: enum amd_ip_block_type
1295  * @major: major version
1296  * @minor: minor version
1297  *
1298  * return 0 if equal or greater
1299  * return 1 if smaller or the ip_block doesn't exist
1300  */
1301 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1302                                        enum amd_ip_block_type type,
1303                                        u32 major, u32 minor)
1304 {
1305         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1306
1307         if (ip_block && ((ip_block->version->major > major) ||
1308                         ((ip_block->version->major == major) &&
1309                         (ip_block->version->minor >= minor))))
1310                 return 0;
1311
1312         return 1;
1313 }
1314
1315 /**
1316  * amdgpu_device_ip_block_add
1317  *
1318  * @adev: amdgpu_device pointer
1319  * @ip_block_version: pointer to the IP to add
1320  *
1321  * Adds the IP block driver information to the collection of IPs
1322  * on the asic.
1323  */
1324 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1325                                const struct amdgpu_ip_block_version *ip_block_version)
1326 {
1327         if (!ip_block_version)
1328                 return -EINVAL;
1329
1330         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1331                   ip_block_version->funcs->name);
1332
1333         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1334
1335         return 0;
1336 }
1337
1338 /**
1339  * amdgpu_device_enable_virtual_display - enable virtual display feature
1340  *
1341  * @adev: amdgpu_device pointer
1342  *
1343  * Enabled the virtual display feature if the user has enabled it via
1344  * the module parameter virtual_display.  This feature provides a virtual
1345  * display hardware on headless boards or in virtualized environments.
1346  * This function parses and validates the configuration string specified by
1347  * the user and configues the virtual display configuration (number of
1348  * virtual connectors, crtcs, etc.) specified.
1349  */
1350 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1351 {
1352         adev->enable_virtual_display = false;
1353
1354         if (amdgpu_virtual_display) {
1355                 struct drm_device *ddev = adev->ddev;
1356                 const char *pci_address_name = pci_name(ddev->pdev);
1357                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1358
1359                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1360                 pciaddstr_tmp = pciaddstr;
1361                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1362                         pciaddname = strsep(&pciaddname_tmp, ",");
1363                         if (!strcmp("all", pciaddname)
1364                             || !strcmp(pci_address_name, pciaddname)) {
1365                                 long num_crtc;
1366                                 int res = -1;
1367
1368                                 adev->enable_virtual_display = true;
1369
1370                                 if (pciaddname_tmp)
1371                                         res = kstrtol(pciaddname_tmp, 10,
1372                                                       &num_crtc);
1373
1374                                 if (!res) {
1375                                         if (num_crtc < 1)
1376                                                 num_crtc = 1;
1377                                         if (num_crtc > 6)
1378                                                 num_crtc = 6;
1379                                         adev->mode_info.num_crtc = num_crtc;
1380                                 } else {
1381                                         adev->mode_info.num_crtc = 1;
1382                                 }
1383                                 break;
1384                         }
1385                 }
1386
1387                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1388                          amdgpu_virtual_display, pci_address_name,
1389                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1390
1391                 kfree(pciaddstr);
1392         }
1393 }
1394
1395 /**
1396  * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1397  *
1398  * @adev: amdgpu_device pointer
1399  *
1400  * Parses the asic configuration parameters specified in the gpu info
1401  * firmware and makes them availale to the driver for use in configuring
1402  * the asic.
1403  * Returns 0 on success, -EINVAL on failure.
1404  */
1405 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1406 {
1407         const char *chip_name;
1408         char fw_name[30];
1409         int err;
1410         const struct gpu_info_firmware_header_v1_0 *hdr;
1411
1412         adev->firmware.gpu_info_fw = NULL;
1413
1414         switch (adev->asic_type) {
1415         case CHIP_TOPAZ:
1416         case CHIP_TONGA:
1417         case CHIP_FIJI:
1418         case CHIP_POLARIS10:
1419         case CHIP_POLARIS11:
1420         case CHIP_POLARIS12:
1421         case CHIP_VEGAM:
1422         case CHIP_CARRIZO:
1423         case CHIP_STONEY:
1424 #ifdef CONFIG_DRM_AMDGPU_SI
1425         case CHIP_VERDE:
1426         case CHIP_TAHITI:
1427         case CHIP_PITCAIRN:
1428         case CHIP_OLAND:
1429         case CHIP_HAINAN:
1430 #endif
1431 #ifdef CONFIG_DRM_AMDGPU_CIK
1432         case CHIP_BONAIRE:
1433         case CHIP_HAWAII:
1434         case CHIP_KAVERI:
1435         case CHIP_KABINI:
1436         case CHIP_MULLINS:
1437 #endif
1438         case CHIP_VEGA20:
1439         default:
1440                 return 0;
1441         case CHIP_VEGA10:
1442                 chip_name = "vega10";
1443                 break;
1444         case CHIP_VEGA12:
1445                 chip_name = "vega12";
1446                 break;
1447         case CHIP_RAVEN:
1448                 if (adev->rev_id >= 8)
1449                         chip_name = "raven2";
1450                 else if (adev->pdev->device == 0x15d8)
1451                         chip_name = "picasso";
1452                 else
1453                         chip_name = "raven";
1454                 break;
1455         case CHIP_ARCTURUS:
1456                 chip_name = "arcturus";
1457                 break;
1458         case CHIP_RENOIR:
1459                 chip_name = "renoir";
1460                 break;
1461         case CHIP_NAVI10:
1462                 chip_name = "navi10";
1463                 break;
1464         case CHIP_NAVI14:
1465                 chip_name = "navi14";
1466                 break;
1467         case CHIP_NAVI12:
1468                 chip_name = "navi12";
1469                 break;
1470         }
1471
1472         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1473         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1474         if (err) {
1475                 dev_err(adev->dev,
1476                         "Failed to load gpu_info firmware \"%s\"\n",
1477                         fw_name);
1478                 goto out;
1479         }
1480         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1481         if (err) {
1482                 dev_err(adev->dev,
1483                         "Failed to validate gpu_info firmware \"%s\"\n",
1484                         fw_name);
1485                 goto out;
1486         }
1487
1488         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1489         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1490
1491         switch (hdr->version_major) {
1492         case 1:
1493         {
1494                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1495                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1496                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1497
1498                 if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
1499                         goto parse_soc_bounding_box;
1500
1501                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1502                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1503                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1504                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1505                 adev->gfx.config.max_texture_channel_caches =
1506                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1507                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1508                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1509                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1510                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1511                 adev->gfx.config.double_offchip_lds_buf =
1512                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1513                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1514                 adev->gfx.cu_info.max_waves_per_simd =
1515                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1516                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1517                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1518                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1519                 if (hdr->version_minor >= 1) {
1520                         const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1521                                 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1522                                                                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1523                         adev->gfx.config.num_sc_per_sh =
1524                                 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1525                         adev->gfx.config.num_packer_per_sc =
1526                                 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1527                 }
1528
1529 parse_soc_bounding_box:
1530                 /*
1531                  * soc bounding box info is not integrated in disocovery table,
1532                  * we always need to parse it from gpu info firmware.
1533                  */
1534                 if (hdr->version_minor == 2) {
1535                         const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1536                                 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1537                                                                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1538                         adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1539                 }
1540                 break;
1541         }
1542         default:
1543                 dev_err(adev->dev,
1544                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1545                 err = -EINVAL;
1546                 goto out;
1547         }
1548 out:
1549         return err;
1550 }
1551
1552 /**
1553  * amdgpu_device_ip_early_init - run early init for hardware IPs
1554  *
1555  * @adev: amdgpu_device pointer
1556  *
1557  * Early initialization pass for hardware IPs.  The hardware IPs that make
1558  * up each asic are discovered each IP's early_init callback is run.  This
1559  * is the first stage in initializing the asic.
1560  * Returns 0 on success, negative error code on failure.
1561  */
1562 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1563 {
1564         int i, r;
1565
1566         amdgpu_device_enable_virtual_display(adev);
1567
1568         switch (adev->asic_type) {
1569         case CHIP_TOPAZ:
1570         case CHIP_TONGA:
1571         case CHIP_FIJI:
1572         case CHIP_POLARIS10:
1573         case CHIP_POLARIS11:
1574         case CHIP_POLARIS12:
1575         case CHIP_VEGAM:
1576         case CHIP_CARRIZO:
1577         case CHIP_STONEY:
1578                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1579                         adev->family = AMDGPU_FAMILY_CZ;
1580                 else
1581                         adev->family = AMDGPU_FAMILY_VI;
1582
1583                 r = vi_set_ip_blocks(adev);
1584                 if (r)
1585                         return r;
1586                 break;
1587 #ifdef CONFIG_DRM_AMDGPU_SI
1588         case CHIP_VERDE:
1589         case CHIP_TAHITI:
1590         case CHIP_PITCAIRN:
1591         case CHIP_OLAND:
1592         case CHIP_HAINAN:
1593                 adev->family = AMDGPU_FAMILY_SI;
1594                 r = si_set_ip_blocks(adev);
1595                 if (r)
1596                         return r;
1597                 break;
1598 #endif
1599 #ifdef CONFIG_DRM_AMDGPU_CIK
1600         case CHIP_BONAIRE:
1601         case CHIP_HAWAII:
1602         case CHIP_KAVERI:
1603         case CHIP_KABINI:
1604         case CHIP_MULLINS:
1605                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1606                         adev->family = AMDGPU_FAMILY_CI;
1607                 else
1608                         adev->family = AMDGPU_FAMILY_KV;
1609
1610                 r = cik_set_ip_blocks(adev);
1611                 if (r)
1612                         return r;
1613                 break;
1614 #endif
1615         case CHIP_VEGA10:
1616         case CHIP_VEGA12:
1617         case CHIP_VEGA20:
1618         case CHIP_RAVEN:
1619         case CHIP_ARCTURUS:
1620         case CHIP_RENOIR:
1621                 if (adev->asic_type == CHIP_RAVEN ||
1622                     adev->asic_type == CHIP_RENOIR)
1623                         adev->family = AMDGPU_FAMILY_RV;
1624                 else
1625                         adev->family = AMDGPU_FAMILY_AI;
1626
1627                 r = soc15_set_ip_blocks(adev);
1628                 if (r)
1629                         return r;
1630                 break;
1631         case  CHIP_NAVI10:
1632         case  CHIP_NAVI14:
1633         case  CHIP_NAVI12:
1634                 adev->family = AMDGPU_FAMILY_NV;
1635
1636                 r = nv_set_ip_blocks(adev);
1637                 if (r)
1638                         return r;
1639                 break;
1640         default:
1641                 /* FIXME: not supported yet */
1642                 return -EINVAL;
1643         }
1644
1645         r = amdgpu_device_parse_gpu_info_fw(adev);
1646         if (r)
1647                 return r;
1648
1649         if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
1650                 amdgpu_discovery_get_gfx_info(adev);
1651
1652         amdgpu_amdkfd_device_probe(adev);
1653
1654         if (amdgpu_sriov_vf(adev)) {
1655                 r = amdgpu_virt_request_full_gpu(adev, true);
1656                 if (r)
1657                         return -EAGAIN;
1658         }
1659
1660         adev->pm.pp_feature = amdgpu_pp_feature_mask;
1661         if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
1662                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1663
1664         for (i = 0; i < adev->num_ip_blocks; i++) {
1665                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1666                         DRM_ERROR("disabled ip block: %d <%s>\n",
1667                                   i, adev->ip_blocks[i].version->funcs->name);
1668                         adev->ip_blocks[i].status.valid = false;
1669                 } else {
1670                         if (adev->ip_blocks[i].version->funcs->early_init) {
1671                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1672                                 if (r == -ENOENT) {
1673                                         adev->ip_blocks[i].status.valid = false;
1674                                 } else if (r) {
1675                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1676                                                   adev->ip_blocks[i].version->funcs->name, r);
1677                                         return r;
1678                                 } else {
1679                                         adev->ip_blocks[i].status.valid = true;
1680                                 }
1681                         } else {
1682                                 adev->ip_blocks[i].status.valid = true;
1683                         }
1684                 }
1685                 /* get the vbios after the asic_funcs are set up */
1686                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
1687                         /* Read BIOS */
1688                         if (!amdgpu_get_bios(adev))
1689                                 return -EINVAL;
1690
1691                         r = amdgpu_atombios_init(adev);
1692                         if (r) {
1693                                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1694                                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1695                                 return r;
1696                         }
1697                 }
1698         }
1699
1700         adev->cg_flags &= amdgpu_cg_mask;
1701         adev->pg_flags &= amdgpu_pg_mask;
1702
1703         return 0;
1704 }
1705
1706 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1707 {
1708         int i, r;
1709
1710         for (i = 0; i < adev->num_ip_blocks; i++) {
1711                 if (!adev->ip_blocks[i].status.sw)
1712                         continue;
1713                 if (adev->ip_blocks[i].status.hw)
1714                         continue;
1715                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1716                     (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
1717                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1718                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1719                         if (r) {
1720                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1721                                           adev->ip_blocks[i].version->funcs->name, r);
1722                                 return r;
1723                         }
1724                         adev->ip_blocks[i].status.hw = true;
1725                 }
1726         }
1727
1728         return 0;
1729 }
1730
1731 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1732 {
1733         int i, r;
1734
1735         for (i = 0; i < adev->num_ip_blocks; i++) {
1736                 if (!adev->ip_blocks[i].status.sw)
1737                         continue;
1738                 if (adev->ip_blocks[i].status.hw)
1739                         continue;
1740                 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1741                 if (r) {
1742                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1743                                   adev->ip_blocks[i].version->funcs->name, r);
1744                         return r;
1745                 }
1746                 adev->ip_blocks[i].status.hw = true;
1747         }
1748
1749         return 0;
1750 }
1751
1752 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1753 {
1754         int r = 0;
1755         int i;
1756         uint32_t smu_version;
1757
1758         if (adev->asic_type >= CHIP_VEGA10) {
1759                 for (i = 0; i < adev->num_ip_blocks; i++) {
1760                         if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
1761                                 continue;
1762
1763                         /* no need to do the fw loading again if already done*/
1764                         if (adev->ip_blocks[i].status.hw == true)
1765                                 break;
1766
1767                         if (adev->in_gpu_reset || adev->in_suspend) {
1768                                 r = adev->ip_blocks[i].version->funcs->resume(adev);
1769                                 if (r) {
1770                                         DRM_ERROR("resume of IP block <%s> failed %d\n",
1771                                                           adev->ip_blocks[i].version->funcs->name, r);
1772                                         return r;
1773                                 }
1774                         } else {
1775                                 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1776                                 if (r) {
1777                                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1778                                                           adev->ip_blocks[i].version->funcs->name, r);
1779                                         return r;
1780                                 }
1781                         }
1782
1783                         adev->ip_blocks[i].status.hw = true;
1784                         break;
1785                 }
1786         }
1787
1788         r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
1789
1790         return r;
1791 }
1792
1793 /**
1794  * amdgpu_device_ip_init - run init for hardware IPs
1795  *
1796  * @adev: amdgpu_device pointer
1797  *
1798  * Main initialization pass for hardware IPs.  The list of all the hardware
1799  * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1800  * are run.  sw_init initializes the software state associated with each IP
1801  * and hw_init initializes the hardware associated with each IP.
1802  * Returns 0 on success, negative error code on failure.
1803  */
1804 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1805 {
1806         int i, r;
1807
1808         r = amdgpu_ras_init(adev);
1809         if (r)
1810                 return r;
1811
1812         for (i = 0; i < adev->num_ip_blocks; i++) {
1813                 if (!adev->ip_blocks[i].status.valid)
1814                         continue;
1815                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1816                 if (r) {
1817                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1818                                   adev->ip_blocks[i].version->funcs->name, r);
1819                         goto init_failed;
1820                 }
1821                 adev->ip_blocks[i].status.sw = true;
1822
1823                 /* need to do gmc hw init early so we can allocate gpu mem */
1824                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1825                         r = amdgpu_device_vram_scratch_init(adev);
1826                         if (r) {
1827                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1828                                 goto init_failed;
1829                         }
1830                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1831                         if (r) {
1832                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1833                                 goto init_failed;
1834                         }
1835                         r = amdgpu_device_wb_init(adev);
1836                         if (r) {
1837                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1838                                 goto init_failed;
1839                         }
1840                         adev->ip_blocks[i].status.hw = true;
1841
1842                         /* right after GMC hw init, we create CSA */
1843                         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1844                                 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1845                                                                 AMDGPU_GEM_DOMAIN_VRAM,
1846                                                                 AMDGPU_CSA_SIZE);
1847                                 if (r) {
1848                                         DRM_ERROR("allocate CSA failed %d\n", r);
1849                                         goto init_failed;
1850                                 }
1851                         }
1852                 }
1853         }
1854
1855         r = amdgpu_ib_pool_init(adev);
1856         if (r) {
1857                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1858                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
1859                 goto init_failed;
1860         }
1861
1862         r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1863         if (r)
1864                 goto init_failed;
1865
1866         r = amdgpu_device_ip_hw_init_phase1(adev);
1867         if (r)
1868                 goto init_failed;
1869
1870         r = amdgpu_device_fw_loading(adev);
1871         if (r)
1872                 goto init_failed;
1873
1874         r = amdgpu_device_ip_hw_init_phase2(adev);
1875         if (r)
1876                 goto init_failed;
1877
1878         /*
1879          * retired pages will be loaded from eeprom and reserved here,
1880          * it should be called after amdgpu_device_ip_hw_init_phase2  since
1881          * for some ASICs the RAS EEPROM code relies on SMU fully functioning
1882          * for I2C communication which only true at this point.
1883          * recovery_init may fail, but it can free all resources allocated by
1884          * itself and its failure should not stop amdgpu init process.
1885          *
1886          * Note: theoretically, this should be called before all vram allocations
1887          * to protect retired page from abusing
1888          */
1889         amdgpu_ras_recovery_init(adev);
1890
1891         if (adev->gmc.xgmi.num_physical_nodes > 1)
1892                 amdgpu_xgmi_add_device(adev);
1893         amdgpu_amdkfd_device_init(adev);
1894
1895 init_failed:
1896         if (amdgpu_sriov_vf(adev)) {
1897                 if (!r)
1898                         amdgpu_virt_init_data_exchange(adev);
1899                 amdgpu_virt_release_full_gpu(adev, true);
1900         }
1901
1902         return r;
1903 }
1904
1905 /**
1906  * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1907  *
1908  * @adev: amdgpu_device pointer
1909  *
1910  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
1911  * this function before a GPU reset.  If the value is retained after a
1912  * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.
1913  */
1914 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1915 {
1916         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1917 }
1918
1919 /**
1920  * amdgpu_device_check_vram_lost - check if vram is valid
1921  *
1922  * @adev: amdgpu_device pointer
1923  *
1924  * Checks the reset magic value written to the gart pointer in VRAM.
1925  * The driver calls this after a GPU reset to see if the contents of
1926  * VRAM is lost or now.
1927  * returns true if vram is lost, false if not.
1928  */
1929 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1930 {
1931         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1932                         AMDGPU_RESET_MAGIC_NUM);
1933 }
1934
1935 /**
1936  * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1937  *
1938  * @adev: amdgpu_device pointer
1939  *
1940  * The list of all the hardware IPs that make up the asic is walked and the
1941  * set_clockgating_state callbacks are run.
1942  * Late initialization pass enabling clockgating for hardware IPs.
1943  * Fini or suspend, pass disabling clockgating for hardware IPs.
1944  * Returns 0 on success, negative error code on failure.
1945  */
1946
1947 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1948                                                 enum amd_clockgating_state state)
1949 {
1950         int i, j, r;
1951
1952         if (amdgpu_emu_mode == 1)
1953                 return 0;
1954
1955         for (j = 0; j < adev->num_ip_blocks; j++) {
1956                 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1957                 if (!adev->ip_blocks[i].status.late_initialized)
1958                         continue;
1959                 /* skip CG for VCE/UVD, it's handled specially */
1960                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1961                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1962                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1963                     adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1964                         /* enable clockgating to save power */
1965                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1966                                                                                      state);
1967                         if (r) {
1968                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1969                                           adev->ip_blocks[i].version->funcs->name, r);
1970                                 return r;
1971                         }
1972                 }
1973         }
1974
1975         return 0;
1976 }
1977
1978 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1979 {
1980         int i, j, r;
1981
1982         if (amdgpu_emu_mode == 1)
1983                 return 0;
1984
1985         for (j = 0; j < adev->num_ip_blocks; j++) {
1986                 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1987                 if (!adev->ip_blocks[i].status.late_initialized)
1988                         continue;
1989                 /* skip CG for VCE/UVD, it's handled specially */
1990                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1991                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1992                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1993                     adev->ip_blocks[i].version->funcs->set_powergating_state) {
1994                         /* enable powergating to save power */
1995                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1996                                                                                         state);
1997                         if (r) {
1998                                 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1999                                           adev->ip_blocks[i].version->funcs->name, r);
2000                                 return r;
2001                         }
2002                 }
2003         }
2004         return 0;
2005 }
2006
2007 static int amdgpu_device_enable_mgpu_fan_boost(void)
2008 {
2009         struct amdgpu_gpu_instance *gpu_ins;
2010         struct amdgpu_device *adev;
2011         int i, ret = 0;
2012
2013         mutex_lock(&mgpu_info.mutex);
2014
2015         /*
2016          * MGPU fan boost feature should be enabled
2017          * only when there are two or more dGPUs in
2018          * the system
2019          */
2020         if (mgpu_info.num_dgpu < 2)
2021                 goto out;
2022
2023         for (i = 0; i < mgpu_info.num_dgpu; i++) {
2024                 gpu_ins = &(mgpu_info.gpu_ins[i]);
2025                 adev = gpu_ins->adev;
2026                 if (!(adev->flags & AMD_IS_APU) &&
2027                     !gpu_ins->mgpu_fan_enabled &&
2028                     adev->powerplay.pp_funcs &&
2029                     adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
2030                         ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2031                         if (ret)
2032                                 break;
2033
2034                         gpu_ins->mgpu_fan_enabled = 1;
2035                 }
2036         }
2037
2038 out:
2039         mutex_unlock(&mgpu_info.mutex);
2040
2041         return ret;
2042 }
2043
2044 /**
2045  * amdgpu_device_ip_late_init - run late init for hardware IPs
2046  *
2047  * @adev: amdgpu_device pointer
2048  *
2049  * Late initialization pass for hardware IPs.  The list of all the hardware
2050  * IPs that make up the asic is walked and the late_init callbacks are run.
2051  * late_init covers any special initialization that an IP requires
2052  * after all of the have been initialized or something that needs to happen
2053  * late in the init process.
2054  * Returns 0 on success, negative error code on failure.
2055  */
2056 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2057 {
2058         struct amdgpu_gpu_instance *gpu_instance;
2059         int i = 0, r;
2060
2061         for (i = 0; i < adev->num_ip_blocks; i++) {
2062                 if (!adev->ip_blocks[i].status.hw)
2063                         continue;
2064                 if (adev->ip_blocks[i].version->funcs->late_init) {
2065                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2066                         if (r) {
2067                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2068                                           adev->ip_blocks[i].version->funcs->name, r);
2069                                 return r;
2070                         }
2071                 }
2072                 adev->ip_blocks[i].status.late_initialized = true;
2073         }
2074
2075         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2076         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2077
2078         amdgpu_device_fill_reset_magic(adev);
2079
2080         r = amdgpu_device_enable_mgpu_fan_boost();
2081         if (r)
2082                 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2083
2084
2085         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2086                 mutex_lock(&mgpu_info.mutex);
2087
2088                 /*
2089                  * Reset device p-state to low as this was booted with high.
2090                  *
2091                  * This should be performed only after all devices from the same
2092                  * hive get initialized.
2093                  *
2094                  * However, it's unknown how many device in the hive in advance.
2095                  * As this is counted one by one during devices initializations.
2096                  *
2097                  * So, we wait for all XGMI interlinked devices initialized.
2098                  * This may bring some delays as those devices may come from
2099                  * different hives. But that should be OK.
2100                  */
2101                 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2102                         for (i = 0; i < mgpu_info.num_gpu; i++) {
2103                                 gpu_instance = &(mgpu_info.gpu_ins[i]);
2104                                 if (gpu_instance->adev->flags & AMD_IS_APU)
2105                                         continue;
2106
2107                                 r = amdgpu_xgmi_set_pstate(gpu_instance->adev, 0);
2108                                 if (r) {
2109                                         DRM_ERROR("pstate setting failed (%d).\n", r);
2110                                         break;
2111                                 }
2112                         }
2113                 }
2114
2115                 mutex_unlock(&mgpu_info.mutex);
2116         }
2117
2118         return 0;
2119 }
2120
2121 /**
2122  * amdgpu_device_ip_fini - run fini for hardware IPs
2123  *
2124  * @adev: amdgpu_device pointer
2125  *
2126  * Main teardown pass for hardware IPs.  The list of all the hardware
2127  * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2128  * are run.  hw_fini tears down the hardware associated with each IP
2129  * and sw_fini tears down any software state associated with each IP.
2130  * Returns 0 on success, negative error code on failure.
2131  */
2132 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2133 {
2134         int i, r;
2135
2136         amdgpu_ras_pre_fini(adev);
2137
2138         if (adev->gmc.xgmi.num_physical_nodes > 1)
2139                 amdgpu_xgmi_remove_device(adev);
2140
2141         amdgpu_amdkfd_device_fini(adev);
2142
2143         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2144         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2145
2146         /* need to disable SMC first */
2147         for (i = 0; i < adev->num_ip_blocks; i++) {
2148                 if (!adev->ip_blocks[i].status.hw)
2149                         continue;
2150                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2151                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2152                         /* XXX handle errors */
2153                         if (r) {
2154                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2155                                           adev->ip_blocks[i].version->funcs->name, r);
2156                         }
2157                         adev->ip_blocks[i].status.hw = false;
2158                         break;
2159                 }
2160         }
2161
2162         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2163                 if (!adev->ip_blocks[i].status.hw)
2164                         continue;
2165
2166                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2167                 /* XXX handle errors */
2168                 if (r) {
2169                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2170                                   adev->ip_blocks[i].version->funcs->name, r);
2171                 }
2172
2173                 adev->ip_blocks[i].status.hw = false;
2174         }
2175
2176
2177         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2178                 if (!adev->ip_blocks[i].status.sw)
2179                         continue;
2180
2181                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2182                         amdgpu_ucode_free_bo(adev);
2183                         amdgpu_free_static_csa(&adev->virt.csa_obj);
2184                         amdgpu_device_wb_fini(adev);
2185                         amdgpu_device_vram_scratch_fini(adev);
2186                         amdgpu_ib_pool_fini(adev);
2187                 }
2188
2189                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2190                 /* XXX handle errors */
2191                 if (r) {
2192                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2193                                   adev->ip_blocks[i].version->funcs->name, r);
2194                 }
2195                 adev->ip_blocks[i].status.sw = false;
2196                 adev->ip_blocks[i].status.valid = false;
2197         }
2198
2199         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2200                 if (!adev->ip_blocks[i].status.late_initialized)
2201                         continue;
2202                 if (adev->ip_blocks[i].version->funcs->late_fini)
2203                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2204                 adev->ip_blocks[i].status.late_initialized = false;
2205         }
2206
2207         amdgpu_ras_fini(adev);
2208
2209         if (amdgpu_sriov_vf(adev))
2210                 if (amdgpu_virt_release_full_gpu(adev, false))
2211                         DRM_ERROR("failed to release exclusive mode on fini\n");
2212
2213         return 0;
2214 }
2215
2216 /**
2217  * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2218  *
2219  * @work: work_struct.
2220  */
2221 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2222 {
2223         struct amdgpu_device *adev =
2224                 container_of(work, struct amdgpu_device, delayed_init_work.work);
2225         int r;
2226
2227         r = amdgpu_ib_ring_tests(adev);
2228         if (r)
2229                 DRM_ERROR("ib ring test failed (%d).\n", r);
2230 }
2231
2232 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2233 {
2234         struct amdgpu_device *adev =
2235                 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2236
2237         mutex_lock(&adev->gfx.gfx_off_mutex);
2238         if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2239                 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2240                         adev->gfx.gfx_off_state = true;
2241         }
2242         mutex_unlock(&adev->gfx.gfx_off_mutex);
2243 }
2244
2245 /**
2246  * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2247  *
2248  * @adev: amdgpu_device pointer
2249  *
2250  * Main suspend function for hardware IPs.  The list of all the hardware
2251  * IPs that make up the asic is walked, clockgating is disabled and the
2252  * suspend callbacks are run.  suspend puts the hardware and software state
2253  * in each IP into a state suitable for suspend.
2254  * Returns 0 on success, negative error code on failure.
2255  */
2256 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2257 {
2258         int i, r;
2259
2260         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2261         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2262
2263         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2264                 if (!adev->ip_blocks[i].status.valid)
2265                         continue;
2266                 /* displays are handled separately */
2267                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2268                         /* XXX handle errors */
2269                         r = adev->ip_blocks[i].version->funcs->suspend(adev);
2270                         /* XXX handle errors */
2271                         if (r) {
2272                                 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2273                                           adev->ip_blocks[i].version->funcs->name, r);
2274                                 return r;
2275                         }
2276                         adev->ip_blocks[i].status.hw = false;
2277                 }
2278         }
2279
2280         return 0;
2281 }
2282
2283 /**
2284  * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2285  *
2286  * @adev: amdgpu_device pointer
2287  *
2288  * Main suspend function for hardware IPs.  The list of all the hardware
2289  * IPs that make up the asic is walked, clockgating is disabled and the
2290  * suspend callbacks are run.  suspend puts the hardware and software state
2291  * in each IP into a state suitable for suspend.
2292  * Returns 0 on success, negative error code on failure.
2293  */
2294 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2295 {
2296         int i, r;
2297
2298         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2299                 if (!adev->ip_blocks[i].status.valid)
2300                         continue;
2301                 /* displays are handled in phase1 */
2302                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2303                         continue;
2304                 /* PSP lost connection when err_event_athub occurs */
2305                 if (amdgpu_ras_intr_triggered() &&
2306                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2307                         adev->ip_blocks[i].status.hw = false;
2308                         continue;
2309                 }
2310                 /* XXX handle errors */
2311                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2312                 /* XXX handle errors */
2313                 if (r) {
2314                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
2315                                   adev->ip_blocks[i].version->funcs->name, r);
2316                 }
2317                 adev->ip_blocks[i].status.hw = false;
2318                 /* handle putting the SMC in the appropriate state */
2319                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2320                         if (is_support_sw_smu(adev)) {
2321                                 r = smu_set_mp1_state(&adev->smu, adev->mp1_state);
2322                         } else if (adev->powerplay.pp_funcs &&
2323                                            adev->powerplay.pp_funcs->set_mp1_state) {
2324                                 r = adev->powerplay.pp_funcs->set_mp1_state(
2325                                         adev->powerplay.pp_handle,
2326                                         adev->mp1_state);
2327                         }
2328                         if (r) {
2329                                 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2330                                           adev->mp1_state, r);
2331                                 return r;
2332                         }
2333                 }
2334
2335                 adev->ip_blocks[i].status.hw = false;
2336         }
2337
2338         return 0;
2339 }
2340
2341 /**
2342  * amdgpu_device_ip_suspend - run suspend for hardware IPs
2343  *
2344  * @adev: amdgpu_device pointer
2345  *
2346  * Main suspend function for hardware IPs.  The list of all the hardware
2347  * IPs that make up the asic is walked, clockgating is disabled and the
2348  * suspend callbacks are run.  suspend puts the hardware and software state
2349  * in each IP into a state suitable for suspend.
2350  * Returns 0 on success, negative error code on failure.
2351  */
2352 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2353 {
2354         int r;
2355
2356         if (amdgpu_sriov_vf(adev))
2357                 amdgpu_virt_request_full_gpu(adev, false);
2358
2359         r = amdgpu_device_ip_suspend_phase1(adev);
2360         if (r)
2361                 return r;
2362         r = amdgpu_device_ip_suspend_phase2(adev);
2363
2364         if (amdgpu_sriov_vf(adev))
2365                 amdgpu_virt_release_full_gpu(adev, false);
2366
2367         return r;
2368 }
2369
2370 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2371 {
2372         int i, r;
2373
2374         static enum amd_ip_block_type ip_order[] = {
2375                 AMD_IP_BLOCK_TYPE_GMC,
2376                 AMD_IP_BLOCK_TYPE_COMMON,
2377                 AMD_IP_BLOCK_TYPE_PSP,
2378                 AMD_IP_BLOCK_TYPE_IH,
2379         };
2380
2381         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2382                 int j;
2383                 struct amdgpu_ip_block *block;
2384
2385                 for (j = 0; j < adev->num_ip_blocks; j++) {
2386                         block = &adev->ip_blocks[j];
2387
2388                         block->status.hw = false;
2389                         if (block->version->type != ip_order[i] ||
2390                                 !block->status.valid)
2391                                 continue;
2392
2393                         r = block->version->funcs->hw_init(adev);
2394                         DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2395                         if (r)
2396                                 return r;
2397                         block->status.hw = true;
2398                 }
2399         }
2400
2401         return 0;
2402 }
2403
2404 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2405 {
2406         int i, r;
2407
2408         static enum amd_ip_block_type ip_order[] = {
2409                 AMD_IP_BLOCK_TYPE_SMC,
2410                 AMD_IP_BLOCK_TYPE_DCE,
2411                 AMD_IP_BLOCK_TYPE_GFX,
2412                 AMD_IP_BLOCK_TYPE_SDMA,
2413                 AMD_IP_BLOCK_TYPE_UVD,
2414                 AMD_IP_BLOCK_TYPE_VCE
2415         };
2416
2417         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2418                 int j;
2419                 struct amdgpu_ip_block *block;
2420
2421                 for (j = 0; j < adev->num_ip_blocks; j++) {
2422                         block = &adev->ip_blocks[j];
2423
2424                         if (block->version->type != ip_order[i] ||
2425                                 !block->status.valid ||
2426                                 block->status.hw)
2427                                 continue;
2428
2429                         r = block->version->funcs->hw_init(adev);
2430                         DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2431                         if (r)
2432                                 return r;
2433                         block->status.hw = true;
2434                 }
2435         }
2436
2437         return 0;
2438 }
2439
2440 /**
2441  * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2442  *
2443  * @adev: amdgpu_device pointer
2444  *
2445  * First resume function for hardware IPs.  The list of all the hardware
2446  * IPs that make up the asic is walked and the resume callbacks are run for
2447  * COMMON, GMC, and IH.  resume puts the hardware into a functional state
2448  * after a suspend and updates the software state as necessary.  This
2449  * function is also used for restoring the GPU after a GPU reset.
2450  * Returns 0 on success, negative error code on failure.
2451  */
2452 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2453 {
2454         int i, r;
2455
2456         for (i = 0; i < adev->num_ip_blocks; i++) {
2457                 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2458                         continue;
2459                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2460                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2461                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2462
2463                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2464                         if (r) {
2465                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2466                                           adev->ip_blocks[i].version->funcs->name, r);
2467                                 return r;
2468                         }
2469                         adev->ip_blocks[i].status.hw = true;
2470                 }
2471         }
2472
2473         return 0;
2474 }
2475
2476 /**
2477  * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2478  *
2479  * @adev: amdgpu_device pointer
2480  *
2481  * First resume function for hardware IPs.  The list of all the hardware
2482  * IPs that make up the asic is walked and the resume callbacks are run for
2483  * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a
2484  * functional state after a suspend and updates the software state as
2485  * necessary.  This function is also used for restoring the GPU after a GPU
2486  * reset.
2487  * Returns 0 on success, negative error code on failure.
2488  */
2489 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2490 {
2491         int i, r;
2492
2493         for (i = 0; i < adev->num_ip_blocks; i++) {
2494                 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2495                         continue;
2496                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2497                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2498                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2499                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2500                         continue;
2501                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2502                 if (r) {
2503                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2504                                   adev->ip_blocks[i].version->funcs->name, r);
2505                         return r;
2506                 }
2507                 adev->ip_blocks[i].status.hw = true;
2508         }
2509
2510         return 0;
2511 }
2512
2513 /**
2514  * amdgpu_device_ip_resume - run resume for hardware IPs
2515  *
2516  * @adev: amdgpu_device pointer
2517  *
2518  * Main resume function for hardware IPs.  The hardware IPs
2519  * are split into two resume functions because they are
2520  * are also used in in recovering from a GPU reset and some additional
2521  * steps need to be take between them.  In this case (S3/S4) they are
2522  * run sequentially.
2523  * Returns 0 on success, negative error code on failure.
2524  */
2525 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2526 {
2527         int r;
2528
2529         r = amdgpu_device_ip_resume_phase1(adev);
2530         if (r)
2531                 return r;
2532
2533         r = amdgpu_device_fw_loading(adev);
2534         if (r)
2535                 return r;
2536
2537         r = amdgpu_device_ip_resume_phase2(adev);
2538
2539         return r;
2540 }
2541
2542 /**
2543  * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2544  *
2545  * @adev: amdgpu_device pointer
2546  *
2547  * Query the VBIOS data tables to determine if the board supports SR-IOV.
2548  */
2549 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2550 {
2551         if (amdgpu_sriov_vf(adev)) {
2552                 if (adev->is_atom_fw) {
2553                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2554                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2555                 } else {
2556                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2557                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2558                 }
2559
2560                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2561                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2562         }
2563 }
2564
2565 /**
2566  * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2567  *
2568  * @asic_type: AMD asic type
2569  *
2570  * Check if there is DC (new modesetting infrastructre) support for an asic.
2571  * returns true if DC has support, false if not.
2572  */
2573 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2574 {
2575         switch (asic_type) {
2576 #if defined(CONFIG_DRM_AMD_DC)
2577         case CHIP_BONAIRE:
2578         case CHIP_KAVERI:
2579         case CHIP_KABINI:
2580         case CHIP_MULLINS:
2581                 /*
2582                  * We have systems in the wild with these ASICs that require
2583                  * LVDS and VGA support which is not supported with DC.
2584                  *
2585                  * Fallback to the non-DC driver here by default so as not to
2586                  * cause regressions.
2587                  */
2588                 return amdgpu_dc > 0;
2589         case CHIP_HAWAII:
2590         case CHIP_CARRIZO:
2591         case CHIP_STONEY:
2592         case CHIP_POLARIS10:
2593         case CHIP_POLARIS11:
2594         case CHIP_POLARIS12:
2595         case CHIP_VEGAM:
2596         case CHIP_TONGA:
2597         case CHIP_FIJI:
2598         case CHIP_VEGA10:
2599         case CHIP_VEGA12:
2600         case CHIP_VEGA20:
2601 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2602         case CHIP_RAVEN:
2603         case CHIP_NAVI10:
2604         case CHIP_NAVI14:
2605         case CHIP_NAVI12:
2606 #endif
2607 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2608         case CHIP_RENOIR:
2609 #endif
2610                 return amdgpu_dc != 0;
2611 #endif
2612         default:
2613                 return false;
2614         }
2615 }
2616
2617 /**
2618  * amdgpu_device_has_dc_support - check if dc is supported
2619  *
2620  * @adev: amdgpu_device_pointer
2621  *
2622  * Returns true for supported, false for not supported
2623  */
2624 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2625 {
2626         if (amdgpu_sriov_vf(adev))
2627                 return false;
2628
2629         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2630 }
2631
2632
2633 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2634 {
2635         struct amdgpu_device *adev =
2636                 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2637
2638         adev->asic_reset_res =  amdgpu_asic_reset(adev);
2639         if (adev->asic_reset_res)
2640                 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
2641                          adev->asic_reset_res, adev->ddev->unique);
2642 }
2643
2644 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
2645 {
2646         char *input = amdgpu_lockup_timeout;
2647         char *timeout_setting = NULL;
2648         int index = 0;
2649         long timeout;
2650         int ret = 0;
2651
2652         /*
2653          * By default timeout for non compute jobs is 10000.
2654          * And there is no timeout enforced on compute jobs.
2655          * In SR-IOV or passthrough mode, timeout for compute
2656          * jobs are 10000 by default.
2657          */
2658         adev->gfx_timeout = msecs_to_jiffies(10000);
2659         adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
2660         if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
2661                 adev->compute_timeout = adev->gfx_timeout;
2662         else
2663                 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
2664
2665         if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
2666                 while ((timeout_setting = strsep(&input, ",")) &&
2667                                 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
2668                         ret = kstrtol(timeout_setting, 0, &timeout);
2669                         if (ret)
2670                                 return ret;
2671
2672                         if (timeout == 0) {
2673                                 index++;
2674                                 continue;
2675                         } else if (timeout < 0) {
2676                                 timeout = MAX_SCHEDULE_TIMEOUT;
2677                         } else {
2678                                 timeout = msecs_to_jiffies(timeout);
2679                         }
2680
2681                         switch (index++) {
2682                         case 0:
2683                                 adev->gfx_timeout = timeout;
2684                                 break;
2685                         case 1:
2686                                 adev->compute_timeout = timeout;
2687                                 break;
2688                         case 2:
2689                                 adev->sdma_timeout = timeout;
2690                                 break;
2691                         case 3:
2692                                 adev->video_timeout = timeout;
2693                                 break;
2694                         default:
2695                                 break;
2696                         }
2697                 }
2698                 /*
2699                  * There is only one value specified and
2700                  * it should apply to all non-compute jobs.
2701                  */
2702                 if (index == 1) {
2703                         adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
2704                         if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
2705                                 adev->compute_timeout = adev->gfx_timeout;
2706                 }
2707         }
2708
2709         return ret;
2710 }
2711
2712 /**
2713  * amdgpu_device_init - initialize the driver
2714  *
2715  * @adev: amdgpu_device pointer
2716  * @ddev: drm dev pointer
2717  * @pdev: pci dev pointer
2718  * @flags: driver flags
2719  *
2720  * Initializes the driver info and hw (all asics).
2721  * Returns 0 for success or an error on failure.
2722  * Called at driver startup.
2723  */
2724 int amdgpu_device_init(struct amdgpu_device *adev,
2725                        struct drm_device *ddev,
2726                        struct pci_dev *pdev,
2727                        uint32_t flags)
2728 {
2729         int r, i;
2730         bool runtime = false;
2731         u32 max_MBps;
2732
2733         adev->shutdown = false;
2734         adev->dev = &pdev->dev;
2735         adev->ddev = ddev;
2736         adev->pdev = pdev;
2737         adev->flags = flags;
2738
2739         if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
2740                 adev->asic_type = amdgpu_force_asic_type;
2741         else
2742                 adev->asic_type = flags & AMD_ASIC_MASK;
2743
2744         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2745         if (amdgpu_emu_mode == 1)
2746                 adev->usec_timeout *= 2;
2747         adev->gmc.gart_size = 512 * 1024 * 1024;
2748         adev->accel_working = false;
2749         adev->num_rings = 0;
2750         adev->mman.buffer_funcs = NULL;
2751         adev->mman.buffer_funcs_ring = NULL;
2752         adev->vm_manager.vm_pte_funcs = NULL;
2753         adev->vm_manager.vm_pte_num_rqs = 0;
2754         adev->gmc.gmc_funcs = NULL;
2755         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2756         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2757
2758         adev->smc_rreg = &amdgpu_invalid_rreg;
2759         adev->smc_wreg = &amdgpu_invalid_wreg;
2760         adev->pcie_rreg = &amdgpu_invalid_rreg;
2761         adev->pcie_wreg = &amdgpu_invalid_wreg;
2762         adev->pciep_rreg = &amdgpu_invalid_rreg;
2763         adev->pciep_wreg = &amdgpu_invalid_wreg;
2764         adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
2765         adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
2766         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2767         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2768         adev->didt_rreg = &amdgpu_invalid_rreg;
2769         adev->didt_wreg = &amdgpu_invalid_wreg;
2770         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2771         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2772         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2773         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2774
2775         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2776                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2777                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2778
2779         /* mutex initialization are all done here so we
2780          * can recall function without having locking issues */
2781         atomic_set(&adev->irq.ih.lock, 0);
2782         mutex_init(&adev->firmware.mutex);
2783         mutex_init(&adev->pm.mutex);
2784         mutex_init(&adev->gfx.gpu_clock_mutex);
2785         mutex_init(&adev->srbm_mutex);
2786         mutex_init(&adev->gfx.pipe_reserve_mutex);
2787         mutex_init(&adev->gfx.gfx_off_mutex);
2788         mutex_init(&adev->grbm_idx_mutex);
2789         mutex_init(&adev->mn_lock);
2790         mutex_init(&adev->virt.vf_errors.lock);
2791         hash_init(adev->mn_hash);
2792         mutex_init(&adev->lock_reset);
2793         mutex_init(&adev->virt.dpm_mutex);
2794         mutex_init(&adev->psp.mutex);
2795
2796         r = amdgpu_device_check_arguments(adev);
2797         if (r)
2798                 return r;
2799
2800         spin_lock_init(&adev->mmio_idx_lock);
2801         spin_lock_init(&adev->smc_idx_lock);
2802         spin_lock_init(&adev->pcie_idx_lock);
2803         spin_lock_init(&adev->uvd_ctx_idx_lock);
2804         spin_lock_init(&adev->didt_idx_lock);
2805         spin_lock_init(&adev->gc_cac_idx_lock);
2806         spin_lock_init(&adev->se_cac_idx_lock);
2807         spin_lock_init(&adev->audio_endpt_idx_lock);
2808         spin_lock_init(&adev->mm_stats.lock);
2809
2810         INIT_LIST_HEAD(&adev->shadow_list);
2811         mutex_init(&adev->shadow_list_lock);
2812
2813         INIT_LIST_HEAD(&adev->ring_lru_list);
2814         spin_lock_init(&adev->ring_lru_list_lock);
2815
2816         INIT_DELAYED_WORK(&adev->delayed_init_work,
2817                           amdgpu_device_delayed_init_work_handler);
2818         INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2819                           amdgpu_device_delay_enable_gfx_off);
2820
2821         INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2822
2823         adev->gfx.gfx_off_req_count = 1;
2824         adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2825
2826         /* Registers mapping */
2827         /* TODO: block userspace mapping of io register */
2828         if (adev->asic_type >= CHIP_BONAIRE) {
2829                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2830                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2831         } else {
2832                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2833                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2834         }
2835
2836         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2837         if (adev->rmmio == NULL) {
2838                 return -ENOMEM;
2839         }
2840         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2841         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2842
2843         /* io port mapping */
2844         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2845                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2846                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2847                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2848                         break;
2849                 }
2850         }
2851         if (adev->rio_mem == NULL)
2852                 DRM_INFO("PCI I/O BAR is not found.\n");
2853
2854         /* enable PCIE atomic ops */
2855         r = pci_enable_atomic_ops_to_root(adev->pdev,
2856                                           PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
2857                                           PCI_EXP_DEVCAP2_ATOMIC_COMP64);
2858         if (r) {
2859                 adev->have_atomics_support = false;
2860                 DRM_INFO("PCIE atomic ops is not supported\n");
2861         } else {
2862                 adev->have_atomics_support = true;
2863         }
2864
2865         amdgpu_device_get_pcie_info(adev);
2866
2867         if (amdgpu_mcbp)
2868                 DRM_INFO("MCBP is enabled\n");
2869
2870         if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
2871                 adev->enable_mes = true;
2872
2873         if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) {
2874                 r = amdgpu_discovery_init(adev);
2875                 if (r) {
2876                         dev_err(adev->dev, "amdgpu_discovery_init failed\n");
2877                         return r;
2878                 }
2879         }
2880
2881         /* early init functions */
2882         r = amdgpu_device_ip_early_init(adev);
2883         if (r)
2884                 return r;
2885
2886         r = amdgpu_device_get_job_timeout_settings(adev);
2887         if (r) {
2888                 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
2889                 return r;
2890         }
2891
2892         /* doorbell bar mapping and doorbell index init*/
2893         amdgpu_device_doorbell_init(adev);
2894
2895         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2896         /* this will fail for cards that aren't VGA class devices, just
2897          * ignore it */
2898         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2899
2900         if (amdgpu_device_is_px(ddev))
2901                 runtime = true;
2902         if (!pci_is_thunderbolt_attached(adev->pdev))
2903                 vga_switcheroo_register_client(adev->pdev,
2904                                                &amdgpu_switcheroo_ops, runtime);
2905         if (runtime)
2906                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2907
2908         if (amdgpu_emu_mode == 1) {
2909                 /* post the asic on emulation mode */
2910                 emu_soc_asic_init(adev);
2911                 goto fence_driver_init;
2912         }
2913
2914         /* detect if we are with an SRIOV vbios */
2915         amdgpu_device_detect_sriov_bios(adev);
2916
2917         /* check if we need to reset the asic
2918          *  E.g., driver was not cleanly unloaded previously, etc.
2919          */
2920         if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
2921                 r = amdgpu_asic_reset(adev);
2922                 if (r) {
2923                         dev_err(adev->dev, "asic reset on init failed\n");
2924                         goto failed;
2925                 }
2926         }
2927
2928         /* Post card if necessary */
2929         if (amdgpu_device_need_post(adev)) {
2930                 if (!adev->bios) {
2931                         dev_err(adev->dev, "no vBIOS found\n");
2932                         r = -EINVAL;
2933                         goto failed;
2934                 }
2935                 DRM_INFO("GPU posting now...\n");
2936                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2937                 if (r) {
2938                         dev_err(adev->dev, "gpu post error!\n");
2939                         goto failed;
2940                 }
2941         }
2942
2943         if (adev->is_atom_fw) {
2944                 /* Initialize clocks */
2945                 r = amdgpu_atomfirmware_get_clock_info(adev);
2946                 if (r) {
2947                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2948                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2949                         goto failed;
2950                 }
2951         } else {
2952                 /* Initialize clocks */
2953                 r = amdgpu_atombios_get_clock_info(adev);
2954                 if (r) {
2955                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2956                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2957                         goto failed;
2958                 }
2959                 /* init i2c buses */
2960                 if (!amdgpu_device_has_dc_support(adev))
2961                         amdgpu_atombios_i2c_init(adev);
2962         }
2963
2964 fence_driver_init:
2965         /* Fence driver */
2966         r = amdgpu_fence_driver_init(adev);
2967         if (r) {
2968                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2969                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2970                 goto failed;
2971         }
2972
2973         /* init the mode config */
2974         drm_mode_config_init(adev->ddev);
2975
2976         r = amdgpu_device_ip_init(adev);
2977         if (r) {
2978                 /* failed in exclusive mode due to timeout */
2979                 if (amdgpu_sriov_vf(adev) &&
2980                     !amdgpu_sriov_runtime(adev) &&
2981                     amdgpu_virt_mmio_blocked(adev) &&
2982                     !amdgpu_virt_wait_reset(adev)) {
2983                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2984                         /* Don't send request since VF is inactive. */
2985                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2986                         adev->virt.ops = NULL;
2987                         r = -EAGAIN;
2988                         goto failed;
2989                 }
2990                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2991                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2992                 if (amdgpu_virt_request_full_gpu(adev, false))
2993                         amdgpu_virt_release_full_gpu(adev, false);
2994                 goto failed;
2995         }
2996
2997         adev->accel_working = true;
2998
2999         amdgpu_vm_check_compute_bug(adev);
3000
3001         /* Initialize the buffer migration limit. */
3002         if (amdgpu_moverate >= 0)
3003                 max_MBps = amdgpu_moverate;
3004         else
3005                 max_MBps = 8; /* Allow 8 MB/s. */
3006         /* Get a log2 for easy divisions. */
3007         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3008
3009         amdgpu_fbdev_init(adev);
3010
3011         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
3012                 amdgpu_pm_virt_sysfs_init(adev);
3013
3014         r = amdgpu_pm_sysfs_init(adev);
3015         if (r)
3016                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3017
3018         r = amdgpu_ucode_sysfs_init(adev);
3019         if (r)
3020                 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3021
3022         r = amdgpu_debugfs_gem_init(adev);
3023         if (r)
3024                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
3025
3026         r = amdgpu_debugfs_regs_init(adev);
3027         if (r)
3028                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
3029
3030         r = amdgpu_debugfs_firmware_init(adev);
3031         if (r)
3032                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
3033
3034         r = amdgpu_debugfs_init(adev);
3035         if (r)
3036                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
3037
3038         if ((amdgpu_testing & 1)) {
3039                 if (adev->accel_working)
3040                         amdgpu_test_moves(adev);
3041                 else
3042                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
3043         }
3044         if (amdgpu_benchmarking) {
3045                 if (adev->accel_working)
3046                         amdgpu_benchmark(adev, amdgpu_benchmarking);
3047                 else
3048                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
3049         }
3050
3051         /*
3052          * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3053          * Otherwise the mgpu fan boost feature will be skipped due to the
3054          * gpu instance is counted less.
3055          */
3056         amdgpu_register_gpu_instance(adev);
3057
3058         /* enable clockgating, etc. after ib tests, etc. since some blocks require
3059          * explicit gating rather than handling it automatically.
3060          */
3061         r = amdgpu_device_ip_late_init(adev);
3062         if (r) {
3063                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3064                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3065                 goto failed;
3066         }
3067
3068         /* must succeed. */
3069         amdgpu_ras_resume(adev);
3070
3071         queue_delayed_work(system_wq, &adev->delayed_init_work,
3072                            msecs_to_jiffies(AMDGPU_RESUME_MS));
3073
3074         r = device_create_file(adev->dev, &dev_attr_pcie_replay_count);
3075         if (r) {
3076                 dev_err(adev->dev, "Could not create pcie_replay_count");
3077                 return r;
3078         }
3079
3080         if (IS_ENABLED(CONFIG_PERF_EVENTS))
3081                 r = amdgpu_pmu_init(adev);
3082         if (r)
3083                 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3084
3085         return 0;
3086
3087 failed:
3088         amdgpu_vf_error_trans_all(adev);
3089         if (runtime)
3090                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3091
3092         return r;
3093 }
3094
3095 /**
3096  * amdgpu_device_fini - tear down the driver
3097  *
3098  * @adev: amdgpu_device pointer
3099  *
3100  * Tear down the driver info (all asics).
3101  * Called at driver shutdown.
3102  */
3103 void amdgpu_device_fini(struct amdgpu_device *adev)
3104 {
3105         int r;
3106
3107         DRM_INFO("amdgpu: finishing device.\n");
3108         adev->shutdown = true;
3109
3110         flush_delayed_work(&adev->delayed_init_work);
3111
3112         /* disable all interrupts */
3113         amdgpu_irq_disable_all(adev);
3114         if (adev->mode_info.mode_config_initialized){
3115                 if (!amdgpu_device_has_dc_support(adev))
3116                         drm_helper_force_disable_all(adev->ddev);
3117                 else
3118                         drm_atomic_helper_shutdown(adev->ddev);
3119         }
3120         amdgpu_fence_driver_fini(adev);
3121         amdgpu_pm_sysfs_fini(adev);
3122         amdgpu_fbdev_fini(adev);
3123         r = amdgpu_device_ip_fini(adev);
3124         if (adev->firmware.gpu_info_fw) {
3125                 release_firmware(adev->firmware.gpu_info_fw);
3126                 adev->firmware.gpu_info_fw = NULL;
3127         }
3128         adev->accel_working = false;
3129         cancel_delayed_work_sync(&adev->delayed_init_work);
3130         /* free i2c buses */
3131         if (!amdgpu_device_has_dc_support(adev))
3132                 amdgpu_i2c_fini(adev);
3133
3134         if (amdgpu_emu_mode != 1)
3135                 amdgpu_atombios_fini(adev);
3136
3137         kfree(adev->bios);
3138         adev->bios = NULL;
3139         if (!pci_is_thunderbolt_attached(adev->pdev))
3140                 vga_switcheroo_unregister_client(adev->pdev);
3141         if (adev->flags & AMD_IS_PX)
3142                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3143         vga_client_register(adev->pdev, NULL, NULL, NULL);
3144         if (adev->rio_mem)
3145                 pci_iounmap(adev->pdev, adev->rio_mem);
3146         adev->rio_mem = NULL;
3147         iounmap(adev->rmmio);
3148         adev->rmmio = NULL;
3149         amdgpu_device_doorbell_fini(adev);
3150         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
3151                 amdgpu_pm_virt_sysfs_fini(adev);
3152
3153         amdgpu_debugfs_regs_cleanup(adev);
3154         device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
3155         amdgpu_ucode_sysfs_fini(adev);
3156         if (IS_ENABLED(CONFIG_PERF_EVENTS))
3157                 amdgpu_pmu_fini(adev);
3158         amdgpu_debugfs_preempt_cleanup(adev);
3159         if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
3160                 amdgpu_discovery_fini(adev);
3161 }
3162
3163
3164 /*
3165  * Suspend & resume.
3166  */
3167 /**
3168  * amdgpu_device_suspend - initiate device suspend
3169  *
3170  * @dev: drm dev pointer
3171  * @suspend: suspend state
3172  * @fbcon : notify the fbdev of suspend
3173  *
3174  * Puts the hw in the suspend state (all asics).
3175  * Returns 0 for success or an error on failure.
3176  * Called at driver suspend.
3177  */
3178 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
3179 {
3180         struct amdgpu_device *adev;
3181         struct drm_crtc *crtc;
3182         struct drm_connector *connector;
3183         struct drm_connector_list_iter iter;
3184         int r;
3185
3186         if (dev == NULL || dev->dev_private == NULL) {
3187                 return -ENODEV;
3188         }
3189
3190         adev = dev->dev_private;
3191
3192         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3193                 return 0;
3194
3195         adev->in_suspend = true;
3196         drm_kms_helper_poll_disable(dev);
3197
3198         if (fbcon)
3199                 amdgpu_fbdev_set_suspend(adev, 1);
3200
3201         cancel_delayed_work_sync(&adev->delayed_init_work);
3202
3203         if (!amdgpu_device_has_dc_support(adev)) {
3204                 /* turn off display hw */
3205                 drm_modeset_lock_all(dev);
3206                 drm_connector_list_iter_begin(dev, &iter);
3207                 drm_for_each_connector_iter(connector, &iter)
3208                         drm_helper_connector_dpms(connector,
3209                                                   DRM_MODE_DPMS_OFF);
3210                 drm_connector_list_iter_end(&iter);
3211                 drm_modeset_unlock_all(dev);
3212                         /* unpin the front buffers and cursors */
3213                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3214                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3215                         struct drm_framebuffer *fb = crtc->primary->fb;
3216                         struct amdgpu_bo *robj;
3217
3218                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3219                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3220                                 r = amdgpu_bo_reserve(aobj, true);
3221                                 if (r == 0) {
3222                                         amdgpu_bo_unpin(aobj);
3223                                         amdgpu_bo_unreserve(aobj);
3224                                 }
3225                         }
3226
3227                         if (fb == NULL || fb->obj[0] == NULL) {
3228                                 continue;
3229                         }
3230                         robj = gem_to_amdgpu_bo(fb->obj[0]);
3231                         /* don't unpin kernel fb objects */
3232                         if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
3233                                 r = amdgpu_bo_reserve(robj, true);
3234                                 if (r == 0) {
3235                                         amdgpu_bo_unpin(robj);
3236                                         amdgpu_bo_unreserve(robj);
3237                                 }
3238                         }
3239                 }
3240         }
3241
3242         amdgpu_amdkfd_suspend(adev);
3243
3244         amdgpu_ras_suspend(adev);
3245
3246         r = amdgpu_device_ip_suspend_phase1(adev);
3247
3248         /* evict vram memory */
3249         amdgpu_bo_evict_vram(adev);
3250
3251         amdgpu_fence_driver_suspend(adev);
3252
3253         r = amdgpu_device_ip_suspend_phase2(adev);
3254
3255         /* evict remaining vram memory
3256          * This second call to evict vram is to evict the gart page table
3257          * using the CPU.
3258          */
3259         amdgpu_bo_evict_vram(adev);
3260
3261         if (suspend) {
3262                 pci_save_state(dev->pdev);
3263                 /* Shut down the device */
3264                 pci_disable_device(dev->pdev);
3265                 pci_set_power_state(dev->pdev, PCI_D3hot);
3266         }
3267
3268         return 0;
3269 }
3270
3271 /**
3272  * amdgpu_device_resume - initiate device resume
3273  *
3274  * @dev: drm dev pointer
3275  * @resume: resume state
3276  * @fbcon : notify the fbdev of resume
3277  *
3278  * Bring the hw back to operating state (all asics).
3279  * Returns 0 for success or an error on failure.
3280  * Called at driver resume.
3281  */
3282 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
3283 {
3284         struct drm_connector *connector;
3285         struct drm_connector_list_iter iter;
3286         struct amdgpu_device *adev = dev->dev_private;
3287         struct drm_crtc *crtc;
3288         int r = 0;
3289
3290         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3291                 return 0;
3292
3293         if (resume) {
3294                 pci_set_power_state(dev->pdev, PCI_D0);
3295                 pci_restore_state(dev->pdev);
3296                 r = pci_enable_device(dev->pdev);
3297                 if (r)
3298                         return r;
3299         }
3300
3301         /* post card */
3302         if (amdgpu_device_need_post(adev)) {
3303                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
3304                 if (r)
3305                         DRM_ERROR("amdgpu asic init failed\n");
3306         }
3307
3308         r = amdgpu_device_ip_resume(adev);
3309         if (r) {
3310                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
3311                 return r;
3312         }
3313         amdgpu_fence_driver_resume(adev);
3314
3315
3316         r = amdgpu_device_ip_late_init(adev);
3317         if (r)
3318                 return r;
3319
3320         queue_delayed_work(system_wq, &adev->delayed_init_work,
3321                            msecs_to_jiffies(AMDGPU_RESUME_MS));
3322
3323         if (!amdgpu_device_has_dc_support(adev)) {
3324                 /* pin cursors */
3325                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3326                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3327
3328                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3329                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3330                                 r = amdgpu_bo_reserve(aobj, true);
3331                                 if (r == 0) {
3332                                         r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3333                                         if (r != 0)
3334                                                 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
3335                                         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3336                                         amdgpu_bo_unreserve(aobj);
3337                                 }
3338                         }
3339                 }
3340         }
3341         r = amdgpu_amdkfd_resume(adev);
3342         if (r)
3343                 return r;
3344
3345         /* Make sure IB tests flushed */
3346         flush_delayed_work(&adev->delayed_init_work);
3347
3348         /* blat the mode back in */
3349         if (fbcon) {
3350                 if (!amdgpu_device_has_dc_support(adev)) {
3351                         /* pre DCE11 */
3352                         drm_helper_resume_force_mode(dev);
3353
3354                         /* turn on display hw */
3355                         drm_modeset_lock_all(dev);
3356
3357                         drm_connector_list_iter_begin(dev, &iter);
3358                         drm_for_each_connector_iter(connector, &iter)
3359                                 drm_helper_connector_dpms(connector,
3360                                                           DRM_MODE_DPMS_ON);
3361                         drm_connector_list_iter_end(&iter);
3362
3363                         drm_modeset_unlock_all(dev);
3364                 }
3365                 amdgpu_fbdev_set_suspend(adev, 0);
3366         }
3367
3368         drm_kms_helper_poll_enable(dev);
3369
3370         amdgpu_ras_resume(adev);
3371
3372         /*
3373          * Most of the connector probing functions try to acquire runtime pm
3374          * refs to ensure that the GPU is powered on when connector polling is
3375          * performed. Since we're calling this from a runtime PM callback,
3376          * trying to acquire rpm refs will cause us to deadlock.
3377          *
3378          * Since we're guaranteed to be holding the rpm lock, it's safe to
3379          * temporarily disable the rpm helpers so this doesn't deadlock us.
3380          */
3381 #ifdef CONFIG_PM
3382         dev->dev->power.disable_depth++;
3383 #endif
3384         if (!amdgpu_device_has_dc_support(adev))
3385                 drm_helper_hpd_irq_event(dev);
3386         else
3387                 drm_kms_helper_hotplug_event(dev);
3388 #ifdef CONFIG_PM
3389         dev->dev->power.disable_depth--;
3390 #endif
3391         adev->in_suspend = false;
3392
3393         return 0;
3394 }
3395
3396 /**
3397  * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3398  *
3399  * @adev: amdgpu_device pointer
3400  *
3401  * The list of all the hardware IPs that make up the asic is walked and
3402  * the check_soft_reset callbacks are run.  check_soft_reset determines
3403  * if the asic is still hung or not.
3404  * Returns true if any of the IPs are still in a hung state, false if not.
3405  */
3406 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3407 {
3408         int i;
3409         bool asic_hang = false;
3410
3411         if (amdgpu_sriov_vf(adev))
3412                 return true;
3413
3414         if (amdgpu_asic_need_full_reset(adev))
3415                 return true;
3416
3417         for (i = 0; i < adev->num_ip_blocks; i++) {
3418                 if (!adev->ip_blocks[i].status.valid)
3419                         continue;
3420                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3421                         adev->ip_blocks[i].status.hang =
3422                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3423                 if (adev->ip_blocks[i].status.hang) {
3424                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3425                         asic_hang = true;
3426                 }
3427         }
3428         return asic_hang;
3429 }
3430
3431 /**
3432  * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3433  *
3434  * @adev: amdgpu_device pointer
3435  *
3436  * The list of all the hardware IPs that make up the asic is walked and the
3437  * pre_soft_reset callbacks are run if the block is hung.  pre_soft_reset
3438  * handles any IP specific hardware or software state changes that are
3439  * necessary for a soft reset to succeed.
3440  * Returns 0 on success, negative error code on failure.
3441  */
3442 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3443 {
3444         int i, r = 0;
3445
3446         for (i = 0; i < adev->num_ip_blocks; i++) {
3447                 if (!adev->ip_blocks[i].status.valid)
3448                         continue;
3449                 if (adev->ip_blocks[i].status.hang &&
3450                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3451                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3452                         if (r)
3453                                 return r;
3454                 }
3455         }
3456
3457         return 0;
3458 }
3459
3460 /**
3461  * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3462  *
3463  * @adev: amdgpu_device pointer
3464  *
3465  * Some hardware IPs cannot be soft reset.  If they are hung, a full gpu
3466  * reset is necessary to recover.
3467  * Returns true if a full asic reset is required, false if not.
3468  */
3469 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3470 {
3471         int i;
3472
3473         if (amdgpu_asic_need_full_reset(adev))
3474                 return true;
3475
3476         for (i = 0; i < adev->num_ip_blocks; i++) {
3477                 if (!adev->ip_blocks[i].status.valid)
3478                         continue;
3479                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3480                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3481                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3482                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3483                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3484                         if (adev->ip_blocks[i].status.hang) {
3485                                 DRM_INFO("Some block need full reset!\n");
3486                                 return true;
3487                         }
3488                 }
3489         }
3490         return false;
3491 }
3492
3493 /**
3494  * amdgpu_device_ip_soft_reset - do a soft reset
3495  *
3496  * @adev: amdgpu_device pointer
3497  *
3498  * The list of all the hardware IPs that make up the asic is walked and the
3499  * soft_reset callbacks are run if the block is hung.  soft_reset handles any
3500  * IP specific hardware or software state changes that are necessary to soft
3501  * reset the IP.
3502  * Returns 0 on success, negative error code on failure.
3503  */
3504 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3505 {
3506         int i, r = 0;
3507
3508         for (i = 0; i < adev->num_ip_blocks; i++) {
3509                 if (!adev->ip_blocks[i].status.valid)
3510                         continue;
3511                 if (adev->ip_blocks[i].status.hang &&
3512                     adev->ip_blocks[i].version->funcs->soft_reset) {
3513                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3514                         if (r)
3515                                 return r;
3516                 }
3517         }
3518
3519         return 0;
3520 }
3521
3522 /**
3523  * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3524  *
3525  * @adev: amdgpu_device pointer
3526  *
3527  * The list of all the hardware IPs that make up the asic is walked and the
3528  * post_soft_reset callbacks are run if the asic was hung.  post_soft_reset
3529  * handles any IP specific hardware or software state changes that are
3530  * necessary after the IP has been soft reset.
3531  * Returns 0 on success, negative error code on failure.
3532  */
3533 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3534 {
3535         int i, r = 0;
3536
3537         for (i = 0; i < adev->num_ip_blocks; i++) {
3538                 if (!adev->ip_blocks[i].status.valid)
3539                         continue;
3540                 if (adev->ip_blocks[i].status.hang &&
3541                     adev->ip_blocks[i].version->funcs->post_soft_reset)
3542                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3543                 if (r)
3544                         return r;
3545         }
3546
3547         return 0;
3548 }
3549
3550 /**
3551  * amdgpu_device_recover_vram - Recover some VRAM contents
3552  *
3553  * @adev: amdgpu_device pointer
3554  *
3555  * Restores the contents of VRAM buffers from the shadows in GTT.  Used to
3556  * restore things like GPUVM page tables after a GPU reset where
3557  * the contents of VRAM might be lost.
3558  *
3559  * Returns:
3560  * 0 on success, negative error code on failure.
3561  */
3562 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3563 {
3564         struct dma_fence *fence = NULL, *next = NULL;
3565         struct amdgpu_bo *shadow;
3566         long r = 1, tmo;
3567
3568         if (amdgpu_sriov_runtime(adev))
3569                 tmo = msecs_to_jiffies(8000);
3570         else
3571                 tmo = msecs_to_jiffies(100);
3572
3573         DRM_INFO("recover vram bo from shadow start\n");
3574         mutex_lock(&adev->shadow_list_lock);
3575         list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3576
3577                 /* No need to recover an evicted BO */
3578                 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3579                     shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
3580                     shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3581                         continue;
3582
3583                 r = amdgpu_bo_restore_shadow(shadow, &next);
3584                 if (r)
3585                         break;
3586
3587                 if (fence) {
3588                         tmo = dma_fence_wait_timeout(fence, false, tmo);
3589                         dma_fence_put(fence);
3590                         fence = next;
3591                         if (tmo == 0) {
3592                                 r = -ETIMEDOUT;
3593                                 break;
3594                         } else if (tmo < 0) {
3595                                 r = tmo;
3596                                 break;
3597                         }
3598                 } else {
3599                         fence = next;
3600                 }
3601         }
3602         mutex_unlock(&adev->shadow_list_lock);
3603
3604         if (fence)
3605                 tmo = dma_fence_wait_timeout(fence, false, tmo);
3606         dma_fence_put(fence);
3607
3608         if (r < 0 || tmo <= 0) {
3609                 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
3610                 return -EIO;
3611         }
3612
3613         DRM_INFO("recover vram bo from shadow done\n");
3614         return 0;
3615 }
3616
3617
3618 /**
3619  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3620  *
3621  * @adev: amdgpu device pointer
3622  * @from_hypervisor: request from hypervisor
3623  *
3624  * do VF FLR and reinitialize Asic
3625  * return 0 means succeeded otherwise failed
3626  */
3627 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3628                                      bool from_hypervisor)
3629 {
3630         int r;
3631
3632         if (from_hypervisor)
3633                 r = amdgpu_virt_request_full_gpu(adev, true);
3634         else
3635                 r = amdgpu_virt_reset_gpu(adev);
3636         if (r)
3637                 return r;
3638
3639         amdgpu_amdkfd_pre_reset(adev);
3640
3641         /* Resume IP prior to SMC */
3642         r = amdgpu_device_ip_reinit_early_sriov(adev);
3643         if (r)
3644                 goto error;
3645
3646         /* we need recover gart prior to run SMC/CP/SDMA resume */
3647         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3648
3649         r = amdgpu_device_fw_loading(adev);
3650         if (r)
3651                 return r;
3652
3653         /* now we are okay to resume SMC/CP/SDMA */
3654         r = amdgpu_device_ip_reinit_late_sriov(adev);
3655         if (r)
3656                 goto error;
3657
3658         amdgpu_irq_gpu_reset_resume_helper(adev);
3659         r = amdgpu_ib_ring_tests(adev);
3660         amdgpu_amdkfd_post_reset(adev);
3661
3662 error:
3663         amdgpu_virt_init_data_exchange(adev);
3664         amdgpu_virt_release_full_gpu(adev, true);
3665         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3666                 amdgpu_inc_vram_lost(adev);
3667                 r = amdgpu_device_recover_vram(adev);
3668         }
3669
3670         return r;
3671 }
3672
3673 /**
3674  * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3675  *
3676  * @adev: amdgpu device pointer
3677  *
3678  * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3679  * a hung GPU.
3680  */
3681 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3682 {
3683         if (!amdgpu_device_ip_check_soft_reset(adev)) {
3684                 DRM_INFO("Timeout, but no hardware hang detected.\n");
3685                 return false;
3686         }
3687
3688         if (amdgpu_gpu_recovery == 0)
3689                 goto disabled;
3690
3691         if (amdgpu_sriov_vf(adev))
3692                 return true;
3693
3694         if (amdgpu_gpu_recovery == -1) {
3695                 switch (adev->asic_type) {
3696                 case CHIP_BONAIRE:
3697                 case CHIP_HAWAII:
3698                 case CHIP_TOPAZ:
3699                 case CHIP_TONGA:
3700                 case CHIP_FIJI:
3701                 case CHIP_POLARIS10:
3702                 case CHIP_POLARIS11:
3703                 case CHIP_POLARIS12:
3704                 case CHIP_VEGAM:
3705                 case CHIP_VEGA20:
3706                 case CHIP_VEGA10:
3707                 case CHIP_VEGA12:
3708                 case CHIP_RAVEN:
3709                         break;
3710                 default:
3711                         goto disabled;
3712                 }
3713         }
3714
3715         return true;
3716
3717 disabled:
3718                 DRM_INFO("GPU recovery disabled.\n");
3719                 return false;
3720 }
3721
3722
3723 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3724                                         struct amdgpu_job *job,
3725                                         bool *need_full_reset_arg)
3726 {
3727         int i, r = 0;
3728         bool need_full_reset  = *need_full_reset_arg;
3729
3730         /* block all schedulers and reset given job's ring */
3731         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3732                 struct amdgpu_ring *ring = adev->rings[i];
3733
3734                 if (!ring || !ring->sched.thread)
3735                         continue;
3736
3737                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3738                 amdgpu_fence_driver_force_completion(ring);
3739         }
3740
3741         if(job)
3742                 drm_sched_increase_karma(&job->base);
3743
3744         /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
3745         if (!amdgpu_sriov_vf(adev)) {
3746
3747                 if (!need_full_reset)
3748                         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3749
3750                 if (!need_full_reset) {
3751                         amdgpu_device_ip_pre_soft_reset(adev);
3752                         r = amdgpu_device_ip_soft_reset(adev);
3753                         amdgpu_device_ip_post_soft_reset(adev);
3754                         if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3755                                 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3756                                 need_full_reset = true;
3757                         }
3758                 }
3759
3760                 if (need_full_reset)
3761                         r = amdgpu_device_ip_suspend(adev);
3762
3763                 *need_full_reset_arg = need_full_reset;
3764         }
3765
3766         return r;
3767 }
3768
3769 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3770                                struct list_head *device_list_handle,
3771                                bool *need_full_reset_arg)
3772 {
3773         struct amdgpu_device *tmp_adev = NULL;
3774         bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3775         int r = 0;
3776
3777         /*
3778          * ASIC reset has to be done on all HGMI hive nodes ASAP
3779          * to allow proper links negotiation in FW (within 1 sec)
3780          */
3781         if (need_full_reset) {
3782                 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3783                         /* For XGMI run all resets in parallel to speed up the process */
3784                         if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3785                                 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3786                                         r = -EALREADY;
3787                         } else
3788                                 r = amdgpu_asic_reset(tmp_adev);
3789
3790                         if (r) {
3791                                 DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
3792                                          r, tmp_adev->ddev->unique);
3793                                 break;
3794                         }
3795                 }
3796
3797                 /* For XGMI wait for all PSP resets to complete before proceed */
3798                 if (!r) {
3799                         list_for_each_entry(tmp_adev, device_list_handle,
3800                                             gmc.xgmi.head) {
3801                                 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3802                                         flush_work(&tmp_adev->xgmi_reset_work);
3803                                         r = tmp_adev->asic_reset_res;
3804                                         if (r)
3805                                                 break;
3806                                 }
3807                         }
3808                 }
3809         }
3810
3811
3812         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3813                 if (need_full_reset) {
3814                         /* post card */
3815                         if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3816                                 DRM_WARN("asic atom init failed!");
3817
3818                         if (!r) {
3819                                 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3820                                 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3821                                 if (r)
3822                                         goto out;
3823
3824                                 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3825                                 if (vram_lost) {
3826                                         DRM_INFO("VRAM is lost due to GPU reset!\n");
3827                                         amdgpu_inc_vram_lost(tmp_adev);
3828                                 }
3829
3830                                 r = amdgpu_gtt_mgr_recover(
3831                                         &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3832                                 if (r)
3833                                         goto out;
3834
3835                                 r = amdgpu_device_fw_loading(tmp_adev);
3836                                 if (r)
3837                                         return r;
3838
3839                                 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3840                                 if (r)
3841                                         goto out;
3842
3843                                 if (vram_lost)
3844                                         amdgpu_device_fill_reset_magic(tmp_adev);
3845
3846                                 /*
3847                                  * Add this ASIC as tracked as reset was already
3848                                  * complete successfully.
3849                                  */
3850                                 amdgpu_register_gpu_instance(tmp_adev);
3851
3852                                 r = amdgpu_device_ip_late_init(tmp_adev);
3853                                 if (r)
3854                                         goto out;
3855
3856                                 /* must succeed. */
3857                                 amdgpu_ras_resume(tmp_adev);
3858
3859                                 /* Update PSP FW topology after reset */
3860                                 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3861                                         r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3862                         }
3863                 }
3864
3865
3866 out:
3867                 if (!r) {
3868                         amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3869                         r = amdgpu_ib_ring_tests(tmp_adev);
3870                         if (r) {
3871                                 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3872                                 r = amdgpu_device_ip_suspend(tmp_adev);
3873                                 need_full_reset = true;
3874                                 r = -EAGAIN;
3875                                 goto end;
3876                         }
3877                 }
3878
3879                 if (!r)
3880                         r = amdgpu_device_recover_vram(tmp_adev);
3881                 else
3882                         tmp_adev->asic_reset_res = r;
3883         }
3884
3885 end:
3886         *need_full_reset_arg = need_full_reset;
3887         return r;
3888 }
3889
3890 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
3891 {
3892         if (trylock) {
3893                 if (!mutex_trylock(&adev->lock_reset))
3894                         return false;
3895         } else
3896                 mutex_lock(&adev->lock_reset);
3897
3898         atomic_inc(&adev->gpu_reset_counter);
3899         adev->in_gpu_reset = 1;
3900         switch (amdgpu_asic_reset_method(adev)) {
3901         case AMD_RESET_METHOD_MODE1:
3902                 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
3903                 break;
3904         case AMD_RESET_METHOD_MODE2:
3905                 adev->mp1_state = PP_MP1_STATE_RESET;
3906                 break;
3907         default:
3908                 adev->mp1_state = PP_MP1_STATE_NONE;
3909                 break;
3910         }
3911
3912         return true;
3913 }
3914
3915 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3916 {
3917         amdgpu_vf_error_trans_all(adev);
3918         adev->mp1_state = PP_MP1_STATE_NONE;
3919         adev->in_gpu_reset = 0;
3920         mutex_unlock(&adev->lock_reset);
3921 }
3922
3923 /**
3924  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3925  *
3926  * @adev: amdgpu device pointer
3927  * @job: which job trigger hang
3928  *
3929  * Attempt to reset the GPU if it has hung (all asics).
3930  * Attempt to do soft-reset or full-reset and reinitialize Asic
3931  * Returns 0 for success or an error on failure.
3932  */
3933
3934 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3935                               struct amdgpu_job *job)
3936 {
3937         struct list_head device_list, *device_list_handle =  NULL;
3938         bool need_full_reset, job_signaled;
3939         struct amdgpu_hive_info *hive = NULL;
3940         struct amdgpu_device *tmp_adev = NULL;
3941         int i, r = 0;
3942         bool in_ras_intr = amdgpu_ras_intr_triggered();
3943
3944         /*
3945          * Flush RAM to disk so that after reboot
3946          * the user can read log and see why the system rebooted.
3947          */
3948         if (in_ras_intr && amdgpu_ras_get_context(adev)->reboot) {
3949
3950                 DRM_WARN("Emergency reboot.");
3951
3952                 ksys_sync_helper();
3953                 emergency_restart();
3954         }
3955
3956         need_full_reset = job_signaled = false;
3957         INIT_LIST_HEAD(&device_list);
3958
3959         dev_info(adev->dev, "GPU %s begin!\n", in_ras_intr ? "jobs stop":"reset");
3960
3961         cancel_delayed_work_sync(&adev->delayed_init_work);
3962
3963         hive = amdgpu_get_xgmi_hive(adev, false);
3964
3965         /*
3966          * Here we trylock to avoid chain of resets executing from
3967          * either trigger by jobs on different adevs in XGMI hive or jobs on
3968          * different schedulers for same device while this TO handler is running.
3969          * We always reset all schedulers for device and all devices for XGMI
3970          * hive so that should take care of them too.
3971          */
3972
3973         if (hive && !mutex_trylock(&hive->reset_lock)) {
3974                 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
3975                           job ? job->base.id : -1, hive->hive_id);
3976                 return 0;
3977         }
3978
3979         /* Start with adev pre asic reset first for soft reset check.*/
3980         if (!amdgpu_device_lock_adev(adev, !hive)) {
3981                 DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
3982                           job ? job->base.id : -1);
3983                 return 0;
3984         }
3985
3986         /* Block kfd: SRIOV would do it separately */
3987         if (!amdgpu_sriov_vf(adev))
3988                 amdgpu_amdkfd_pre_reset(adev);
3989
3990         /* Build list of devices to reset */
3991         if  (adev->gmc.xgmi.num_physical_nodes > 1) {
3992                 if (!hive) {
3993                         /*unlock kfd: SRIOV would do it separately */
3994                         if (!amdgpu_sriov_vf(adev))
3995                                 amdgpu_amdkfd_post_reset(adev);
3996                         amdgpu_device_unlock_adev(adev);
3997                         return -ENODEV;
3998                 }
3999
4000                 /*
4001                  * In case we are in XGMI hive mode device reset is done for all the
4002                  * nodes in the hive to retrain all XGMI links and hence the reset
4003                  * sequence is executed in loop on all nodes.
4004                  */
4005                 device_list_handle = &hive->device_list;
4006         } else {
4007                 list_add_tail(&adev->gmc.xgmi.head, &device_list);
4008                 device_list_handle = &device_list;
4009         }
4010
4011         /* block all schedulers and reset given job's ring */
4012         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4013                 if (tmp_adev != adev) {
4014                         amdgpu_device_lock_adev(tmp_adev, false);
4015                         if (!amdgpu_sriov_vf(tmp_adev))
4016                                         amdgpu_amdkfd_pre_reset(tmp_adev);
4017                 }
4018
4019                 /*
4020                  * Mark these ASICs to be reseted as untracked first
4021                  * And add them back after reset completed
4022                  */
4023                 amdgpu_unregister_gpu_instance(tmp_adev);
4024
4025                 /* disable ras on ALL IPs */
4026                 if (!in_ras_intr && amdgpu_device_ip_need_full_reset(tmp_adev))
4027                         amdgpu_ras_suspend(tmp_adev);
4028
4029                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4030                         struct amdgpu_ring *ring = tmp_adev->rings[i];
4031
4032                         if (!ring || !ring->sched.thread)
4033                                 continue;
4034
4035                         drm_sched_stop(&ring->sched, job ? &job->base : NULL);
4036
4037                         if (in_ras_intr)
4038                                 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
4039                 }
4040         }
4041
4042
4043         if (in_ras_intr)
4044                 goto skip_sched_resume;
4045
4046         /*
4047          * Must check guilty signal here since after this point all old
4048          * HW fences are force signaled.
4049          *
4050          * job->base holds a reference to parent fence
4051          */
4052         if (job && job->base.s_fence->parent &&
4053             dma_fence_is_signaled(job->base.s_fence->parent))
4054                 job_signaled = true;
4055
4056         if (job_signaled) {
4057                 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
4058                 goto skip_hw_reset;
4059         }
4060
4061
4062         /* Guilty job will be freed after this*/
4063         r = amdgpu_device_pre_asic_reset(adev, job, &need_full_reset);
4064         if (r) {
4065                 /*TODO Should we stop ?*/
4066                 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
4067                           r, adev->ddev->unique);
4068                 adev->asic_reset_res = r;
4069         }
4070
4071 retry:  /* Rest of adevs pre asic reset from XGMI hive. */
4072         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4073
4074                 if (tmp_adev == adev)
4075                         continue;
4076
4077                 r = amdgpu_device_pre_asic_reset(tmp_adev,
4078                                                  NULL,
4079                                                  &need_full_reset);
4080                 /*TODO Should we stop ?*/
4081                 if (r) {
4082                         DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
4083                                   r, tmp_adev->ddev->unique);
4084                         tmp_adev->asic_reset_res = r;
4085                 }
4086         }
4087
4088         /* Actual ASIC resets if needed.*/
4089         /* TODO Implement XGMI hive reset logic for SRIOV */
4090         if (amdgpu_sriov_vf(adev)) {
4091                 r = amdgpu_device_reset_sriov(adev, job ? false : true);
4092                 if (r)
4093                         adev->asic_reset_res = r;
4094         } else {
4095                 r  = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
4096                 if (r && r == -EAGAIN)
4097                         goto retry;
4098         }
4099
4100 skip_hw_reset:
4101
4102         /* Post ASIC reset for all devs .*/
4103         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4104
4105                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4106                         struct amdgpu_ring *ring = tmp_adev->rings[i];
4107
4108                         if (!ring || !ring->sched.thread)
4109                                 continue;
4110
4111                         /* No point to resubmit jobs if we didn't HW reset*/
4112                         if (!tmp_adev->asic_reset_res && !job_signaled)
4113                                 drm_sched_resubmit_jobs(&ring->sched);
4114
4115                         drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
4116                 }
4117
4118                 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
4119                         drm_helper_resume_force_mode(tmp_adev->ddev);
4120                 }
4121
4122                 tmp_adev->asic_reset_res = 0;
4123
4124                 if (r) {
4125                         /* bad news, how to tell it to userspace ? */
4126                         dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
4127                         amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
4128                 } else {
4129                         dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
4130                 }
4131         }
4132
4133 skip_sched_resume:
4134         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4135                 /*unlock kfd: SRIOV would do it separately */
4136                 if (!in_ras_intr && !amdgpu_sriov_vf(tmp_adev))
4137                         amdgpu_amdkfd_post_reset(tmp_adev);
4138                 amdgpu_device_unlock_adev(tmp_adev);
4139         }
4140
4141         if (hive)
4142                 mutex_unlock(&hive->reset_lock);
4143
4144         if (r)
4145                 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
4146         return r;
4147 }
4148
4149 /**
4150  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
4151  *
4152  * @adev: amdgpu_device pointer
4153  *
4154  * Fetchs and stores in the driver the PCIE capabilities (gen speed
4155  * and lanes) of the slot the device is in. Handles APUs and
4156  * virtualized environments where PCIE config space may not be available.
4157  */
4158 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
4159 {
4160         struct pci_dev *pdev;
4161         enum pci_bus_speed speed_cap, platform_speed_cap;
4162         enum pcie_link_width platform_link_width;
4163
4164         if (amdgpu_pcie_gen_cap)
4165                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
4166
4167         if (amdgpu_pcie_lane_cap)
4168                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
4169
4170         /* covers APUs as well */
4171         if (pci_is_root_bus(adev->pdev->bus)) {
4172                 if (adev->pm.pcie_gen_mask == 0)
4173                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
4174                 if (adev->pm.pcie_mlw_mask == 0)
4175                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4176                 return;
4177         }
4178
4179         if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
4180                 return;
4181
4182         pcie_bandwidth_available(adev->pdev, NULL,
4183                                  &platform_speed_cap, &platform_link_width);
4184
4185         if (adev->pm.pcie_gen_mask == 0) {
4186                 /* asic caps */
4187                 pdev = adev->pdev;
4188                 speed_cap = pcie_get_speed_cap(pdev);
4189                 if (speed_cap == PCI_SPEED_UNKNOWN) {
4190                         adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4191                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4192                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4193                 } else {
4194                         if (speed_cap == PCIE_SPEED_16_0GT)
4195                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4196                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4197                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4198                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
4199                         else if (speed_cap == PCIE_SPEED_8_0GT)
4200                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4201                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4202                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4203                         else if (speed_cap == PCIE_SPEED_5_0GT)
4204                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4205                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
4206                         else
4207                                 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
4208                 }
4209                 /* platform caps */
4210                 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
4211                         adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4212                                                    CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4213                 } else {
4214                         if (platform_speed_cap == PCIE_SPEED_16_0GT)
4215                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4216                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4217                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4218                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
4219                         else if (platform_speed_cap == PCIE_SPEED_8_0GT)
4220                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4221                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4222                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
4223                         else if (platform_speed_cap == PCIE_SPEED_5_0GT)
4224                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4225                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4226                         else
4227                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
4228
4229                 }
4230         }
4231         if (adev->pm.pcie_mlw_mask == 0) {
4232                 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
4233                         adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
4234                 } else {
4235                         switch (platform_link_width) {
4236                         case PCIE_LNK_X32:
4237                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
4238                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4239                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4240                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4241                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4242                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4243                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4244                                 break;
4245                         case PCIE_LNK_X16:
4246                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4247                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4248                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4249                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4250                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4251                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4252                                 break;
4253                         case PCIE_LNK_X12:
4254                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4255                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4256                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4257                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4258                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4259                                 break;
4260                         case PCIE_LNK_X8:
4261                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4262                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4263                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4264                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4265                                 break;
4266                         case PCIE_LNK_X4:
4267                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4268                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4269                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4270                                 break;
4271                         case PCIE_LNK_X2:
4272                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4273                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4274                                 break;
4275                         case PCIE_LNK_X1:
4276                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
4277                                 break;
4278                         default:
4279                                 break;
4280                         }
4281                 }
4282         }
4283 }
4284