2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/kthread.h>
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/poll.h>
31 #include <drm/drm_debugfs.h>
34 #include "amdgpu_pm.h"
35 #include "amdgpu_dm_debugfs.h"
36 #include "amdgpu_ras.h"
37 #include "amdgpu_rap.h"
38 #include "amdgpu_fw_attestation.h"
41 * amdgpu_debugfs_add_files - Add simple debugfs entries
43 * @adev: Device to attach debugfs entries to
44 * @files: Array of function callbacks that respond to reads
45 * @nfiles: Number of callbacks to register
48 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
49 const struct drm_info_list *files,
54 for (i = 0; i < adev->debugfs_count; i++) {
55 if (adev->debugfs[i].files == files) {
56 /* Already registered */
61 i = adev->debugfs_count + 1;
62 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
63 DRM_ERROR("Reached maximum number of debugfs components.\n");
64 DRM_ERROR("Report so we increase "
65 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
68 adev->debugfs[adev->debugfs_count].files = files;
69 adev->debugfs[adev->debugfs_count].num_files = nfiles;
70 adev->debugfs_count = i;
71 #if defined(CONFIG_DEBUG_FS)
72 drm_debugfs_create_files(files, nfiles,
73 adev_to_drm(adev)->primary->debugfs_root,
74 adev_to_drm(adev)->primary);
79 int amdgpu_debugfs_wait_dump(struct amdgpu_device *adev)
81 #if defined(CONFIG_DEBUG_FS)
82 unsigned long timeout = 600 * HZ;
85 wake_up_interruptible(&adev->autodump.gpu_hang);
87 ret = wait_for_completion_interruptible_timeout(&adev->autodump.dumping, timeout);
89 pr_err("autodump: timeout, move on to gpu recovery\n");
96 #if defined(CONFIG_DEBUG_FS)
98 static int amdgpu_debugfs_autodump_open(struct inode *inode, struct file *file)
100 struct amdgpu_device *adev = inode->i_private;
103 file->private_data = adev;
105 ret = down_read_killable(&adev->reset_sem);
109 if (adev->autodump.dumping.done) {
110 reinit_completion(&adev->autodump.dumping);
116 up_read(&adev->reset_sem);
121 static int amdgpu_debugfs_autodump_release(struct inode *inode, struct file *file)
123 struct amdgpu_device *adev = file->private_data;
125 complete_all(&adev->autodump.dumping);
129 static unsigned int amdgpu_debugfs_autodump_poll(struct file *file, struct poll_table_struct *poll_table)
131 struct amdgpu_device *adev = file->private_data;
133 poll_wait(file, &adev->autodump.gpu_hang, poll_table);
135 if (amdgpu_in_reset(adev))
136 return POLLIN | POLLRDNORM | POLLWRNORM;
141 static const struct file_operations autodump_debug_fops = {
142 .owner = THIS_MODULE,
143 .open = amdgpu_debugfs_autodump_open,
144 .poll = amdgpu_debugfs_autodump_poll,
145 .release = amdgpu_debugfs_autodump_release,
148 static void amdgpu_debugfs_autodump_init(struct amdgpu_device *adev)
150 init_completion(&adev->autodump.dumping);
151 complete_all(&adev->autodump.dumping);
152 init_waitqueue_head(&adev->autodump.gpu_hang);
154 debugfs_create_file("amdgpu_autodump", 0600,
155 adev_to_drm(adev)->primary->debugfs_root,
156 adev, &autodump_debug_fops);
160 * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
162 * @read: True if reading
163 * @f: open file handle
164 * @buf: User buffer to write/read to
165 * @size: Number of bytes to write/read
166 * @pos: Offset to seek to
168 * This debugfs entry has special meaning on the offset being sought.
169 * Various bits have different meanings:
171 * Bit 62: Indicates a GRBM bank switch is needed
172 * Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is
174 * Bits 24..33: The SE or ME selector if needed
175 * Bits 34..43: The SH (or SA) or PIPE selector if needed
176 * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
178 * Bit 23: Indicates that the PM power gating lock should be held
179 * This is necessary to read registers that might be
180 * unreliable during a power gating transistion.
182 * The lower bits are the BYTE offset of the register to read. This
183 * allows reading multiple registers in a single call and having
184 * the returned size reflect that.
186 static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
187 char __user *buf, size_t size, loff_t *pos)
189 struct amdgpu_device *adev = file_inode(f)->i_private;
192 bool pm_pg_lock, use_bank, use_ring;
193 unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
195 pm_pg_lock = use_bank = use_ring = false;
196 instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
198 if (size & 0x3 || *pos & 0x3 ||
199 ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
202 /* are we reading registers for which a PG lock is necessary? */
203 pm_pg_lock = (*pos >> 23) & 1;
205 if (*pos & (1ULL << 62)) {
206 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
207 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
208 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
210 if (se_bank == 0x3FF)
211 se_bank = 0xFFFFFFFF;
212 if (sh_bank == 0x3FF)
213 sh_bank = 0xFFFFFFFF;
214 if (instance_bank == 0x3FF)
215 instance_bank = 0xFFFFFFFF;
217 } else if (*pos & (1ULL << 61)) {
219 me = (*pos & GENMASK_ULL(33, 24)) >> 24;
220 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
221 queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
222 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
226 use_bank = use_ring = false;
229 *pos &= (1UL << 22) - 1;
231 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
233 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
237 r = amdgpu_virt_enable_access_debugfs(adev);
239 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
244 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
245 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
246 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
247 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
248 amdgpu_virt_disable_access_debugfs(adev);
251 mutex_lock(&adev->grbm_idx_mutex);
252 amdgpu_gfx_select_se_sh(adev, se_bank,
253 sh_bank, instance_bank);
254 } else if (use_ring) {
255 mutex_lock(&adev->srbm_mutex);
256 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
260 mutex_lock(&adev->pm.mutex);
266 value = RREG32(*pos >> 2);
267 r = put_user(value, (uint32_t *)buf);
269 r = get_user(value, (uint32_t *)buf);
271 amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value);
286 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
287 mutex_unlock(&adev->grbm_idx_mutex);
288 } else if (use_ring) {
289 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
290 mutex_unlock(&adev->srbm_mutex);
294 mutex_unlock(&adev->pm.mutex);
296 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
297 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
299 amdgpu_virt_disable_access_debugfs(adev);
304 * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
306 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
307 size_t size, loff_t *pos)
309 return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
313 * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
315 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
316 size_t size, loff_t *pos)
318 return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
323 * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
325 * @f: open file handle
326 * @buf: User buffer to store read data in
327 * @size: Number of bytes to read
328 * @pos: Offset to seek to
330 * The lower bits are the BYTE offset of the register to read. This
331 * allows reading multiple registers in a single call and having
332 * the returned size reflect that.
334 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
335 size_t size, loff_t *pos)
337 struct amdgpu_device *adev = file_inode(f)->i_private;
341 if (size & 0x3 || *pos & 0x3)
344 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
346 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
350 r = amdgpu_virt_enable_access_debugfs(adev);
352 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
359 value = RREG32_PCIE(*pos >> 2);
360 r = put_user(value, (uint32_t *)buf);
362 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
363 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
364 amdgpu_virt_disable_access_debugfs(adev);
374 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
375 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
377 amdgpu_virt_disable_access_debugfs(adev);
382 * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
384 * @f: open file handle
385 * @buf: User buffer to write data from
386 * @size: Number of bytes to write
387 * @pos: Offset to seek to
389 * The lower bits are the BYTE offset of the register to write. This
390 * allows writing multiple registers in a single call and having
391 * the returned size reflect that.
393 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
394 size_t size, loff_t *pos)
396 struct amdgpu_device *adev = file_inode(f)->i_private;
400 if (size & 0x3 || *pos & 0x3)
403 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
405 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
409 r = amdgpu_virt_enable_access_debugfs(adev);
411 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
418 r = get_user(value, (uint32_t *)buf);
420 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
421 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
422 amdgpu_virt_disable_access_debugfs(adev);
426 WREG32_PCIE(*pos >> 2, value);
434 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
435 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
437 amdgpu_virt_disable_access_debugfs(adev);
442 * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
444 * @f: open file handle
445 * @buf: User buffer to store read data in
446 * @size: Number of bytes to read
447 * @pos: Offset to seek to
449 * The lower bits are the BYTE offset of the register to read. This
450 * allows reading multiple registers in a single call and having
451 * the returned size reflect that.
453 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
454 size_t size, loff_t *pos)
456 struct amdgpu_device *adev = file_inode(f)->i_private;
460 if (size & 0x3 || *pos & 0x3)
463 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
465 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
469 r = amdgpu_virt_enable_access_debugfs(adev);
471 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
478 value = RREG32_DIDT(*pos >> 2);
479 r = put_user(value, (uint32_t *)buf);
481 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
482 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
483 amdgpu_virt_disable_access_debugfs(adev);
493 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
494 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
496 amdgpu_virt_disable_access_debugfs(adev);
501 * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
503 * @f: open file handle
504 * @buf: User buffer to write data from
505 * @size: Number of bytes to write
506 * @pos: Offset to seek to
508 * The lower bits are the BYTE offset of the register to write. This
509 * allows writing multiple registers in a single call and having
510 * the returned size reflect that.
512 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
513 size_t size, loff_t *pos)
515 struct amdgpu_device *adev = file_inode(f)->i_private;
519 if (size & 0x3 || *pos & 0x3)
522 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
524 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
528 r = amdgpu_virt_enable_access_debugfs(adev);
530 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
537 r = get_user(value, (uint32_t *)buf);
539 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
540 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
541 amdgpu_virt_disable_access_debugfs(adev);
545 WREG32_DIDT(*pos >> 2, value);
553 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
554 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
556 amdgpu_virt_disable_access_debugfs(adev);
561 * amdgpu_debugfs_regs_smc_read - Read from a SMC register
563 * @f: open file handle
564 * @buf: User buffer to store read data in
565 * @size: Number of bytes to read
566 * @pos: Offset to seek to
568 * The lower bits are the BYTE offset of the register to read. This
569 * allows reading multiple registers in a single call and having
570 * the returned size reflect that.
572 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
573 size_t size, loff_t *pos)
575 struct amdgpu_device *adev = file_inode(f)->i_private;
579 if (size & 0x3 || *pos & 0x3)
582 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
584 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
588 r = amdgpu_virt_enable_access_debugfs(adev);
590 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
597 value = RREG32_SMC(*pos);
598 r = put_user(value, (uint32_t *)buf);
600 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
601 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
602 amdgpu_virt_disable_access_debugfs(adev);
612 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
613 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
615 amdgpu_virt_disable_access_debugfs(adev);
620 * amdgpu_debugfs_regs_smc_write - Write to a SMC register
622 * @f: open file handle
623 * @buf: User buffer to write data from
624 * @size: Number of bytes to write
625 * @pos: Offset to seek to
627 * The lower bits are the BYTE offset of the register to write. This
628 * allows writing multiple registers in a single call and having
629 * the returned size reflect that.
631 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
632 size_t size, loff_t *pos)
634 struct amdgpu_device *adev = file_inode(f)->i_private;
638 if (size & 0x3 || *pos & 0x3)
641 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
643 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
647 r = amdgpu_virt_enable_access_debugfs(adev);
649 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
656 r = get_user(value, (uint32_t *)buf);
658 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
659 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
660 amdgpu_virt_disable_access_debugfs(adev);
664 WREG32_SMC(*pos, value);
672 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
673 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
675 amdgpu_virt_disable_access_debugfs(adev);
680 * amdgpu_debugfs_gca_config_read - Read from gfx config data
682 * @f: open file handle
683 * @buf: User buffer to store read data in
684 * @size: Number of bytes to read
685 * @pos: Offset to seek to
687 * This file is used to access configuration data in a somewhat
688 * stable fashion. The format is a series of DWORDs with the first
689 * indicating which revision it is. New content is appended to the
690 * end so that older software can still read the data.
693 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
694 size_t size, loff_t *pos)
696 struct amdgpu_device *adev = file_inode(f)->i_private;
699 uint32_t *config, no_regs = 0;
701 if (size & 0x3 || *pos & 0x3)
704 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
708 /* version, increment each time something is added */
709 config[no_regs++] = 3;
710 config[no_regs++] = adev->gfx.config.max_shader_engines;
711 config[no_regs++] = adev->gfx.config.max_tile_pipes;
712 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
713 config[no_regs++] = adev->gfx.config.max_sh_per_se;
714 config[no_regs++] = adev->gfx.config.max_backends_per_se;
715 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
716 config[no_regs++] = adev->gfx.config.max_gprs;
717 config[no_regs++] = adev->gfx.config.max_gs_threads;
718 config[no_regs++] = adev->gfx.config.max_hw_contexts;
719 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
720 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
721 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
722 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
723 config[no_regs++] = adev->gfx.config.num_tile_pipes;
724 config[no_regs++] = adev->gfx.config.backend_enable_mask;
725 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
726 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
727 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
728 config[no_regs++] = adev->gfx.config.num_gpus;
729 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
730 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
731 config[no_regs++] = adev->gfx.config.gb_addr_config;
732 config[no_regs++] = adev->gfx.config.num_rbs;
735 config[no_regs++] = adev->rev_id;
736 config[no_regs++] = adev->pg_flags;
737 config[no_regs++] = adev->cg_flags;
740 config[no_regs++] = adev->family;
741 config[no_regs++] = adev->external_rev_id;
744 config[no_regs++] = adev->pdev->device;
745 config[no_regs++] = adev->pdev->revision;
746 config[no_regs++] = adev->pdev->subsystem_device;
747 config[no_regs++] = adev->pdev->subsystem_vendor;
749 while (size && (*pos < no_regs * 4)) {
752 value = config[*pos >> 2];
753 r = put_user(value, (uint32_t *)buf);
770 * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
772 * @f: open file handle
773 * @buf: User buffer to store read data in
774 * @size: Number of bytes to read
775 * @pos: Offset to seek to
777 * The offset is treated as the BYTE address of one of the sensors
778 * enumerated in amd/include/kgd_pp_interface.h under the
779 * 'amd_pp_sensors' enumeration. For instance to read the UVD VCLK
780 * you would use the offset 3 * 4 = 12.
782 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
783 size_t size, loff_t *pos)
785 struct amdgpu_device *adev = file_inode(f)->i_private;
786 int idx, x, outsize, r, valuesize;
789 if (size & 3 || *pos & 0x3)
792 if (!adev->pm.dpm_enabled)
795 /* convert offset to sensor number */
798 valuesize = sizeof(values);
800 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
802 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
806 r = amdgpu_virt_enable_access_debugfs(adev);
808 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
812 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
814 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
815 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
818 amdgpu_virt_disable_access_debugfs(adev);
822 if (size > valuesize) {
823 amdgpu_virt_disable_access_debugfs(adev);
831 r = put_user(values[x++], (int32_t *)buf);
838 amdgpu_virt_disable_access_debugfs(adev);
839 return !r ? outsize : r;
842 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data
844 * @f: open file handle
845 * @buf: User buffer to store read data in
846 * @size: Number of bytes to read
847 * @pos: Offset to seek to
849 * The offset being sought changes which wave that the status data
850 * will be returned for. The bits are used as follows:
852 * Bits 0..6: Byte offset into data
853 * Bits 7..14: SE selector
854 * Bits 15..22: SH/SA selector
855 * Bits 23..30: CU/{WGP+SIMD} selector
856 * Bits 31..36: WAVE ID selector
857 * Bits 37..44: SIMD ID selector
859 * The returned data begins with one DWORD of version information
860 * Followed by WAVE STATUS registers relevant to the GFX IP version
861 * being used. See gfx_v8_0_read_wave_data() for an example output.
863 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
864 size_t size, loff_t *pos)
866 struct amdgpu_device *adev = f->f_inode->i_private;
869 uint32_t offset, se, sh, cu, wave, simd, data[32];
871 if (size & 3 || *pos & 3)
875 offset = (*pos & GENMASK_ULL(6, 0));
876 se = (*pos & GENMASK_ULL(14, 7)) >> 7;
877 sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
878 cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
879 wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
880 simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
882 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
884 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
888 r = amdgpu_virt_enable_access_debugfs(adev);
890 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
894 /* switch to the specific se/sh/cu */
895 mutex_lock(&adev->grbm_idx_mutex);
896 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
899 if (adev->gfx.funcs->read_wave_data)
900 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
902 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
903 mutex_unlock(&adev->grbm_idx_mutex);
905 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
906 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
909 amdgpu_virt_disable_access_debugfs(adev);
913 while (size && (offset < x * 4)) {
916 value = data[offset >> 2];
917 r = put_user(value, (uint32_t *)buf);
919 amdgpu_virt_disable_access_debugfs(adev);
929 amdgpu_virt_disable_access_debugfs(adev);
933 /** amdgpu_debugfs_gpr_read - Read wave gprs
935 * @f: open file handle
936 * @buf: User buffer to store read data in
937 * @size: Number of bytes to read
938 * @pos: Offset to seek to
940 * The offset being sought changes which wave that the status data
941 * will be returned for. The bits are used as follows:
943 * Bits 0..11: Byte offset into data
944 * Bits 12..19: SE selector
945 * Bits 20..27: SH/SA selector
946 * Bits 28..35: CU/{WGP+SIMD} selector
947 * Bits 36..43: WAVE ID selector
948 * Bits 37..44: SIMD ID selector
949 * Bits 52..59: Thread selector
950 * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
952 * The return data comes from the SGPR or VGPR register bank for
953 * the selected operational unit.
955 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
956 size_t size, loff_t *pos)
958 struct amdgpu_device *adev = f->f_inode->i_private;
961 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
963 if (size > 4096 || size & 3 || *pos & 3)
967 offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
968 se = (*pos & GENMASK_ULL(19, 12)) >> 12;
969 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
970 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
971 wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
972 simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
973 thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
974 bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
976 data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
980 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
984 r = amdgpu_virt_enable_access_debugfs(adev);
988 /* switch to the specific se/sh/cu */
989 mutex_lock(&adev->grbm_idx_mutex);
990 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
993 if (adev->gfx.funcs->read_wave_vgprs)
994 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
996 if (adev->gfx.funcs->read_wave_sgprs)
997 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
1000 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1001 mutex_unlock(&adev->grbm_idx_mutex);
1003 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1004 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1009 value = data[result >> 2];
1010 r = put_user(value, (uint32_t *)buf);
1012 amdgpu_virt_disable_access_debugfs(adev);
1022 amdgpu_virt_disable_access_debugfs(adev);
1026 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1032 * amdgpu_debugfs_regs_gfxoff_write - Enable/disable GFXOFF
1034 * @f: open file handle
1035 * @buf: User buffer to write data from
1036 * @size: Number of bytes to write
1037 * @pos: Offset to seek to
1039 * Write a 32-bit zero to disable or a 32-bit non-zero to enable
1041 static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf,
1042 size_t size, loff_t *pos)
1044 struct amdgpu_device *adev = file_inode(f)->i_private;
1048 if (size & 0x3 || *pos & 0x3)
1051 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1053 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1060 r = get_user(value, (uint32_t *)buf);
1062 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1063 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1067 amdgpu_gfx_off_ctrl(adev, value ? true : false);
1075 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1076 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1083 * amdgpu_debugfs_regs_gfxoff_status - read gfxoff status
1085 * @f: open file handle
1086 * @buf: User buffer to store read data in
1087 * @size: Number of bytes to read
1088 * @pos: Offset to seek to
1090 static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf,
1091 size_t size, loff_t *pos)
1093 struct amdgpu_device *adev = file_inode(f)->i_private;
1097 if (size & 0x3 || *pos & 0x3)
1100 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1107 r = amdgpu_get_gfx_off_status(adev, &value);
1109 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1110 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1114 r = put_user(value, (uint32_t *)buf);
1116 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1117 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1127 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1128 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1133 static const struct file_operations amdgpu_debugfs_regs_fops = {
1134 .owner = THIS_MODULE,
1135 .read = amdgpu_debugfs_regs_read,
1136 .write = amdgpu_debugfs_regs_write,
1137 .llseek = default_llseek
1139 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
1140 .owner = THIS_MODULE,
1141 .read = amdgpu_debugfs_regs_didt_read,
1142 .write = amdgpu_debugfs_regs_didt_write,
1143 .llseek = default_llseek
1145 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
1146 .owner = THIS_MODULE,
1147 .read = amdgpu_debugfs_regs_pcie_read,
1148 .write = amdgpu_debugfs_regs_pcie_write,
1149 .llseek = default_llseek
1151 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
1152 .owner = THIS_MODULE,
1153 .read = amdgpu_debugfs_regs_smc_read,
1154 .write = amdgpu_debugfs_regs_smc_write,
1155 .llseek = default_llseek
1158 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
1159 .owner = THIS_MODULE,
1160 .read = amdgpu_debugfs_gca_config_read,
1161 .llseek = default_llseek
1164 static const struct file_operations amdgpu_debugfs_sensors_fops = {
1165 .owner = THIS_MODULE,
1166 .read = amdgpu_debugfs_sensor_read,
1167 .llseek = default_llseek
1170 static const struct file_operations amdgpu_debugfs_wave_fops = {
1171 .owner = THIS_MODULE,
1172 .read = amdgpu_debugfs_wave_read,
1173 .llseek = default_llseek
1175 static const struct file_operations amdgpu_debugfs_gpr_fops = {
1176 .owner = THIS_MODULE,
1177 .read = amdgpu_debugfs_gpr_read,
1178 .llseek = default_llseek
1181 static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
1182 .owner = THIS_MODULE,
1183 .read = amdgpu_debugfs_gfxoff_read,
1184 .write = amdgpu_debugfs_gfxoff_write,
1185 .llseek = default_llseek
1188 static const struct file_operations *debugfs_regs[] = {
1189 &amdgpu_debugfs_regs_fops,
1190 &amdgpu_debugfs_regs_didt_fops,
1191 &amdgpu_debugfs_regs_pcie_fops,
1192 &amdgpu_debugfs_regs_smc_fops,
1193 &amdgpu_debugfs_gca_config_fops,
1194 &amdgpu_debugfs_sensors_fops,
1195 &amdgpu_debugfs_wave_fops,
1196 &amdgpu_debugfs_gpr_fops,
1197 &amdgpu_debugfs_gfxoff_fops,
1200 static const char *debugfs_regs_names[] = {
1205 "amdgpu_gca_config",
1213 * amdgpu_debugfs_regs_init - Initialize debugfs entries that provide
1216 * @adev: The device to attach the debugfs entries to
1218 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1220 struct drm_minor *minor = adev_to_drm(adev)->primary;
1221 struct dentry *ent, *root = minor->debugfs_root;
1224 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
1225 ent = debugfs_create_file(debugfs_regs_names[i],
1226 S_IFREG | S_IRUGO, root,
1227 adev, debugfs_regs[i]);
1228 if (!i && !IS_ERR_OR_NULL(ent))
1229 i_size_write(ent->d_inode, adev->rmmio_size);
1230 adev->debugfs_regs[i] = ent;
1236 static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
1238 struct drm_info_node *node = (struct drm_info_node *) m->private;
1239 struct drm_device *dev = node->minor->dev;
1240 struct amdgpu_device *adev = drm_to_adev(dev);
1243 r = pm_runtime_get_sync(dev->dev);
1245 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1249 /* Avoid accidently unparking the sched thread during GPU reset */
1250 r = down_read_killable(&adev->reset_sem);
1254 /* hold on the scheduler */
1255 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1256 struct amdgpu_ring *ring = adev->rings[i];
1258 if (!ring || !ring->sched.thread)
1260 kthread_park(ring->sched.thread);
1263 seq_printf(m, "run ib test:\n");
1264 r = amdgpu_ib_ring_tests(adev);
1266 seq_printf(m, "ib ring tests failed (%d).\n", r);
1268 seq_printf(m, "ib ring tests passed.\n");
1270 /* go on the scheduler */
1271 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1272 struct amdgpu_ring *ring = adev->rings[i];
1274 if (!ring || !ring->sched.thread)
1276 kthread_unpark(ring->sched.thread);
1279 up_read(&adev->reset_sem);
1281 pm_runtime_mark_last_busy(dev->dev);
1282 pm_runtime_put_autosuspend(dev->dev);
1287 static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
1289 struct drm_info_node *node = (struct drm_info_node *) m->private;
1290 struct drm_device *dev = node->minor->dev;
1291 struct amdgpu_device *adev = drm_to_adev(dev);
1293 seq_write(m, adev->bios, adev->bios_size);
1297 static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data)
1299 struct drm_info_node *node = (struct drm_info_node *)m->private;
1300 struct drm_device *dev = node->minor->dev;
1301 struct amdgpu_device *adev = drm_to_adev(dev);
1304 r = pm_runtime_get_sync(dev->dev);
1306 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1310 seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev));
1312 pm_runtime_mark_last_busy(dev->dev);
1313 pm_runtime_put_autosuspend(dev->dev);
1318 static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data)
1320 struct drm_info_node *node = (struct drm_info_node *)m->private;
1321 struct drm_device *dev = node->minor->dev;
1322 struct amdgpu_device *adev = drm_to_adev(dev);
1323 struct ttm_resource_manager *man;
1326 r = pm_runtime_get_sync(dev->dev);
1328 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1332 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
1333 r = ttm_resource_manager_evict_all(&adev->mman.bdev, man);
1334 seq_printf(m, "(%d)\n", r);
1336 pm_runtime_mark_last_busy(dev->dev);
1337 pm_runtime_put_autosuspend(dev->dev);
1342 static int amdgpu_debugfs_vm_info(struct seq_file *m, void *data)
1344 struct drm_info_node *node = (struct drm_info_node *)m->private;
1345 struct drm_device *dev = node->minor->dev;
1346 struct drm_file *file;
1349 r = mutex_lock_interruptible(&dev->filelist_mutex);
1353 list_for_each_entry(file, &dev->filelist, lhead) {
1354 struct amdgpu_fpriv *fpriv = file->driver_priv;
1355 struct amdgpu_vm *vm = &fpriv->vm;
1357 seq_printf(m, "pid:%d\tProcess:%s ----------\n",
1358 vm->task_info.pid, vm->task_info.process_name);
1359 r = amdgpu_bo_reserve(vm->root.base.bo, true);
1362 amdgpu_debugfs_vm_bo_info(vm, m);
1363 amdgpu_bo_unreserve(vm->root.base.bo);
1366 mutex_unlock(&dev->filelist_mutex);
1371 static const struct drm_info_list amdgpu_debugfs_list[] = {
1372 {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump},
1373 {"amdgpu_test_ib", &amdgpu_debugfs_test_ib},
1374 {"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram},
1375 {"amdgpu_evict_gtt", &amdgpu_debugfs_evict_gtt},
1376 {"amdgpu_vm_info", &amdgpu_debugfs_vm_info},
1379 static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
1380 struct dma_fence **fences)
1382 struct amdgpu_fence_driver *drv = &ring->fence_drv;
1383 uint32_t sync_seq, last_seq;
1385 last_seq = atomic_read(&ring->fence_drv.last_seq);
1386 sync_seq = ring->fence_drv.sync_seq;
1388 last_seq &= drv->num_fences_mask;
1389 sync_seq &= drv->num_fences_mask;
1392 struct dma_fence *fence, **ptr;
1395 last_seq &= drv->num_fences_mask;
1396 ptr = &drv->fences[last_seq];
1398 fence = rcu_dereference_protected(*ptr, 1);
1399 RCU_INIT_POINTER(*ptr, NULL);
1404 fences[last_seq] = fence;
1406 } while (last_seq != sync_seq);
1409 static void amdgpu_ib_preempt_signal_fences(struct dma_fence **fences,
1413 struct dma_fence *fence;
1415 for (i = 0; i < length; i++) {
1419 dma_fence_signal(fence);
1420 dma_fence_put(fence);
1424 static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched)
1426 struct drm_sched_job *s_job;
1427 struct dma_fence *fence;
1429 spin_lock(&sched->job_list_lock);
1430 list_for_each_entry(s_job, &sched->ring_mirror_list, node) {
1431 fence = sched->ops->run_job(s_job);
1432 dma_fence_put(fence);
1434 spin_unlock(&sched->job_list_lock);
1437 static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
1439 struct amdgpu_job *job;
1440 struct drm_sched_job *s_job, *tmp;
1441 uint32_t preempt_seq;
1442 struct dma_fence *fence, **ptr;
1443 struct amdgpu_fence_driver *drv = &ring->fence_drv;
1444 struct drm_gpu_scheduler *sched = &ring->sched;
1445 bool preempted = true;
1447 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
1450 preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
1451 if (preempt_seq <= atomic_read(&drv->last_seq)) {
1456 preempt_seq &= drv->num_fences_mask;
1457 ptr = &drv->fences[preempt_seq];
1458 fence = rcu_dereference_protected(*ptr, 1);
1461 spin_lock(&sched->job_list_lock);
1462 list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
1463 if (dma_fence_is_signaled(&s_job->s_fence->finished)) {
1464 /* remove job from ring_mirror_list */
1465 list_del_init(&s_job->node);
1466 sched->ops->free_job(s_job);
1469 job = to_amdgpu_job(s_job);
1470 if (preempted && job->fence == fence)
1471 /* mark the job as preempted */
1472 job->preemption_status |= AMDGPU_IB_PREEMPTED;
1474 spin_unlock(&sched->job_list_lock);
1477 static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
1479 int r, resched, length;
1480 struct amdgpu_ring *ring;
1481 struct dma_fence **fences = NULL;
1482 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1484 if (val >= AMDGPU_MAX_RINGS)
1487 ring = adev->rings[val];
1489 if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread)
1492 /* the last preemption failed */
1493 if (ring->trail_seq != le32_to_cpu(*ring->trail_fence_cpu_addr))
1496 length = ring->fence_drv.num_fences_mask + 1;
1497 fences = kcalloc(length, sizeof(void *), GFP_KERNEL);
1501 /* Avoid accidently unparking the sched thread during GPU reset */
1502 r = down_read_killable(&adev->reset_sem);
1506 /* stop the scheduler */
1507 kthread_park(ring->sched.thread);
1509 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1511 /* preempt the IB */
1512 r = amdgpu_ring_preempt_ib(ring);
1514 DRM_WARN("failed to preempt ring %d\n", ring->idx);
1518 amdgpu_fence_process(ring);
1520 if (atomic_read(&ring->fence_drv.last_seq) !=
1521 ring->fence_drv.sync_seq) {
1522 DRM_INFO("ring %d was preempted\n", ring->idx);
1524 amdgpu_ib_preempt_mark_partial_job(ring);
1526 /* swap out the old fences */
1527 amdgpu_ib_preempt_fences_swap(ring, fences);
1529 amdgpu_fence_driver_force_completion(ring);
1531 /* resubmit unfinished jobs */
1532 amdgpu_ib_preempt_job_recovery(&ring->sched);
1534 /* wait for jobs finished */
1535 amdgpu_fence_wait_empty(ring);
1537 /* signal the old fences */
1538 amdgpu_ib_preempt_signal_fences(fences, length);
1542 /* restart the scheduler */
1543 kthread_unpark(ring->sched.thread);
1545 up_read(&adev->reset_sem);
1547 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1555 static int amdgpu_debugfs_sclk_set(void *data, u64 val)
1558 uint32_t max_freq, min_freq;
1559 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1561 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1564 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1566 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1570 if (is_support_sw_smu(adev)) {
1571 ret = smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, &min_freq, &max_freq);
1572 if (ret || val > max_freq || val < min_freq)
1574 ret = smu_set_soft_freq_range(&adev->smu, SMU_SCLK, (uint32_t)val, (uint32_t)val);
1579 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1580 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1588 DEFINE_SIMPLE_ATTRIBUTE(fops_ib_preempt, NULL,
1589 amdgpu_debugfs_ib_preempt, "%llu\n");
1591 DEFINE_SIMPLE_ATTRIBUTE(fops_sclk_set, NULL,
1592 amdgpu_debugfs_sclk_set, "%llu\n");
1594 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1598 adev->debugfs_preempt =
1599 debugfs_create_file("amdgpu_preempt_ib", 0600,
1600 adev_to_drm(adev)->primary->debugfs_root, adev,
1602 if (!(adev->debugfs_preempt)) {
1603 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
1607 adev->smu.debugfs_sclk =
1608 debugfs_create_file("amdgpu_force_sclk", 0200,
1609 adev_to_drm(adev)->primary->debugfs_root, adev,
1611 if (!(adev->smu.debugfs_sclk)) {
1612 DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
1616 /* Register debugfs entries for amdgpu_ttm */
1617 r = amdgpu_ttm_debugfs_init(adev);
1619 DRM_ERROR("Failed to init debugfs\n");
1623 r = amdgpu_debugfs_pm_init(adev);
1625 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1629 if (amdgpu_debugfs_sa_init(adev)) {
1630 dev_err(adev->dev, "failed to register debugfs file for SA\n");
1633 if (amdgpu_debugfs_fence_init(adev))
1634 dev_err(adev->dev, "fence debugfs file creation failed\n");
1636 r = amdgpu_debugfs_gem_init(adev);
1638 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1640 r = amdgpu_debugfs_regs_init(adev);
1642 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1644 r = amdgpu_debugfs_firmware_init(adev);
1646 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1648 #if defined(CONFIG_DRM_AMD_DC)
1649 if (amdgpu_device_has_dc_support(adev)) {
1650 if (dtn_debugfs_init(adev))
1651 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
1655 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1656 struct amdgpu_ring *ring = adev->rings[i];
1661 if (amdgpu_debugfs_ring_init(adev, ring)) {
1662 DRM_ERROR("Failed to register debugfs file for rings !\n");
1666 amdgpu_ras_debugfs_create_all(adev);
1668 amdgpu_debugfs_autodump_init(adev);
1670 amdgpu_rap_debugfs_init(adev);
1672 amdgpu_fw_attestation_debugfs_init(adev);
1674 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list,
1675 ARRAY_SIZE(amdgpu_debugfs_list));
1679 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1683 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)