drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/kthread.h>
  27 #include <linux/pci.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include <drm/drm_debugfs.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35
  36 /**
  37  * amdgpu_debugfs_add_files - Add simple debugfs entries
  38  *
  39  * @adev:  Device to attach debugfs entries to
  40  * @files:  Array of function callbacks that respond to reads
  41  * @nfiles: Number of callbacks to register
  42  *
  43  */
  44 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
  45                              const struct drm_info_list *files,
  46                              unsigned nfiles)
  47 {
  48         unsigned i;
  49
  50         for (i = 0; i < adev->debugfs_count; i++) {
  51                 if (adev->debugfs[i].files == files) {
  52                         /* Already registered */
  53                         return 0;
  54                 }
  55         }
  56
  57         i = adev->debugfs_count + 1;
  58         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
  59                 DRM_ERROR("Reached maximum number of debugfs components.\n");
  60                 DRM_ERROR("Report so we increase "
  61                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
  62                 return -EINVAL;
  63         }
  64         adev->debugfs[adev->debugfs_count].files = files;
  65         adev->debugfs[adev->debugfs_count].num_files = nfiles;
  66         adev->debugfs_count = i;
  67 #if defined(CONFIG_DEBUG_FS)
  68         drm_debugfs_create_files(files, nfiles,
  69                                  adev->ddev->primary->debugfs_root,
  70                                  adev->ddev->primary);
  71 #endif
  72         return 0;
  73 }
  74
  75 #if defined(CONFIG_DEBUG_FS)
  76
  77 /**
  78  * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
  79  *
  80  * @read: True if reading
  81  * @f: open file handle
  82  * @buf: User buffer to write/read to
  83  * @size: Number of bytes to write/read
  84  * @pos:  Offset to seek to
  85  *
  86  * This debugfs entry has special meaning on the offset being sought.
  87  * Various bits have different meanings:
  88  *
  89  * Bit 62:  Indicates a GRBM bank switch is needed
  90  * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is
  91  *                      zero)
  92  * Bits 24..33: The SE or ME selector if needed
  93  * Bits 34..43: The SH (or SA) or PIPE selector if needed
  94  * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
  95  *
  96  * Bit 23:  Indicates that the PM power gating lock should be held
  97  *                      This is necessary to read registers that might be
  98  *                      unreliable during a power gating transistion.
  99  *
 100  * The lower bits are the BYTE offset of the register to read.  This
 101  * allows reading multiple registers in a single call and having
 102  * the returned size reflect that.
 103  */
 104 static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,
 105                 char __user *buf, size_t size, loff_t *pos)
 106 {
 107         struct amdgpu_device *adev = file_inode(f)->i_private;
 108         ssize_t result = 0;
 109         int r;
 110         bool pm_pg_lock, use_bank, use_ring;
 111         unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
 112
 113         pm_pg_lock = use_bank = use_ring = false;
 114         instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
 115
 116         if (size & 0x3 || *pos & 0x3 ||
 117                         ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
 118                 return -EINVAL;
 119
 120         /* are we reading registers for which a PG lock is necessary? */
 121         pm_pg_lock = (*pos >> 23) & 1;
 122
 123         if (*pos & (1ULL << 62)) {
 124                 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
 125                 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
 126                 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
 127
 128                 if (se_bank == 0x3FF)
 129                         se_bank = 0xFFFFFFFF;
 130                 if (sh_bank == 0x3FF)
 131                         sh_bank = 0xFFFFFFFF;
 132                 if (instance_bank == 0x3FF)
 133                         instance_bank = 0xFFFFFFFF;
 134                 use_bank = true;
 135         } else if (*pos & (1ULL << 61)) {
 136
 137                 me = (*pos & GENMASK_ULL(33, 24)) >> 24;
 138                 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
 139                 queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
 140                 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
 141
 142                 use_ring = true;
 143         } else {
 144                 use_bank = use_ring = false;
 145         }
 146
 147         *pos &= (1UL << 22) - 1;
 148
 149         r = pm_runtime_get_sync(adev->ddev->dev);
 150         if (r < 0)
 151                 return r;
 152
 153         if (use_bank) {
 154                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
 155                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
 156                         pm_runtime_mark_last_busy(adev->ddev->dev);
 157                         pm_runtime_put_autosuspend(adev->ddev->dev);
 158                         return -EINVAL;
 159                 }
 160                 mutex_lock(&adev->grbm_idx_mutex);
 161                 amdgpu_gfx_select_se_sh(adev, se_bank,
 162                                         sh_bank, instance_bank);
 163         } else if (use_ring) {
 164                 mutex_lock(&adev->srbm_mutex);
 165                 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
 166         }
 167
 168         if (pm_pg_lock)
 169                 mutex_lock(&adev->pm.mutex);
 170
 171         while (size) {
 172                 uint32_t value;
 173
 174                 if (read) {
 175                         value = RREG32(*pos >> 2);
 176                         r = put_user(value, (uint32_t *)buf);
 177                 } else {
 178                         r = get_user(value, (uint32_t *)buf);
 179                         if (!r)
 180                                 WREG32(*pos >> 2, value);
 181                 }
 182                 if (r) {
 183                         result = r;
 184                         goto end;
 185                 }
 186
 187                 result += 4;
 188                 buf += 4;
 189                 *pos += 4;
 190                 size -= 4;
 191         }
 192
 193 end:
 194         if (use_bank) {
 195                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 196                 mutex_unlock(&adev->grbm_idx_mutex);
 197         } else if (use_ring) {
 198                 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
 199                 mutex_unlock(&adev->srbm_mutex);
 200         }
 201
 202         if (pm_pg_lock)
 203                 mutex_unlock(&adev->pm.mutex);
 204
 205         pm_runtime_mark_last_busy(adev->ddev->dev);
 206         pm_runtime_put_autosuspend(adev->ddev->dev);
 207
 208         return result;
 209 }
 210
 211 /**
 212  * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
 213  */
 214 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
 215                                         size_t size, loff_t *pos)
 216 {
 217         return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
 218 }
 219
 220 /**
 221  * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
 222  */
 223 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
 224                                          size_t size, loff_t *pos)
 225 {
 226         return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
 227 }
 228
 229
 230 /**
 231  * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
 232  *
 233  * @f: open file handle
 234  * @buf: User buffer to store read data in
 235  * @size: Number of bytes to read
 236  * @pos:  Offset to seek to
 237  *
 238  * The lower bits are the BYTE offset of the register to read.  This
 239  * allows reading multiple registers in a single call and having
 240  * the returned size reflect that.
 241  */
 242 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
 243                                         size_t size, loff_t *pos)
 244 {
 245         struct amdgpu_device *adev = file_inode(f)->i_private;
 246         ssize_t result = 0;
 247         int r;
 248
 249         if (size & 0x3 || *pos & 0x3)
 250                 return -EINVAL;
 251
 252         r = pm_runtime_get_sync(adev->ddev->dev);
 253         if (r < 0)
 254                 return r;
 255
 256         while (size) {
 257                 uint32_t value;
 258
 259                 value = RREG32_PCIE(*pos >> 2);
 260                 r = put_user(value, (uint32_t *)buf);
 261                 if (r) {
 262                         pm_runtime_mark_last_busy(adev->ddev->dev);
 263                         pm_runtime_put_autosuspend(adev->ddev->dev);
 264                         return r;
 265                 }
 266
 267                 result += 4;
 268                 buf += 4;
 269                 *pos += 4;
 270                 size -= 4;
 271         }
 272
 273         pm_runtime_mark_last_busy(adev->ddev->dev);
 274         pm_runtime_put_autosuspend(adev->ddev->dev);
 275
 276         return result;
 277 }
 278
 279 /**
 280  * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
 281  *
 282  * @f: open file handle
 283  * @buf: User buffer to write data from
 284  * @size: Number of bytes to write
 285  * @pos:  Offset to seek to
 286  *
 287  * The lower bits are the BYTE offset of the register to write.  This
 288  * allows writing multiple registers in a single call and having
 289  * the returned size reflect that.
 290  */
 291 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
 292                                          size_t size, loff_t *pos)
 293 {
 294         struct amdgpu_device *adev = file_inode(f)->i_private;
 295         ssize_t result = 0;
 296         int r;
 297
 298         if (size & 0x3 || *pos & 0x3)
 299                 return -EINVAL;
 300
 301         r = pm_runtime_get_sync(adev->ddev->dev);
 302         if (r < 0)
 303                 return r;
 304
 305         while (size) {
 306                 uint32_t value;
 307
 308                 r = get_user(value, (uint32_t *)buf);
 309                 if (r) {
 310                         pm_runtime_mark_last_busy(adev->ddev->dev);
 311                         pm_runtime_put_autosuspend(adev->ddev->dev);
 312                         return r;
 313                 }
 314
 315                 WREG32_PCIE(*pos >> 2, value);
 316
 317                 result += 4;
 318                 buf += 4;
 319                 *pos += 4;
 320                 size -= 4;
 321         }
 322
 323         pm_runtime_mark_last_busy(adev->ddev->dev);
 324         pm_runtime_put_autosuspend(adev->ddev->dev);
 325
 326         return result;
 327 }
 328
 329 /**
 330  * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
 331  *
 332  * @f: open file handle
 333  * @buf: User buffer to store read data in
 334  * @size: Number of bytes to read
 335  * @pos:  Offset to seek to
 336  *
 337  * The lower bits are the BYTE offset of the register to read.  This
 338  * allows reading multiple registers in a single call and having
 339  * the returned size reflect that.
 340  */
 341 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
 342                                         size_t size, loff_t *pos)
 343 {
 344         struct amdgpu_device *adev = file_inode(f)->i_private;
 345         ssize_t result = 0;
 346         int r;
 347
 348         if (size & 0x3 || *pos & 0x3)
 349                 return -EINVAL;
 350
 351         r = pm_runtime_get_sync(adev->ddev->dev);
 352         if (r < 0)
 353                 return r;
 354
 355         while (size) {
 356                 uint32_t value;
 357
 358                 value = RREG32_DIDT(*pos >> 2);
 359                 r = put_user(value, (uint32_t *)buf);
 360                 if (r) {
 361                         pm_runtime_mark_last_busy(adev->ddev->dev);
 362                         pm_runtime_put_autosuspend(adev->ddev->dev);
 363                         return r;
 364                 }
 365
 366                 result += 4;
 367                 buf += 4;
 368                 *pos += 4;
 369                 size -= 4;
 370         }
 371
 372         pm_runtime_mark_last_busy(adev->ddev->dev);
 373         pm_runtime_put_autosuspend(adev->ddev->dev);
 374
 375         return result;
 376 }
 377
 378 /**
 379  * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
 380  *
 381  * @f: open file handle
 382  * @buf: User buffer to write data from
 383  * @size: Number of bytes to write
 384  * @pos:  Offset to seek to
 385  *
 386  * The lower bits are the BYTE offset of the register to write.  This
 387  * allows writing multiple registers in a single call and having
 388  * the returned size reflect that.
 389  */
 390 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
 391                                          size_t size, loff_t *pos)
 392 {
 393         struct amdgpu_device *adev = file_inode(f)->i_private;
 394         ssize_t result = 0;
 395         int r;
 396
 397         if (size & 0x3 || *pos & 0x3)
 398                 return -EINVAL;
 399
 400         r = pm_runtime_get_sync(adev->ddev->dev);
 401         if (r < 0)
 402                 return r;
 403
 404         while (size) {
 405                 uint32_t value;
 406
 407                 r = get_user(value, (uint32_t *)buf);
 408                 if (r) {
 409                         pm_runtime_mark_last_busy(adev->ddev->dev);
 410                         pm_runtime_put_autosuspend(adev->ddev->dev);
 411                         return r;
 412                 }
 413
 414                 WREG32_DIDT(*pos >> 2, value);
 415
 416                 result += 4;
 417                 buf += 4;
 418                 *pos += 4;
 419                 size -= 4;
 420         }
 421
 422         pm_runtime_mark_last_busy(adev->ddev->dev);
 423         pm_runtime_put_autosuspend(adev->ddev->dev);
 424
 425         return result;
 426 }
 427
 428 /**
 429  * amdgpu_debugfs_regs_smc_read - Read from a SMC register
 430  *
 431  * @f: open file handle
 432  * @buf: User buffer to store read data in
 433  * @size: Number of bytes to read
 434  * @pos:  Offset to seek to
 435  *
 436  * The lower bits are the BYTE offset of the register to read.  This
 437  * allows reading multiple registers in a single call and having
 438  * the returned size reflect that.
 439  */
 440 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
 441                                         size_t size, loff_t *pos)
 442 {
 443         struct amdgpu_device *adev = file_inode(f)->i_private;
 444         ssize_t result = 0;
 445         int r;
 446
 447         if (size & 0x3 || *pos & 0x3)
 448                 return -EINVAL;
 449
 450         r = pm_runtime_get_sync(adev->ddev->dev);
 451         if (r < 0)
 452                 return r;
 453
 454         while (size) {
 455                 uint32_t value;
 456
 457                 value = RREG32_SMC(*pos);
 458                 r = put_user(value, (uint32_t *)buf);
 459                 if (r) {
 460                         pm_runtime_mark_last_busy(adev->ddev->dev);
 461                         pm_runtime_put_autosuspend(adev->ddev->dev);
 462                         return r;
 463                 }
 464
 465                 result += 4;
 466                 buf += 4;
 467                 *pos += 4;
 468                 size -= 4;
 469         }
 470
 471         pm_runtime_mark_last_busy(adev->ddev->dev);
 472         pm_runtime_put_autosuspend(adev->ddev->dev);
 473
 474         return result;
 475 }
 476
 477 /**
 478  * amdgpu_debugfs_regs_smc_write - Write to a SMC register
 479  *
 480  * @f: open file handle
 481  * @buf: User buffer to write data from
 482  * @size: Number of bytes to write
 483  * @pos:  Offset to seek to
 484  *
 485  * The lower bits are the BYTE offset of the register to write.  This
 486  * allows writing multiple registers in a single call and having
 487  * the returned size reflect that.
 488  */
 489 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
 490                                          size_t size, loff_t *pos)
 491 {
 492         struct amdgpu_device *adev = file_inode(f)->i_private;
 493         ssize_t result = 0;
 494         int r;
 495
 496         if (size & 0x3 || *pos & 0x3)
 497                 return -EINVAL;
 498
 499         r = pm_runtime_get_sync(adev->ddev->dev);
 500         if (r < 0)
 501                 return r;
 502
 503         while (size) {
 504                 uint32_t value;
 505
 506                 r = get_user(value, (uint32_t *)buf);
 507                 if (r) {
 508                         pm_runtime_mark_last_busy(adev->ddev->dev);
 509                         pm_runtime_put_autosuspend(adev->ddev->dev);
 510                         return r;
 511                 }
 512
 513                 WREG32_SMC(*pos, value);
 514
 515                 result += 4;
 516                 buf += 4;
 517                 *pos += 4;
 518                 size -= 4;
 519         }
 520
 521         pm_runtime_mark_last_busy(adev->ddev->dev);
 522         pm_runtime_put_autosuspend(adev->ddev->dev);
 523
 524         return result;
 525 }
 526
 527 /**
 528  * amdgpu_debugfs_gca_config_read - Read from gfx config data
 529  *
 530  * @f: open file handle
 531  * @buf: User buffer to store read data in
 532  * @size: Number of bytes to read
 533  * @pos:  Offset to seek to
 534  *
 535  * This file is used to access configuration data in a somewhat
 536  * stable fashion.  The format is a series of DWORDs with the first
 537  * indicating which revision it is.  New content is appended to the
 538  * end so that older software can still read the data.
 539  */
 540
 541 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
 542                                         size_t size, loff_t *pos)
 543 {
 544         struct amdgpu_device *adev = file_inode(f)->i_private;
 545         ssize_t result = 0;
 546         int r;
 547         uint32_t *config, no_regs = 0;
 548
 549         if (size & 0x3 || *pos & 0x3)
 550                 return -EINVAL;
 551
 552         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
 553         if (!config)
 554                 return -ENOMEM;
 555
 556         /* version, increment each time something is added */
 557         config[no_regs++] = 3;
 558         config[no_regs++] = adev->gfx.config.max_shader_engines;
 559         config[no_regs++] = adev->gfx.config.max_tile_pipes;
 560         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
 561         config[no_regs++] = adev->gfx.config.max_sh_per_se;
 562         config[no_regs++] = adev->gfx.config.max_backends_per_se;
 563         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
 564         config[no_regs++] = adev->gfx.config.max_gprs;
 565         config[no_regs++] = adev->gfx.config.max_gs_threads;
 566         config[no_regs++] = adev->gfx.config.max_hw_contexts;
 567         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
 568         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
 569         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
 570         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
 571         config[no_regs++] = adev->gfx.config.num_tile_pipes;
 572         config[no_regs++] = adev->gfx.config.backend_enable_mask;
 573         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
 574         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
 575         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
 576         config[no_regs++] = adev->gfx.config.num_gpus;
 577         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
 578         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
 579         config[no_regs++] = adev->gfx.config.gb_addr_config;
 580         config[no_regs++] = adev->gfx.config.num_rbs;
 581
 582         /* rev==1 */
 583         config[no_regs++] = adev->rev_id;
 584         config[no_regs++] = adev->pg_flags;
 585         config[no_regs++] = adev->cg_flags;
 586
 587         /* rev==2 */
 588         config[no_regs++] = adev->family;
 589         config[no_regs++] = adev->external_rev_id;
 590
 591         /* rev==3 */
 592         config[no_regs++] = adev->pdev->device;
 593         config[no_regs++] = adev->pdev->revision;
 594         config[no_regs++] = adev->pdev->subsystem_device;
 595         config[no_regs++] = adev->pdev->subsystem_vendor;
 596
 597         while (size && (*pos < no_regs * 4)) {
 598                 uint32_t value;
 599
 600                 value = config[*pos >> 2];
 601                 r = put_user(value, (uint32_t *)buf);
 602                 if (r) {
 603                         kfree(config);
 604                         return r;
 605                 }
 606
 607                 result += 4;
 608                 buf += 4;
 609                 *pos += 4;
 610                 size -= 4;
 611         }
 612
 613         kfree(config);
 614         return result;
 615 }
 616
 617 /**
 618  * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
 619  *
 620  * @f: open file handle
 621  * @buf: User buffer to store read data in
 622  * @size: Number of bytes to read
 623  * @pos:  Offset to seek to
 624  *
 625  * The offset is treated as the BYTE address of one of the sensors
 626  * enumerated in amd/include/kgd_pp_interface.h under the
 627  * 'amd_pp_sensors' enumeration.  For instance to read the UVD VCLK
 628  * you would use the offset 3 * 4 = 12.
 629  */
 630 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
 631                                         size_t size, loff_t *pos)
 632 {
 633         struct amdgpu_device *adev = file_inode(f)->i_private;
 634         int idx, x, outsize, r, valuesize;
 635         uint32_t values[16];
 636
 637         if (size & 3 || *pos & 0x3)
 638                 return -EINVAL;
 639
 640         if (!adev->pm.dpm_enabled)
 641                 return -EINVAL;
 642
 643         /* convert offset to sensor number */
 644         idx = *pos >> 2;
 645
 646         valuesize = sizeof(values);
 647
 648         r = pm_runtime_get_sync(adev->ddev->dev);
 649         if (r < 0)
 650                 return r;
 651
 652         r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
 653
 654         pm_runtime_mark_last_busy(adev->ddev->dev);
 655         pm_runtime_put_autosuspend(adev->ddev->dev);
 656
 657         if (r)
 658                 return r;
 659
 660         if (size > valuesize)
 661                 return -EINVAL;
 662
 663         outsize = 0;
 664         x = 0;
 665         if (!r) {
 666                 while (size) {
 667                         r = put_user(values[x++], (int32_t *)buf);
 668                         buf += 4;
 669                         size -= 4;
 670                         outsize += 4;
 671                 }
 672         }
 673
 674         return !r ? outsize : r;
 675 }
 676
 677 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data
 678  *
 679  * @f: open file handle
 680  * @buf: User buffer to store read data in
 681  * @size: Number of bytes to read
 682  * @pos:  Offset to seek to
 683  *
 684  * The offset being sought changes which wave that the status data
 685  * will be returned for.  The bits are used as follows:
 686  *
 687  * Bits 0..6:   Byte offset into data
 688  * Bits 7..14:  SE selector
 689  * Bits 15..22: SH/SA selector
 690  * Bits 23..30: CU/{WGP+SIMD} selector
 691  * Bits 31..36: WAVE ID selector
 692  * Bits 37..44: SIMD ID selector
 693  *
 694  * The returned data begins with one DWORD of version information
 695  * Followed by WAVE STATUS registers relevant to the GFX IP version
 696  * being used.  See gfx_v8_0_read_wave_data() for an example output.
 697  */
 698 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
 699                                         size_t size, loff_t *pos)
 700 {
 701         struct amdgpu_device *adev = f->f_inode->i_private;
 702         int r, x;
 703         ssize_t result=0;
 704         uint32_t offset, se, sh, cu, wave, simd, data[32];
 705
 706         if (size & 3 || *pos & 3)
 707                 return -EINVAL;
 708
 709         /* decode offset */
 710         offset = (*pos & GENMASK_ULL(6, 0));
 711         se = (*pos & GENMASK_ULL(14, 7)) >> 7;
 712         sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
 713         cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
 714         wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
 715         simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
 716
 717         r = pm_runtime_get_sync(adev->ddev->dev);
 718         if (r < 0)
 719                 return r;
 720
 721         /* switch to the specific se/sh/cu */
 722         mutex_lock(&adev->grbm_idx_mutex);
 723         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
 724
 725         x = 0;
 726         if (adev->gfx.funcs->read_wave_data)
 727                 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
 728
 729         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
 730         mutex_unlock(&adev->grbm_idx_mutex);
 731
 732         pm_runtime_mark_last_busy(adev->ddev->dev);
 733         pm_runtime_put_autosuspend(adev->ddev->dev);
 734
 735         if (!x)
 736                 return -EINVAL;
 737
 738         while (size && (offset < x * 4)) {
 739                 uint32_t value;
 740
 741                 value = data[offset >> 2];
 742                 r = put_user(value, (uint32_t *)buf);
 743                 if (r)
 744                         return r;
 745
 746                 result += 4;
 747                 buf += 4;
 748                 offset += 4;
 749                 size -= 4;
 750         }
 751
 752         return result;
 753 }
 754
 755 /** amdgpu_debugfs_gpr_read - Read wave gprs
 756  *
 757  * @f: open file handle
 758  * @buf: User buffer to store read data in
 759  * @size: Number of bytes to read
 760  * @pos:  Offset to seek to
 761  *
 762  * The offset being sought changes which wave that the status data
 763  * will be returned for.  The bits are used as follows:
 764  *
 765  * Bits 0..11:  Byte offset into data
 766  * Bits 12..19: SE selector
 767  * Bits 20..27: SH/SA selector
 768  * Bits 28..35: CU/{WGP+SIMD} selector
 769  * Bits 36..43: WAVE ID selector
 770  * Bits 37..44: SIMD ID selector
 771  * Bits 52..59: Thread selector
 772  * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
 773  *
 774  * The return data comes from the SGPR or VGPR register bank for
 775  * the selected operational unit.
 776  */
 777 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
 778                                         size_t size, loff_t *pos)
 779 {
 780         struct amdgpu_device *adev = f->f_inode->i_private;
 781         int r;
 782         ssize_t result = 0;
 783         uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
 784
 785         if (size & 3 || *pos & 3)
 786                 return -EINVAL;
 787
 788         /* decode offset */
 789         offset = *pos & GENMASK_ULL(11, 0);
 790         se = (*pos & GENMASK_ULL(19, 12)) >> 12;
 791         sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
 792         cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
 793         wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
 794         simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
 795         thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
 796         bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
 797
 798         data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
 799         if (!data)
 800                 return -ENOMEM;
 801
 802         r = pm_runtime_get_sync(adev->ddev->dev);
 803         if (r < 0)
 804                 return r;
 805
 806         /* switch to the specific se/sh/cu */
 807         mutex_lock(&adev->grbm_idx_mutex);
 808         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
 809
 810         if (bank == 0) {
 811                 if (adev->gfx.funcs->read_wave_vgprs)
 812                         adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
 813         } else {
 814                 if (adev->gfx.funcs->read_wave_sgprs)
 815                         adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
 816         }
 817
 818         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
 819         mutex_unlock(&adev->grbm_idx_mutex);
 820
 821         pm_runtime_mark_last_busy(adev->ddev->dev);
 822         pm_runtime_put_autosuspend(adev->ddev->dev);
 823
 824         while (size) {
 825                 uint32_t value;
 826
 827                 value = data[offset++];
 828                 r = put_user(value, (uint32_t *)buf);
 829                 if (r) {
 830                         result = r;
 831                         goto err;
 832                 }
 833
 834                 result += 4;
 835                 buf += 4;
 836                 size -= 4;
 837         }
 838
 839 err:
 840         kfree(data);
 841         return result;
 842 }
 843
 844 /**
 845  * amdgpu_debugfs_regs_gfxoff_write - Enable/disable GFXOFF
 846  *
 847  * @f: open file handle
 848  * @buf: User buffer to write data from
 849  * @size: Number of bytes to write
 850  * @pos:  Offset to seek to
 851  *
 852  * Write a 32-bit zero to disable or a 32-bit non-zero to enable
 853  */
 854 static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf,
 855                                          size_t size, loff_t *pos)
 856 {
 857         struct amdgpu_device *adev = file_inode(f)->i_private;
 858         ssize_t result = 0;
 859         int r;
 860
 861         if (size & 0x3 || *pos & 0x3)
 862                 return -EINVAL;
 863
 864         r = pm_runtime_get_sync(adev->ddev->dev);
 865         if (r < 0)
 866                 return r;
 867
 868         while (size) {
 869                 uint32_t value;
 870
 871                 r = get_user(value, (uint32_t *)buf);
 872                 if (r) {
 873                         pm_runtime_mark_last_busy(adev->ddev->dev);
 874                         pm_runtime_put_autosuspend(adev->ddev->dev);
 875                         return r;
 876                 }
 877
 878                 amdgpu_gfx_off_ctrl(adev, value ? true : false);
 879
 880                 result += 4;
 881                 buf += 4;
 882                 *pos += 4;
 883                 size -= 4;
 884         }
 885
 886         pm_runtime_mark_last_busy(adev->ddev->dev);
 887         pm_runtime_put_autosuspend(adev->ddev->dev);
 888
 889         return result;
 890 }
 891
 892
 893 static const struct file_operations amdgpu_debugfs_regs_fops = {
 894         .owner = THIS_MODULE,
 895         .read = amdgpu_debugfs_regs_read,
 896         .write = amdgpu_debugfs_regs_write,
 897         .llseek = default_llseek
 898 };
 899 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
 900         .owner = THIS_MODULE,
 901         .read = amdgpu_debugfs_regs_didt_read,
 902         .write = amdgpu_debugfs_regs_didt_write,
 903         .llseek = default_llseek
 904 };
 905 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
 906         .owner = THIS_MODULE,
 907         .read = amdgpu_debugfs_regs_pcie_read,
 908         .write = amdgpu_debugfs_regs_pcie_write,
 909         .llseek = default_llseek
 910 };
 911 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
 912         .owner = THIS_MODULE,
 913         .read = amdgpu_debugfs_regs_smc_read,
 914         .write = amdgpu_debugfs_regs_smc_write,
 915         .llseek = default_llseek
 916 };
 917
 918 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
 919         .owner = THIS_MODULE,
 920         .read = amdgpu_debugfs_gca_config_read,
 921         .llseek = default_llseek
 922 };
 923
 924 static const struct file_operations amdgpu_debugfs_sensors_fops = {
 925         .owner = THIS_MODULE,
 926         .read = amdgpu_debugfs_sensor_read,
 927         .llseek = default_llseek
 928 };
 929
 930 static const struct file_operations amdgpu_debugfs_wave_fops = {
 931         .owner = THIS_MODULE,
 932         .read = amdgpu_debugfs_wave_read,
 933         .llseek = default_llseek
 934 };
 935 static const struct file_operations amdgpu_debugfs_gpr_fops = {
 936         .owner = THIS_MODULE,
 937         .read = amdgpu_debugfs_gpr_read,
 938         .llseek = default_llseek
 939 };
 940
 941 static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
 942         .owner = THIS_MODULE,
 943         .write = amdgpu_debugfs_gfxoff_write,
 944 };
 945
 946 static const struct file_operations *debugfs_regs[] = {
 947         &amdgpu_debugfs_regs_fops,
 948         &amdgpu_debugfs_regs_didt_fops,
 949         &amdgpu_debugfs_regs_pcie_fops,
 950         &amdgpu_debugfs_regs_smc_fops,
 951         &amdgpu_debugfs_gca_config_fops,
 952         &amdgpu_debugfs_sensors_fops,
 953         &amdgpu_debugfs_wave_fops,
 954         &amdgpu_debugfs_gpr_fops,
 955         &amdgpu_debugfs_gfxoff_fops,
 956 };
 957
 958 static const char *debugfs_regs_names[] = {
 959         "amdgpu_regs",
 960         "amdgpu_regs_didt",
 961         "amdgpu_regs_pcie",
 962         "amdgpu_regs_smc",
 963         "amdgpu_gca_config",
 964         "amdgpu_sensors",
 965         "amdgpu_wave",
 966         "amdgpu_gpr",
 967         "amdgpu_gfxoff",
 968 };
 969
 970 /**
 971  * amdgpu_debugfs_regs_init -   Initialize debugfs entries that provide
 972  *                                                              register access.
 973  *
 974  * @adev: The device to attach the debugfs entries to
 975  */
 976 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
 977 {
 978         struct drm_minor *minor = adev->ddev->primary;
 979         struct dentry *ent, *root = minor->debugfs_root;
 980         unsigned int i;
 981
 982         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
 983                 ent = debugfs_create_file(debugfs_regs_names[i],
 984                                           S_IFREG | S_IRUGO, root,
 985                                           adev, debugfs_regs[i]);
 986                 if (!i && !IS_ERR_OR_NULL(ent))
 987                         i_size_write(ent->d_inode, adev->rmmio_size);
 988                 adev->debugfs_regs[i] = ent;
 989         }
 990
 991         return 0;
 992 }
 993
 994 void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
 995 {
 996         unsigned i;
 997
 998         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
 999                 if (adev->debugfs_regs[i]) {
1000                         debugfs_remove(adev->debugfs_regs[i]);
1001                         adev->debugfs_regs[i] = NULL;
1002                 }
1003         }
1004 }
1005
1006 static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
1007 {
1008         struct drm_info_node *node = (struct drm_info_node *) m->private;
1009         struct drm_device *dev = node->minor->dev;
1010         struct amdgpu_device *adev = dev->dev_private;
1011         int r = 0, i;
1012
1013         r = pm_runtime_get_sync(dev->dev);
1014         if (r < 0)
1015                 return r;
1016
1017         /* Avoid accidently unparking the sched thread during GPU reset */
1018         mutex_lock(&adev->lock_reset);
1019
1020         /* hold on the scheduler */
1021         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1022                 struct amdgpu_ring *ring = adev->rings[i];
1023
1024                 if (!ring || !ring->sched.thread)
1025                         continue;
1026                 kthread_park(ring->sched.thread);
1027         }
1028
1029         seq_printf(m, "run ib test:\n");
1030         r = amdgpu_ib_ring_tests(adev);
1031         if (r)
1032                 seq_printf(m, "ib ring tests failed (%d).\n", r);
1033         else
1034                 seq_printf(m, "ib ring tests passed.\n");
1035
1036         /* go on the scheduler */
1037         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1038                 struct amdgpu_ring *ring = adev->rings[i];
1039
1040                 if (!ring || !ring->sched.thread)
1041                         continue;
1042                 kthread_unpark(ring->sched.thread);
1043         }
1044
1045         mutex_unlock(&adev->lock_reset);
1046
1047         pm_runtime_mark_last_busy(dev->dev);
1048         pm_runtime_put_autosuspend(dev->dev);
1049
1050         return 0;
1051 }
1052
1053 static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
1054 {
1055         struct drm_info_node *node = (struct drm_info_node *) m->private;
1056         struct drm_device *dev = node->minor->dev;
1057         struct amdgpu_device *adev = dev->dev_private;
1058
1059         seq_write(m, adev->bios, adev->bios_size);
1060         return 0;
1061 }
1062
1063 static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data)
1064 {
1065         struct drm_info_node *node = (struct drm_info_node *)m->private;
1066         struct drm_device *dev = node->minor->dev;
1067         struct amdgpu_device *adev = dev->dev_private;
1068         int r;
1069
1070         r = pm_runtime_get_sync(dev->dev);
1071         if (r < 0)
1072                 return r;
1073
1074         seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev));
1075
1076         pm_runtime_mark_last_busy(dev->dev);
1077         pm_runtime_put_autosuspend(dev->dev);
1078
1079         return 0;
1080 }
1081
1082 static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data)
1083 {
1084         struct drm_info_node *node = (struct drm_info_node *)m->private;
1085         struct drm_device *dev = node->minor->dev;
1086         struct amdgpu_device *adev = dev->dev_private;
1087         int r;
1088
1089         r = pm_runtime_get_sync(dev->dev);
1090         if (r < 0)
1091                 return r;
1092
1093         seq_printf(m, "(%d)\n", ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_TT));
1094
1095         pm_runtime_mark_last_busy(dev->dev);
1096         pm_runtime_put_autosuspend(dev->dev);
1097
1098         return 0;
1099 }
1100
1101 static const struct drm_info_list amdgpu_debugfs_list[] = {
1102         {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump},
1103         {"amdgpu_test_ib", &amdgpu_debugfs_test_ib},
1104         {"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram},
1105         {"amdgpu_evict_gtt", &amdgpu_debugfs_evict_gtt},
1106 };
1107
1108 static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
1109                                           struct dma_fence **fences)
1110 {
1111         struct amdgpu_fence_driver *drv = &ring->fence_drv;
1112         uint32_t sync_seq, last_seq;
1113
1114         last_seq = atomic_read(&ring->fence_drv.last_seq);
1115         sync_seq = ring->fence_drv.sync_seq;
1116
1117         last_seq &= drv->num_fences_mask;
1118         sync_seq &= drv->num_fences_mask;
1119
1120         do {
1121                 struct dma_fence *fence, **ptr;
1122
1123                 ++last_seq;
1124                 last_seq &= drv->num_fences_mask;
1125                 ptr = &drv->fences[last_seq];
1126
1127                 fence = rcu_dereference_protected(*ptr, 1);
1128                 RCU_INIT_POINTER(*ptr, NULL);
1129
1130                 if (!fence)
1131                         continue;
1132
1133                 fences[last_seq] = fence;
1134
1135         } while (last_seq != sync_seq);
1136 }
1137
1138 static void amdgpu_ib_preempt_signal_fences(struct dma_fence **fences,
1139                                             int length)
1140 {
1141         int i;
1142         struct dma_fence *fence;
1143
1144         for (i = 0; i < length; i++) {
1145                 fence = fences[i];
1146                 if (!fence)
1147                         continue;
1148                 dma_fence_signal(fence);
1149                 dma_fence_put(fence);
1150         }
1151 }
1152
1153 static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched)
1154 {
1155         struct drm_sched_job *s_job;
1156         struct dma_fence *fence;
1157
1158         spin_lock(&sched->job_list_lock);
1159         list_for_each_entry(s_job, &sched->ring_mirror_list, node) {
1160                 fence = sched->ops->run_job(s_job);
1161                 dma_fence_put(fence);
1162         }
1163         spin_unlock(&sched->job_list_lock);
1164 }
1165
1166 static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
1167 {
1168         struct amdgpu_job *job;
1169         struct drm_sched_job *s_job;
1170         uint32_t preempt_seq;
1171         struct dma_fence *fence, **ptr;
1172         struct amdgpu_fence_driver *drv = &ring->fence_drv;
1173         struct drm_gpu_scheduler *sched = &ring->sched;
1174
1175         if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
1176                 return;
1177
1178         preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
1179         if (preempt_seq <= atomic_read(&drv->last_seq))
1180                 return;
1181
1182         preempt_seq &= drv->num_fences_mask;
1183         ptr = &drv->fences[preempt_seq];
1184         fence = rcu_dereference_protected(*ptr, 1);
1185
1186         spin_lock(&sched->job_list_lock);
1187         list_for_each_entry(s_job, &sched->ring_mirror_list, node) {
1188                 job = to_amdgpu_job(s_job);
1189                 if (job->fence == fence)
1190                         /* mark the job as preempted */
1191                         job->preemption_status |= AMDGPU_IB_PREEMPTED;
1192         }
1193         spin_unlock(&sched->job_list_lock);
1194 }
1195
1196 static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
1197 {
1198         int r, resched, length;
1199         struct amdgpu_ring *ring;
1200         struct dma_fence **fences = NULL;
1201         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1202
1203         if (val >= AMDGPU_MAX_RINGS)
1204                 return -EINVAL;
1205
1206         ring = adev->rings[val];
1207
1208         if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread)
1209                 return -EINVAL;
1210
1211         /* the last preemption failed */
1212         if (ring->trail_seq != le32_to_cpu(*ring->trail_fence_cpu_addr))
1213                 return -EBUSY;
1214
1215         length = ring->fence_drv.num_fences_mask + 1;
1216         fences = kcalloc(length, sizeof(void *), GFP_KERNEL);
1217         if (!fences)
1218                 return -ENOMEM;
1219
1220         /* Avoid accidently unparking the sched thread during GPU reset */
1221         mutex_lock(&adev->lock_reset);
1222
1223         /* stop the scheduler */
1224         kthread_park(ring->sched.thread);
1225
1226         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1227
1228         /* preempt the IB */
1229         r = amdgpu_ring_preempt_ib(ring);
1230         if (r) {
1231                 DRM_WARN("failed to preempt ring %d\n", ring->idx);
1232                 goto failure;
1233         }
1234
1235         amdgpu_fence_process(ring);
1236
1237         if (atomic_read(&ring->fence_drv.last_seq) !=
1238             ring->fence_drv.sync_seq) {
1239                 DRM_INFO("ring %d was preempted\n", ring->idx);
1240
1241                 amdgpu_ib_preempt_mark_partial_job(ring);
1242
1243                 /* swap out the old fences */
1244                 amdgpu_ib_preempt_fences_swap(ring, fences);
1245
1246                 amdgpu_fence_driver_force_completion(ring);
1247
1248                 /* resubmit unfinished jobs */
1249                 amdgpu_ib_preempt_job_recovery(&ring->sched);
1250
1251                 /* wait for jobs finished */
1252                 amdgpu_fence_wait_empty(ring);
1253
1254                 /* signal the old fences */
1255                 amdgpu_ib_preempt_signal_fences(fences, length);
1256         }
1257
1258 failure:
1259         /* restart the scheduler */
1260         kthread_unpark(ring->sched.thread);
1261
1262         mutex_unlock(&adev->lock_reset);
1263
1264         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1265
1266         kfree(fences);
1267
1268         return 0;
1269 }
1270
1271 DEFINE_SIMPLE_ATTRIBUTE(fops_ib_preempt, NULL,
1272                         amdgpu_debugfs_ib_preempt, "%llu\n");
1273
1274 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1275 {
1276         int r;
1277
1278         adev->debugfs_preempt =
1279                 debugfs_create_file("amdgpu_preempt_ib", 0600,
1280                                     adev->ddev->primary->debugfs_root, adev,
1281                                     &fops_ib_preempt);
1282         if (!(adev->debugfs_preempt)) {
1283                 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
1284                 return -EIO;
1285         }
1286
1287         /* Register debugfs entries for amdgpu_ttm */
1288         r = amdgpu_ttm_debugfs_init(adev);
1289         if (r) {
1290                 DRM_ERROR("Failed to init debugfs\n");
1291                 return r;
1292         }
1293
1294         r = amdgpu_debugfs_pm_init(adev);
1295         if (r) {
1296                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1297                 return r;
1298         }
1299
1300         if (amdgpu_debugfs_sa_init(adev)) {
1301                 dev_err(adev->dev, "failed to register debugfs file for SA\n");
1302         }
1303
1304         if (amdgpu_debugfs_fence_init(adev))
1305                 dev_err(adev->dev, "fence debugfs file creation failed\n");
1306
1307         r = amdgpu_debugfs_gem_init(adev);
1308         if (r)
1309                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1310
1311         r = amdgpu_debugfs_regs_init(adev);
1312         if (r)
1313                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1314
1315         r = amdgpu_debugfs_firmware_init(adev);
1316         if (r)
1317                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1318
1319         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list,
1320                                         ARRAY_SIZE(amdgpu_debugfs_list));
1321 }
1322
1323 void amdgpu_debugfs_fini(struct amdgpu_device *adev)
1324 {
1325         amdgpu_ttm_debugfs_fini(adev);
1326         debugfs_remove(adev->debugfs_preempt);
1327 }
1328
1329 #else
1330 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1331 {
1332         return 0;
1333 }
1334 void amdgpu_debugfs_fini(struct amdgpu_device *adev) { }
1335 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1336 {
1337         return 0;
1338 }
1339 void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
1340 #endif