drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 #define AMDGPU_CS_MAX_PRIORITY          32u
  34 #define AMDGPU_CS_NUM_BUCKETS           (AMDGPU_CS_MAX_PRIORITY + 1)
  35
  36 /* This is based on the bucket sort with O(n) time complexity.
  37  * An item with priority "i" is added to bucket[i]. The lists are then
  38  * concatenated in descending order.
  39  */
  40 struct amdgpu_cs_buckets {
  41         struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
  42 };
  43
  44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
  49                 INIT_LIST_HEAD(&b->bucket[i]);
  50 }
  51
  52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
  53                                   struct list_head *item, unsigned priority)
  54 {
  55         /* Since buffers which appear sooner in the relocation list are
  56          * likely to be used more often than buffers which appear later
  57          * in the list, the sort mustn't change the ordering of buffers
  58          * with the same priority, i.e. it must be stable.
  59          */
  60         list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
  61 }
  62
  63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
  64                                        struct list_head *out_list)
  65 {
  66         unsigned i;
  67
  68         /* Connect the sorted buckets in the output list. */
  69         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
  70                 list_splice(&b->bucket[i], out_list);
  71         }
  72 }
  73
  74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  75                        u32 ip_instance, u32 ring,
  76                        struct amdgpu_ring **out_ring)
  77 {
  78         /* Right now all IPs have only one instance - multiple rings. */
  79         if (ip_instance != 0) {
  80                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  81                 return -EINVAL;
  82         }
  83
  84         switch (ip_type) {
  85         default:
  86                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  87                 return -EINVAL;
  88         case AMDGPU_HW_IP_GFX:
  89                 if (ring < adev->gfx.num_gfx_rings) {
  90                         *out_ring = &adev->gfx.gfx_ring[ring];
  91                 } else {
  92                         DRM_ERROR("only %d gfx rings are supported now\n",
  93                                   adev->gfx.num_gfx_rings);
  94                         return -EINVAL;
  95                 }
  96                 break;
  97         case AMDGPU_HW_IP_COMPUTE:
  98                 if (ring < adev->gfx.num_compute_rings) {
  99                         *out_ring = &adev->gfx.compute_ring[ring];
 100                 } else {
 101                         DRM_ERROR("only %d compute rings are supported now\n",
 102                                   adev->gfx.num_compute_rings);
 103                         return -EINVAL;
 104                 }
 105                 break;
 106         case AMDGPU_HW_IP_DMA:
 107                 if (ring < 2) {
 108                         *out_ring = &adev->sdma[ring].ring;
 109                 } else {
 110                         DRM_ERROR("only two SDMA rings are supported\n");
 111                         return -EINVAL;
 112                 }
 113                 break;
 114         case AMDGPU_HW_IP_UVD:
 115                 *out_ring = &adev->uvd.ring;
 116                 break;
 117         case AMDGPU_HW_IP_VCE:
 118                 if (ring < 2){
 119                         *out_ring = &adev->vce.ring[ring];
 120                 } else {
 121                         DRM_ERROR("only two VCE rings are supported\n");
 122                         return -EINVAL;
 123                 }
 124                 break;
 125         }
 126         return 0;
 127 }
 128
 129 static void amdgpu_job_work_func(struct work_struct *work)
 130 {
 131         struct amdgpu_cs_parser *sched_job =
 132                 container_of(work, struct amdgpu_cs_parser,
 133                              job_work);
 134         mutex_lock(&sched_job->job_lock);
 135         if (sched_job->free_job)
 136                 sched_job->free_job(sched_job);
 137         mutex_unlock(&sched_job->job_lock);
 138         /* after processing job, free memory */
 139         kfree(sched_job);
 140 }
 141 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
 142                                                struct drm_file *filp,
 143                                                struct amdgpu_ctx *ctx,
 144                                                struct amdgpu_ib *ibs,
 145                                                uint32_t num_ibs)
 146 {
 147         struct amdgpu_cs_parser *parser;
 148         int i;
 149
 150         parser = kzalloc(sizeof(struct amdgpu_cs_parser), GFP_KERNEL);
 151         if (!parser)
 152                 return NULL;
 153
 154         parser->adev = adev;
 155         parser->filp = filp;
 156         parser->ctx = ctx;
 157         parser->ibs = ibs;
 158         parser->num_ibs = num_ibs;
 159         if (amdgpu_enable_scheduler) {
 160                 mutex_init(&parser->job_lock);
 161                 INIT_WORK(&parser->job_work, amdgpu_job_work_func);
 162         }
 163         for (i = 0; i < num_ibs; i++)
 164                 ibs[i].ctx = ctx;
 165
 166         return parser;
 167 }
 168
 169 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 170 {
 171         union drm_amdgpu_cs *cs = data;
 172         uint64_t *chunk_array_user;
 173         uint64_t *chunk_array = NULL;
 174         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 175         struct amdgpu_bo_list *bo_list = NULL;
 176         unsigned size, i;
 177         int r = 0;
 178
 179         if (!cs->in.num_chunks)
 180                 goto out;
 181
 182         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 183         if (!p->ctx) {
 184                 r = -EINVAL;
 185                 goto out;
 186         }
 187         bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 188         if (bo_list && !bo_list->has_userptr) {
 189                 p->bo_list = amdgpu_bo_list_clone(bo_list);
 190                 amdgpu_bo_list_put(bo_list);
 191                 if (!p->bo_list)
 192                         return -ENOMEM;
 193         } else if (bo_list && bo_list->has_userptr)
 194                 p->bo_list = bo_list;
 195         else
 196                 p->bo_list = NULL;
 197
 198         /* get chunks */
 199         INIT_LIST_HEAD(&p->validated);
 200         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 201         if (chunk_array == NULL) {
 202                 r = -ENOMEM;
 203                 goto out;
 204         }
 205
 206         chunk_array_user = (uint64_t __user *)(cs->in.chunks);
 207         if (copy_from_user(chunk_array, chunk_array_user,
 208                            sizeof(uint64_t)*cs->in.num_chunks)) {
 209                 r = -EFAULT;
 210                 goto out;
 211         }
 212
 213         p->nchunks = cs->in.num_chunks;
 214         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 215                             GFP_KERNEL);
 216         if (p->chunks == NULL) {
 217                 r = -ENOMEM;
 218                 goto out;
 219         }
 220
 221         for (i = 0; i < p->nchunks; i++) {
 222                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 223                 struct drm_amdgpu_cs_chunk user_chunk;
 224                 uint32_t __user *cdata;
 225
 226                 chunk_ptr = (void __user *)chunk_array[i];
 227                 if (copy_from_user(&user_chunk, chunk_ptr,
 228                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 229                         r = -EFAULT;
 230                         goto out;
 231                 }
 232                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 233                 p->chunks[i].length_dw = user_chunk.length_dw;
 234
 235                 size = p->chunks[i].length_dw;
 236                 cdata = (void __user *)user_chunk.chunk_data;
 237                 p->chunks[i].user_ptr = cdata;
 238
 239                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 240                 if (p->chunks[i].kdata == NULL) {
 241                         r = -ENOMEM;
 242                         goto out;
 243                 }
 244                 size *= sizeof(uint32_t);
 245                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 246                         r = -EFAULT;
 247                         goto out;
 248                 }
 249
 250                 switch (p->chunks[i].chunk_id) {
 251                 case AMDGPU_CHUNK_ID_IB:
 252                         p->num_ibs++;
 253                         break;
 254
 255                 case AMDGPU_CHUNK_ID_FENCE:
 256                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 257                         if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
 258                                 uint32_t handle;
 259                                 struct drm_gem_object *gobj;
 260                                 struct drm_amdgpu_cs_chunk_fence *fence_data;
 261
 262                                 fence_data = (void *)p->chunks[i].kdata;
 263                                 handle = fence_data->handle;
 264                                 gobj = drm_gem_object_lookup(p->adev->ddev,
 265                                                              p->filp, handle);
 266                                 if (gobj == NULL) {
 267                                         r = -EINVAL;
 268                                         goto out;
 269                                 }
 270
 271                                 p->uf.bo = gem_to_amdgpu_bo(gobj);
 272                                 p->uf.offset = fence_data->offset;
 273                         } else {
 274                                 r = -EINVAL;
 275                                 goto out;
 276                         }
 277                         break;
 278
 279                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 280                         break;
 281
 282                 default:
 283                         r = -EINVAL;
 284                         goto out;
 285                 }
 286         }
 287
 288
 289         p->ibs = kmalloc_array(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
 290         if (!p->ibs)
 291                 r = -ENOMEM;
 292
 293 out:
 294         kfree(chunk_array);
 295         return r;
 296 }
 297
 298 /* Returns how many bytes TTM can move per IB.
 299  */
 300 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 301 {
 302         u64 real_vram_size = adev->mc.real_vram_size;
 303         u64 vram_usage = atomic64_read(&adev->vram_usage);
 304
 305         /* This function is based on the current VRAM usage.
 306          *
 307          * - If all of VRAM is free, allow relocating the number of bytes that
 308          *   is equal to 1/4 of the size of VRAM for this IB.
 309
 310          * - If more than one half of VRAM is occupied, only allow relocating
 311          *   1 MB of data for this IB.
 312          *
 313          * - From 0 to one half of used VRAM, the threshold decreases
 314          *   linearly.
 315          *         __________________
 316          * 1/4 of -|\               |
 317          * VRAM    | \              |
 318          *         |  \             |
 319          *         |   \            |
 320          *         |    \           |
 321          *         |     \          |
 322          *         |      \         |
 323          *         |       \________|1 MB
 324          *         |----------------|
 325          *    VRAM 0 %             100 %
 326          *         used            used
 327          *
 328          * Note: It's a threshold, not a limit. The threshold must be crossed
 329          * for buffer relocations to stop, so any buffer of an arbitrary size
 330          * can be moved as long as the threshold isn't crossed before
 331          * the relocation takes place. We don't want to disable buffer
 332          * relocations completely.
 333          *
 334          * The idea is that buffers should be placed in VRAM at creation time
 335          * and TTM should only do a minimum number of relocations during
 336          * command submission. In practice, you need to submit at least
 337          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 338          *
 339          * Also, things can get pretty crazy under memory pressure and actual
 340          * VRAM usage can change a lot, so playing safe even at 50% does
 341          * consistently increase performance.
 342          */
 343
 344         u64 half_vram = real_vram_size >> 1;
 345         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 346         u64 bytes_moved_threshold = half_free_vram >> 1;
 347         return max(bytes_moved_threshold, 1024*1024ull);
 348 }
 349
 350 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p)
 351 {
 352         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 353         struct amdgpu_vm *vm = &fpriv->vm;
 354         struct amdgpu_device *adev = p->adev;
 355         struct amdgpu_bo_list_entry *lobj;
 356         struct list_head duplicates;
 357         struct amdgpu_bo *bo;
 358         u64 bytes_moved = 0, initial_bytes_moved;
 359         u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
 360         int r;
 361
 362         INIT_LIST_HEAD(&duplicates);
 363         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
 364         if (unlikely(r != 0)) {
 365                 return r;
 366         }
 367
 368         list_for_each_entry(lobj, &p->validated, tv.head) {
 369                 bo = lobj->robj;
 370                 if (!bo->pin_count) {
 371                         u32 domain = lobj->prefered_domains;
 372                         u32 current_domain =
 373                                 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 374
 375                         /* Check if this buffer will be moved and don't move it
 376                          * if we have moved too many buffers for this IB already.
 377                          *
 378                          * Note that this allows moving at least one buffer of
 379                          * any size, because it doesn't take the current "bo"
 380                          * into account. We don't want to disallow buffer moves
 381                          * completely.
 382                          */
 383                         if (current_domain != AMDGPU_GEM_DOMAIN_CPU &&
 384                             (domain & current_domain) == 0 && /* will be moved */
 385                             bytes_moved > bytes_moved_threshold) {
 386                                 /* don't move it */
 387                                 domain = current_domain;
 388                         }
 389
 390                 retry:
 391                         amdgpu_ttm_placement_from_domain(bo, domain);
 392                         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 393                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 394                         bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 395                                        initial_bytes_moved;
 396
 397                         if (unlikely(r)) {
 398                                 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
 399                                         domain = lobj->allowed_domains;
 400                                         goto retry;
 401                                 }
 402                                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 403                                 return r;
 404                         }
 405                 }
 406                 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
 407         }
 408         return 0;
 409 }
 410
 411 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
 412 {
 413         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 414         struct amdgpu_cs_buckets buckets;
 415         bool need_mmap_lock = false;
 416         int i, r;
 417
 418         if (p->bo_list) {
 419                 need_mmap_lock = p->bo_list->has_userptr;
 420                 amdgpu_cs_buckets_init(&buckets);
 421                 for (i = 0; i < p->bo_list->num_entries; i++)
 422                         amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
 423                                                                   p->bo_list->array[i].priority);
 424
 425                 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
 426         }
 427
 428         p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
 429                                       &p->validated);
 430
 431         if (need_mmap_lock)
 432                 down_read(&current->mm->mmap_sem);
 433
 434         r = amdgpu_cs_list_validate(p);
 435
 436         if (need_mmap_lock)
 437                 up_read(&current->mm->mmap_sem);
 438
 439         return r;
 440 }
 441
 442 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 443 {
 444         struct amdgpu_bo_list_entry *e;
 445         int r;
 446
 447         list_for_each_entry(e, &p->validated, tv.head) {
 448                 struct reservation_object *resv = e->robj->tbo.resv;
 449                 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
 450
 451                 if (r)
 452                         return r;
 453         }
 454         return 0;
 455 }
 456
 457 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 458                                   struct list_head *b)
 459 {
 460         struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
 461         struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
 462
 463         /* Sort A before B if A is smaller. */
 464         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 465 }
 466
 467 static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int error, bool backoff)
 468 {
 469         if (!error) {
 470                 /* Sort the buffer list from the smallest to largest buffer,
 471                  * which affects the order of buffers in the LRU list.
 472                  * This assures that the smallest buffers are added first
 473                  * to the LRU list, so they are likely to be later evicted
 474                  * first, instead of large buffers whose eviction is more
 475                  * expensive.
 476                  *
 477                  * This slightly lowers the number of bytes moved by TTM
 478                  * per frame under memory pressure.
 479                  */
 480                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 481
 482                 ttm_eu_fence_buffer_objects(&parser->ticket,
 483                                 &parser->validated,
 484                                 &parser->ibs[parser->num_ibs-1].fence->base);
 485         } else if (backoff) {
 486                 ttm_eu_backoff_reservation(&parser->ticket,
 487                                            &parser->validated);
 488         }
 489 }
 490
 491 static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser)
 492 {
 493         unsigned i;
 494         if (parser->ctx)
 495                 amdgpu_ctx_put(parser->ctx);
 496         if (parser->bo_list) {
 497                 if (!parser->bo_list->has_userptr)
 498                         amdgpu_bo_list_free(parser->bo_list);
 499                 else
 500                         amdgpu_bo_list_put(parser->bo_list);
 501         }
 502         drm_free_large(parser->vm_bos);
 503         for (i = 0; i < parser->nchunks; i++)
 504                 drm_free_large(parser->chunks[i].kdata);
 505         kfree(parser->chunks);
 506         if (parser->ibs)
 507                 for (i = 0; i < parser->num_ibs; i++)
 508                         amdgpu_ib_free(parser->adev, &parser->ibs[i]);
 509         kfree(parser->ibs);
 510         if (parser->uf.bo)
 511                 drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
 512
 513         if (!amdgpu_enable_scheduler)
 514                 kfree(parser);
 515 }
 516
 517 /**
 518  * cs_parser_fini() - clean parser states
 519  * @parser:     parser structure holding parsing context.
 520  * @error:      error number
 521  *
 522  * If error is set than unvalidate buffer, otherwise just free memory
 523  * used by parsing context.
 524  **/
 525 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 526 {
 527        amdgpu_cs_parser_fini_early(parser, error, backoff);
 528        amdgpu_cs_parser_fini_late(parser);
 529 }
 530
 531 static int amdgpu_cs_parser_run_job(struct amdgpu_cs_parser *sched_job)
 532 {
 533        amdgpu_cs_parser_fini_early(sched_job, 0, true);
 534        return 0;
 535 }
 536
 537 static int amdgpu_cs_parser_free_job(struct amdgpu_cs_parser *sched_job)
 538 {
 539        amdgpu_cs_parser_fini_late(sched_job);
 540        return 0;
 541 }
 542
 543 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 544                                    struct amdgpu_vm *vm)
 545 {
 546         struct amdgpu_device *adev = p->adev;
 547         struct amdgpu_bo_va *bo_va;
 548         struct amdgpu_bo *bo;
 549         int i, r;
 550
 551         r = amdgpu_vm_update_page_directory(adev, vm);
 552         if (r)
 553                 return r;
 554
 555         r = amdgpu_vm_clear_freed(adev, vm);
 556         if (r)
 557                 return r;
 558
 559         if (p->bo_list) {
 560                 for (i = 0; i < p->bo_list->num_entries; i++) {
 561                         struct fence *f;
 562
 563                         /* ignore duplicates */
 564                         bo = p->bo_list->array[i].robj;
 565                         if (!bo)
 566                                 continue;
 567
 568                         bo_va = p->bo_list->array[i].bo_va;
 569                         if (bo_va == NULL)
 570                                 continue;
 571
 572                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 573                         if (r)
 574                                 return r;
 575
 576                         f = bo_va->last_pt_update;
 577                         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f);
 578                         if (r)
 579                                 return r;
 580                 }
 581         }
 582
 583         return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
 584 }
 585
 586 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 587                                  struct amdgpu_cs_parser *parser)
 588 {
 589         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 590         struct amdgpu_vm *vm = &fpriv->vm;
 591         struct amdgpu_ring *ring;
 592         int i, r;
 593
 594         if (parser->num_ibs == 0)
 595                 return 0;
 596
 597         /* Only for UVD/VCE VM emulation */
 598         for (i = 0; i < parser->num_ibs; i++) {
 599                 ring = parser->ibs[i].ring;
 600                 if (ring->funcs->parse_cs) {
 601                         r = amdgpu_ring_parse_cs(ring, parser, i);
 602                         if (r)
 603                                 return r;
 604                 }
 605         }
 606
 607         mutex_lock(&vm->mutex);
 608         r = amdgpu_bo_vm_update_pte(parser, vm);
 609         if (r) {
 610                 goto out;
 611         }
 612         amdgpu_cs_sync_rings(parser);
 613         if (!amdgpu_enable_scheduler)
 614                 r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
 615                                        parser->filp);
 616
 617 out:
 618         mutex_unlock(&vm->mutex);
 619         return r;
 620 }
 621
 622 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 623 {
 624         if (r == -EDEADLK) {
 625                 r = amdgpu_gpu_reset(adev);
 626                 if (!r)
 627                         r = -EAGAIN;
 628         }
 629         return r;
 630 }
 631
 632 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 633                              struct amdgpu_cs_parser *parser)
 634 {
 635         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 636         struct amdgpu_vm *vm = &fpriv->vm;
 637         int i, j;
 638         int r;
 639
 640         for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
 641                 struct amdgpu_cs_chunk *chunk;
 642                 struct amdgpu_ib *ib;
 643                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 644                 struct amdgpu_ring *ring;
 645
 646                 chunk = &parser->chunks[i];
 647                 ib = &parser->ibs[j];
 648                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 649
 650                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 651                         continue;
 652
 653                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 654                                        chunk_ib->ip_instance, chunk_ib->ring,
 655                                        &ring);
 656                 if (r)
 657                         return r;
 658
 659                 if (ring->funcs->parse_cs) {
 660                         struct amdgpu_bo_va_mapping *m;
 661                         struct amdgpu_bo *aobj = NULL;
 662                         uint64_t offset;
 663                         uint8_t *kptr;
 664
 665                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 666                                                    &aobj);
 667                         if (!aobj) {
 668                                 DRM_ERROR("IB va_start is invalid\n");
 669                                 return -EINVAL;
 670                         }
 671
 672                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 673                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 674                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 675                                 return -EINVAL;
 676                         }
 677
 678                         /* the IB should be reserved at this point */
 679                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 680                         if (r) {
 681                                 return r;
 682                         }
 683
 684                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 685                         kptr += chunk_ib->va_start - offset;
 686
 687                         r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
 688                         if (r) {
 689                                 DRM_ERROR("Failed to get ib !\n");
 690                                 return r;
 691                         }
 692
 693                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 694                         amdgpu_bo_kunmap(aobj);
 695                 } else {
 696                         r =  amdgpu_ib_get(ring, vm, 0, ib);
 697                         if (r) {
 698                                 DRM_ERROR("Failed to get ib !\n");
 699                                 return r;
 700                         }
 701
 702                         ib->gpu_addr = chunk_ib->va_start;
 703                 }
 704
 705                 ib->length_dw = chunk_ib->ib_bytes / 4;
 706                 ib->flags = chunk_ib->flags;
 707                 ib->ctx = parser->ctx;
 708                 j++;
 709         }
 710
 711         if (!parser->num_ibs)
 712                 return 0;
 713
 714         /* add GDS resources to first IB */
 715         if (parser->bo_list) {
 716                 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
 717                 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
 718                 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
 719                 struct amdgpu_ib *ib = &parser->ibs[0];
 720
 721                 if (gds) {
 722                         ib->gds_base = amdgpu_bo_gpu_offset(gds);
 723                         ib->gds_size = amdgpu_bo_size(gds);
 724                 }
 725                 if (gws) {
 726                         ib->gws_base = amdgpu_bo_gpu_offset(gws);
 727                         ib->gws_size = amdgpu_bo_size(gws);
 728                 }
 729                 if (oa) {
 730                         ib->oa_base = amdgpu_bo_gpu_offset(oa);
 731                         ib->oa_size = amdgpu_bo_size(oa);
 732                 }
 733         }
 734         /* wrap the last IB with user fence */
 735         if (parser->uf.bo) {
 736                 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
 737
 738                 /* UVD & VCE fw doesn't support user fences */
 739                 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
 740                     ib->ring->type == AMDGPU_RING_TYPE_VCE)
 741                         return -EINVAL;
 742
 743                 ib->user = &parser->uf;
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 750                                   struct amdgpu_cs_parser *p)
 751 {
 752         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 753         struct amdgpu_ib *ib;
 754         int i, j, r;
 755
 756         if (!p->num_ibs)
 757                 return 0;
 758
 759         /* Add dependencies to first IB */
 760         ib = &p->ibs[0];
 761         for (i = 0; i < p->nchunks; ++i) {
 762                 struct drm_amdgpu_cs_chunk_dep *deps;
 763                 struct amdgpu_cs_chunk *chunk;
 764                 unsigned num_deps;
 765
 766                 chunk = &p->chunks[i];
 767
 768                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 769                         continue;
 770
 771                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 772                 num_deps = chunk->length_dw * 4 /
 773                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 774
 775                 for (j = 0; j < num_deps; ++j) {
 776                         struct amdgpu_ring *ring;
 777                         struct amdgpu_ctx *ctx;
 778                         struct fence *fence;
 779
 780                         r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
 781                                                deps[j].ip_instance,
 782                                                deps[j].ring, &ring);
 783                         if (r)
 784                                 return r;
 785
 786                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 787                         if (ctx == NULL)
 788                                 return -EINVAL;
 789
 790                         fence = amdgpu_ctx_get_fence(ctx, ring,
 791                                                      deps[j].handle);
 792                         if (IS_ERR(fence)) {
 793                                 r = PTR_ERR(fence);
 794                                 amdgpu_ctx_put(ctx);
 795                                 return r;
 796
 797                         } else if (fence) {
 798                                 r = amdgpu_sync_fence(adev, &ib->sync, fence);
 799                                 fence_put(fence);
 800                                 amdgpu_ctx_put(ctx);
 801                                 if (r)
 802                                         return r;
 803                         }
 804                 }
 805         }
 806
 807         return 0;
 808 }
 809
 810 static int amdgpu_cs_parser_prepare_job(struct amdgpu_cs_parser *sched_job)
 811 {
 812         int r, i;
 813         struct amdgpu_cs_parser *parser = sched_job;
 814         struct amdgpu_device *adev = sched_job->adev;
 815         bool reserved_buffers = false;
 816
 817         r = amdgpu_cs_parser_relocs(parser);
 818         if (r) {
 819                 if (r != -ERESTARTSYS) {
 820                         if (r == -ENOMEM)
 821                                 DRM_ERROR("Not enough memory for command submission!\n");
 822                         else
 823                                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
 824                 }
 825         }
 826
 827         if (!r) {
 828                 reserved_buffers = true;
 829                 r = amdgpu_cs_ib_fill(adev, parser);
 830         }
 831         if (!r) {
 832                 r = amdgpu_cs_dependencies(adev, parser);
 833                 if (r)
 834                         DRM_ERROR("Failed in the dependencies handling %d!\n", r);
 835         }
 836         if (r) {
 837                 amdgpu_cs_parser_fini(parser, r, reserved_buffers);
 838                 return r;
 839         }
 840
 841         for (i = 0; i < parser->num_ibs; i++)
 842                 trace_amdgpu_cs(parser, i);
 843
 844         r = amdgpu_cs_ib_vm_chunk(adev, parser);
 845         return r;
 846 }
 847
 848 static struct amdgpu_ring *amdgpu_cs_parser_get_ring(
 849         struct amdgpu_device *adev,
 850         struct amdgpu_cs_parser *parser)
 851 {
 852         int i, r;
 853
 854         struct amdgpu_cs_chunk *chunk;
 855         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 856         struct amdgpu_ring *ring;
 857         for (i = 0; i < parser->nchunks; i++) {
 858                 chunk = &parser->chunks[i];
 859                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 860
 861                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 862                         continue;
 863
 864                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 865                                        chunk_ib->ip_instance, chunk_ib->ring,
 866                                        &ring);
 867                 if (r)
 868                         return NULL;
 869                 break;
 870         }
 871         return ring;
 872 }
 873
 874 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 875 {
 876         struct amdgpu_device *adev = dev->dev_private;
 877         union drm_amdgpu_cs *cs = data;
 878         struct amdgpu_cs_parser *parser;
 879         int r;
 880
 881         down_read(&adev->exclusive_lock);
 882         if (!adev->accel_working) {
 883                 up_read(&adev->exclusive_lock);
 884                 return -EBUSY;
 885         }
 886
 887         parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0);
 888         if (!parser)
 889                 return -ENOMEM;
 890         r = amdgpu_cs_parser_init(parser, data);
 891         if (r) {
 892                 DRM_ERROR("Failed to initialize parser !\n");
 893                 amdgpu_cs_parser_fini(parser, r, false);
 894                 up_read(&adev->exclusive_lock);
 895                 r = amdgpu_cs_handle_lockup(adev, r);
 896                 return r;
 897         }
 898
 899         if (amdgpu_enable_scheduler && parser->num_ibs) {
 900                 struct amdgpu_ring * ring =
 901                         amdgpu_cs_parser_get_ring(adev, parser);
 902                 parser->ibs[parser->num_ibs - 1].sequence = atomic64_inc_return(
 903                         &parser->ctx->rings[ring->idx].entity.last_queued_v_seq);
 904                 if (ring->is_pte_ring || (parser->bo_list && parser->bo_list->has_userptr)) {
 905                         r = amdgpu_cs_parser_prepare_job(parser);
 906                         if (r)
 907                                 goto out;
 908                 } else
 909                         parser->prepare_job = amdgpu_cs_parser_prepare_job;
 910                 parser->ring = ring;
 911                 parser->run_job = amdgpu_cs_parser_run_job;
 912                 parser->free_job = amdgpu_cs_parser_free_job;
 913                 amd_sched_push_job(ring->scheduler,
 914                                    &parser->ctx->rings[ring->idx].entity,
 915                                    parser);
 916                 cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
 917                 up_read(&adev->exclusive_lock);
 918                 return 0;
 919         }
 920         r = amdgpu_cs_parser_prepare_job(parser);
 921         if (r)
 922                 goto out;
 923
 924         cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
 925 out:
 926         amdgpu_cs_parser_fini(parser, r, true);
 927         up_read(&adev->exclusive_lock);
 928         r = amdgpu_cs_handle_lockup(adev, r);
 929         return r;
 930 }
 931
 932 /**
 933  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 934  *
 935  * @dev: drm device
 936  * @data: data from userspace
 937  * @filp: file private
 938  *
 939  * Wait for the command submission identified by handle to finish.
 940  */
 941 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 942                          struct drm_file *filp)
 943 {
 944         union drm_amdgpu_wait_cs *wait = data;
 945         struct amdgpu_device *adev = dev->dev_private;
 946         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 947         struct amdgpu_ring *ring = NULL;
 948         struct amdgpu_ctx *ctx;
 949         struct fence *fence;
 950         long r;
 951
 952         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 953                                wait->in.ring, &ring);
 954         if (r)
 955                 return r;
 956
 957         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 958         if (ctx == NULL)
 959                 return -EINVAL;
 960
 961         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
 962         if (IS_ERR(fence))
 963                 r = PTR_ERR(fence);
 964         else if (fence) {
 965                 r = fence_wait_timeout(fence, true, timeout);
 966                 fence_put(fence);
 967         } else
 968                 r = 1;
 969
 970         amdgpu_ctx_put(ctx);
 971         if (r < 0)
 972                 return r;
 973
 974         memset(wait, 0, sizeof(*wait));
 975         wait->out.status = (r == 0);
 976
 977         return 0;
 978 }
 979
 980 /**
 981  * amdgpu_cs_find_bo_va - find bo_va for VM address
 982  *
 983  * @parser: command submission parser context
 984  * @addr: VM address
 985  * @bo: resulting BO of the mapping found
 986  *
 987  * Search the buffer objects in the command submission context for a certain
 988  * virtual memory address. Returns allocation structure when found, NULL
 989  * otherwise.
 990  */
 991 struct amdgpu_bo_va_mapping *
 992 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
 993                        uint64_t addr, struct amdgpu_bo **bo)
 994 {
 995         struct amdgpu_bo_list_entry *reloc;
 996         struct amdgpu_bo_va_mapping *mapping;
 997
 998         addr /= AMDGPU_GPU_PAGE_SIZE;
 999
1000         list_for_each_entry(reloc, &parser->validated, tv.head) {
1001                 if (!reloc->bo_va)
1002                         continue;
1003
1004                 list_for_each_entry(mapping, &reloc->bo_va->valids, list) {
1005                         if (mapping->it.start > addr ||
1006                             addr > mapping->it.last)
1007                                 continue;
1008
1009                         *bo = reloc->bo_va->bo;
1010                         return mapping;
1011                 }
1012
1013                 list_for_each_entry(mapping, &reloc->bo_va->invalids, list) {
1014                         if (mapping->it.start > addr ||
1015                             addr > mapping->it.last)
1016                                 continue;
1017
1018                         *bo = reloc->bo_va->bo;
1019                         return mapping;
1020                 }
1021         }
1022
1023         return NULL;
1024 }