2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include <linux/file.h>
29 #include <linux/pagemap.h>
30 #include <linux/sync_file.h>
31 #include <linux/dma-buf.h>
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_syncobj.h>
35 #include "amdgpu_cs.h"
37 #include "amdgpu_trace.h"
38 #include "amdgpu_gmc.h"
39 #include "amdgpu_gem.h"
40 #include "amdgpu_ras.h"
42 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
43 struct drm_amdgpu_cs_chunk_fence *data,
46 struct drm_gem_object *gobj;
51 gobj = drm_gem_object_lookup(p->filp, data->handle);
55 bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
56 p->uf_entry.priority = 0;
57 p->uf_entry.tv.bo = &bo->tbo;
58 /* One for TTM and one for the CS job */
59 p->uf_entry.tv.num_shared = 2;
61 drm_gem_object_put(gobj);
63 size = amdgpu_bo_size(bo);
64 if (size != PAGE_SIZE || (data->offset + 8) > size) {
69 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
74 *offset = data->offset;
83 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
84 struct drm_amdgpu_bo_list_in *data)
87 struct drm_amdgpu_bo_list_entry *info = NULL;
89 r = amdgpu_bo_create_list_entry_array(data, &info);
93 r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
107 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
109 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
110 struct amdgpu_vm *vm = &fpriv->vm;
111 uint64_t *chunk_array_user;
112 uint64_t *chunk_array;
113 unsigned size, num_ibs = 0;
114 uint32_t uf_offset = 0;
118 if (cs->in.num_chunks == 0)
121 chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
125 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
131 mutex_lock(&p->ctx->lock);
133 /* skip guilty context job */
134 if (atomic_read(&p->ctx->guilty) == 1) {
140 chunk_array_user = u64_to_user_ptr(cs->in.chunks);
141 if (copy_from_user(chunk_array, chunk_array_user,
142 sizeof(uint64_t)*cs->in.num_chunks)) {
147 p->nchunks = cs->in.num_chunks;
148 p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
155 for (i = 0; i < p->nchunks; i++) {
156 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
157 struct drm_amdgpu_cs_chunk user_chunk;
158 uint32_t __user *cdata;
160 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
161 if (copy_from_user(&user_chunk, chunk_ptr,
162 sizeof(struct drm_amdgpu_cs_chunk))) {
165 goto free_partial_kdata;
167 p->chunks[i].chunk_id = user_chunk.chunk_id;
168 p->chunks[i].length_dw = user_chunk.length_dw;
170 size = p->chunks[i].length_dw;
171 cdata = u64_to_user_ptr(user_chunk.chunk_data);
173 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
174 if (p->chunks[i].kdata == NULL) {
177 goto free_partial_kdata;
179 size *= sizeof(uint32_t);
180 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
182 goto free_partial_kdata;
185 switch (p->chunks[i].chunk_id) {
186 case AMDGPU_CHUNK_ID_IB:
190 case AMDGPU_CHUNK_ID_FENCE:
191 size = sizeof(struct drm_amdgpu_cs_chunk_fence);
192 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
194 goto free_partial_kdata;
197 ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
200 goto free_partial_kdata;
204 case AMDGPU_CHUNK_ID_BO_HANDLES:
205 size = sizeof(struct drm_amdgpu_bo_list_in);
206 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
208 goto free_partial_kdata;
211 ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
213 goto free_partial_kdata;
217 case AMDGPU_CHUNK_ID_DEPENDENCIES:
218 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
219 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
220 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
221 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
222 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
227 goto free_partial_kdata;
231 ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
235 if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
240 if (p->uf_entry.tv.bo)
241 p->job->uf_addr = uf_offset;
244 /* Use this opportunity to fill in task info for the vm */
245 amdgpu_vm_set_task_info(vm);
253 kvfree(p->chunks[i].kdata);
263 /* Convert microseconds to bytes. */
264 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
266 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
269 /* Since accum_us is incremented by a million per second, just
270 * multiply it by the number of MB/s to get the number of bytes.
272 return us << adev->mm_stats.log2_max_MBps;
275 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
277 if (!adev->mm_stats.log2_max_MBps)
280 return bytes >> adev->mm_stats.log2_max_MBps;
283 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
284 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
285 * which means it can go over the threshold once. If that happens, the driver
286 * will be in debt and no other buffer migrations can be done until that debt
289 * This approach allows moving a buffer of any size (it's important to allow
292 * The currency is simply time in microseconds and it increases as the clock
293 * ticks. The accumulated microseconds (us) are converted to bytes and
296 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
300 s64 time_us, increment_us;
301 u64 free_vram, total_vram, used_vram;
302 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
305 * It means that in order to get full max MBps, at least 5 IBs per
306 * second must be submitted and not more than 200ms apart from each
309 const s64 us_upper_bound = 200000;
311 if (!adev->mm_stats.log2_max_MBps) {
317 total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
318 used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
319 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
321 spin_lock(&adev->mm_stats.lock);
323 /* Increase the amount of accumulated us. */
324 time_us = ktime_to_us(ktime_get());
325 increment_us = time_us - adev->mm_stats.last_update_us;
326 adev->mm_stats.last_update_us = time_us;
327 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
330 /* This prevents the short period of low performance when the VRAM
331 * usage is low and the driver is in debt or doesn't have enough
332 * accumulated us to fill VRAM quickly.
334 * The situation can occur in these cases:
335 * - a lot of VRAM is freed by userspace
336 * - the presence of a big buffer causes a lot of evictions
337 * (solution: split buffers into smaller ones)
339 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
340 * accum_us to a positive number.
342 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
345 /* Be more aggressive on dGPUs. Try to fill a portion of free
348 if (!(adev->flags & AMD_IS_APU))
349 min_us = bytes_to_us(adev, free_vram / 4);
351 min_us = 0; /* Reset accum_us on APUs. */
353 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
356 /* This is set to 0 if the driver is in debt to disallow (optional)
359 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
361 /* Do the same for visible VRAM if half of it is free */
362 if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
363 u64 total_vis_vram = adev->gmc.visible_vram_size;
365 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
367 if (used_vis_vram < total_vis_vram) {
368 u64 free_vis_vram = total_vis_vram - used_vis_vram;
369 adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
370 increment_us, us_upper_bound);
372 if (free_vis_vram >= total_vis_vram / 2)
373 adev->mm_stats.accum_us_vis =
374 max(bytes_to_us(adev, free_vis_vram / 2),
375 adev->mm_stats.accum_us_vis);
378 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
383 spin_unlock(&adev->mm_stats.lock);
386 /* Report how many bytes have really been moved for the last command
387 * submission. This can result in a debt that can stop buffer migrations
390 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
393 spin_lock(&adev->mm_stats.lock);
394 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
395 adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
396 spin_unlock(&adev->mm_stats.lock);
399 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
401 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
402 struct amdgpu_cs_parser *p = param;
403 struct ttm_operation_ctx ctx = {
404 .interruptible = true,
405 .no_wait_gpu = false,
406 .resv = bo->tbo.base.resv
411 if (bo->tbo.pin_count)
414 /* Don't move this buffer if we have depleted our allowance
415 * to move it. Don't move anything if the threshold is zero.
417 if (p->bytes_moved < p->bytes_moved_threshold &&
418 (!bo->tbo.base.dma_buf ||
419 list_empty(&bo->tbo.base.dma_buf->attachments))) {
420 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
421 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
422 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
423 * visible VRAM if we've depleted our allowance to do
426 if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
427 domain = bo->preferred_domains;
429 domain = bo->allowed_domains;
431 domain = bo->preferred_domains;
434 domain = bo->allowed_domains;
438 amdgpu_bo_placement_from_domain(bo, domain);
439 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
441 p->bytes_moved += ctx.bytes_moved;
442 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
443 amdgpu_bo_in_cpu_visible_vram(bo))
444 p->bytes_moved_vis += ctx.bytes_moved;
446 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
447 domain = bo->allowed_domains;
454 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
455 struct list_head *validated)
457 struct ttm_operation_ctx ctx = { true, false };
458 struct amdgpu_bo_list_entry *lobj;
461 list_for_each_entry(lobj, validated, tv.head) {
462 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
463 struct mm_struct *usermm;
465 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
466 if (usermm && usermm != current->mm)
469 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
470 lobj->user_invalidated && lobj->user_pages) {
471 amdgpu_bo_placement_from_domain(bo,
472 AMDGPU_GEM_DOMAIN_CPU);
473 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
477 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
481 r = amdgpu_cs_bo_validate(p, bo);
485 kvfree(lobj->user_pages);
486 lobj->user_pages = NULL;
491 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
492 union drm_amdgpu_cs *cs)
494 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
495 struct amdgpu_vm *vm = &fpriv->vm;
496 struct amdgpu_bo_list_entry *e;
497 struct list_head duplicates;
498 struct amdgpu_bo *gds;
499 struct amdgpu_bo *gws;
500 struct amdgpu_bo *oa;
503 INIT_LIST_HEAD(&p->validated);
505 /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
506 if (cs->in.bo_list_handle) {
510 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
514 } else if (!p->bo_list) {
515 /* Create a empty bo_list when no handle is provided */
516 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
522 /* One for TTM and one for the CS job */
523 amdgpu_bo_list_for_each_entry(e, p->bo_list)
524 e->tv.num_shared = 2;
526 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
528 INIT_LIST_HEAD(&duplicates);
529 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
531 if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
532 list_add(&p->uf_entry.tv.head, &p->validated);
534 /* Get userptr backing pages. If pages are updated after registered
535 * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
536 * amdgpu_ttm_backend_bind() to flush and invalidate new pages
538 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
539 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
540 bool userpage_invalidated = false;
543 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
544 sizeof(struct page *),
545 GFP_KERNEL | __GFP_ZERO);
546 if (!e->user_pages) {
547 DRM_ERROR("kvmalloc_array failure\n");
551 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);
553 kvfree(e->user_pages);
554 e->user_pages = NULL;
558 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
559 if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
560 userpage_invalidated = true;
564 e->user_invalidated = userpage_invalidated;
567 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
569 if (unlikely(r != 0)) {
570 if (r != -ERESTARTSYS)
571 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
575 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
576 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
578 e->bo_va = amdgpu_vm_bo_find(vm, bo);
580 if (bo->tbo.base.dma_buf && !amdgpu_bo_explicit_sync(bo)) {
581 e->chain = dma_fence_chain_alloc();
589 /* Move fence waiting after getting reservation lock of
590 * PD root. Then there is no need on a ctx mutex lock.
592 r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entity);
593 if (unlikely(r != 0)) {
594 if (r != -ERESTARTSYS)
595 DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
599 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
600 &p->bytes_moved_vis_threshold);
602 p->bytes_moved_vis = 0;
604 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
605 amdgpu_cs_bo_validate, p);
607 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
611 r = amdgpu_cs_list_validate(p, &duplicates);
615 r = amdgpu_cs_list_validate(p, &p->validated);
619 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
622 gds = p->bo_list->gds_obj;
623 gws = p->bo_list->gws_obj;
624 oa = p->bo_list->oa_obj;
627 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
628 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
631 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
632 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
635 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
636 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
639 if (!r && p->uf_entry.tv.bo) {
640 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
642 r = amdgpu_ttm_alloc_gart(&uf->tbo);
643 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
648 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
649 dma_fence_chain_free(e->chain);
652 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
658 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
660 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
661 struct amdgpu_bo_list_entry *e;
664 list_for_each_entry(e, &p->validated, tv.head) {
665 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
666 struct dma_resv *resv = bo->tbo.base.resv;
667 enum amdgpu_sync_mode sync_mode;
669 sync_mode = amdgpu_bo_explicit_sync(bo) ?
670 AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
671 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode,
680 * amdgpu_cs_parser_fini() - clean parser states
681 * @parser: parser structure holding parsing context.
682 * @error: error number
683 * @backoff: indicator to backoff the reservation
685 * If error is set then unvalidate buffer, otherwise just free memory
686 * used by parsing context.
688 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
693 if (error && backoff) {
694 struct amdgpu_bo_list_entry *e;
696 amdgpu_bo_list_for_each_entry(e, parser->bo_list) {
697 dma_fence_chain_free(e->chain);
701 ttm_eu_backoff_reservation(&parser->ticket,
705 for (i = 0; i < parser->num_post_deps; i++) {
706 drm_syncobj_put(parser->post_deps[i].syncobj);
707 kfree(parser->post_deps[i].chain);
709 kfree(parser->post_deps);
711 dma_fence_put(parser->fence);
714 mutex_unlock(&parser->ctx->lock);
715 amdgpu_ctx_put(parser->ctx);
718 amdgpu_bo_list_put(parser->bo_list);
720 for (i = 0; i < parser->nchunks; i++)
721 kvfree(parser->chunks[i].kdata);
722 kvfree(parser->chunks);
724 amdgpu_job_free(parser->job);
725 if (parser->uf_entry.tv.bo) {
726 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
728 amdgpu_bo_unref(&uf);
732 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
734 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
735 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
736 struct amdgpu_device *adev = p->adev;
737 struct amdgpu_vm *vm = &fpriv->vm;
738 struct amdgpu_bo_list_entry *e;
739 struct amdgpu_bo_va *bo_va;
740 struct amdgpu_bo *bo;
743 /* Only for UVD/VCE VM emulation */
744 if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
747 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
748 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
749 struct amdgpu_bo_va_mapping *m;
750 struct amdgpu_bo *aobj = NULL;
751 struct amdgpu_cs_chunk *chunk;
752 uint64_t offset, va_start;
753 struct amdgpu_ib *ib;
756 chunk = &p->chunks[i];
757 ib = &p->job->ibs[j];
758 chunk_ib = chunk->kdata;
760 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
763 va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
764 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
766 DRM_ERROR("IB va_start is invalid\n");
770 if ((va_start + chunk_ib->ib_bytes) >
771 (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
772 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
776 /* the IB should be reserved at this point */
777 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
782 offset = m->start * AMDGPU_GPU_PAGE_SIZE;
783 kptr += va_start - offset;
785 if (ring->funcs->parse_cs) {
786 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
787 amdgpu_bo_kunmap(aobj);
789 r = amdgpu_ring_parse_cs(ring, p, p->job, ib);
793 ib->ptr = (uint32_t *)kptr;
794 r = amdgpu_ring_patch_cs_in_place(ring, p, p->job, ib);
795 amdgpu_bo_kunmap(aobj);
805 return amdgpu_cs_sync_rings(p);
808 r = amdgpu_vm_clear_freed(adev, vm, NULL);
812 r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false, NULL);
816 r = amdgpu_sync_vm_fence(&p->job->sync, fpriv->prt_va->last_pt_update);
820 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
821 bo_va = fpriv->csa_va;
823 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
827 r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
832 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
833 /* ignore duplicates */
834 bo = ttm_to_amdgpu_bo(e->tv.bo);
842 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
846 r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
851 r = amdgpu_vm_handle_moved(adev, vm);
855 r = amdgpu_vm_update_pdes(adev, vm, false);
859 r = amdgpu_sync_vm_fence(&p->job->sync, vm->last_update);
863 p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
865 if (amdgpu_vm_debug) {
866 /* Invalidate all BOs to test for userspace bugs */
867 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
868 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
870 /* ignore duplicates */
874 amdgpu_vm_bo_invalidate(adev, bo, false);
878 return amdgpu_cs_sync_rings(p);
881 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
882 struct amdgpu_cs_parser *parser)
884 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
885 struct amdgpu_vm *vm = &fpriv->vm;
886 int r, ce_preempt = 0, de_preempt = 0;
887 struct amdgpu_ring *ring;
890 for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
891 struct amdgpu_cs_chunk *chunk;
892 struct amdgpu_ib *ib;
893 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
894 struct drm_sched_entity *entity;
896 chunk = &parser->chunks[i];
897 ib = &parser->job->ibs[j];
898 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
900 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
903 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
904 (amdgpu_mcbp || amdgpu_sriov_vf(adev))) {
905 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
906 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
912 /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
913 if (ce_preempt > 1 || de_preempt > 1)
917 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
918 chunk_ib->ip_instance, chunk_ib->ring,
923 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
924 parser->job->preamble_status |=
925 AMDGPU_PREAMBLE_IB_PRESENT;
927 if (parser->entity && parser->entity != entity)
930 /* Return if there is no run queue associated with this entity.
931 * Possibly because of disabled HW IP*/
932 if (entity->rq == NULL)
935 parser->entity = entity;
937 ring = to_amdgpu_ring(entity->rq->sched);
938 r = amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
939 chunk_ib->ib_bytes : 0,
940 AMDGPU_IB_POOL_DELAYED, ib);
942 DRM_ERROR("Failed to get ib !\n");
946 ib->gpu_addr = chunk_ib->va_start;
947 ib->length_dw = chunk_ib->ib_bytes / 4;
948 ib->flags = chunk_ib->flags;
953 /* MM engine doesn't support user fences */
954 ring = to_amdgpu_ring(parser->entity->rq->sched);
955 if (parser->job->uf_addr && ring->funcs->no_user_fence)
961 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
962 struct amdgpu_cs_chunk *chunk)
964 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
967 struct drm_amdgpu_cs_chunk_dep *deps;
969 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
970 num_deps = chunk->length_dw * 4 /
971 sizeof(struct drm_amdgpu_cs_chunk_dep);
973 for (i = 0; i < num_deps; ++i) {
974 struct amdgpu_ctx *ctx;
975 struct drm_sched_entity *entity;
976 struct dma_fence *fence;
978 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
982 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
984 deps[i].ring, &entity);
990 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
994 return PTR_ERR(fence);
998 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
999 struct drm_sched_fence *s_fence;
1000 struct dma_fence *old = fence;
1002 s_fence = to_drm_sched_fence(fence);
1003 fence = dma_fence_get(&s_fence->scheduled);
1007 r = amdgpu_sync_fence(&p->job->sync, fence);
1008 dma_fence_put(fence);
1015 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1016 uint32_t handle, u64 point,
1019 struct dma_fence *fence;
1022 r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
1024 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
1029 r = amdgpu_sync_fence(&p->job->sync, fence);
1030 dma_fence_put(fence);
1035 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1036 struct amdgpu_cs_chunk *chunk)
1038 struct drm_amdgpu_cs_chunk_sem *deps;
1042 deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1043 num_deps = chunk->length_dw * 4 /
1044 sizeof(struct drm_amdgpu_cs_chunk_sem);
1045 for (i = 0; i < num_deps; ++i) {
1046 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
1056 static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
1057 struct amdgpu_cs_chunk *chunk)
1059 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1063 syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1064 num_deps = chunk->length_dw * 4 /
1065 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1066 for (i = 0; i < num_deps; ++i) {
1067 r = amdgpu_syncobj_lookup_and_add_to_sync(p,
1068 syncobj_deps[i].handle,
1069 syncobj_deps[i].point,
1070 syncobj_deps[i].flags);
1078 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1079 struct amdgpu_cs_chunk *chunk)
1081 struct drm_amdgpu_cs_chunk_sem *deps;
1085 deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1086 num_deps = chunk->length_dw * 4 /
1087 sizeof(struct drm_amdgpu_cs_chunk_sem);
1092 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1094 p->num_post_deps = 0;
1100 for (i = 0; i < num_deps; ++i) {
1101 p->post_deps[i].syncobj =
1102 drm_syncobj_find(p->filp, deps[i].handle);
1103 if (!p->post_deps[i].syncobj)
1105 p->post_deps[i].chain = NULL;
1106 p->post_deps[i].point = 0;
1114 static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
1115 struct amdgpu_cs_chunk *chunk)
1117 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1121 syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1122 num_deps = chunk->length_dw * 4 /
1123 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1128 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1130 p->num_post_deps = 0;
1135 for (i = 0; i < num_deps; ++i) {
1136 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
1139 if (syncobj_deps[i].point) {
1140 dep->chain = dma_fence_chain_alloc();
1145 dep->syncobj = drm_syncobj_find(p->filp,
1146 syncobj_deps[i].handle);
1147 if (!dep->syncobj) {
1148 dma_fence_chain_free(dep->chain);
1151 dep->point = syncobj_deps[i].point;
1158 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1159 struct amdgpu_cs_parser *p)
1163 /* TODO: Investigate why we still need the context lock */
1164 mutex_unlock(&p->ctx->lock);
1166 for (i = 0; i < p->nchunks; ++i) {
1167 struct amdgpu_cs_chunk *chunk;
1169 chunk = &p->chunks[i];
1171 switch (chunk->chunk_id) {
1172 case AMDGPU_CHUNK_ID_DEPENDENCIES:
1173 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
1174 r = amdgpu_cs_process_fence_dep(p, chunk);
1178 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
1179 r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1183 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
1184 r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1188 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
1189 r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
1193 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
1194 r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
1202 mutex_lock(&p->ctx->lock);
1206 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1210 for (i = 0; i < p->num_post_deps; ++i) {
1211 if (p->post_deps[i].chain && p->post_deps[i].point) {
1212 drm_syncobj_add_point(p->post_deps[i].syncobj,
1213 p->post_deps[i].chain,
1214 p->fence, p->post_deps[i].point);
1215 p->post_deps[i].chain = NULL;
1217 drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1223 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1224 union drm_amdgpu_cs *cs)
1226 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1227 struct drm_sched_entity *entity = p->entity;
1228 struct amdgpu_bo_list_entry *e;
1229 struct amdgpu_job *job;
1236 r = drm_sched_job_init(&job->base, entity, &fpriv->vm);
1240 drm_sched_job_arm(&job->base);
1242 /* No memory allocation is allowed while holding the notifier lock.
1243 * The lock is held until amdgpu_cs_submit is finished and fence is
1246 mutex_lock(&p->adev->notifier_lock);
1248 /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1249 * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1251 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1252 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1254 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1261 p->fence = dma_fence_get(&job->base.s_fence->finished);
1263 amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1264 amdgpu_cs_post_dependencies(p);
1266 if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1267 !p->ctx->preamble_presented) {
1268 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1269 p->ctx->preamble_presented = true;
1272 cs->out.handle = seq;
1273 job->uf_sequence = seq;
1275 amdgpu_job_free_resources(job);
1277 trace_amdgpu_cs_ioctl(job);
1278 amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1279 drm_sched_entity_push_job(&job->base);
1281 amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1283 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1284 struct dma_resv *resv = e->tv.bo->base.resv;
1285 struct dma_fence_chain *chain = e->chain;
1291 * Work around dma_resv shortcomings by wrapping up the
1292 * submission in a dma_fence_chain and add it as exclusive
1295 dma_fence_chain_init(chain, dma_resv_excl_fence(resv),
1296 dma_fence_get(p->fence), 1);
1298 rcu_assign_pointer(resv->fence_excl, &chain->base);
1302 ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1303 mutex_unlock(&p->adev->notifier_lock);
1308 drm_sched_job_cleanup(&job->base);
1309 mutex_unlock(&p->adev->notifier_lock);
1312 amdgpu_job_free(job);
1316 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser)
1320 if (!trace_amdgpu_cs_enabled())
1323 for (i = 0; i < parser->job->num_ibs; i++)
1324 trace_amdgpu_cs(parser, i);
1327 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1329 struct amdgpu_device *adev = drm_to_adev(dev);
1330 union drm_amdgpu_cs *cs = data;
1331 struct amdgpu_cs_parser parser = {};
1332 bool reserved_buffers = false;
1335 if (amdgpu_ras_intr_triggered())
1338 if (!adev->accel_working)
1344 r = amdgpu_cs_parser_init(&parser, data);
1346 if (printk_ratelimit())
1347 DRM_ERROR("Failed to initialize parser %d!\n", r);
1351 r = amdgpu_cs_ib_fill(adev, &parser);
1355 r = amdgpu_cs_dependencies(adev, &parser);
1357 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1361 r = amdgpu_cs_parser_bos(&parser, data);
1364 DRM_ERROR("Not enough memory for command submission!\n");
1365 else if (r != -ERESTARTSYS && r != -EAGAIN)
1366 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1370 reserved_buffers = true;
1372 trace_amdgpu_cs_ibs(&parser);
1374 r = amdgpu_cs_vm_handling(&parser);
1378 r = amdgpu_cs_submit(&parser, cs);
1381 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1387 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1390 * @data: data from userspace
1391 * @filp: file private
1393 * Wait for the command submission identified by handle to finish.
1395 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1396 struct drm_file *filp)
1398 union drm_amdgpu_wait_cs *wait = data;
1399 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1400 struct drm_sched_entity *entity;
1401 struct amdgpu_ctx *ctx;
1402 struct dma_fence *fence;
1405 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1409 r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1410 wait->in.ring, &entity);
1412 amdgpu_ctx_put(ctx);
1416 fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1420 r = dma_fence_wait_timeout(fence, true, timeout);
1421 if (r > 0 && fence->error)
1423 dma_fence_put(fence);
1427 amdgpu_ctx_put(ctx);
1431 memset(wait, 0, sizeof(*wait));
1432 wait->out.status = (r == 0);
1438 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1440 * @adev: amdgpu device
1441 * @filp: file private
1442 * @user: drm_amdgpu_fence copied from user space
1444 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1445 struct drm_file *filp,
1446 struct drm_amdgpu_fence *user)
1448 struct drm_sched_entity *entity;
1449 struct amdgpu_ctx *ctx;
1450 struct dma_fence *fence;
1453 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1455 return ERR_PTR(-EINVAL);
1457 r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1458 user->ring, &entity);
1460 amdgpu_ctx_put(ctx);
1464 fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1465 amdgpu_ctx_put(ctx);
1470 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1471 struct drm_file *filp)
1473 struct amdgpu_device *adev = drm_to_adev(dev);
1474 union drm_amdgpu_fence_to_handle *info = data;
1475 struct dma_fence *fence;
1476 struct drm_syncobj *syncobj;
1477 struct sync_file *sync_file;
1480 fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1482 return PTR_ERR(fence);
1485 fence = dma_fence_get_stub();
1487 switch (info->in.what) {
1488 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1489 r = drm_syncobj_create(&syncobj, 0, fence);
1490 dma_fence_put(fence);
1493 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1494 drm_syncobj_put(syncobj);
1497 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1498 r = drm_syncobj_create(&syncobj, 0, fence);
1499 dma_fence_put(fence);
1502 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1503 drm_syncobj_put(syncobj);
1506 case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1507 fd = get_unused_fd_flags(O_CLOEXEC);
1509 dma_fence_put(fence);
1513 sync_file = sync_file_create(fence);
1514 dma_fence_put(fence);
1520 fd_install(fd, sync_file->file);
1521 info->out.handle = fd;
1525 dma_fence_put(fence);
1531 * amdgpu_cs_wait_all_fences - wait on all fences to signal
1533 * @adev: amdgpu device
1534 * @filp: file private
1535 * @wait: wait parameters
1536 * @fences: array of drm_amdgpu_fence
1538 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1539 struct drm_file *filp,
1540 union drm_amdgpu_wait_fences *wait,
1541 struct drm_amdgpu_fence *fences)
1543 uint32_t fence_count = wait->in.fence_count;
1547 for (i = 0; i < fence_count; i++) {
1548 struct dma_fence *fence;
1549 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1551 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1553 return PTR_ERR(fence);
1557 r = dma_fence_wait_timeout(fence, true, timeout);
1558 dma_fence_put(fence);
1566 return fence->error;
1569 memset(wait, 0, sizeof(*wait));
1570 wait->out.status = (r > 0);
1576 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1578 * @adev: amdgpu device
1579 * @filp: file private
1580 * @wait: wait parameters
1581 * @fences: array of drm_amdgpu_fence
1583 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1584 struct drm_file *filp,
1585 union drm_amdgpu_wait_fences *wait,
1586 struct drm_amdgpu_fence *fences)
1588 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1589 uint32_t fence_count = wait->in.fence_count;
1590 uint32_t first = ~0;
1591 struct dma_fence **array;
1595 /* Prepare the fence array */
1596 array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1601 for (i = 0; i < fence_count; i++) {
1602 struct dma_fence *fence;
1604 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1605 if (IS_ERR(fence)) {
1607 goto err_free_fence_array;
1610 } else { /* NULL, the fence has been already signaled */
1617 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1620 goto err_free_fence_array;
1623 memset(wait, 0, sizeof(*wait));
1624 wait->out.status = (r > 0);
1625 wait->out.first_signaled = first;
1627 if (first < fence_count && array[first])
1628 r = array[first]->error;
1632 err_free_fence_array:
1633 for (i = 0; i < fence_count; i++)
1634 dma_fence_put(array[i]);
1641 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1644 * @data: data from userspace
1645 * @filp: file private
1647 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1648 struct drm_file *filp)
1650 struct amdgpu_device *adev = drm_to_adev(dev);
1651 union drm_amdgpu_wait_fences *wait = data;
1652 uint32_t fence_count = wait->in.fence_count;
1653 struct drm_amdgpu_fence *fences_user;
1654 struct drm_amdgpu_fence *fences;
1657 /* Get the fences from userspace */
1658 fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1663 fences_user = u64_to_user_ptr(wait->in.fences);
1664 if (copy_from_user(fences, fences_user,
1665 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1667 goto err_free_fences;
1670 if (wait->in.wait_all)
1671 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1673 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1682 * amdgpu_cs_find_mapping - find bo_va for VM address
1684 * @parser: command submission parser context
1686 * @bo: resulting BO of the mapping found
1687 * @map: Placeholder to return found BO mapping
1689 * Search the buffer objects in the command submission context for a certain
1690 * virtual memory address. Returns allocation structure when found, NULL
1693 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1694 uint64_t addr, struct amdgpu_bo **bo,
1695 struct amdgpu_bo_va_mapping **map)
1697 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1698 struct ttm_operation_ctx ctx = { false, false };
1699 struct amdgpu_vm *vm = &fpriv->vm;
1700 struct amdgpu_bo_va_mapping *mapping;
1703 addr /= AMDGPU_GPU_PAGE_SIZE;
1705 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1706 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1709 *bo = mapping->bo_va->base.bo;
1712 /* Double check that the BO is reserved by this CS */
1713 if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1716 if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1717 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1718 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1719 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1724 return amdgpu_ttm_alloc_gart(&(*bo)->tbo);