drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30 #include "soc15_hw_ip.h"
  31
  32 union firmware_info {
  33         struct atom_firmware_info_v3_1 v31;
  34         struct atom_firmware_info_v3_2 v32;
  35         struct atom_firmware_info_v3_3 v33;
  36         struct atom_firmware_info_v3_4 v34;
  37 };
  38
  39 /*
  40  * Helper function to query firmware capability
  41  *
  42  * @adev: amdgpu_device pointer
  43  *
  44  * Return firmware_capability in firmwareinfo table on success or 0 if not
  45  */
  46 uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_mode_info *mode_info = &adev->mode_info;
  49         int index;
  50         u16 data_offset, size;
  51         union firmware_info *firmware_info;
  52         u8 frev, crev;
  53         u32 fw_cap = 0;
  54
  55         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  56                         firmwareinfo);
  57
  58         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
  59                                 index, &size, &frev, &crev, &data_offset)) {
  60                 /* support firmware_info 3.1 + */
  61                 if ((frev == 3 && crev >=1) || (frev > 3)) {
  62                         firmware_info = (union firmware_info *)
  63                                 (mode_info->atom_context->bios + data_offset);
  64                         fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
  65                 }
  66         }
  67
  68         return fw_cap;
  69 }
  70
  71 /*
  72  * Helper function to query gpu virtualizaiton capability
  73  *
  74  * @adev: amdgpu_device pointer
  75  *
  76  * Return true if gpu virtualization is supported or false if not
  77  */
  78 bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev)
  79 {
  80         u32 fw_cap;
  81
  82         fw_cap = adev->mode_info.firmware_flags;
  83
  84         return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;
  85 }
  86
  87 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  88 {
  89         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  90                                                 firmwareinfo);
  91         uint16_t data_offset;
  92
  93         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  94                                           NULL, NULL, &data_offset)) {
  95                 struct atom_firmware_info_v3_1 *firmware_info =
  96                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  97                                                            data_offset);
  98
  99                 adev->bios_scratch_reg_offset =
 100                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
 101         }
 102 }
 103
 104 static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
 105         struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes)
 106 {
 107         u32 start_addr, fw_size, drv_size;
 108
 109         start_addr = le32_to_cpu(fw_usage->start_address_in_kb);
 110         fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
 111         drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb);
 112
 113         DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
 114                           start_addr,
 115                           fw_size,
 116                           drv_size);
 117
 118         if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
 119                 (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
 120                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
 121                 /* Firmware request VRAM reservation for SR-IOV */
 122                 adev->mman.fw_vram_usage_start_offset = (start_addr &
 123                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 124                 adev->mman.fw_vram_usage_size = fw_size << 10;
 125                 /* Use the default scratch size */
 126                 *usage_bytes = 0;
 127         } else {
 128                 *usage_bytes = drv_size << 10;
 129         }
 130         return 0;
 131 }
 132
 133 static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
 134                 struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes)
 135 {
 136         u32 fw_start_addr, fw_size, drv_start_addr, drv_size;
 137
 138         fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb);
 139         fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
 140
 141         drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb);
 142         drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb);
 143
 144         DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n",
 145                           fw_start_addr,
 146                           fw_size,
 147                           drv_start_addr,
 148                           drv_size);
 149
 150         if (amdgpu_sriov_vf(adev) &&
 151             ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
 152                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
 153                 /* Firmware request VRAM reservation for SR-IOV */
 154                 adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
 155                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 156                 adev->mman.fw_vram_usage_size = fw_size << 10;
 157         }
 158
 159         if (amdgpu_sriov_vf(adev) &&
 160             ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
 161                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
 162                 /* driver request VRAM reservation for SR-IOV */
 163                 adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
 164                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 165                 adev->mman.drv_vram_usage_size = drv_size << 10;
 166         }
 167
 168         *usage_bytes = 0;
 169         return 0;
 170 }
 171
 172 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 173 {
 174         struct atom_context *ctx = adev->mode_info.atom_context;
 175         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 176                                                 vram_usagebyfirmware);
 177         struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1;
 178         struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2;
 179         u16 data_offset;
 180         u8 frev, crev;
 181         int usage_bytes = 0;
 182
 183         if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) {
 184                 if (frev == 2 && crev == 1) {
 185                         fw_usage_v2_1 =
 186                                 (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
 187                         amdgpu_atomfirmware_allocate_fb_v2_1(adev,
 188                                         fw_usage_v2_1,
 189                                         &usage_bytes);
 190                 } else if (frev >= 2 && crev >= 2) {
 191                         fw_usage_v2_2 =
 192                                 (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset);
 193                         amdgpu_atomfirmware_allocate_fb_v2_2(adev,
 194                                         fw_usage_v2_2,
 195                                         &usage_bytes);
 196                 }
 197         }
 198
 199         ctx->scratch_size_bytes = 0;
 200         if (usage_bytes == 0)
 201                 usage_bytes = 20 * 1024;
 202         /* allocate some scratch memory */
 203         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 204         if (!ctx->scratch)
 205                 return -ENOMEM;
 206         ctx->scratch_size_bytes = usage_bytes;
 207         return 0;
 208 }
 209
 210 union igp_info {
 211         struct atom_integrated_system_info_v1_11 v11;
 212         struct atom_integrated_system_info_v1_12 v12;
 213         struct atom_integrated_system_info_v2_1 v21;
 214 };
 215
 216 union umc_info {
 217         struct atom_umc_info_v3_1 v31;
 218         struct atom_umc_info_v3_2 v32;
 219         struct atom_umc_info_v3_3 v33;
 220 };
 221
 222 union vram_info {
 223         struct atom_vram_info_header_v2_3 v23;
 224         struct atom_vram_info_header_v2_4 v24;
 225         struct atom_vram_info_header_v2_5 v25;
 226         struct atom_vram_info_header_v2_6 v26;
 227         struct atom_vram_info_header_v3_0 v30;
 228 };
 229
 230 union vram_module {
 231         struct atom_vram_module_v9 v9;
 232         struct atom_vram_module_v10 v10;
 233         struct atom_vram_module_v11 v11;
 234         struct atom_vram_module_v3_0 v30;
 235 };
 236
 237 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 238                                               int atom_mem_type)
 239 {
 240         int vram_type;
 241
 242         if (adev->flags & AMD_IS_APU) {
 243                 switch (atom_mem_type) {
 244                 case Ddr2MemType:
 245                 case LpDdr2MemType:
 246                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 247                         break;
 248                 case Ddr3MemType:
 249                 case LpDdr3MemType:
 250                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 251                         break;
 252                 case Ddr4MemType:
 253                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 254                         break;
 255                 case LpDdr4MemType:
 256                         vram_type = AMDGPU_VRAM_TYPE_LPDDR4;
 257                         break;
 258                 case Ddr5MemType:
 259                         vram_type = AMDGPU_VRAM_TYPE_DDR5;
 260                         break;
 261                 case LpDdr5MemType:
 262                         vram_type = AMDGPU_VRAM_TYPE_LPDDR5;
 263                         break;
 264                 default:
 265                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 266                         break;
 267                 }
 268         } else {
 269                 switch (atom_mem_type) {
 270                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 271                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 272                         break;
 273                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 274                 case ATOM_DGPU_VRAM_TYPE_HBM2E:
 275                 case ATOM_DGPU_VRAM_TYPE_HBM3:
 276                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 277                         break;
 278                 case ATOM_DGPU_VRAM_TYPE_GDDR6:
 279                         vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 280                         break;
 281                 default:
 282                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 283                         break;
 284                 }
 285         }
 286
 287         return vram_type;
 288 }
 289
 290
 291 int
 292 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 293                                   int *vram_width, int *vram_type,
 294                                   int *vram_vendor)
 295 {
 296         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 297         int index, i = 0;
 298         u16 data_offset, size;
 299         union igp_info *igp_info;
 300         union vram_info *vram_info;
 301         union vram_module *vram_module;
 302         u8 frev, crev;
 303         u8 mem_type;
 304         u8 mem_vendor;
 305         u32 mem_channel_number;
 306         u32 mem_channel_width;
 307         u32 module_id;
 308
 309         if (adev->flags & AMD_IS_APU)
 310                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 311                                                     integratedsysteminfo);
 312         else
 313                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 314                                                     vram_info);
 315
 316         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 317                                           index, &size,
 318                                           &frev, &crev, &data_offset)) {
 319                 if (adev->flags & AMD_IS_APU) {
 320                         igp_info = (union igp_info *)
 321                                 (mode_info->atom_context->bios + data_offset);
 322                         switch (frev) {
 323                         case 1:
 324                                 switch (crev) {
 325                                 case 11:
 326                                 case 12:
 327                                         mem_channel_number = igp_info->v11.umachannelnumber;
 328                                         if (!mem_channel_number)
 329                                                 mem_channel_number = 1;
 330                                         /* channel width is 64 */
 331                                         if (vram_width)
 332                                                 *vram_width = mem_channel_number * 64;
 333                                         mem_type = igp_info->v11.memorytype;
 334                                         if (vram_type)
 335                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 336                                         break;
 337                                 default:
 338                                         return -EINVAL;
 339                                 }
 340                                 break;
 341                         case 2:
 342                                 switch (crev) {
 343                                 case 1:
 344                                 case 2:
 345                                         mem_channel_number = igp_info->v21.umachannelnumber;
 346                                         if (!mem_channel_number)
 347                                                 mem_channel_number = 1;
 348                                         /* channel width is 64 */
 349                                         if (vram_width)
 350                                                 *vram_width = mem_channel_number * 64;
 351                                         mem_type = igp_info->v21.memorytype;
 352                                         if (vram_type)
 353                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 354                                         break;
 355                                 default:
 356                                         return -EINVAL;
 357                                 }
 358                                 break;
 359                         default:
 360                                 return -EINVAL;
 361                         }
 362                 } else {
 363                         vram_info = (union vram_info *)
 364                                 (mode_info->atom_context->bios + data_offset);
 365                         module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
 366                         if (frev == 3) {
 367                                 switch (crev) {
 368                                 /* v30 */
 369                                 case 0:
 370                                         vram_module = (union vram_module *)vram_info->v30.vram_module;
 371                                         mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
 372                                         if (vram_vendor)
 373                                                 *vram_vendor = mem_vendor;
 374                                         mem_type = vram_info->v30.memory_type;
 375                                         if (vram_type)
 376                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 377                                         mem_channel_number = vram_info->v30.channel_num;
 378                                         mem_channel_width = vram_info->v30.channel_width;
 379                                         if (vram_width)
 380                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 381                                         break;
 382                                 default:
 383                                         return -EINVAL;
 384                                 }
 385                         } else if (frev == 2) {
 386                                 switch (crev) {
 387                                 /* v23 */
 388                                 case 3:
 389                                         if (module_id > vram_info->v23.vram_module_num)
 390                                                 module_id = 0;
 391                                         vram_module = (union vram_module *)vram_info->v23.vram_module;
 392                                         while (i < module_id) {
 393                                                 vram_module = (union vram_module *)
 394                                                         ((u8 *)vram_module + vram_module->v9.vram_module_size);
 395                                                 i++;
 396                                         }
 397                                         mem_type = vram_module->v9.memory_type;
 398                                         if (vram_type)
 399                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 400                                         mem_channel_number = vram_module->v9.channel_num;
 401                                         mem_channel_width = vram_module->v9.channel_width;
 402                                         if (vram_width)
 403                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 404                                         mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 405                                         if (vram_vendor)
 406                                                 *vram_vendor = mem_vendor;
 407                                         break;
 408                                 /* v24 */
 409                                 case 4:
 410                                         if (module_id > vram_info->v24.vram_module_num)
 411                                                 module_id = 0;
 412                                         vram_module = (union vram_module *)vram_info->v24.vram_module;
 413                                         while (i < module_id) {
 414                                                 vram_module = (union vram_module *)
 415                                                         ((u8 *)vram_module + vram_module->v10.vram_module_size);
 416                                                 i++;
 417                                         }
 418                                         mem_type = vram_module->v10.memory_type;
 419                                         if (vram_type)
 420                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 421                                         mem_channel_number = vram_module->v10.channel_num;
 422                                         mem_channel_width = vram_module->v10.channel_width;
 423                                         if (vram_width)
 424                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 425                                         mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
 426                                         if (vram_vendor)
 427                                                 *vram_vendor = mem_vendor;
 428                                         break;
 429                                 /* v25 */
 430                                 case 5:
 431                                         if (module_id > vram_info->v25.vram_module_num)
 432                                                 module_id = 0;
 433                                         vram_module = (union vram_module *)vram_info->v25.vram_module;
 434                                         while (i < module_id) {
 435                                                 vram_module = (union vram_module *)
 436                                                         ((u8 *)vram_module + vram_module->v11.vram_module_size);
 437                                                 i++;
 438                                         }
 439                                         mem_type = vram_module->v11.memory_type;
 440                                         if (vram_type)
 441                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 442                                         mem_channel_number = vram_module->v11.channel_num;
 443                                         mem_channel_width = vram_module->v11.channel_width;
 444                                         if (vram_width)
 445                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 446                                         mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
 447                                         if (vram_vendor)
 448                                                 *vram_vendor = mem_vendor;
 449                                         break;
 450                                 /* v26 */
 451                                 case 6:
 452                                         if (module_id > vram_info->v26.vram_module_num)
 453                                                 module_id = 0;
 454                                         vram_module = (union vram_module *)vram_info->v26.vram_module;
 455                                         while (i < module_id) {
 456                                                 vram_module = (union vram_module *)
 457                                                         ((u8 *)vram_module + vram_module->v9.vram_module_size);
 458                                                 i++;
 459                                         }
 460                                         mem_type = vram_module->v9.memory_type;
 461                                         if (vram_type)
 462                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 463                                         mem_channel_number = vram_module->v9.channel_num;
 464                                         mem_channel_width = vram_module->v9.channel_width;
 465                                         if (vram_width)
 466                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 467                                         mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 468                                         if (vram_vendor)
 469                                                 *vram_vendor = mem_vendor;
 470                                         break;
 471                                 default:
 472                                         return -EINVAL;
 473                                 }
 474                         } else {
 475                                 /* invalid frev */
 476                                 return -EINVAL;
 477                         }
 478                 }
 479
 480         }
 481
 482         return 0;
 483 }
 484
 485 /*
 486  * Return true if vbios enabled ecc by default, if umc info table is available
 487  * or false if ecc is not enabled or umc info table is not available
 488  */
 489 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 490 {
 491         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 492         int index;
 493         u16 data_offset, size;
 494         union umc_info *umc_info;
 495         u8 frev, crev;
 496         bool ecc_default_enabled = false;
 497         u8 umc_config;
 498         u32 umc_config1;
 499
 500         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 501                         umc_info);
 502
 503         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 504                                 index, &size, &frev, &crev, &data_offset)) {
 505                 if (frev == 3) {
 506                         umc_info = (union umc_info *)
 507                                 (mode_info->atom_context->bios + data_offset);
 508                         switch (crev) {
 509                         case 1:
 510                                 umc_config = le32_to_cpu(umc_info->v31.umc_config);
 511                                 ecc_default_enabled =
 512                                         (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 513                                 break;
 514                         case 2:
 515                                 umc_config = le32_to_cpu(umc_info->v32.umc_config);
 516                                 ecc_default_enabled =
 517                                         (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 518                                 break;
 519                         case 3:
 520                                 umc_config = le32_to_cpu(umc_info->v33.umc_config);
 521                                 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
 522                                 ecc_default_enabled =
 523                                         ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||
 524                                          (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
 525                                 break;
 526                         default:
 527                                 /* unsupported crev */
 528                                 return false;
 529                         }
 530                 }
 531         }
 532
 533         return ecc_default_enabled;
 534 }
 535
 536 /*
 537  * Helper function to query sram ecc capablity
 538  *
 539  * @adev: amdgpu_device pointer
 540  *
 541  * Return true if vbios supports sram ecc or false if not
 542  */
 543 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 544 {
 545         u32 fw_cap;
 546
 547         fw_cap = adev->mode_info.firmware_flags;
 548
 549         return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 550 }
 551
 552 /*
 553  * Helper function to query dynamic boot config capability
 554  *
 555  * @adev: amdgpu_device pointer
 556  *
 557  * Return true if vbios supports dynamic boot config or false if not
 558  */
 559 bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev)
 560 {
 561         u32 fw_cap;
 562
 563         fw_cap = adev->mode_info.firmware_flags;
 564
 565         return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
 566 }
 567
 568 /**
 569  * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS
 570  * @adev: amdgpu_device pointer
 571  * @i2c_address: pointer to u8; if not NULL, will contain
 572  *    the RAS EEPROM address if the function returns true
 573  *
 574  * Return true if VBIOS supports RAS EEPROM address reporting,
 575  * else return false. If true and @i2c_address is not NULL,
 576  * will contain the RAS ROM address.
 577  */
 578 bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
 579                                       u8 *i2c_address)
 580 {
 581         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 582         int index;
 583         u16 data_offset, size;
 584         union firmware_info *firmware_info;
 585         u8 frev, crev;
 586
 587         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 588                                             firmwareinfo);
 589
 590         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 591                                           index, &size, &frev, &crev,
 592                                           &data_offset)) {
 593                 /* support firmware_info 3.4 + */
 594                 if ((frev == 3 && crev >=4) || (frev > 3)) {
 595                         firmware_info = (union firmware_info *)
 596                                 (mode_info->atom_context->bios + data_offset);
 597                         /* The ras_rom_i2c_slave_addr should ideally
 598                          * be a 19-bit EEPROM address, which would be
 599                          * used as is by the driver; see top of
 600                          * amdgpu_eeprom.c.
 601                          *
 602                          * When this is the case, 0 is of course a
 603                          * valid RAS EEPROM address, in which case,
 604                          * we'll drop the first "if (firm...)" and only
 605                          * leave the check for the pointer.
 606                          *
 607                          * The reason this works right now is because
 608                          * ras_rom_i2c_slave_addr contains the EEPROM
 609                          * device type qualifier 1010b in the top 4
 610                          * bits.
 611                          */
 612                         if (firmware_info->v34.ras_rom_i2c_slave_addr) {
 613                                 if (i2c_address)
 614                                         *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
 615                                 return true;
 616                         }
 617                 }
 618         }
 619
 620         return false;
 621 }
 622
 623
 624 union smu_info {
 625         struct atom_smu_info_v3_1 v31;
 626         struct atom_smu_info_v4_0 v40;
 627 };
 628
 629 union gfx_info {
 630         struct atom_gfx_info_v2_2 v22;
 631         struct atom_gfx_info_v2_4 v24;
 632         struct atom_gfx_info_v2_7 v27;
 633         struct atom_gfx_info_v3_0 v30;
 634 };
 635
 636 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 637 {
 638         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 639         struct amdgpu_pll *spll = &adev->clock.spll;
 640         struct amdgpu_pll *mpll = &adev->clock.mpll;
 641         uint8_t frev, crev;
 642         uint16_t data_offset;
 643         int ret = -EINVAL, index;
 644
 645         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 646                                             firmwareinfo);
 647         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 648                                    &frev, &crev, &data_offset)) {
 649                 union firmware_info *firmware_info =
 650                         (union firmware_info *)(mode_info->atom_context->bios +
 651                                                 data_offset);
 652
 653                 adev->clock.default_sclk =
 654                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 655                 adev->clock.default_mclk =
 656                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 657
 658                 adev->pm.current_sclk = adev->clock.default_sclk;
 659                 adev->pm.current_mclk = adev->clock.default_mclk;
 660
 661                 ret = 0;
 662         }
 663
 664         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 665                                             smu_info);
 666         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 667                                    &frev, &crev, &data_offset)) {
 668                 union smu_info *smu_info =
 669                         (union smu_info *)(mode_info->atom_context->bios +
 670                                            data_offset);
 671
 672                 /* system clock */
 673                 if (frev == 3)
 674                         spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 675                 else if (frev == 4)
 676                         spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz);
 677
 678                 spll->reference_div = 0;
 679                 spll->min_post_div = 1;
 680                 spll->max_post_div = 1;
 681                 spll->min_ref_div = 2;
 682                 spll->max_ref_div = 0xff;
 683                 spll->min_feedback_div = 4;
 684                 spll->max_feedback_div = 0xff;
 685                 spll->best_vco = 0;
 686
 687                 ret = 0;
 688         }
 689
 690         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 691                                             umc_info);
 692         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 693                                    &frev, &crev, &data_offset)) {
 694                 union umc_info *umc_info =
 695                         (union umc_info *)(mode_info->atom_context->bios +
 696                                            data_offset);
 697
 698                 /* memory clock */
 699                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 700
 701                 mpll->reference_div = 0;
 702                 mpll->min_post_div = 1;
 703                 mpll->max_post_div = 1;
 704                 mpll->min_ref_div = 2;
 705                 mpll->max_ref_div = 0xff;
 706                 mpll->min_feedback_div = 4;
 707                 mpll->max_feedback_div = 0xff;
 708                 mpll->best_vco = 0;
 709
 710                 ret = 0;
 711         }
 712
 713         /* if asic is Navi+, the rlc reference clock is used for system clock
 714          * from vbios gfx_info table */
 715         if (adev->asic_type >= CHIP_NAVI10) {
 716                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 717                                                    gfx_info);
 718                 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 719                                           &frev, &crev, &data_offset)) {
 720                         union gfx_info *gfx_info = (union gfx_info *)
 721                                 (mode_info->atom_context->bios + data_offset);
 722                         if ((frev == 3) ||
 723                             (frev == 2 && crev == 6)) {
 724                                 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);
 725                                 ret = 0;
 726                         } else if ((frev == 2) &&
 727                                    (crev >= 2) &&
 728                                    (crev != 6)) {
 729                                 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);
 730                                 ret = 0;
 731                         } else {
 732                                 BUG();
 733                         }
 734                 }
 735         }
 736
 737         return ret;
 738 }
 739
 740 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 741 {
 742         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 743         int index;
 744         uint8_t frev, crev;
 745         uint16_t data_offset;
 746
 747         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 748                                             gfx_info);
 749         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 750                                    &frev, &crev, &data_offset)) {
 751                 union gfx_info *gfx_info = (union gfx_info *)
 752                         (mode_info->atom_context->bios + data_offset);
 753                 if (frev == 2) {
 754                         switch (crev) {
 755                         case 4:
 756                                 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 757                                 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 758                                 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 759                                 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 760                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 761                                 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 762                                 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 763                                 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 764                                 adev->gfx.config.gs_prim_buffer_depth =
 765                                         le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 766                                 adev->gfx.config.double_offchip_lds_buf =
 767                                         gfx_info->v24.gc_double_offchip_lds_buffer;
 768                                 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 769                                 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 770                                 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 771                                 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 772                                 return 0;
 773                         case 7:
 774                                 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
 775                                 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
 776                                 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
 777                                 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
 778                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
 779                                 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
 780                                 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
 781                                 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
 782                                 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
 783                                 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
 784                                 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
 785                                 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
 786                                 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
 787                                 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
 788                                 return 0;
 789                         default:
 790                                 return -EINVAL;
 791                         }
 792                 } else if (frev == 3) {
 793                         switch (crev) {
 794                         case 0:
 795                                 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;
 796                                 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;
 797                                 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;
 798                                 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;
 799                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;
 800                                 return 0;
 801                         default:
 802                                 return -EINVAL;
 803                         }
 804                 } else {
 805                         return -EINVAL;
 806                 }
 807
 808         }
 809         return -EINVAL;
 810 }
 811
 812 /*
 813  * Helper function to query two stage mem training capability
 814  *
 815  * @adev: amdgpu_device pointer
 816  *
 817  * Return true if two stage mem training is supported or false if not
 818  */
 819 bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev)
 820 {
 821         u32 fw_cap;
 822
 823         fw_cap = adev->mode_info.firmware_flags;
 824
 825         return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;
 826 }
 827
 828 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 829 {
 830         struct atom_context *ctx = adev->mode_info.atom_context;
 831         union firmware_info *firmware_info;
 832         int index;
 833         u16 data_offset, size;
 834         u8 frev, crev;
 835         int fw_reserved_fb_size;
 836
 837         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 838                         firmwareinfo);
 839
 840         if (!amdgpu_atom_parse_data_header(ctx, index, &size,
 841                                 &frev, &crev, &data_offset))
 842                 /* fail to parse data_header */
 843                 return 0;
 844
 845         firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 846
 847         if (frev !=3)
 848                 return -EINVAL;
 849
 850         switch (crev) {
 851         case 4:
 852                 fw_reserved_fb_size =
 853                         (firmware_info->v34.fw_reserved_size_in_kb << 10);
 854                 break;
 855         default:
 856                 fw_reserved_fb_size = 0;
 857                 break;
 858         }
 859
 860         return fw_reserved_fb_size;
 861 }
 862
 863 /*
 864  * Helper function to execute asic_init table
 865  *
 866  * @adev: amdgpu_device pointer
 867  * @fb_reset: flag to indicate whether fb is reset or not
 868  *
 869  * Return 0 if succeed, otherwise failed
 870  */
 871 int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)
 872 {
 873         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 874         struct atom_context *ctx;
 875         uint8_t frev, crev;
 876         uint16_t data_offset;
 877         uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz;
 878         struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1;
 879         int index;
 880
 881         if (!mode_info)
 882                 return -EINVAL;
 883
 884         ctx = mode_info->atom_context;
 885         if (!ctx)
 886                 return -EINVAL;
 887
 888         /* query bootup sclk/mclk from firmware_info table */
 889         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 890                                             firmwareinfo);
 891         if (amdgpu_atom_parse_data_header(ctx, index, NULL,
 892                                 &frev, &crev, &data_offset)) {
 893                 union firmware_info *firmware_info =
 894                         (union firmware_info *)(ctx->bios +
 895                                                 data_offset);
 896
 897                 bootup_sclk_in10khz =
 898                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 899                 bootup_mclk_in10khz =
 900                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 901         } else {
 902                 return -EINVAL;
 903         }
 904
 905         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 906                                             asic_init);
 907         if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) {
 908                 if (frev == 2 && crev >= 1) {
 909                         memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1));
 910                         asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz;
 911                         asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz;
 912                         asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT;
 913                         if (!fb_reset)
 914                                 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT;
 915                         else
 916                                 asic_init_ps_v2_1.param.memparam.memflag = 0;
 917                 } else {
 918                         return -EINVAL;
 919                 }
 920         } else {
 921                 return -EINVAL;
 922         }
 923
 924         return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1);
 925 }