2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/amdgpu_drm.h>
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_i2c.h"
32 #include "amdgpu_display.h"
35 #include "atom-bits.h"
36 #include "atombios_encoders.h"
37 #include "bif/bif_4_1_d.h"
39 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
40 ATOM_GPIO_I2C_ASSIGMENT *gpio,
46 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
48 struct amdgpu_i2c_bus_rec i2c;
50 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
52 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
53 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
54 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
55 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
56 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
57 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
58 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
59 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
60 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
61 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
62 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
63 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
64 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
65 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
66 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
67 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
69 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
70 i2c.hw_capable = true;
72 i2c.hw_capable = false;
74 if (gpio->sucI2cId.ucAccess == 0xa0)
79 i2c.i2c_id = gpio->sucI2cId.ucAccess;
89 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
92 struct atom_context *ctx = adev->mode_info.atom_context;
93 ATOM_GPIO_I2C_ASSIGMENT *gpio;
94 struct amdgpu_i2c_bus_rec i2c;
95 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
96 struct _ATOM_GPIO_I2C_INFO *i2c_info;
97 uint16_t data_offset, size;
100 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
103 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
104 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
106 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
107 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
109 gpio = &i2c_info->asGPIO_Info[0];
110 for (i = 0; i < num_indices; i++) {
112 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
114 if (gpio->sucI2cId.ucAccess == id) {
115 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
118 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
119 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
126 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
128 struct atom_context *ctx = adev->mode_info.atom_context;
129 ATOM_GPIO_I2C_ASSIGMENT *gpio;
130 struct amdgpu_i2c_bus_rec i2c;
131 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
132 struct _ATOM_GPIO_I2C_INFO *i2c_info;
133 uint16_t data_offset, size;
137 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
138 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
140 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
141 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
143 gpio = &i2c_info->asGPIO_Info[0];
144 for (i = 0; i < num_indices; i++) {
145 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
147 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
150 sprintf(stmp, "0x%x", i2c.i2c_id);
151 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
153 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
154 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
159 struct amdgpu_gpio_rec
160 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
163 struct atom_context *ctx = adev->mode_info.atom_context;
164 struct amdgpu_gpio_rec gpio;
165 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
166 struct _ATOM_GPIO_PIN_LUT *gpio_info;
167 ATOM_GPIO_PIN_ASSIGNMENT *pin;
168 u16 data_offset, size;
171 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
174 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
175 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
177 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
178 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
180 pin = gpio_info->asGPIO_Pin;
181 for (i = 0; i < num_indices; i++) {
182 if (id == pin->ucGPIO_ID) {
183 gpio.id = pin->ucGPIO_ID;
184 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
185 gpio.shift = pin->ucGpioPinBitShift;
186 gpio.mask = (1 << pin->ucGpioPinBitShift);
190 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
191 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
198 static struct amdgpu_hpd
199 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
200 struct amdgpu_gpio_rec *gpio)
202 struct amdgpu_hpd hpd;
205 memset(&hpd, 0, sizeof(struct amdgpu_hpd));
207 reg = amdgpu_display_hpd_get_gpio_reg(adev);
210 if (gpio->reg == reg) {
213 hpd.hpd = AMDGPU_HPD_1;
216 hpd.hpd = AMDGPU_HPD_2;
219 hpd.hpd = AMDGPU_HPD_3;
222 hpd.hpd = AMDGPU_HPD_4;
225 hpd.hpd = AMDGPU_HPD_5;
228 hpd.hpd = AMDGPU_HPD_6;
231 hpd.hpd = AMDGPU_HPD_NONE;
235 hpd.hpd = AMDGPU_HPD_NONE;
239 static const int object_connector_convert[] = {
240 DRM_MODE_CONNECTOR_Unknown,
241 DRM_MODE_CONNECTOR_DVII,
242 DRM_MODE_CONNECTOR_DVII,
243 DRM_MODE_CONNECTOR_DVID,
244 DRM_MODE_CONNECTOR_DVID,
245 DRM_MODE_CONNECTOR_VGA,
246 DRM_MODE_CONNECTOR_Composite,
247 DRM_MODE_CONNECTOR_SVIDEO,
248 DRM_MODE_CONNECTOR_Unknown,
249 DRM_MODE_CONNECTOR_Unknown,
250 DRM_MODE_CONNECTOR_9PinDIN,
251 DRM_MODE_CONNECTOR_Unknown,
252 DRM_MODE_CONNECTOR_HDMIA,
253 DRM_MODE_CONNECTOR_HDMIB,
254 DRM_MODE_CONNECTOR_LVDS,
255 DRM_MODE_CONNECTOR_9PinDIN,
256 DRM_MODE_CONNECTOR_Unknown,
257 DRM_MODE_CONNECTOR_Unknown,
258 DRM_MODE_CONNECTOR_Unknown,
259 DRM_MODE_CONNECTOR_DisplayPort,
260 DRM_MODE_CONNECTOR_eDP,
261 DRM_MODE_CONNECTOR_Unknown
264 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
266 struct amdgpu_mode_info *mode_info = &adev->mode_info;
267 struct atom_context *ctx = mode_info->atom_context;
268 int index = GetIndexIntoMasterTable(DATA, Object_Header);
269 u16 size, data_offset;
271 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
272 ATOM_OBJECT_HEADER *obj_header;
274 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
280 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
281 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
282 (ctx->bios + data_offset +
283 le16_to_cpu(obj_header->usDisplayPathTableOffset));
285 if (path_obj->ucNumOfDispPath)
291 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
293 struct amdgpu_mode_info *mode_info = &adev->mode_info;
294 struct atom_context *ctx = mode_info->atom_context;
295 int index = GetIndexIntoMasterTable(DATA, Object_Header);
296 u16 size, data_offset;
298 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
299 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
300 ATOM_OBJECT_TABLE *router_obj;
301 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
302 ATOM_OBJECT_HEADER *obj_header;
303 int i, j, k, path_size, device_support;
305 u16 conn_id, connector_object_id;
306 struct amdgpu_i2c_bus_rec ddc_bus;
307 struct amdgpu_router router;
308 struct amdgpu_gpio_rec gpio;
309 struct amdgpu_hpd hpd;
311 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
317 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
318 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
319 (ctx->bios + data_offset +
320 le16_to_cpu(obj_header->usDisplayPathTableOffset));
321 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
322 (ctx->bios + data_offset +
323 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
324 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
325 (ctx->bios + data_offset +
326 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
327 router_obj = (ATOM_OBJECT_TABLE *)
328 (ctx->bios + data_offset +
329 le16_to_cpu(obj_header->usRouterObjectTableOffset));
330 device_support = le16_to_cpu(obj_header->usDeviceSupport);
333 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
334 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
335 ATOM_DISPLAY_OBJECT_PATH *path;
337 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
338 path_size += le16_to_cpu(path->usSize);
340 if (device_support & le16_to_cpu(path->usDeviceTag)) {
342 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
345 /* Skip TV/CV support */
346 if ((le16_to_cpu(path->usDeviceTag) ==
347 ATOM_DEVICE_TV1_SUPPORT) ||
348 (le16_to_cpu(path->usDeviceTag) ==
349 ATOM_DEVICE_CV_SUPPORT))
352 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
353 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
354 con_obj_id, le16_to_cpu(path->usDeviceTag));
359 object_connector_convert[con_obj_id];
360 connector_object_id = con_obj_id;
362 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
365 router.ddc_valid = false;
366 router.cd_valid = false;
367 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
368 uint8_t grph_obj_type=
370 (le16_to_cpu(path->usGraphicObjIds[j]) &
371 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
373 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
374 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
375 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
376 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
377 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
378 (ctx->bios + data_offset +
379 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
380 ATOM_ENCODER_CAP_RECORD *cap_record;
383 while (record->ucRecordSize > 0 &&
384 record->ucRecordType > 0 &&
385 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
386 switch (record->ucRecordType) {
387 case ATOM_ENCODER_CAP_RECORD_TYPE:
388 cap_record =(ATOM_ENCODER_CAP_RECORD *)
390 caps = le16_to_cpu(cap_record->usEncoderCap);
393 record = (ATOM_COMMON_RECORD_HEADER *)
394 ((char *)record + record->ucRecordSize);
396 amdgpu_display_add_encoder(adev, encoder_obj,
397 le16_to_cpu(path->usDeviceTag),
401 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
402 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
403 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
404 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
405 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
406 (ctx->bios + data_offset +
407 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
408 ATOM_I2C_RECORD *i2c_record;
409 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
410 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
411 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
412 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
413 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
414 (ctx->bios + data_offset +
415 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
416 u8 *num_dst_objs = (u8 *)
417 ((u8 *)router_src_dst_table + 1 +
418 (router_src_dst_table->ucNumberOfSrc * 2));
419 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
422 router.router_id = router_obj_id;
423 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
424 if (le16_to_cpu(path->usConnObjectId) ==
425 le16_to_cpu(dst_objs[enum_id]))
429 while (record->ucRecordSize > 0 &&
430 record->ucRecordType > 0 &&
431 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
432 switch (record->ucRecordType) {
433 case ATOM_I2C_RECORD_TYPE:
438 (ATOM_I2C_ID_CONFIG_ACCESS *)
439 &i2c_record->sucI2cId;
441 amdgpu_atombios_lookup_i2c_gpio(adev,
444 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
446 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
447 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
449 router.ddc_valid = true;
450 router.ddc_mux_type = ddc_path->ucMuxType;
451 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
452 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
454 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
455 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
457 router.cd_valid = true;
458 router.cd_mux_type = cd_path->ucMuxType;
459 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
460 router.cd_mux_state = cd_path->ucMuxState[enum_id];
463 record = (ATOM_COMMON_RECORD_HEADER *)
464 ((char *)record + record->ucRecordSize);
471 /* look up gpio for ddc, hpd */
472 ddc_bus.valid = false;
473 hpd.hpd = AMDGPU_HPD_NONE;
474 if ((le16_to_cpu(path->usDeviceTag) &
475 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
476 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
477 if (le16_to_cpu(path->usConnObjectId) ==
478 le16_to_cpu(con_obj->asObjects[j].
480 ATOM_COMMON_RECORD_HEADER
482 (ATOM_COMMON_RECORD_HEADER
484 (ctx->bios + data_offset +
485 le16_to_cpu(con_obj->
488 ATOM_I2C_RECORD *i2c_record;
489 ATOM_HPD_INT_RECORD *hpd_record;
490 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
492 while (record->ucRecordSize > 0 &&
493 record->ucRecordType > 0 &&
494 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
495 switch (record->ucRecordType) {
496 case ATOM_I2C_RECORD_TYPE:
501 (ATOM_I2C_ID_CONFIG_ACCESS *)
502 &i2c_record->sucI2cId;
503 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
507 case ATOM_HPD_INT_RECORD_TYPE:
509 (ATOM_HPD_INT_RECORD *)
511 gpio = amdgpu_atombios_lookup_gpio(adev,
512 hpd_record->ucHPDIntGPIOID);
513 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
514 hpd.plugged_state = hpd_record->ucPlugged_PinState;
518 (ATOM_COMMON_RECORD_HEADER
529 /* needed for aux chan transactions */
530 ddc_bus.hpd = hpd.hpd;
532 conn_id = le16_to_cpu(path->usConnObjectId);
534 amdgpu_display_add_connector(adev,
536 le16_to_cpu(path->usDeviceTag),
537 connector_type, &ddc_bus,
545 amdgpu_link_encoder_connector(adev->ddev);
550 union firmware_info {
551 ATOM_FIRMWARE_INFO info;
552 ATOM_FIRMWARE_INFO_V1_2 info_12;
553 ATOM_FIRMWARE_INFO_V1_3 info_13;
554 ATOM_FIRMWARE_INFO_V1_4 info_14;
555 ATOM_FIRMWARE_INFO_V2_1 info_21;
556 ATOM_FIRMWARE_INFO_V2_2 info_22;
559 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
561 struct amdgpu_mode_info *mode_info = &adev->mode_info;
562 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
564 uint16_t data_offset;
567 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
568 &frev, &crev, &data_offset)) {
570 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
571 struct amdgpu_pll *spll = &adev->clock.spll;
572 struct amdgpu_pll *mpll = &adev->clock.mpll;
573 union firmware_info *firmware_info =
574 (union firmware_info *)(mode_info->atom_context->bios +
577 ppll->reference_freq =
578 le16_to_cpu(firmware_info->info.usReferenceClock);
579 ppll->reference_div = 0;
582 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
584 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
586 ppll->lcd_pll_out_min =
587 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
588 if (ppll->lcd_pll_out_min == 0)
589 ppll->lcd_pll_out_min = ppll->pll_out_min;
590 ppll->lcd_pll_out_max =
591 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
592 if (ppll->lcd_pll_out_max == 0)
593 ppll->lcd_pll_out_max = ppll->pll_out_max;
595 if (ppll->pll_out_min == 0)
596 ppll->pll_out_min = 64800;
599 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
601 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
603 ppll->min_post_div = 2;
604 ppll->max_post_div = 0x7f;
605 ppll->min_frac_feedback_div = 0;
606 ppll->max_frac_feedback_div = 9;
607 ppll->min_ref_div = 2;
608 ppll->max_ref_div = 0x3ff;
609 ppll->min_feedback_div = 4;
610 ppll->max_feedback_div = 0xfff;
613 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
614 adev->clock.ppll[i] = *ppll;
617 spll->reference_freq =
618 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
619 spll->reference_div = 0;
622 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
624 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
627 if (spll->pll_out_min == 0)
628 spll->pll_out_min = 64800;
631 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
633 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
635 spll->min_post_div = 1;
636 spll->max_post_div = 1;
637 spll->min_ref_div = 2;
638 spll->max_ref_div = 0xff;
639 spll->min_feedback_div = 4;
640 spll->max_feedback_div = 0xff;
644 mpll->reference_freq =
645 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
646 mpll->reference_div = 0;
649 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
651 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
654 if (mpll->pll_out_min == 0)
655 mpll->pll_out_min = 64800;
658 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
660 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
662 adev->clock.default_sclk =
663 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
664 adev->clock.default_mclk =
665 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
667 mpll->min_post_div = 1;
668 mpll->max_post_div = 1;
669 mpll->min_ref_div = 2;
670 mpll->max_ref_div = 0xff;
671 mpll->min_feedback_div = 4;
672 mpll->max_feedback_div = 0xff;
676 adev->clock.default_dispclk =
677 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
678 /* set a reasonable default for DP */
679 if (adev->clock.default_dispclk < 53900) {
680 DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n",
681 adev->clock.default_dispclk / 100);
682 adev->clock.default_dispclk = 60000;
683 } else if (adev->clock.default_dispclk <= 60000) {
684 DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n",
685 adev->clock.default_dispclk / 100);
686 adev->clock.default_dispclk = 62500;
688 adev->clock.dp_extclk =
689 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
690 adev->clock.current_dispclk = adev->clock.default_dispclk;
692 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
693 if (adev->clock.max_pixel_clock == 0)
694 adev->clock.max_pixel_clock = 40000;
696 /* not technically a clock, but... */
697 adev->mode_info.firmware_flags =
698 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
703 adev->pm.current_sclk = adev->clock.default_sclk;
704 adev->pm.current_mclk = adev->clock.default_mclk;
710 ATOM_GFX_INFO_V2_1 info;
713 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
715 struct amdgpu_mode_info *mode_info = &adev->mode_info;
716 int index = GetIndexIntoMasterTable(DATA, GFX_Info);
718 uint16_t data_offset;
721 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
722 &frev, &crev, &data_offset)) {
723 union gfx_info *gfx_info = (union gfx_info *)
724 (mode_info->atom_context->bios + data_offset);
726 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
727 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
728 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
729 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
730 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
731 adev->gfx.config.max_texture_channel_caches =
732 gfx_info->info.max_texture_channel_caches;
740 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
741 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
742 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
743 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
744 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
745 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
749 * Return vram width from integrated system info table, if available,
752 int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev)
754 struct amdgpu_mode_info *mode_info = &adev->mode_info;
755 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
756 u16 data_offset, size;
757 union igp_info *igp_info;
760 /* get any igp specific overrides */
761 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
762 &frev, &crev, &data_offset)) {
763 igp_info = (union igp_info *)
764 (mode_info->atom_context->bios + data_offset);
768 return igp_info->info_8.ucUMAChannelNumber * 64;
777 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
778 struct amdgpu_atom_ss *ss,
781 struct amdgpu_mode_info *mode_info = &adev->mode_info;
782 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
783 u16 data_offset, size;
784 union igp_info *igp_info;
786 u16 percentage = 0, rate = 0;
788 /* get any igp specific overrides */
789 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
790 &frev, &crev, &data_offset)) {
791 igp_info = (union igp_info *)
792 (mode_info->atom_context->bios + data_offset);
796 case ASIC_INTERNAL_SS_ON_TMDS:
797 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
798 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
800 case ASIC_INTERNAL_SS_ON_HDMI:
801 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
802 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
804 case ASIC_INTERNAL_SS_ON_LVDS:
805 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
806 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
812 case ASIC_INTERNAL_SS_ON_TMDS:
813 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
814 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
816 case ASIC_INTERNAL_SS_ON_HDMI:
817 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
818 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
820 case ASIC_INTERNAL_SS_ON_LVDS:
821 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
822 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
828 case ASIC_INTERNAL_SS_ON_TMDS:
829 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
830 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
832 case ASIC_INTERNAL_SS_ON_HDMI:
833 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
834 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
836 case ASIC_INTERNAL_SS_ON_LVDS:
837 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
838 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
844 case ASIC_INTERNAL_SS_ON_TMDS:
845 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
846 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
848 case ASIC_INTERNAL_SS_ON_HDMI:
849 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
850 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
852 case ASIC_INTERNAL_SS_ON_LVDS:
853 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
854 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
859 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
863 ss->percentage = percentage;
870 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
871 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
872 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
875 union asic_ss_assignment {
876 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
877 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
878 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
881 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
882 struct amdgpu_atom_ss *ss,
885 struct amdgpu_mode_info *mode_info = &adev->mode_info;
886 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
887 uint16_t data_offset, size;
888 union asic_ss_info *ss_info;
889 union asic_ss_assignment *ss_assign;
893 if (id == ASIC_INTERNAL_MEMORY_SS) {
894 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
897 if (id == ASIC_INTERNAL_ENGINE_SS) {
898 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
902 memset(ss, 0, sizeof(struct amdgpu_atom_ss));
903 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
904 &frev, &crev, &data_offset)) {
907 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
911 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
912 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
914 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
915 for (i = 0; i < num_indices; i++) {
916 if ((ss_assign->v1.ucClockIndication == id) &&
917 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
919 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
920 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
921 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
922 ss->percentage_divider = 100;
925 ss_assign = (union asic_ss_assignment *)
926 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
930 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
931 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
932 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
933 for (i = 0; i < num_indices; i++) {
934 if ((ss_assign->v2.ucClockIndication == id) &&
935 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
937 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
938 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
939 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
940 ss->percentage_divider = 100;
942 ((id == ASIC_INTERNAL_ENGINE_SS) ||
943 (id == ASIC_INTERNAL_MEMORY_SS)))
947 ss_assign = (union asic_ss_assignment *)
948 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
952 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
953 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
954 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
955 for (i = 0; i < num_indices; i++) {
956 if ((ss_assign->v3.ucClockIndication == id) &&
957 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
959 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
960 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
961 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
962 if (ss_assign->v3.ucSpreadSpectrumMode &
963 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
964 ss->percentage_divider = 1000;
966 ss->percentage_divider = 100;
967 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
968 (id == ASIC_INTERNAL_MEMORY_SS))
970 if (adev->flags & AMD_IS_APU)
971 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
974 ss_assign = (union asic_ss_assignment *)
975 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
979 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
987 union get_clock_dividers {
988 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
989 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
990 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
991 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
992 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
993 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
994 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
997 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
1001 struct atom_clock_dividers *dividers)
1003 union get_clock_dividers args;
1004 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
1007 memset(&args, 0, sizeof(args));
1008 memset(dividers, 0, sizeof(struct atom_clock_dividers));
1010 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1017 /* r6xx, r7xx, evergreen, ni, si.
1018 * TODO: add support for asic_type <= CHIP_RV770*/
1019 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
1020 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1022 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1024 dividers->post_div = args.v3.ucPostDiv;
1025 dividers->enable_post_div = (args.v3.ucCntlFlag &
1026 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1027 dividers->enable_dithen = (args.v3.ucCntlFlag &
1028 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1029 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
1030 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
1031 dividers->ref_div = args.v3.ucRefDiv;
1032 dividers->vco_mode = (args.v3.ucCntlFlag &
1033 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1035 /* for SI we use ComputeMemoryClockParam for memory plls */
1036 if (adev->asic_type >= CHIP_TAHITI)
1038 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1040 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1042 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1044 dividers->post_div = args.v5.ucPostDiv;
1045 dividers->enable_post_div = (args.v5.ucCntlFlag &
1046 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1047 dividers->enable_dithen = (args.v5.ucCntlFlag &
1048 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1049 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1050 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1051 dividers->ref_div = args.v5.ucRefDiv;
1052 dividers->vco_mode = (args.v5.ucCntlFlag &
1053 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1058 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
1060 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1062 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1063 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1067 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1068 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1069 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
1071 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1073 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1074 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1075 dividers->ref_div = args.v6_out.ucPllRefDiv;
1076 dividers->post_div = args.v6_out.ucPllPostDiv;
1077 dividers->flags = args.v6_out.ucPllCntlFlag;
1078 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1079 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1087 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1090 struct atom_mpll_param *mpll_param)
1092 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1093 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1096 memset(&args, 0, sizeof(args));
1097 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1099 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1107 args.ulClock = cpu_to_le32(clock); /* 10 khz */
1108 args.ucInputFlag = 0;
1110 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1112 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1114 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1115 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1116 mpll_param->post_div = args.ucPostDiv;
1117 mpll_param->dll_speed = args.ucDllSpeed;
1118 mpll_param->bwcntl = args.ucBWCntl;
1119 mpll_param->vco_mode =
1120 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1121 mpll_param->yclk_sel =
1122 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1124 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1125 mpll_param->half_rate =
1126 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1138 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1139 u32 eng_clock, u32 mem_clock)
1141 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1142 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1145 memset(&args, 0, sizeof(args));
1147 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1148 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1150 args.ulTargetEngineClock = cpu_to_le32(tmp);
1152 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1154 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1157 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1158 u16 *vddc, u16 *vddci, u16 *mvdd)
1160 struct amdgpu_mode_info *mode_info = &adev->mode_info;
1161 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1164 union firmware_info *firmware_info;
1170 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1171 &frev, &crev, &data_offset)) {
1173 (union firmware_info *)(mode_info->atom_context->bios +
1175 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1176 if ((frev == 2) && (crev >= 2)) {
1177 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1178 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1184 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1185 struct _SET_VOLTAGE_PARAMETERS v1;
1186 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1187 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1190 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1191 u16 voltage_id, u16 *voltage)
1193 union set_voltage args;
1194 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1197 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1204 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1205 args.v2.ucVoltageMode = 0;
1206 args.v2.usVoltageLevel = 0;
1208 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1210 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1213 args.v3.ucVoltageType = voltage_type;
1214 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1215 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1217 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1219 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1222 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1229 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1233 return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
1236 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1239 union set_voltage args;
1240 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1243 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1249 args.v3.ucVoltageType = 0;
1250 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1251 args.v3.usVoltageLevel = 0;
1253 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1255 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1258 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1265 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1266 u16 *vddc, u16 *vddci,
1267 u16 virtual_voltage_id,
1268 u16 vbios_voltage_id)
1270 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1272 u16 data_offset, size;
1274 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1275 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1280 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1281 &frev, &crev, &data_offset))
1284 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1285 (adev->mode_info.atom_context->bios + data_offset);
1293 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1295 leakage_bin = (u16 *)
1296 (adev->mode_info.atom_context->bios + data_offset +
1297 le16_to_cpu(profile->usLeakageBinArrayOffset));
1298 vddc_id_buf = (u16 *)
1299 (adev->mode_info.atom_context->bios + data_offset +
1300 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1302 (adev->mode_info.atom_context->bios + data_offset +
1303 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1304 vddci_id_buf = (u16 *)
1305 (adev->mode_info.atom_context->bios + data_offset +
1306 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1308 (adev->mode_info.atom_context->bios + data_offset +
1309 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1311 if (profile->ucElbVDDC_Num > 0) {
1312 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1313 if (vddc_id_buf[i] == virtual_voltage_id) {
1314 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1315 if (vbios_voltage_id <= leakage_bin[j]) {
1316 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1324 if (profile->ucElbVDDCI_Num > 0) {
1325 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1326 if (vddci_id_buf[i] == virtual_voltage_id) {
1327 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1328 if (vbios_voltage_id <= leakage_bin[j]) {
1329 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1339 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1344 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1351 union get_voltage_info {
1352 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1353 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1356 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1357 u16 virtual_voltage_id,
1360 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1362 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1363 union get_voltage_info args;
1365 for (entry_id = 0; entry_id < count; entry_id++) {
1366 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1371 if (entry_id >= count)
1374 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1375 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1376 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1377 args.in.ulSCLKFreq =
1378 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1380 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1382 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1387 union voltage_object_info {
1388 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1389 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1390 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1393 union voltage_object {
1394 struct _ATOM_VOLTAGE_OBJECT v1;
1395 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1396 union _ATOM_VOLTAGE_OBJECT_V3 v3;
1400 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1401 u8 voltage_type, u8 voltage_mode)
1403 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1404 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1405 u8 *start = (u8*)v3;
1407 while (offset < size) {
1408 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1409 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1410 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1412 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1417 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1419 u8 *svd_gpio_id, u8 *svc_gpio_id)
1421 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1423 u16 data_offset, size;
1424 union voltage_object_info *voltage_info;
1425 union voltage_object *voltage_object = NULL;
1427 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1428 &frev, &crev, &data_offset)) {
1429 voltage_info = (union voltage_object_info *)
1430 (adev->mode_info.atom_context->bios + data_offset);
1436 voltage_object = (union voltage_object *)
1437 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1440 if (voltage_object) {
1441 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1442 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1448 DRM_ERROR("unknown voltage object table\n");
1453 DRM_ERROR("unknown voltage object table\n");
1462 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1463 u8 voltage_type, u8 voltage_mode)
1465 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1467 u16 data_offset, size;
1468 union voltage_object_info *voltage_info;
1470 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1471 &frev, &crev, &data_offset)) {
1472 voltage_info = (union voltage_object_info *)
1473 (adev->mode_info.atom_context->bios + data_offset);
1479 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1480 voltage_type, voltage_mode))
1484 DRM_ERROR("unknown voltage object table\n");
1489 DRM_ERROR("unknown voltage object table\n");
1497 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1498 u8 voltage_type, u8 voltage_mode,
1499 struct atom_voltage_table *voltage_table)
1501 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1503 u16 data_offset, size;
1505 union voltage_object_info *voltage_info;
1506 union voltage_object *voltage_object = NULL;
1508 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1509 &frev, &crev, &data_offset)) {
1510 voltage_info = (union voltage_object_info *)
1511 (adev->mode_info.atom_context->bios + data_offset);
1517 voltage_object = (union voltage_object *)
1518 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1519 voltage_type, voltage_mode);
1520 if (voltage_object) {
1521 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1522 &voltage_object->v3.asGpioVoltageObj;
1523 VOLTAGE_LUT_ENTRY_V2 *lut;
1524 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1526 lut = &gpio->asVolGpioLut[0];
1527 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1528 voltage_table->entries[i].value =
1529 le16_to_cpu(lut->usVoltageValue);
1530 voltage_table->entries[i].smio_low =
1531 le32_to_cpu(lut->ulVoltageId);
1532 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1533 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1535 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1536 voltage_table->count = gpio->ucGpioEntryNum;
1537 voltage_table->phase_delay = gpio->ucPhaseDelay;
1542 DRM_ERROR("unknown voltage object table\n");
1547 DRM_ERROR("unknown voltage object table\n");
1555 struct _ATOM_VRAM_INFO_V3 v1_3;
1556 struct _ATOM_VRAM_INFO_V4 v1_4;
1557 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1560 #define MEM_ID_MASK 0xff000000
1561 #define MEM_ID_SHIFT 24
1562 #define CLOCK_RANGE_MASK 0x00ffffff
1563 #define CLOCK_RANGE_SHIFT 0
1564 #define LOW_NIBBLE_MASK 0xf
1565 #define DATA_EQU_PREV 0
1566 #define DATA_FROM_TABLE 4
1568 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1570 struct atom_mc_reg_table *reg_table)
1572 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1573 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1575 u16 data_offset, size;
1576 union vram_info *vram_info;
1578 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1580 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1581 &frev, &crev, &data_offset)) {
1582 vram_info = (union vram_info *)
1583 (adev->mode_info.atom_context->bios + data_offset);
1586 DRM_ERROR("old table version %d, %d\n", frev, crev);
1591 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1592 ATOM_INIT_REG_BLOCK *reg_block =
1593 (ATOM_INIT_REG_BLOCK *)
1594 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1595 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1596 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1597 ((u8 *)reg_block + (2 * sizeof(u16)) +
1598 le16_to_cpu(reg_block->usRegIndexTblSize));
1599 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
1600 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1601 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1602 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1604 while (i < num_entries) {
1605 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1607 reg_table->mc_reg_address[i].s1 =
1608 (u16)(le16_to_cpu(format->usRegIndex));
1609 reg_table->mc_reg_address[i].pre_reg_data =
1610 (u8)(format->ucPreRegDataLength);
1612 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1613 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1615 reg_table->last = i;
1616 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1617 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1618 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1620 if (module_index == t_mem_id) {
1621 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1622 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1623 >> CLOCK_RANGE_SHIFT);
1624 for (i = 0, j = 1; i < reg_table->last; i++) {
1625 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1626 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1627 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1629 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1630 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1631 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1636 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1637 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1639 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1641 reg_table->num_entries = num_ranges;
1646 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1651 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1659 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1661 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1663 u16 data_offset, size;
1665 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1666 &frev, &crev, &data_offset))
1672 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1674 uint32_t bios_6_scratch;
1676 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1679 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1680 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1682 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1683 bios_6_scratch |= ATOM_S6_ACC_MODE;
1686 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1689 static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1691 uint32_t bios_2_scratch, bios_6_scratch;
1693 adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
1695 bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
1696 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1698 /* let the bios control the backlight */
1699 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1701 /* tell the bios not to handle mode switching */
1702 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1704 /* clear the vbios dpms state */
1705 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1707 WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);
1708 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1711 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
1714 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
1717 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1719 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1721 WREG32(adev->bios_scratch_reg_offset + 3, tmp);
1724 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
1726 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
1728 if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
1734 /* Atom needs data in little endian format so swap as appropriate when copying
1735 * data to or from atom. Note that atom operates on dw units.
1737 * Use to_le=true when sending data to atom and provide at least
1738 * ALIGN(num_bytes,4) bytes in the dst buffer.
1740 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
1741 * byes in the src buffer.
1743 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1746 u32 src_tmp[5], dst_tmp[5];
1748 u8 align_num_bytes = ALIGN(num_bytes, 4);
1751 memcpy(src_tmp, src, num_bytes);
1752 for (i = 0; i < align_num_bytes / 4; i++)
1753 dst_tmp[i] = cpu_to_le32(src_tmp[i]);
1754 memcpy(dst, dst_tmp, align_num_bytes);
1756 memcpy(src_tmp, src, align_num_bytes);
1757 for (i = 0; i < align_num_bytes / 4; i++)
1758 dst_tmp[i] = le32_to_cpu(src_tmp[i]);
1759 memcpy(dst, dst_tmp, num_bytes);
1762 memcpy(dst, src, num_bytes);
1766 static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
1768 struct atom_context *ctx = adev->mode_info.atom_context;
1769 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
1770 uint16_t data_offset;
1771 int usage_bytes = 0;
1772 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
1776 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
1777 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1779 DRM_DEBUG("atom firmware requested %08x %dkb\n",
1780 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1781 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1783 start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
1784 size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
1786 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
1787 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
1788 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
1789 /* Firmware request VRAM reservation for SR-IOV */
1790 adev->fw_vram_usage.start_offset = (start_addr &
1791 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
1792 adev->fw_vram_usage.size = size << 10;
1793 /* Use the default scratch size */
1796 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1799 ctx->scratch_size_bytes = 0;
1800 if (usage_bytes == 0)
1801 usage_bytes = 20 * 1024;
1802 /* allocate some scratch memory */
1803 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
1806 ctx->scratch_size_bytes = usage_bytes;
1810 /* ATOM accessor methods */
1812 * ATOM is an interpreted byte code stored in tables in the vbios. The
1813 * driver registers callbacks to access registers and the interpreter
1814 * in the driver parses the tables and executes then to program specific
1815 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
1816 * atombios.h, and atom.c
1820 * cail_pll_read - read PLL register
1822 * @info: atom card_info pointer
1823 * @reg: PLL register offset
1825 * Provides a PLL register accessor for the atom interpreter (r4xx+).
1826 * Returns the value of the PLL register.
1828 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
1834 * cail_pll_write - write PLL register
1836 * @info: atom card_info pointer
1837 * @reg: PLL register offset
1838 * @val: value to write to the pll register
1840 * Provides a PLL register accessor for the atom interpreter (r4xx+).
1842 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
1848 * cail_mc_read - read MC (Memory Controller) register
1850 * @info: atom card_info pointer
1851 * @reg: MC register offset
1853 * Provides an MC register accessor for the atom interpreter (r4xx+).
1854 * Returns the value of the MC register.
1856 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
1862 * cail_mc_write - write MC (Memory Controller) register
1864 * @info: atom card_info pointer
1865 * @reg: MC register offset
1866 * @val: value to write to the pll register
1868 * Provides a MC register accessor for the atom interpreter (r4xx+).
1870 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
1876 * cail_reg_write - write MMIO register
1878 * @info: atom card_info pointer
1879 * @reg: MMIO register offset
1880 * @val: value to write to the pll register
1882 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
1884 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
1886 struct amdgpu_device *adev = info->dev->dev_private;
1892 * cail_reg_read - read MMIO register
1894 * @info: atom card_info pointer
1895 * @reg: MMIO register offset
1897 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
1898 * Returns the value of the MMIO register.
1900 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
1902 struct amdgpu_device *adev = info->dev->dev_private;
1910 * cail_ioreg_write - write IO register
1912 * @info: atom card_info pointer
1913 * @reg: IO register offset
1914 * @val: value to write to the pll register
1916 * Provides a IO register accessor for the atom interpreter (r4xx+).
1918 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
1920 struct amdgpu_device *adev = info->dev->dev_private;
1922 WREG32_IO(reg, val);
1926 * cail_ioreg_read - read IO register
1928 * @info: atom card_info pointer
1929 * @reg: IO register offset
1931 * Provides an IO register accessor for the atom interpreter (r4xx+).
1932 * Returns the value of the IO register.
1934 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
1936 struct amdgpu_device *adev = info->dev->dev_private;
1943 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
1944 struct device_attribute *attr,
1947 struct drm_device *ddev = dev_get_drvdata(dev);
1948 struct amdgpu_device *adev = ddev->dev_private;
1949 struct atom_context *ctx = adev->mode_info.atom_context;
1951 return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
1954 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
1958 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
1960 * @adev: amdgpu_device pointer
1962 * Frees the driver info and register access callbacks for the ATOM
1963 * interpreter (r4xx+).
1964 * Called at driver shutdown.
1966 void amdgpu_atombios_fini(struct amdgpu_device *adev)
1968 if (adev->mode_info.atom_context) {
1969 kfree(adev->mode_info.atom_context->scratch);
1970 kfree(adev->mode_info.atom_context->iio);
1972 kfree(adev->mode_info.atom_context);
1973 adev->mode_info.atom_context = NULL;
1974 kfree(adev->mode_info.atom_card_info);
1975 adev->mode_info.atom_card_info = NULL;
1976 device_remove_file(adev->dev, &dev_attr_vbios_version);
1980 * amdgpu_atombios_init - init the driver info and callbacks for atombios
1982 * @adev: amdgpu_device pointer
1984 * Initializes the driver info and register access callbacks for the
1985 * ATOM interpreter (r4xx+).
1986 * Returns 0 on sucess, -ENOMEM on failure.
1987 * Called at driver startup.
1989 int amdgpu_atombios_init(struct amdgpu_device *adev)
1991 struct card_info *atom_card_info =
1992 kzalloc(sizeof(struct card_info), GFP_KERNEL);
1995 if (!atom_card_info)
1998 adev->mode_info.atom_card_info = atom_card_info;
1999 atom_card_info->dev = adev->ddev;
2000 atom_card_info->reg_read = cail_reg_read;
2001 atom_card_info->reg_write = cail_reg_write;
2002 /* needed for iio ops */
2003 if (adev->rio_mem) {
2004 atom_card_info->ioreg_read = cail_ioreg_read;
2005 atom_card_info->ioreg_write = cail_ioreg_write;
2007 DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
2008 atom_card_info->ioreg_read = cail_reg_read;
2009 atom_card_info->ioreg_write = cail_reg_write;
2011 atom_card_info->mc_read = cail_mc_read;
2012 atom_card_info->mc_write = cail_mc_write;
2013 atom_card_info->pll_read = cail_pll_read;
2014 atom_card_info->pll_write = cail_pll_write;
2016 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
2017 if (!adev->mode_info.atom_context) {
2018 amdgpu_atombios_fini(adev);
2022 mutex_init(&adev->mode_info.atom_context->mutex);
2023 if (adev->is_atom_fw) {
2024 amdgpu_atomfirmware_scratch_regs_init(adev);
2025 amdgpu_atomfirmware_allocate_fb_scratch(adev);
2026 ret = amdgpu_atomfirmware_get_mem_train_fb_loc(adev);
2028 DRM_ERROR("Failed to get mem train fb location.\n");
2032 amdgpu_atombios_scratch_regs_init(adev);
2033 amdgpu_atombios_allocate_fb_scratch(adev);
2036 ret = device_create_file(adev->dev, &dev_attr_vbios_version);
2038 DRM_ERROR("Failed to create device file for VBIOS version\n");