2 * Copyright 2014-2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #include <linux/dma-buf.h>
23 #include <linux/list.h>
24 #include <linux/pagemap.h>
25 #include <linux/sched/mm.h>
26 #include <linux/sched/task.h>
28 #include "amdgpu_object.h"
29 #include "amdgpu_gem.h"
30 #include "amdgpu_vm.h"
31 #include "amdgpu_amdkfd.h"
32 #include "amdgpu_dma_buf.h"
33 #include <uapi/linux/kfd_ioctl.h>
34 #include "amdgpu_xgmi.h"
36 /* Userptr restore delay, just long enough to allow consecutive VM
37 * changes to accumulate
39 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
41 /* Impose limit on how much memory KFD can use */
43 uint64_t max_system_mem_limit;
44 uint64_t max_ttm_mem_limit;
45 int64_t system_mem_used;
47 spinlock_t mem_limit_lock;
50 static const char * const domain_bit_to_string[] = {
59 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
61 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
63 static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
66 struct kfd_mem_attachment *entry;
68 list_for_each_entry(entry, &mem->attachments, list)
69 if (entry->bo_va->base.vm == avm)
75 /* Set memory usage limits. Current, limits are
76 * System (TTM + userptr) memory - 15/16th System RAM
77 * TTM memory - 3/8th System RAM
79 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
85 mem = si.freeram - si.freehigh;
88 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
89 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
90 kfd_mem_limit.max_ttm_mem_limit = (mem >> 1) - (mem >> 3);
91 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
92 (kfd_mem_limit.max_system_mem_limit >> 20),
93 (kfd_mem_limit.max_ttm_mem_limit >> 20));
96 void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
98 kfd_mem_limit.system_mem_used += size;
101 /* Estimate page table size needed to represent a given memory size
103 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
104 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
105 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
106 * for 2MB pages for TLB efficiency. However, small allocations and
107 * fragmented system memory still need some 4KB pages. We choose a
108 * compromise that should work in most cases without reserving too
109 * much memory for page tables unnecessarily (factor 16K, >> 14).
111 #define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)
113 static size_t amdgpu_amdkfd_acc_size(uint64_t size)
116 size *= sizeof(dma_addr_t) + sizeof(void *);
118 return __roundup_pow_of_two(sizeof(struct amdgpu_bo)) +
119 __roundup_pow_of_two(sizeof(struct ttm_tt)) +
124 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
125 * of buffer including any reserved for control structures
127 * @adev: Device to which allocated BO belongs to
128 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
129 * equivalent to amdgpu_bo_size(BO)
130 * @alloc_flag: Flag used in allocating a BO as noted above
132 * Return: returns -ENOMEM in case of error, ZERO otherwise
134 static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
135 uint64_t size, u32 alloc_flag)
137 uint64_t reserved_for_pt =
138 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
139 size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed;
142 acc_size = amdgpu_amdkfd_acc_size(size);
145 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
146 system_mem_needed = acc_size + size;
147 ttm_mem_needed = acc_size + size;
148 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
149 system_mem_needed = acc_size;
150 ttm_mem_needed = acc_size;
152 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
153 system_mem_needed = acc_size + size;
154 ttm_mem_needed = acc_size;
155 } else if (alloc_flag &
156 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
157 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
158 system_mem_needed = acc_size;
159 ttm_mem_needed = acc_size;
161 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
165 spin_lock(&kfd_mem_limit.mem_limit_lock);
167 if (kfd_mem_limit.system_mem_used + system_mem_needed >
168 kfd_mem_limit.max_system_mem_limit)
169 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
171 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
172 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
173 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
174 kfd_mem_limit.max_ttm_mem_limit) ||
175 (adev->kfd.vram_used + vram_needed >
176 adev->gmc.real_vram_size - reserved_for_pt)) {
181 /* Update memory accounting by decreasing available system
182 * memory, TTM memory and GPU memory as computed above
184 adev->kfd.vram_used += vram_needed;
185 kfd_mem_limit.system_mem_used += system_mem_needed;
186 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
189 spin_unlock(&kfd_mem_limit.mem_limit_lock);
193 static void unreserve_mem_limit(struct amdgpu_device *adev,
194 uint64_t size, u32 alloc_flag)
198 acc_size = amdgpu_amdkfd_acc_size(size);
200 spin_lock(&kfd_mem_limit.mem_limit_lock);
202 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
203 kfd_mem_limit.system_mem_used -= (acc_size + size);
204 kfd_mem_limit.ttm_mem_used -= (acc_size + size);
205 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
206 kfd_mem_limit.system_mem_used -= acc_size;
207 kfd_mem_limit.ttm_mem_used -= acc_size;
208 adev->kfd.vram_used -= size;
209 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
210 kfd_mem_limit.system_mem_used -= (acc_size + size);
211 kfd_mem_limit.ttm_mem_used -= acc_size;
212 } else if (alloc_flag &
213 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
214 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
215 kfd_mem_limit.system_mem_used -= acc_size;
216 kfd_mem_limit.ttm_mem_used -= acc_size;
218 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
222 WARN_ONCE(adev->kfd.vram_used < 0,
223 "KFD VRAM memory accounting unbalanced");
224 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
225 "KFD TTM memory accounting unbalanced");
226 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
227 "KFD system memory accounting unbalanced");
230 spin_unlock(&kfd_mem_limit.mem_limit_lock);
233 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
235 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
236 u32 alloc_flags = bo->kfd_bo->alloc_flags;
237 u64 size = amdgpu_bo_size(bo);
239 unreserve_mem_limit(adev, size, alloc_flags);
244 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
245 * reservation object.
247 * @bo: [IN] Remove eviction fence(s) from this BO
248 * @ef: [IN] This eviction fence is removed if it
249 * is present in the shared list.
251 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
253 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
254 struct amdgpu_amdkfd_fence *ef)
256 struct dma_fence *replacement;
261 /* TODO: Instead of block before we should use the fence of the page
262 * table update and TLB flush here directly.
264 replacement = dma_fence_get_stub();
265 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
266 replacement, DMA_RESV_USAGE_READ);
267 dma_fence_put(replacement);
271 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
273 struct amdgpu_bo *root = bo;
274 struct amdgpu_vm_bo_base *vm_bo;
275 struct amdgpu_vm *vm;
276 struct amdkfd_process_info *info;
277 struct amdgpu_amdkfd_fence *ef;
280 /* we can always get vm_bo from root PD bo.*/
292 info = vm->process_info;
293 if (!info || !info->eviction_fence)
296 ef = container_of(dma_fence_get(&info->eviction_fence->base),
297 struct amdgpu_amdkfd_fence, base);
299 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
300 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
301 dma_resv_unlock(bo->tbo.base.resv);
303 dma_fence_put(&ef->base);
307 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
310 struct ttm_operation_ctx ctx = { false, false };
313 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
314 "Called with userptr BO"))
317 amdgpu_bo_placement_from_domain(bo, domain);
319 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
323 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
329 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
331 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
334 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
336 * Page directories are not updated here because huge page handling
337 * during page table updates can invalidate page directory entries
338 * again. Page directories are only updated after updating page
341 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
343 struct amdgpu_bo *pd = vm->root.bo;
344 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
347 ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
349 pr_err("failed to validate PT BOs\n");
353 ret = amdgpu_amdkfd_validate_vm_bo(NULL, pd);
355 pr_err("failed to validate PD\n");
359 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
361 if (vm->use_cpu_for_update) {
362 ret = amdgpu_bo_kmap(pd, NULL);
364 pr_err("failed to kmap PD, ret=%d\n", ret);
372 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
374 struct amdgpu_bo *pd = vm->root.bo;
375 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
378 ret = amdgpu_vm_update_pdes(adev, vm, false);
382 return amdgpu_sync_fence(sync, vm->last_update);
385 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
387 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
388 bool coherent = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT;
389 bool uncached = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED;
390 uint32_t mapping_flags;
394 mapping_flags = AMDGPU_VM_PAGE_READABLE;
395 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
396 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
397 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
398 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
400 switch (adev->asic_type) {
402 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
404 mapping_flags |= coherent ?
405 AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
407 mapping_flags |= coherent ?
408 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
410 mapping_flags |= coherent ?
411 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
415 if (coherent && uncached) {
416 if (adev->gmc.xgmi.connected_to_cpu ||
417 !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM))
419 mapping_flags |= AMDGPU_VM_MTYPE_UC;
420 } else if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
421 if (bo_adev == adev) {
422 mapping_flags |= coherent ?
423 AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
424 if (adev->gmc.xgmi.connected_to_cpu)
427 mapping_flags |= coherent ?
428 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
429 if (amdgpu_xgmi_same_hive(adev, bo_adev))
434 mapping_flags |= coherent ?
435 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
439 mapping_flags |= coherent ?
440 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
443 pte_flags = amdgpu_gem_va_map_flags(adev, mapping_flags);
444 pte_flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
450 kfd_mem_dmamap_userptr(struct kgd_mem *mem,
451 struct kfd_mem_attachment *attachment)
453 enum dma_data_direction direction =
454 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
455 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
456 struct ttm_operation_ctx ctx = {.interruptible = true};
457 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
458 struct amdgpu_device *adev = attachment->adev;
459 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
460 struct ttm_tt *ttm = bo->tbo.ttm;
463 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
464 if (unlikely(!ttm->sg))
467 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
470 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
471 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
473 (u64)ttm->num_pages << PAGE_SHIFT,
478 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
482 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm->dma_address,
485 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
486 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
493 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
495 pr_err("DMA map userptr failed: %d\n", ret);
496 sg_free_table(ttm->sg);
504 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
506 struct ttm_operation_ctx ctx = {.interruptible = true};
507 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
509 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
510 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
514 kfd_mem_dmamap_attachment(struct kgd_mem *mem,
515 struct kfd_mem_attachment *attachment)
517 switch (attachment->type) {
518 case KFD_MEM_ATT_SHARED:
520 case KFD_MEM_ATT_USERPTR:
521 return kfd_mem_dmamap_userptr(mem, attachment);
522 case KFD_MEM_ATT_DMABUF:
523 return kfd_mem_dmamap_dmabuf(attachment);
531 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
532 struct kfd_mem_attachment *attachment)
534 enum dma_data_direction direction =
535 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
536 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
537 struct ttm_operation_ctx ctx = {.interruptible = false};
538 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
539 struct amdgpu_device *adev = attachment->adev;
540 struct ttm_tt *ttm = bo->tbo.ttm;
542 if (unlikely(!ttm->sg))
545 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
546 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
548 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
549 sg_free_table(ttm->sg);
555 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
557 struct ttm_operation_ctx ctx = {.interruptible = true};
558 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
560 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
561 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
565 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
566 struct kfd_mem_attachment *attachment)
568 switch (attachment->type) {
569 case KFD_MEM_ATT_SHARED:
571 case KFD_MEM_ATT_USERPTR:
572 kfd_mem_dmaunmap_userptr(mem, attachment);
574 case KFD_MEM_ATT_DMABUF:
575 kfd_mem_dmaunmap_dmabuf(attachment);
583 kfd_mem_attach_userptr(struct amdgpu_device *adev, struct kgd_mem *mem,
584 struct amdgpu_bo **bo)
586 unsigned long bo_size = mem->bo->tbo.base.size;
587 struct drm_gem_object *gobj;
590 ret = amdgpu_bo_reserve(mem->bo, false);
594 ret = amdgpu_gem_object_create(adev, bo_size, 1,
595 AMDGPU_GEM_DOMAIN_CPU,
596 AMDGPU_GEM_CREATE_PREEMPTIBLE,
597 ttm_bo_type_sg, mem->bo->tbo.base.resv,
599 amdgpu_bo_unreserve(mem->bo);
603 *bo = gem_to_amdgpu_bo(gobj);
604 (*bo)->parent = amdgpu_bo_ref(mem->bo);
610 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
611 struct amdgpu_bo **bo)
613 struct drm_gem_object *gobj;
617 mem->dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base,
618 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
620 if (IS_ERR(mem->dmabuf)) {
621 ret = PTR_ERR(mem->dmabuf);
627 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
629 return PTR_ERR(gobj);
631 *bo = gem_to_amdgpu_bo(gobj);
632 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
633 (*bo)->parent = amdgpu_bo_ref(mem->bo);
638 /* kfd_mem_attach - Add a BO to a VM
640 * Everything that needs to bo done only once when a BO is first added
641 * to a VM. It can later be mapped and unmapped many times without
642 * repeating these steps.
644 * 0. Create BO for DMA mapping, if needed
645 * 1. Allocate and initialize BO VA entry data structure
646 * 2. Add BO to the VM
647 * 3. Determine ASIC-specific PTE flags
648 * 4. Alloc page tables and directories if needed
649 * 4a. Validate new page tables and directories
651 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
652 struct amdgpu_vm *vm, bool is_aql)
654 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
655 unsigned long bo_size = mem->bo->tbo.base.size;
656 uint64_t va = mem->va;
657 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
658 struct amdgpu_bo *bo[2] = {NULL, NULL};
662 pr_err("Invalid VA when adding BO to VM\n");
666 for (i = 0; i <= is_aql; i++) {
667 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
668 if (unlikely(!attachment[i])) {
673 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
676 if (adev == bo_adev ||
677 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && adev->ram_is_direct_mapped) ||
678 (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && amdgpu_xgmi_same_hive(adev, bo_adev))) {
679 /* Mappings on the local GPU, or VRAM mappings in the
680 * local hive, or userptr mapping IOMMU direct map mode
681 * share the original BO
683 attachment[i]->type = KFD_MEM_ATT_SHARED;
685 drm_gem_object_get(&bo[i]->tbo.base);
687 /* Multiple mappings on the same GPU share the BO */
688 attachment[i]->type = KFD_MEM_ATT_SHARED;
690 drm_gem_object_get(&bo[i]->tbo.base);
691 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
692 /* Create an SG BO to DMA-map userptrs on other GPUs */
693 attachment[i]->type = KFD_MEM_ATT_USERPTR;
694 ret = kfd_mem_attach_userptr(adev, mem, &bo[i]);
697 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT &&
698 mem->bo->tbo.type != ttm_bo_type_sg) {
699 /* GTT BOs use DMA-mapping ability of dynamic-attach
700 * DMA bufs. TODO: The same should work for VRAM on
703 attachment[i]->type = KFD_MEM_ATT_DMABUF;
704 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
708 /* FIXME: Need to DMA-map other BO types:
709 * large-BAR VRAM, doorbells, MMIO remap
711 attachment[i]->type = KFD_MEM_ATT_SHARED;
713 drm_gem_object_get(&bo[i]->tbo.base);
716 /* Add BO to VM internal data structures */
717 ret = amdgpu_bo_reserve(bo[i], false);
719 pr_debug("Unable to reserve BO during memory attach");
722 attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
723 amdgpu_bo_unreserve(bo[i]);
724 if (unlikely(!attachment[i]->bo_va)) {
726 pr_err("Failed to add BO object to VM. ret == %d\n",
730 attachment[i]->va = va;
731 attachment[i]->pte_flags = get_pte_flags(adev, mem);
732 attachment[i]->adev = adev;
733 list_add(&attachment[i]->list, &mem->attachments);
741 for (; i >= 0; i--) {
744 if (attachment[i]->bo_va) {
745 amdgpu_bo_reserve(bo[i], true);
746 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
747 amdgpu_bo_unreserve(bo[i]);
748 list_del(&attachment[i]->list);
751 drm_gem_object_put(&bo[i]->tbo.base);
752 kfree(attachment[i]);
757 static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
759 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
761 pr_debug("\t remove VA 0x%llx in entry %p\n",
762 attachment->va, attachment);
763 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
764 drm_gem_object_put(&bo->tbo.base);
765 list_del(&attachment->list);
769 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
770 struct amdkfd_process_info *process_info,
773 struct ttm_validate_buffer *entry = &mem->validate_list;
774 struct amdgpu_bo *bo = mem->bo;
776 INIT_LIST_HEAD(&entry->head);
777 entry->num_shared = 1;
778 entry->bo = &bo->tbo;
779 mutex_lock(&process_info->lock);
781 list_add_tail(&entry->head, &process_info->userptr_valid_list);
783 list_add_tail(&entry->head, &process_info->kfd_bo_list);
784 mutex_unlock(&process_info->lock);
787 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
788 struct amdkfd_process_info *process_info)
790 struct ttm_validate_buffer *bo_list_entry;
792 bo_list_entry = &mem->validate_list;
793 mutex_lock(&process_info->lock);
794 list_del(&bo_list_entry->head);
795 mutex_unlock(&process_info->lock);
798 /* Initializes user pages. It registers the MMU notifier and validates
799 * the userptr BO in the GTT domain.
801 * The BO must already be on the userptr_valid_list. Otherwise an
802 * eviction and restore may happen that leaves the new BO unmapped
803 * with the user mode queues running.
805 * Takes the process_info->lock to protect against concurrent restore
808 * Returns 0 for success, negative errno for errors.
810 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
813 struct amdkfd_process_info *process_info = mem->process_info;
814 struct amdgpu_bo *bo = mem->bo;
815 struct ttm_operation_ctx ctx = { true, false };
818 mutex_lock(&process_info->lock);
820 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
822 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
826 ret = amdgpu_mn_register(bo, user_addr);
828 pr_err("%s: Failed to register MMU notifier: %d\n",
835 * During a CRIU restore operation, the userptr buffer objects
836 * will be validated in the restore_userptr_work worker at a
837 * later stage when it is scheduled by another ioctl called by
838 * CRIU master process for the target pid for restore.
840 atomic_inc(&mem->invalid);
841 mutex_unlock(&process_info->lock);
845 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
847 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
851 ret = amdgpu_bo_reserve(bo, true);
853 pr_err("%s: Failed to reserve BO\n", __func__);
856 amdgpu_bo_placement_from_domain(bo, mem->domain);
857 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
859 pr_err("%s: failed to validate BO\n", __func__);
860 amdgpu_bo_unreserve(bo);
863 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
866 amdgpu_mn_unregister(bo);
868 mutex_unlock(&process_info->lock);
872 /* Reserving a BO and its page table BOs must happen atomically to
873 * avoid deadlocks. Some operations update multiple VMs at once. Track
874 * all the reservation info in a context structure. Optionally a sync
875 * object can track VM updates.
877 struct bo_vm_reservation_context {
878 struct amdgpu_bo_list_entry kfd_bo; /* BO list entry for the KFD BO */
879 unsigned int n_vms; /* Number of VMs reserved */
880 struct amdgpu_bo_list_entry *vm_pd; /* Array of VM BO list entries */
881 struct ww_acquire_ctx ticket; /* Reservation ticket */
882 struct list_head list, duplicates; /* BO lists */
883 struct amdgpu_sync *sync; /* Pointer to sync object */
884 bool reserved; /* Whether BOs are reserved */
888 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
889 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
890 BO_VM_ALL, /* Match all VMs a BO was added to */
894 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
895 * @mem: KFD BO structure.
896 * @vm: the VM to reserve.
897 * @ctx: the struct that will be used in unreserve_bo_and_vms().
899 static int reserve_bo_and_vm(struct kgd_mem *mem,
900 struct amdgpu_vm *vm,
901 struct bo_vm_reservation_context *ctx)
903 struct amdgpu_bo *bo = mem->bo;
908 ctx->reserved = false;
910 ctx->sync = &mem->sync;
912 INIT_LIST_HEAD(&ctx->list);
913 INIT_LIST_HEAD(&ctx->duplicates);
915 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd), GFP_KERNEL);
919 ctx->kfd_bo.priority = 0;
920 ctx->kfd_bo.tv.bo = &bo->tbo;
921 ctx->kfd_bo.tv.num_shared = 1;
922 list_add(&ctx->kfd_bo.tv.head, &ctx->list);
924 amdgpu_vm_get_pd_bo(vm, &ctx->list, &ctx->vm_pd[0]);
926 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
927 false, &ctx->duplicates);
929 pr_err("Failed to reserve buffers in ttm.\n");
935 ctx->reserved = true;
940 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
941 * @mem: KFD BO structure.
942 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
943 * is used. Otherwise, a single VM associated with the BO.
944 * @map_type: the mapping status that will be used to filter the VMs.
945 * @ctx: the struct that will be used in unreserve_bo_and_vms().
947 * Returns 0 for success, negative for failure.
949 static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
950 struct amdgpu_vm *vm, enum bo_vm_match map_type,
951 struct bo_vm_reservation_context *ctx)
953 struct amdgpu_bo *bo = mem->bo;
954 struct kfd_mem_attachment *entry;
958 ctx->reserved = false;
961 ctx->sync = &mem->sync;
963 INIT_LIST_HEAD(&ctx->list);
964 INIT_LIST_HEAD(&ctx->duplicates);
966 list_for_each_entry(entry, &mem->attachments, list) {
967 if ((vm && vm != entry->bo_va->base.vm) ||
968 (entry->is_mapped != map_type
969 && map_type != BO_VM_ALL))
975 if (ctx->n_vms != 0) {
976 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd),
982 ctx->kfd_bo.priority = 0;
983 ctx->kfd_bo.tv.bo = &bo->tbo;
984 ctx->kfd_bo.tv.num_shared = 1;
985 list_add(&ctx->kfd_bo.tv.head, &ctx->list);
988 list_for_each_entry(entry, &mem->attachments, list) {
989 if ((vm && vm != entry->bo_va->base.vm) ||
990 (entry->is_mapped != map_type
991 && map_type != BO_VM_ALL))
994 amdgpu_vm_get_pd_bo(entry->bo_va->base.vm, &ctx->list,
999 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
1000 false, &ctx->duplicates);
1002 pr_err("Failed to reserve buffers in ttm.\n");
1008 ctx->reserved = true;
1013 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1014 * @ctx: Reservation context to unreserve
1015 * @wait: Optionally wait for a sync object representing pending VM updates
1016 * @intr: Whether the wait is interruptible
1018 * Also frees any resources allocated in
1019 * reserve_bo_and_(cond_)vm(s). Returns the status from
1022 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1023 bool wait, bool intr)
1028 ret = amdgpu_sync_wait(ctx->sync, intr);
1031 ttm_eu_backoff_reservation(&ctx->ticket, &ctx->list);
1036 ctx->reserved = false;
1042 static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1043 struct kfd_mem_attachment *entry,
1044 struct amdgpu_sync *sync)
1046 struct amdgpu_bo_va *bo_va = entry->bo_va;
1047 struct amdgpu_device *adev = entry->adev;
1048 struct amdgpu_vm *vm = bo_va->base.vm;
1050 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1052 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1054 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1056 kfd_mem_dmaunmap_attachment(mem, entry);
1059 static int update_gpuvm_pte(struct kgd_mem *mem,
1060 struct kfd_mem_attachment *entry,
1061 struct amdgpu_sync *sync)
1063 struct amdgpu_bo_va *bo_va = entry->bo_va;
1064 struct amdgpu_device *adev = entry->adev;
1067 ret = kfd_mem_dmamap_attachment(mem, entry);
1071 /* Update the page tables */
1072 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1074 pr_err("amdgpu_vm_bo_update failed\n");
1078 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1081 static int map_bo_to_gpuvm(struct kgd_mem *mem,
1082 struct kfd_mem_attachment *entry,
1083 struct amdgpu_sync *sync,
1088 /* Set virtual address for the allocation */
1089 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1090 amdgpu_bo_size(entry->bo_va->base.bo),
1093 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1101 ret = update_gpuvm_pte(mem, entry, sync);
1103 pr_err("update_gpuvm_pte() failed\n");
1104 goto update_gpuvm_pte_failed;
1109 update_gpuvm_pte_failed:
1110 unmap_bo_from_gpuvm(mem, entry, sync);
1114 static struct sg_table *create_doorbell_sg(uint64_t addr, uint32_t size)
1116 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
1120 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
1124 sg->sgl->dma_address = addr;
1125 sg->sgl->length = size;
1126 #ifdef CONFIG_NEED_SG_DMA_LENGTH
1127 sg->sgl->dma_length = size;
1132 static int process_validate_vms(struct amdkfd_process_info *process_info)
1134 struct amdgpu_vm *peer_vm;
1137 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1139 ret = vm_validate_pt_pd_bos(peer_vm);
1147 static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1148 struct amdgpu_sync *sync)
1150 struct amdgpu_vm *peer_vm;
1153 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1155 struct amdgpu_bo *pd = peer_vm->root.bo;
1157 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1158 AMDGPU_SYNC_NE_OWNER,
1159 AMDGPU_FENCE_OWNER_KFD);
1167 static int process_update_pds(struct amdkfd_process_info *process_info,
1168 struct amdgpu_sync *sync)
1170 struct amdgpu_vm *peer_vm;
1173 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1175 ret = vm_update_pds(peer_vm, sync);
1183 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1184 struct dma_fence **ef)
1186 struct amdkfd_process_info *info = NULL;
1189 if (!*process_info) {
1190 info = kzalloc(sizeof(*info), GFP_KERNEL);
1194 mutex_init(&info->lock);
1195 INIT_LIST_HEAD(&info->vm_list_head);
1196 INIT_LIST_HEAD(&info->kfd_bo_list);
1197 INIT_LIST_HEAD(&info->userptr_valid_list);
1198 INIT_LIST_HEAD(&info->userptr_inval_list);
1200 info->eviction_fence =
1201 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1204 if (!info->eviction_fence) {
1205 pr_err("Failed to create eviction fence\n");
1207 goto create_evict_fence_fail;
1210 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1211 atomic_set(&info->evicted_bos, 0);
1212 INIT_DELAYED_WORK(&info->restore_userptr_work,
1213 amdgpu_amdkfd_restore_userptr_worker);
1215 *process_info = info;
1216 *ef = dma_fence_get(&info->eviction_fence->base);
1219 vm->process_info = *process_info;
1221 /* Validate page directory and attach eviction fence */
1222 ret = amdgpu_bo_reserve(vm->root.bo, true);
1224 goto reserve_pd_fail;
1225 ret = vm_validate_pt_pd_bos(vm);
1227 pr_err("validate_pt_pd_bos() failed\n");
1228 goto validate_pd_fail;
1230 ret = amdgpu_bo_sync_wait(vm->root.bo,
1231 AMDGPU_FENCE_OWNER_KFD, false);
1234 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1236 goto reserve_shared_fail;
1237 amdgpu_bo_fence(vm->root.bo,
1238 &vm->process_info->eviction_fence->base, true);
1239 amdgpu_bo_unreserve(vm->root.bo);
1241 /* Update process info */
1242 mutex_lock(&vm->process_info->lock);
1243 list_add_tail(&vm->vm_list_node,
1244 &(vm->process_info->vm_list_head));
1245 vm->process_info->n_vms++;
1246 mutex_unlock(&vm->process_info->lock);
1250 reserve_shared_fail:
1253 amdgpu_bo_unreserve(vm->root.bo);
1255 vm->process_info = NULL;
1257 /* Two fence references: one in info and one in *ef */
1258 dma_fence_put(&info->eviction_fence->base);
1261 *process_info = NULL;
1263 create_evict_fence_fail:
1264 mutex_destroy(&info->lock);
1271 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1272 * @bo: Handle of buffer object being pinned
1273 * @domain: Domain into which BO should be pinned
1275 * - USERPTR BOs are UNPINNABLE and will return error
1276 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1277 * PIN count incremented. It is valid to PIN a BO multiple times
1279 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1281 static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1285 ret = amdgpu_bo_reserve(bo, false);
1289 ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1291 pr_err("Error in Pinning BO to domain: %d\n", domain);
1293 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1294 amdgpu_bo_unreserve(bo);
1300 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1301 * @bo: Handle of buffer object being unpinned
1303 * - Is a illegal request for USERPTR BOs and is ignored
1304 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1305 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1307 static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1311 ret = amdgpu_bo_reserve(bo, false);
1315 amdgpu_bo_unpin(bo);
1316 amdgpu_bo_unreserve(bo);
1319 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1320 struct file *filp, u32 pasid,
1321 void **process_info,
1322 struct dma_fence **ef)
1324 struct amdgpu_fpriv *drv_priv;
1325 struct amdgpu_vm *avm;
1328 ret = amdgpu_file_to_fpriv(filp, &drv_priv);
1331 avm = &drv_priv->vm;
1333 /* Already a compute VM? */
1334 if (avm->process_info)
1337 /* Free the original amdgpu allocated pasid,
1338 * will be replaced with kfd allocated pasid.
1341 amdgpu_pasid_free(avm->pasid);
1342 amdgpu_vm_set_pasid(adev, avm, 0);
1345 /* Convert VM into a compute VM */
1346 ret = amdgpu_vm_make_compute(adev, avm);
1350 ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1353 /* Initialize KFD part of the VM and process info */
1354 ret = init_kfd_vm(avm, process_info, ef);
1358 amdgpu_vm_set_task_info(avm);
1363 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1364 struct amdgpu_vm *vm)
1366 struct amdkfd_process_info *process_info = vm->process_info;
1367 struct amdgpu_bo *pd = vm->root.bo;
1372 /* Release eviction fence from PD */
1373 amdgpu_bo_reserve(pd, false);
1374 amdgpu_bo_fence(pd, NULL, false);
1375 amdgpu_bo_unreserve(pd);
1377 /* Update process info */
1378 mutex_lock(&process_info->lock);
1379 process_info->n_vms--;
1380 list_del(&vm->vm_list_node);
1381 mutex_unlock(&process_info->lock);
1383 vm->process_info = NULL;
1385 /* Release per-process resources when last compute VM is destroyed */
1386 if (!process_info->n_vms) {
1387 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1388 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1389 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1391 dma_fence_put(&process_info->eviction_fence->base);
1392 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1393 put_pid(process_info->pid);
1394 mutex_destroy(&process_info->lock);
1395 kfree(process_info);
1399 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1402 struct amdgpu_vm *avm;
1404 if (WARN_ON(!adev || !drm_priv))
1407 avm = drm_priv_to_vm(drm_priv);
1409 pr_debug("Releasing process vm %p\n", avm);
1411 /* The original pasid of amdgpu vm has already been
1412 * released during making a amdgpu vm to a compute vm
1413 * The current pasid is managed by kfd and will be
1414 * released on kfd process destroy. Set amdgpu pasid
1415 * to 0 to avoid duplicate release.
1417 amdgpu_vm_release_compute(adev, avm);
1420 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1422 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1423 struct amdgpu_bo *pd = avm->root.bo;
1424 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1426 if (adev->asic_type < CHIP_VEGA10)
1427 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1428 return avm->pd_phys_addr;
1431 void amdgpu_amdkfd_block_mmu_notifications(void *p)
1433 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1435 mutex_lock(&pinfo->lock);
1436 WRITE_ONCE(pinfo->block_mmu_notifications, true);
1437 mutex_unlock(&pinfo->lock);
1440 int amdgpu_amdkfd_criu_resume(void *p)
1443 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1445 mutex_lock(&pinfo->lock);
1446 pr_debug("scheduling work\n");
1447 atomic_inc(&pinfo->evicted_bos);
1448 if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1452 WRITE_ONCE(pinfo->block_mmu_notifications, false);
1453 schedule_delayed_work(&pinfo->restore_userptr_work, 0);
1456 mutex_unlock(&pinfo->lock);
1460 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1461 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1462 void *drm_priv, struct kgd_mem **mem,
1463 uint64_t *offset, uint32_t flags, bool criu_resume)
1465 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1466 enum ttm_bo_type bo_type = ttm_bo_type_device;
1467 struct sg_table *sg = NULL;
1468 uint64_t user_addr = 0;
1469 struct amdgpu_bo *bo;
1470 struct drm_gem_object *gobj = NULL;
1471 u32 domain, alloc_domain;
1476 * Check on which domain to allocate BO
1478 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1479 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1480 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1481 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1482 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1483 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1484 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1487 domain = AMDGPU_GEM_DOMAIN_GTT;
1488 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1489 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1491 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1492 if (!offset || !*offset)
1494 user_addr = untagged_addr(*offset);
1495 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1496 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1497 bo_type = ttm_bo_type_sg;
1498 if (size > UINT_MAX)
1500 sg = create_doorbell_sg(*offset, size);
1508 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1513 INIT_LIST_HEAD(&(*mem)->attachments);
1514 mutex_init(&(*mem)->lock);
1515 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1517 /* Workaround for AQL queue wraparound bug. Map the same
1518 * memory twice. That means we only actually allocate half
1521 if ((*mem)->aql_queue)
1524 (*mem)->alloc_flags = flags;
1526 amdgpu_sync_create(&(*mem)->sync);
1528 ret = amdgpu_amdkfd_reserve_mem_limit(adev, size, flags);
1530 pr_debug("Insufficient memory\n");
1531 goto err_reserve_limit;
1534 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
1535 va, size, domain_string(alloc_domain));
1537 ret = amdgpu_gem_object_create(adev, size, 1, alloc_domain, alloc_flags,
1538 bo_type, NULL, &gobj);
1540 pr_debug("Failed to create BO on domain %s. ret %d\n",
1541 domain_string(alloc_domain), ret);
1544 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1546 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1547 goto err_node_allow;
1549 bo = gem_to_amdgpu_bo(gobj);
1550 if (bo_type == ttm_bo_type_sg) {
1552 bo->tbo.ttm->sg = sg;
1557 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1560 (*mem)->domain = domain;
1561 (*mem)->mapped_to_gpu_memory = 0;
1562 (*mem)->process_info = avm->process_info;
1563 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1566 pr_debug("creating userptr BO for user_addr = %llu\n", user_addr);
1567 ret = init_user_pages(*mem, user_addr, criu_resume);
1569 goto allocate_init_user_pages_failed;
1570 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1571 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1572 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1574 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1577 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1578 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1582 *offset = amdgpu_bo_mmap_offset(bo);
1586 allocate_init_user_pages_failed:
1588 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1589 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1591 /* Don't unreserve system mem limit twice */
1592 goto err_reserve_limit;
1594 unreserve_mem_limit(adev, size, flags);
1596 mutex_destroy(&(*mem)->lock);
1598 drm_gem_object_put(gobj);
1609 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1610 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1613 struct amdkfd_process_info *process_info = mem->process_info;
1614 unsigned long bo_size = mem->bo->tbo.base.size;
1615 struct kfd_mem_attachment *entry, *tmp;
1616 struct bo_vm_reservation_context ctx;
1617 struct ttm_validate_buffer *bo_list_entry;
1618 unsigned int mapped_to_gpu_memory;
1620 bool is_imported = false;
1622 mutex_lock(&mem->lock);
1624 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1625 if (mem->alloc_flags &
1626 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1627 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1628 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1631 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1632 is_imported = mem->is_imported;
1633 mutex_unlock(&mem->lock);
1634 /* lock is not needed after this, since mem is unused and will
1638 if (mapped_to_gpu_memory > 0) {
1639 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1644 /* Make sure restore workers don't access the BO any more */
1645 bo_list_entry = &mem->validate_list;
1646 mutex_lock(&process_info->lock);
1647 list_del(&bo_list_entry->head);
1648 mutex_unlock(&process_info->lock);
1650 /* No more MMU notifiers */
1651 amdgpu_mn_unregister(mem->bo);
1653 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1657 /* The eviction fence should be removed by the last unmap.
1658 * TODO: Log an error condition if the bo still has the eviction fence
1661 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1662 process_info->eviction_fence);
1663 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1664 mem->va + bo_size * (1 + mem->aql_queue));
1666 /* Remove from VM internal data structures */
1667 list_for_each_entry_safe(entry, tmp, &mem->attachments, list)
1668 kfd_mem_detach(entry);
1670 ret = unreserve_bo_and_vms(&ctx, false, false);
1672 /* Free the sync object */
1673 amdgpu_sync_free(&mem->sync);
1675 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1676 * remap BO. We need to free it.
1678 if (mem->bo->tbo.sg) {
1679 sg_free_table(mem->bo->tbo.sg);
1680 kfree(mem->bo->tbo.sg);
1683 /* Update the size of the BO being freed if it was allocated from
1684 * VRAM and is not imported.
1687 if ((mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) &&
1695 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1697 dma_buf_put(mem->dmabuf);
1698 mutex_destroy(&mem->lock);
1700 /* If this releases the last reference, it will end up calling
1701 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1702 * this needs to be the last call here.
1704 drm_gem_object_put(&mem->bo->tbo.base);
1709 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1710 struct amdgpu_device *adev, struct kgd_mem *mem,
1713 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1715 struct amdgpu_bo *bo;
1717 struct kfd_mem_attachment *entry;
1718 struct bo_vm_reservation_context ctx;
1719 unsigned long bo_size;
1720 bool is_invalid_userptr = false;
1724 pr_err("Invalid BO when mapping memory to GPU\n");
1728 /* Make sure restore is not running concurrently. Since we
1729 * don't map invalid userptr BOs, we rely on the next restore
1730 * worker to do the mapping
1732 mutex_lock(&mem->process_info->lock);
1734 /* Lock mmap-sem. If we find an invalid userptr BO, we can be
1735 * sure that the MMU notifier is no longer running
1736 * concurrently and the queues are actually stopped
1738 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1739 mmap_write_lock(current->mm);
1740 is_invalid_userptr = atomic_read(&mem->invalid);
1741 mmap_write_unlock(current->mm);
1744 mutex_lock(&mem->lock);
1746 domain = mem->domain;
1747 bo_size = bo->tbo.base.size;
1749 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
1751 mem->va + bo_size * (1 + mem->aql_queue),
1752 avm, domain_string(domain));
1754 if (!kfd_mem_is_attached(avm, mem)) {
1755 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
1760 ret = reserve_bo_and_vm(mem, avm, &ctx);
1764 /* Userptr can be marked as "not invalid", but not actually be
1765 * validated yet (still in the system domain). In that case
1766 * the queues are still stopped and we can leave mapping for
1767 * the next restore worker
1769 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
1770 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
1771 is_invalid_userptr = true;
1773 ret = vm_validate_pt_pd_bos(avm);
1777 if (mem->mapped_to_gpu_memory == 0 &&
1778 !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1779 /* Validate BO only once. The eviction fence gets added to BO
1780 * the first time it is mapped. Validate will wait for all
1781 * background evictions to complete.
1783 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
1785 pr_debug("Validate failed\n");
1790 list_for_each_entry(entry, &mem->attachments, list) {
1791 if (entry->bo_va->base.vm != avm || entry->is_mapped)
1794 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
1795 entry->va, entry->va + bo_size, entry);
1797 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
1798 is_invalid_userptr);
1800 pr_err("Failed to map bo to gpuvm\n");
1804 ret = vm_update_pds(avm, ctx.sync);
1806 pr_err("Failed to update page directories\n");
1810 entry->is_mapped = true;
1811 mem->mapped_to_gpu_memory++;
1812 pr_debug("\t INC mapping count %d\n",
1813 mem->mapped_to_gpu_memory);
1816 if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
1818 &avm->process_info->eviction_fence->base,
1820 ret = unreserve_bo_and_vms(&ctx, false, false);
1825 unreserve_bo_and_vms(&ctx, false, false);
1827 mutex_unlock(&mem->process_info->lock);
1828 mutex_unlock(&mem->lock);
1832 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1833 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
1835 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1836 struct amdkfd_process_info *process_info = avm->process_info;
1837 unsigned long bo_size = mem->bo->tbo.base.size;
1838 struct kfd_mem_attachment *entry;
1839 struct bo_vm_reservation_context ctx;
1842 mutex_lock(&mem->lock);
1844 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
1847 /* If no VMs were reserved, it means the BO wasn't actually mapped */
1848 if (ctx.n_vms == 0) {
1853 ret = vm_validate_pt_pd_bos(avm);
1857 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
1859 mem->va + bo_size * (1 + mem->aql_queue),
1862 list_for_each_entry(entry, &mem->attachments, list) {
1863 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
1866 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
1867 entry->va, entry->va + bo_size, entry);
1869 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
1870 entry->is_mapped = false;
1872 mem->mapped_to_gpu_memory--;
1873 pr_debug("\t DEC mapping count %d\n",
1874 mem->mapped_to_gpu_memory);
1877 /* If BO is unmapped from all VMs, unfence it. It can be evicted if
1880 if (mem->mapped_to_gpu_memory == 0 &&
1881 !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
1882 !mem->bo->tbo.pin_count)
1883 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1884 process_info->eviction_fence);
1887 unreserve_bo_and_vms(&ctx, false, false);
1889 mutex_unlock(&mem->lock);
1893 int amdgpu_amdkfd_gpuvm_sync_memory(
1894 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
1896 struct amdgpu_sync sync;
1899 amdgpu_sync_create(&sync);
1901 mutex_lock(&mem->lock);
1902 amdgpu_sync_clone(&mem->sync, &sync);
1903 mutex_unlock(&mem->lock);
1905 ret = amdgpu_sync_wait(&sync, intr);
1906 amdgpu_sync_free(&sync);
1910 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct amdgpu_device *adev,
1911 struct kgd_mem *mem, void **kptr, uint64_t *size)
1914 struct amdgpu_bo *bo = mem->bo;
1916 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1917 pr_err("userptr can't be mapped to kernel\n");
1921 mutex_lock(&mem->process_info->lock);
1923 ret = amdgpu_bo_reserve(bo, true);
1925 pr_err("Failed to reserve bo. ret %d\n", ret);
1926 goto bo_reserve_failed;
1929 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
1931 pr_err("Failed to pin bo. ret %d\n", ret);
1935 ret = amdgpu_bo_kmap(bo, kptr);
1937 pr_err("Failed to map bo to kernel. ret %d\n", ret);
1941 amdgpu_amdkfd_remove_eviction_fence(
1942 bo, mem->process_info->eviction_fence);
1945 *size = amdgpu_bo_size(bo);
1947 amdgpu_bo_unreserve(bo);
1949 mutex_unlock(&mem->process_info->lock);
1953 amdgpu_bo_unpin(bo);
1955 amdgpu_bo_unreserve(bo);
1957 mutex_unlock(&mem->process_info->lock);
1962 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct amdgpu_device *adev,
1963 struct kgd_mem *mem)
1965 struct amdgpu_bo *bo = mem->bo;
1967 amdgpu_bo_reserve(bo, true);
1968 amdgpu_bo_kunmap(bo);
1969 amdgpu_bo_unpin(bo);
1970 amdgpu_bo_unreserve(bo);
1973 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
1974 struct kfd_vm_fault_info *mem)
1976 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
1977 *mem = *adev->gmc.vm_fault_info;
1979 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1984 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
1985 struct dma_buf *dma_buf,
1986 uint64_t va, void *drm_priv,
1987 struct kgd_mem **mem, uint64_t *size,
1988 uint64_t *mmap_offset)
1990 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1991 struct drm_gem_object *obj;
1992 struct amdgpu_bo *bo;
1995 if (dma_buf->ops != &amdgpu_dmabuf_ops)
1996 /* Can't handle non-graphics buffers */
1999 obj = dma_buf->priv;
2000 if (drm_to_adev(obj->dev) != adev)
2001 /* Can't handle buffers from other devices */
2004 bo = gem_to_amdgpu_bo(obj);
2005 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2006 AMDGPU_GEM_DOMAIN_GTT)))
2007 /* Only VRAM and GTT BOs are supported */
2010 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2014 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2021 *size = amdgpu_bo_size(bo);
2024 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2026 INIT_LIST_HEAD(&(*mem)->attachments);
2027 mutex_init(&(*mem)->lock);
2029 (*mem)->alloc_flags =
2030 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2031 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2032 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2033 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2035 drm_gem_object_get(&bo->tbo.base);
2038 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2039 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2040 (*mem)->mapped_to_gpu_memory = 0;
2041 (*mem)->process_info = avm->process_info;
2042 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2043 amdgpu_sync_create(&(*mem)->sync);
2044 (*mem)->is_imported = true;
2049 /* Evict a userptr BO by stopping the queues if necessary
2051 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2052 * cannot do any memory allocations, and cannot take any locks that
2053 * are held elsewhere while allocating memory. Therefore this is as
2054 * simple as possible, using atomic counters.
2056 * It doesn't do anything to the BO itself. The real work happens in
2057 * restore, where we get updated page addresses. This function only
2058 * ensures that GPU access to the BO is stopped.
2060 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
2061 struct mm_struct *mm)
2063 struct amdkfd_process_info *process_info = mem->process_info;
2067 /* Do not process MMU notifications until stage-4 IOCTL is received */
2068 if (READ_ONCE(process_info->block_mmu_notifications))
2071 atomic_inc(&mem->invalid);
2072 evicted_bos = atomic_inc_return(&process_info->evicted_bos);
2073 if (evicted_bos == 1) {
2074 /* First eviction, stop the queues */
2075 r = kgd2kfd_quiesce_mm(mm);
2077 pr_err("Failed to quiesce KFD\n");
2078 schedule_delayed_work(&process_info->restore_userptr_work,
2079 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2085 /* Update invalid userptr BOs
2087 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2088 * userptr_inval_list and updates user pages for all BOs that have
2089 * been invalidated since their last update.
2091 static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2092 struct mm_struct *mm)
2094 struct kgd_mem *mem, *tmp_mem;
2095 struct amdgpu_bo *bo;
2096 struct ttm_operation_ctx ctx = { false, false };
2099 /* Move all invalidated BOs to the userptr_inval_list and
2100 * release their user pages by migration to the CPU domain
2102 list_for_each_entry_safe(mem, tmp_mem,
2103 &process_info->userptr_valid_list,
2104 validate_list.head) {
2105 if (!atomic_read(&mem->invalid))
2106 continue; /* BO is still valid */
2110 if (amdgpu_bo_reserve(bo, true))
2112 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2113 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2114 amdgpu_bo_unreserve(bo);
2116 pr_err("%s: Failed to invalidate userptr BO\n",
2121 list_move_tail(&mem->validate_list.head,
2122 &process_info->userptr_inval_list);
2125 if (list_empty(&process_info->userptr_inval_list))
2126 return 0; /* All evicted userptr BOs were freed */
2128 /* Go through userptr_inval_list and update any invalid user_pages */
2129 list_for_each_entry(mem, &process_info->userptr_inval_list,
2130 validate_list.head) {
2131 invalid = atomic_read(&mem->invalid);
2133 /* BO hasn't been invalidated since the last
2134 * revalidation attempt. Keep its BO list.
2140 /* Get updated user pages */
2141 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
2143 pr_debug("Failed %d to get user pages\n", ret);
2145 /* Return -EFAULT bad address error as success. It will
2146 * fail later with a VM fault if the GPU tries to access
2147 * it. Better than hanging indefinitely with stalled
2150 * Return other error -EBUSY or -ENOMEM to retry restore
2157 * FIXME: Cannot ignore the return code, must hold
2160 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
2163 /* Mark the BO as valid unless it was invalidated
2164 * again concurrently.
2166 if (atomic_cmpxchg(&mem->invalid, invalid, 0) != invalid)
2173 /* Validate invalid userptr BOs
2175 * Validates BOs on the userptr_inval_list, and moves them back to the
2176 * userptr_valid_list. Also updates GPUVM page tables with new page
2177 * addresses and waits for the page table updates to complete.
2179 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2181 struct amdgpu_bo_list_entry *pd_bo_list_entries;
2182 struct list_head resv_list, duplicates;
2183 struct ww_acquire_ctx ticket;
2184 struct amdgpu_sync sync;
2186 struct amdgpu_vm *peer_vm;
2187 struct kgd_mem *mem, *tmp_mem;
2188 struct amdgpu_bo *bo;
2189 struct ttm_operation_ctx ctx = { false, false };
2192 pd_bo_list_entries = kcalloc(process_info->n_vms,
2193 sizeof(struct amdgpu_bo_list_entry),
2195 if (!pd_bo_list_entries) {
2196 pr_err("%s: Failed to allocate PD BO list entries\n", __func__);
2201 INIT_LIST_HEAD(&resv_list);
2202 INIT_LIST_HEAD(&duplicates);
2204 /* Get all the page directory BOs that need to be reserved */
2206 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2208 amdgpu_vm_get_pd_bo(peer_vm, &resv_list,
2209 &pd_bo_list_entries[i++]);
2210 /* Add the userptr_inval_list entries to resv_list */
2211 list_for_each_entry(mem, &process_info->userptr_inval_list,
2212 validate_list.head) {
2213 list_add_tail(&mem->resv_list.head, &resv_list);
2214 mem->resv_list.bo = mem->validate_list.bo;
2215 mem->resv_list.num_shared = mem->validate_list.num_shared;
2218 /* Reserve all BOs and page tables for validation */
2219 ret = ttm_eu_reserve_buffers(&ticket, &resv_list, false, &duplicates);
2220 WARN(!list_empty(&duplicates), "Duplicates should be empty");
2224 amdgpu_sync_create(&sync);
2226 ret = process_validate_vms(process_info);
2230 /* Validate BOs and update GPUVM page tables */
2231 list_for_each_entry_safe(mem, tmp_mem,
2232 &process_info->userptr_inval_list,
2233 validate_list.head) {
2234 struct kfd_mem_attachment *attachment;
2238 /* Validate the BO if we got user pages */
2239 if (bo->tbo.ttm->pages[0]) {
2240 amdgpu_bo_placement_from_domain(bo, mem->domain);
2241 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2243 pr_err("%s: failed to validate BO\n", __func__);
2248 list_move_tail(&mem->validate_list.head,
2249 &process_info->userptr_valid_list);
2251 /* Update mapping. If the BO was not validated
2252 * (because we couldn't get user pages), this will
2253 * clear the page table entries, which will result in
2254 * VM faults if the GPU tries to access the invalid
2257 list_for_each_entry(attachment, &mem->attachments, list) {
2258 if (!attachment->is_mapped)
2261 kfd_mem_dmaunmap_attachment(mem, attachment);
2262 ret = update_gpuvm_pte(mem, attachment, &sync);
2264 pr_err("%s: update PTE failed\n", __func__);
2265 /* make sure this gets validated again */
2266 atomic_inc(&mem->invalid);
2272 /* Update page directories */
2273 ret = process_update_pds(process_info, &sync);
2276 ttm_eu_backoff_reservation(&ticket, &resv_list);
2277 amdgpu_sync_wait(&sync, false);
2278 amdgpu_sync_free(&sync);
2280 kfree(pd_bo_list_entries);
2286 /* Worker callback to restore evicted userptr BOs
2288 * Tries to update and validate all userptr BOs. If successful and no
2289 * concurrent evictions happened, the queues are restarted. Otherwise,
2290 * reschedule for another attempt later.
2292 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2294 struct delayed_work *dwork = to_delayed_work(work);
2295 struct amdkfd_process_info *process_info =
2296 container_of(dwork, struct amdkfd_process_info,
2297 restore_userptr_work);
2298 struct task_struct *usertask;
2299 struct mm_struct *mm;
2302 evicted_bos = atomic_read(&process_info->evicted_bos);
2306 /* Reference task and mm in case of concurrent process termination */
2307 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2310 mm = get_task_mm(usertask);
2312 put_task_struct(usertask);
2316 mutex_lock(&process_info->lock);
2318 if (update_invalid_user_pages(process_info, mm))
2320 /* userptr_inval_list can be empty if all evicted userptr BOs
2321 * have been freed. In that case there is nothing to validate
2322 * and we can just restart the queues.
2324 if (!list_empty(&process_info->userptr_inval_list)) {
2325 if (atomic_read(&process_info->evicted_bos) != evicted_bos)
2326 goto unlock_out; /* Concurrent eviction, try again */
2328 if (validate_invalid_user_pages(process_info))
2331 /* Final check for concurrent evicton and atomic update. If
2332 * another eviction happens after successful update, it will
2333 * be a first eviction that calls quiesce_mm. The eviction
2334 * reference counting inside KFD will handle this case.
2336 if (atomic_cmpxchg(&process_info->evicted_bos, evicted_bos, 0) !=
2340 if (kgd2kfd_resume_mm(mm)) {
2341 pr_err("%s: Failed to resume KFD\n", __func__);
2342 /* No recovery from this failure. Probably the CP is
2343 * hanging. No point trying again.
2348 mutex_unlock(&process_info->lock);
2350 put_task_struct(usertask);
2352 /* If validation failed, reschedule another attempt */
2354 schedule_delayed_work(&process_info->restore_userptr_work,
2355 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2358 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2359 * KFD process identified by process_info
2361 * @process_info: amdkfd_process_info of the KFD process
2363 * After memory eviction, restore thread calls this function. The function
2364 * should be called when the Process is still valid. BO restore involves -
2366 * 1. Release old eviction fence and create new one
2367 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2368 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2369 * BOs that need to be reserved.
2370 * 4. Reserve all the BOs
2371 * 5. Validate of PD and PT BOs.
2372 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2373 * 7. Add fence to all PD and PT BOs.
2374 * 8. Unreserve all BOs
2376 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
2378 struct amdgpu_bo_list_entry *pd_bo_list;
2379 struct amdkfd_process_info *process_info = info;
2380 struct amdgpu_vm *peer_vm;
2381 struct kgd_mem *mem;
2382 struct bo_vm_reservation_context ctx;
2383 struct amdgpu_amdkfd_fence *new_fence;
2385 struct list_head duplicate_save;
2386 struct amdgpu_sync sync_obj;
2387 unsigned long failed_size = 0;
2388 unsigned long total_size = 0;
2390 INIT_LIST_HEAD(&duplicate_save);
2391 INIT_LIST_HEAD(&ctx.list);
2392 INIT_LIST_HEAD(&ctx.duplicates);
2394 pd_bo_list = kcalloc(process_info->n_vms,
2395 sizeof(struct amdgpu_bo_list_entry),
2401 mutex_lock(&process_info->lock);
2402 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2404 amdgpu_vm_get_pd_bo(peer_vm, &ctx.list, &pd_bo_list[i++]);
2406 /* Reserve all BOs and page tables/directory. Add all BOs from
2407 * kfd_bo_list to ctx.list
2409 list_for_each_entry(mem, &process_info->kfd_bo_list,
2410 validate_list.head) {
2412 list_add_tail(&mem->resv_list.head, &ctx.list);
2413 mem->resv_list.bo = mem->validate_list.bo;
2414 mem->resv_list.num_shared = mem->validate_list.num_shared;
2417 ret = ttm_eu_reserve_buffers(&ctx.ticket, &ctx.list,
2418 false, &duplicate_save);
2420 pr_debug("Memory eviction: TTM Reserve Failed. Try again\n");
2421 goto ttm_reserve_fail;
2424 amdgpu_sync_create(&sync_obj);
2426 /* Validate PDs and PTs */
2427 ret = process_validate_vms(process_info);
2429 goto validate_map_fail;
2431 ret = process_sync_pds_resv(process_info, &sync_obj);
2433 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2434 goto validate_map_fail;
2437 /* Validate BOs and map them to GPUVM (update VM page tables). */
2438 list_for_each_entry(mem, &process_info->kfd_bo_list,
2439 validate_list.head) {
2441 struct amdgpu_bo *bo = mem->bo;
2442 uint32_t domain = mem->domain;
2443 struct kfd_mem_attachment *attachment;
2444 struct dma_resv_iter cursor;
2445 struct dma_fence *fence;
2447 total_size += amdgpu_bo_size(bo);
2449 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2451 pr_debug("Memory eviction: Validate BOs failed\n");
2452 failed_size += amdgpu_bo_size(bo);
2453 ret = amdgpu_amdkfd_bo_validate(bo,
2454 AMDGPU_GEM_DOMAIN_GTT, false);
2456 pr_debug("Memory eviction: Try again\n");
2457 goto validate_map_fail;
2460 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2461 DMA_RESV_USAGE_KERNEL, fence) {
2462 ret = amdgpu_sync_fence(&sync_obj, fence);
2464 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2465 goto validate_map_fail;
2468 list_for_each_entry(attachment, &mem->attachments, list) {
2469 if (!attachment->is_mapped)
2472 kfd_mem_dmaunmap_attachment(mem, attachment);
2473 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2475 pr_debug("Memory eviction: update PTE failed. Try again\n");
2476 goto validate_map_fail;
2482 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2484 /* Update page directories */
2485 ret = process_update_pds(process_info, &sync_obj);
2487 pr_debug("Memory eviction: update PDs failed. Try again\n");
2488 goto validate_map_fail;
2491 /* Wait for validate and PT updates to finish */
2492 amdgpu_sync_wait(&sync_obj, false);
2494 /* Release old eviction fence and create new one, because fence only
2495 * goes from unsignaled to signaled, fence cannot be reused.
2496 * Use context and mm from the old fence.
2498 new_fence = amdgpu_amdkfd_fence_create(
2499 process_info->eviction_fence->base.context,
2500 process_info->eviction_fence->mm,
2503 pr_err("Failed to create eviction fence\n");
2505 goto validate_map_fail;
2507 dma_fence_put(&process_info->eviction_fence->base);
2508 process_info->eviction_fence = new_fence;
2509 *ef = dma_fence_get(&new_fence->base);
2511 /* Attach new eviction fence to all BOs except pinned ones */
2512 list_for_each_entry(mem, &process_info->kfd_bo_list,
2513 validate_list.head) {
2514 if (mem->bo->tbo.pin_count)
2517 amdgpu_bo_fence(mem->bo,
2518 &process_info->eviction_fence->base, true);
2520 /* Attach eviction fence to PD / PT BOs */
2521 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2523 struct amdgpu_bo *bo = peer_vm->root.bo;
2525 amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true);
2529 ttm_eu_backoff_reservation(&ctx.ticket, &ctx.list);
2530 amdgpu_sync_free(&sync_obj);
2532 mutex_unlock(&process_info->lock);
2537 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
2539 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2540 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
2546 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2550 mutex_init(&(*mem)->lock);
2551 INIT_LIST_HEAD(&(*mem)->attachments);
2552 (*mem)->bo = amdgpu_bo_ref(gws_bo);
2553 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
2554 (*mem)->process_info = process_info;
2555 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
2556 amdgpu_sync_create(&(*mem)->sync);
2559 /* Validate gws bo the first time it is added to process */
2560 mutex_lock(&(*mem)->process_info->lock);
2561 ret = amdgpu_bo_reserve(gws_bo, false);
2562 if (unlikely(ret)) {
2563 pr_err("Reserve gws bo failed %d\n", ret);
2564 goto bo_reservation_failure;
2567 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
2569 pr_err("GWS BO validate failed %d\n", ret);
2570 goto bo_validation_failure;
2572 /* GWS resource is shared b/t amdgpu and amdkfd
2573 * Add process eviction fence to bo so they can
2576 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
2578 goto reserve_shared_fail;
2579 amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true);
2580 amdgpu_bo_unreserve(gws_bo);
2581 mutex_unlock(&(*mem)->process_info->lock);
2585 reserve_shared_fail:
2586 bo_validation_failure:
2587 amdgpu_bo_unreserve(gws_bo);
2588 bo_reservation_failure:
2589 mutex_unlock(&(*mem)->process_info->lock);
2590 amdgpu_sync_free(&(*mem)->sync);
2591 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
2592 amdgpu_bo_unref(&gws_bo);
2593 mutex_destroy(&(*mem)->lock);
2599 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
2602 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2603 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
2604 struct amdgpu_bo *gws_bo = kgd_mem->bo;
2606 /* Remove BO from process's validate list so restore worker won't touch
2609 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
2611 ret = amdgpu_bo_reserve(gws_bo, false);
2612 if (unlikely(ret)) {
2613 pr_err("Reserve gws bo failed %d\n", ret);
2614 //TODO add BO back to validate_list?
2617 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
2618 process_info->eviction_fence);
2619 amdgpu_bo_unreserve(gws_bo);
2620 amdgpu_sync_free(&kgd_mem->sync);
2621 amdgpu_bo_unref(&gws_bo);
2622 mutex_destroy(&kgd_mem->lock);
2627 /* Returns GPU-specific tiling mode information */
2628 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
2629 struct tile_config *config)
2631 config->gb_addr_config = adev->gfx.config.gb_addr_config;
2632 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
2633 config->num_tile_configs =
2634 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2635 config->macro_tile_config_ptr =
2636 adev->gfx.config.macrotile_mode_array;
2637 config->num_macro_tile_configs =
2638 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2640 /* Those values are not set from GFX9 onwards */
2641 config->num_banks = adev->gfx.config.num_banks;
2642 config->num_ranks = adev->gfx.config.num_ranks;
2647 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
2649 struct kfd_mem_attachment *entry;
2651 list_for_each_entry(entry, &mem->attachments, list) {
2652 if (entry->is_mapped && entry->adev == adev)