drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

   1 /*
   2  * Copyright 2014-2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include <linux/dma-buf.h>
  23 #include <linux/list.h>
  24 #include <linux/pagemap.h>
  25 #include <linux/sched/mm.h>
  26 #include <linux/sched/task.h>
  27
  28 #include "amdgpu_object.h"
  29 #include "amdgpu_gem.h"
  30 #include "amdgpu_vm.h"
  31 #include "amdgpu_amdkfd.h"
  32 #include "amdgpu_dma_buf.h"
  33 #include <uapi/linux/kfd_ioctl.h>
  34 #include "amdgpu_xgmi.h"
  35
  36 /* Userptr restore delay, just long enough to allow consecutive VM
  37  * changes to accumulate
  38  */
  39 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
  40
  41 /* Impose limit on how much memory KFD can use */
  42 static struct {
  43         uint64_t max_system_mem_limit;
  44         uint64_t max_ttm_mem_limit;
  45         int64_t system_mem_used;
  46         int64_t ttm_mem_used;
  47         spinlock_t mem_limit_lock;
  48 } kfd_mem_limit;
  49
  50 /* Struct used for amdgpu_amdkfd_bo_validate */
  51 struct amdgpu_vm_parser {
  52         uint32_t        domain;
  53         bool            wait;
  54 };
  55
  56 static const char * const domain_bit_to_string[] = {
  57                 "CPU",
  58                 "GTT",
  59                 "VRAM",
  60                 "GDS",
  61                 "GWS",
  62                 "OA"
  63 };
  64
  65 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
  66
  67 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
  68
  69
  70 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
  71 {
  72         return (struct amdgpu_device *)kgd;
  73 }
  74
  75 static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
  76                 struct kgd_mem *mem)
  77 {
  78         struct kfd_mem_attachment *entry;
  79
  80         list_for_each_entry(entry, &mem->attachments, list)
  81                 if (entry->bo_va->base.vm == avm)
  82                         return true;
  83
  84         return false;
  85 }
  86
  87 /* Set memory usage limits. Current, limits are
  88  *  System (TTM + userptr) memory - 15/16th System RAM
  89  *  TTM memory - 3/8th System RAM
  90  */
  91 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
  92 {
  93         struct sysinfo si;
  94         uint64_t mem;
  95
  96         si_meminfo(&si);
  97         mem = si.freeram - si.freehigh;
  98         mem *= si.mem_unit;
  99
 100         spin_lock_init(&kfd_mem_limit.mem_limit_lock);
 101         kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
 102         kfd_mem_limit.max_ttm_mem_limit = (mem >> 1) - (mem >> 3);
 103         pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
 104                 (kfd_mem_limit.max_system_mem_limit >> 20),
 105                 (kfd_mem_limit.max_ttm_mem_limit >> 20));
 106 }
 107
 108 void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
 109 {
 110         kfd_mem_limit.system_mem_used += size;
 111 }
 112
 113 /* Estimate page table size needed to represent a given memory size
 114  *
 115  * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
 116  * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
 117  * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
 118  * for 2MB pages for TLB efficiency. However, small allocations and
 119  * fragmented system memory still need some 4KB pages. We choose a
 120  * compromise that should work in most cases without reserving too
 121  * much memory for page tables unnecessarily (factor 16K, >> 14).
 122  */
 123 #define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)
 124
 125 static size_t amdgpu_amdkfd_acc_size(uint64_t size)
 126 {
 127         size >>= PAGE_SHIFT;
 128         size *= sizeof(dma_addr_t) + sizeof(void *);
 129
 130         return __roundup_pow_of_two(sizeof(struct amdgpu_bo)) +
 131                 __roundup_pow_of_two(sizeof(struct ttm_tt)) +
 132                 PAGE_ALIGN(size);
 133 }
 134
 135 static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
 136                 uint64_t size, u32 domain, bool sg)
 137 {
 138         uint64_t reserved_for_pt =
 139                 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
 140         size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed;
 141         int ret = 0;
 142
 143         acc_size = amdgpu_amdkfd_acc_size(size);
 144
 145         vram_needed = 0;
 146         if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 147                 /* TTM GTT memory */
 148                 system_mem_needed = acc_size + size;
 149                 ttm_mem_needed = acc_size + size;
 150         } else if (domain == AMDGPU_GEM_DOMAIN_CPU && !sg) {
 151                 /* Userptr */
 152                 system_mem_needed = acc_size + size;
 153                 ttm_mem_needed = acc_size;
 154         } else {
 155                 /* VRAM and SG */
 156                 system_mem_needed = acc_size;
 157                 ttm_mem_needed = acc_size;
 158                 if (domain == AMDGPU_GEM_DOMAIN_VRAM)
 159                         vram_needed = size;
 160         }
 161
 162         spin_lock(&kfd_mem_limit.mem_limit_lock);
 163
 164         if (kfd_mem_limit.system_mem_used + system_mem_needed >
 165             kfd_mem_limit.max_system_mem_limit)
 166                 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
 167
 168         if ((kfd_mem_limit.system_mem_used + system_mem_needed >
 169              kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
 170             (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
 171              kfd_mem_limit.max_ttm_mem_limit) ||
 172             (adev->kfd.vram_used + vram_needed >
 173              adev->gmc.real_vram_size - reserved_for_pt)) {
 174                 ret = -ENOMEM;
 175         } else {
 176                 kfd_mem_limit.system_mem_used += system_mem_needed;
 177                 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
 178                 adev->kfd.vram_used += vram_needed;
 179         }
 180
 181         spin_unlock(&kfd_mem_limit.mem_limit_lock);
 182         return ret;
 183 }
 184
 185 static void unreserve_mem_limit(struct amdgpu_device *adev,
 186                 uint64_t size, u32 domain, bool sg)
 187 {
 188         size_t acc_size;
 189
 190         acc_size = amdgpu_amdkfd_acc_size(size);
 191
 192         spin_lock(&kfd_mem_limit.mem_limit_lock);
 193         if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 194                 kfd_mem_limit.system_mem_used -= (acc_size + size);
 195                 kfd_mem_limit.ttm_mem_used -= (acc_size + size);
 196         } else if (domain == AMDGPU_GEM_DOMAIN_CPU && !sg) {
 197                 kfd_mem_limit.system_mem_used -= (acc_size + size);
 198                 kfd_mem_limit.ttm_mem_used -= acc_size;
 199         } else {
 200                 kfd_mem_limit.system_mem_used -= acc_size;
 201                 kfd_mem_limit.ttm_mem_used -= acc_size;
 202                 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 203                         adev->kfd.vram_used -= size;
 204                         WARN_ONCE(adev->kfd.vram_used < 0,
 205                                   "kfd VRAM memory accounting unbalanced");
 206                 }
 207         }
 208         WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
 209                   "kfd system memory accounting unbalanced");
 210         WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
 211                   "kfd TTM memory accounting unbalanced");
 212
 213         spin_unlock(&kfd_mem_limit.mem_limit_lock);
 214 }
 215
 216 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
 217 {
 218         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 219         u32 domain = bo->preferred_domains;
 220         bool sg = (bo->preferred_domains == AMDGPU_GEM_DOMAIN_CPU);
 221
 222         if (bo->flags & AMDGPU_AMDKFD_CREATE_USERPTR_BO) {
 223                 domain = AMDGPU_GEM_DOMAIN_CPU;
 224                 sg = false;
 225         }
 226
 227         unreserve_mem_limit(adev, amdgpu_bo_size(bo), domain, sg);
 228 }
 229
 230
 231 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
 232  *  reservation object.
 233  *
 234  * @bo: [IN] Remove eviction fence(s) from this BO
 235  * @ef: [IN] This eviction fence is removed if it
 236  *  is present in the shared list.
 237  *
 238  * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
 239  */
 240 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
 241                                         struct amdgpu_amdkfd_fence *ef)
 242 {
 243         struct dma_resv *resv = bo->tbo.base.resv;
 244         struct dma_resv_list *old, *new;
 245         unsigned int i, j, k;
 246
 247         if (!ef)
 248                 return -EINVAL;
 249
 250         old = dma_resv_get_list(resv);
 251         if (!old)
 252                 return 0;
 253
 254         new = kmalloc(struct_size(new, shared, old->shared_max), GFP_KERNEL);
 255         if (!new)
 256                 return -ENOMEM;
 257
 258         /* Go through all the shared fences in the resevation object and sort
 259          * the interesting ones to the end of the list.
 260          */
 261         for (i = 0, j = old->shared_count, k = 0; i < old->shared_count; ++i) {
 262                 struct dma_fence *f;
 263
 264                 f = rcu_dereference_protected(old->shared[i],
 265                                               dma_resv_held(resv));
 266
 267                 if (f->context == ef->base.context)
 268                         RCU_INIT_POINTER(new->shared[--j], f);
 269                 else
 270                         RCU_INIT_POINTER(new->shared[k++], f);
 271         }
 272         new->shared_max = old->shared_max;
 273         new->shared_count = k;
 274
 275         /* Install the new fence list, seqcount provides the barriers */
 276         write_seqcount_begin(&resv->seq);
 277         RCU_INIT_POINTER(resv->fence, new);
 278         write_seqcount_end(&resv->seq);
 279
 280         /* Drop the references to the removed fences or move them to ef_list */
 281         for (i = j, k = 0; i < old->shared_count; ++i) {
 282                 struct dma_fence *f;
 283
 284                 f = rcu_dereference_protected(new->shared[i],
 285                                               dma_resv_held(resv));
 286                 dma_fence_put(f);
 287         }
 288         kfree_rcu(old, rcu);
 289
 290         return 0;
 291 }
 292
 293 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
 294 {
 295         struct amdgpu_bo *root = bo;
 296         struct amdgpu_vm_bo_base *vm_bo;
 297         struct amdgpu_vm *vm;
 298         struct amdkfd_process_info *info;
 299         struct amdgpu_amdkfd_fence *ef;
 300         int ret;
 301
 302         /* we can always get vm_bo from root PD bo.*/
 303         while (root->parent)
 304                 root = root->parent;
 305
 306         vm_bo = root->vm_bo;
 307         if (!vm_bo)
 308                 return 0;
 309
 310         vm = vm_bo->vm;
 311         if (!vm)
 312                 return 0;
 313
 314         info = vm->process_info;
 315         if (!info || !info->eviction_fence)
 316                 return 0;
 317
 318         ef = container_of(dma_fence_get(&info->eviction_fence->base),
 319                         struct amdgpu_amdkfd_fence, base);
 320
 321         BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
 322         ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
 323         dma_resv_unlock(bo->tbo.base.resv);
 324
 325         dma_fence_put(&ef->base);
 326         return ret;
 327 }
 328
 329 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
 330                                      bool wait)
 331 {
 332         struct ttm_operation_ctx ctx = { false, false };
 333         int ret;
 334
 335         if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
 336                  "Called with userptr BO"))
 337                 return -EINVAL;
 338
 339         amdgpu_bo_placement_from_domain(bo, domain);
 340
 341         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 342         if (ret)
 343                 goto validate_fail;
 344         if (wait)
 345                 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
 346
 347 validate_fail:
 348         return ret;
 349 }
 350
 351 static int amdgpu_amdkfd_validate(void *param, struct amdgpu_bo *bo)
 352 {
 353         struct amdgpu_vm_parser *p = param;
 354
 355         return amdgpu_amdkfd_bo_validate(bo, p->domain, p->wait);
 356 }
 357
 358 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
 359  *
 360  * Page directories are not updated here because huge page handling
 361  * during page table updates can invalidate page directory entries
 362  * again. Page directories are only updated after updating page
 363  * tables.
 364  */
 365 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
 366 {
 367         struct amdgpu_bo *pd = vm->root.base.bo;
 368         struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
 369         struct amdgpu_vm_parser param;
 370         int ret;
 371
 372         param.domain = AMDGPU_GEM_DOMAIN_VRAM;
 373         param.wait = false;
 374
 375         ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate,
 376                                         &param);
 377         if (ret) {
 378                 pr_err("failed to validate PT BOs\n");
 379                 return ret;
 380         }
 381
 382         ret = amdgpu_amdkfd_validate(&param, pd);
 383         if (ret) {
 384                 pr_err("failed to validate PD\n");
 385                 return ret;
 386         }
 387
 388         vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
 389
 390         if (vm->use_cpu_for_update) {
 391                 ret = amdgpu_bo_kmap(pd, NULL);
 392                 if (ret) {
 393                         pr_err("failed to kmap PD, ret=%d\n", ret);
 394                         return ret;
 395                 }
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
 402 {
 403         struct amdgpu_bo *pd = vm->root.base.bo;
 404         struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
 405         int ret;
 406
 407         ret = amdgpu_vm_update_pdes(adev, vm, false);
 408         if (ret)
 409                 return ret;
 410
 411         return amdgpu_sync_fence(sync, vm->last_update);
 412 }
 413
 414 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
 415 {
 416         struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
 417         bool coherent = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT;
 418         bool uncached = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED;
 419         uint32_t mapping_flags;
 420         uint64_t pte_flags;
 421         bool snoop = false;
 422
 423         mapping_flags = AMDGPU_VM_PAGE_READABLE;
 424         if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
 425                 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
 426         if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
 427                 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
 428
 429         switch (adev->asic_type) {
 430         case CHIP_ARCTURUS:
 431                 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
 432                         if (bo_adev == adev)
 433                                 mapping_flags |= coherent ?
 434                                         AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
 435                         else
 436                                 mapping_flags |= coherent ?
 437                                         AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
 438                 } else {
 439                         mapping_flags |= coherent ?
 440                                 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
 441                 }
 442                 break;
 443         case CHIP_ALDEBARAN:
 444                 if (coherent && uncached) {
 445                         if (adev->gmc.xgmi.connected_to_cpu ||
 446                                 !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM))
 447                                 snoop = true;
 448                         mapping_flags |= AMDGPU_VM_MTYPE_UC;
 449                 } else if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
 450                         if (bo_adev == adev) {
 451                                 mapping_flags |= coherent ?
 452                                         AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
 453                                 if (adev->gmc.xgmi.connected_to_cpu)
 454                                         snoop = true;
 455                         } else {
 456                                 mapping_flags |= coherent ?
 457                                         AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
 458                                 if (amdgpu_xgmi_same_hive(adev, bo_adev))
 459                                         snoop = true;
 460                         }
 461                 } else {
 462                         snoop = true;
 463                         mapping_flags |= coherent ?
 464                                 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
 465                 }
 466                 break;
 467         default:
 468                 mapping_flags |= coherent ?
 469                         AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
 470         }
 471
 472         pte_flags = amdgpu_gem_va_map_flags(adev, mapping_flags);
 473         pte_flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
 474
 475         return pte_flags;
 476 }
 477
 478 static int
 479 kfd_mem_dmamap_userptr(struct kgd_mem *mem,
 480                        struct kfd_mem_attachment *attachment)
 481 {
 482         enum dma_data_direction direction =
 483                 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
 484                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 485         struct ttm_operation_ctx ctx = {.interruptible = true};
 486         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
 487         struct amdgpu_device *adev = attachment->adev;
 488         struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
 489         struct ttm_tt *ttm = bo->tbo.ttm;
 490         int ret;
 491
 492         ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
 493         if (unlikely(!ttm->sg))
 494                 return -ENOMEM;
 495
 496         if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
 497                 return -EINVAL;
 498
 499         /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
 500         ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
 501                                         ttm->num_pages, 0,
 502                                         (u64)ttm->num_pages << PAGE_SHIFT,
 503                                         GFP_KERNEL);
 504         if (unlikely(ret))
 505                 goto free_sg;
 506
 507         ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 508         if (unlikely(ret))
 509                 goto release_sg;
 510
 511         drm_prime_sg_to_dma_addr_array(ttm->sg, ttm->dma_address,
 512                                        ttm->num_pages);
 513
 514         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 515         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 516         if (ret)
 517                 goto unmap_sg;
 518
 519         return 0;
 520
 521 unmap_sg:
 522         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 523 release_sg:
 524         pr_err("DMA map userptr failed: %d\n", ret);
 525         sg_free_table(ttm->sg);
 526 free_sg:
 527         kfree(ttm->sg);
 528         ttm->sg = NULL;
 529         return ret;
 530 }
 531
 532 static int
 533 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
 534 {
 535         struct ttm_operation_ctx ctx = {.interruptible = true};
 536         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
 537
 538         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 539         return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 540 }
 541
 542 static int
 543 kfd_mem_dmamap_attachment(struct kgd_mem *mem,
 544                           struct kfd_mem_attachment *attachment)
 545 {
 546         switch (attachment->type) {
 547         case KFD_MEM_ATT_SHARED:
 548                 return 0;
 549         case KFD_MEM_ATT_USERPTR:
 550                 return kfd_mem_dmamap_userptr(mem, attachment);
 551         case KFD_MEM_ATT_DMABUF:
 552                 return kfd_mem_dmamap_dmabuf(attachment);
 553         default:
 554                 WARN_ON_ONCE(1);
 555         }
 556         return -EINVAL;
 557 }
 558
 559 static void
 560 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
 561                          struct kfd_mem_attachment *attachment)
 562 {
 563         enum dma_data_direction direction =
 564                 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
 565                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 566         struct ttm_operation_ctx ctx = {.interruptible = false};
 567         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
 568         struct amdgpu_device *adev = attachment->adev;
 569         struct ttm_tt *ttm = bo->tbo.ttm;
 570
 571         if (unlikely(!ttm->sg))
 572                 return;
 573
 574         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
 575         ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 576
 577         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 578         sg_free_table(ttm->sg);
 579         ttm->sg = NULL;
 580 }
 581
 582 static void
 583 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
 584 {
 585         struct ttm_operation_ctx ctx = {.interruptible = true};
 586         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
 587
 588         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
 589         ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 590 }
 591
 592 static void
 593 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
 594                             struct kfd_mem_attachment *attachment)
 595 {
 596         switch (attachment->type) {
 597         case KFD_MEM_ATT_SHARED:
 598                 break;
 599         case KFD_MEM_ATT_USERPTR:
 600                 kfd_mem_dmaunmap_userptr(mem, attachment);
 601                 break;
 602         case KFD_MEM_ATT_DMABUF:
 603                 kfd_mem_dmaunmap_dmabuf(attachment);
 604                 break;
 605         default:
 606                 WARN_ON_ONCE(1);
 607         }
 608 }
 609
 610 static int
 611 kfd_mem_attach_userptr(struct amdgpu_device *adev, struct kgd_mem *mem,
 612                        struct amdgpu_bo **bo)
 613 {
 614         unsigned long bo_size = mem->bo->tbo.base.size;
 615         struct drm_gem_object *gobj;
 616         int ret;
 617
 618         ret = amdgpu_bo_reserve(mem->bo, false);
 619         if (ret)
 620                 return ret;
 621
 622         ret = amdgpu_gem_object_create(adev, bo_size, 1,
 623                                        AMDGPU_GEM_DOMAIN_CPU,
 624                                        AMDGPU_GEM_CREATE_PREEMPTIBLE,
 625                                        ttm_bo_type_sg, mem->bo->tbo.base.resv,
 626                                        &gobj);
 627         if (ret)
 628                 return ret;
 629
 630         amdgpu_bo_unreserve(mem->bo);
 631
 632         *bo = gem_to_amdgpu_bo(gobj);
 633         (*bo)->parent = amdgpu_bo_ref(mem->bo);
 634
 635         return 0;
 636 }
 637
 638 static int
 639 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
 640                       struct amdgpu_bo **bo)
 641 {
 642         struct drm_gem_object *gobj;
 643
 644         if (!mem->dmabuf) {
 645                 mem->dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base,
 646                         mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
 647                                 DRM_RDWR : 0);
 648                 if (IS_ERR(mem->dmabuf)) {
 649                         mem->dmabuf = NULL;
 650                         return PTR_ERR(mem->dmabuf);
 651                 }
 652         }
 653
 654         gobj = amdgpu_gem_prime_import(&adev->ddev, mem->dmabuf);
 655         if (IS_ERR(gobj))
 656                 return PTR_ERR(gobj);
 657
 658         /* Import takes an extra reference on the dmabuf. Drop it now to
 659          * avoid leaking it. We only need the one reference in
 660          * kgd_mem->dmabuf.
 661          */
 662         dma_buf_put(mem->dmabuf);
 663
 664         *bo = gem_to_amdgpu_bo(gobj);
 665         (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
 666         (*bo)->parent = amdgpu_bo_ref(mem->bo);
 667
 668         return 0;
 669 }
 670
 671 /* kfd_mem_attach - Add a BO to a VM
 672  *
 673  * Everything that needs to bo done only once when a BO is first added
 674  * to a VM. It can later be mapped and unmapped many times without
 675  * repeating these steps.
 676  *
 677  * 0. Create BO for DMA mapping, if needed
 678  * 1. Allocate and initialize BO VA entry data structure
 679  * 2. Add BO to the VM
 680  * 3. Determine ASIC-specific PTE flags
 681  * 4. Alloc page tables and directories if needed
 682  * 4a.  Validate new page tables and directories
 683  */
 684 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 685                 struct amdgpu_vm *vm, bool is_aql)
 686 {
 687         struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
 688         unsigned long bo_size = mem->bo->tbo.base.size;
 689         uint64_t va = mem->va;
 690         struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
 691         struct amdgpu_bo *bo[2] = {NULL, NULL};
 692         int i, ret;
 693
 694         if (!va) {
 695                 pr_err("Invalid VA when adding BO to VM\n");
 696                 return -EINVAL;
 697         }
 698
 699         for (i = 0; i <= is_aql; i++) {
 700                 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
 701                 if (unlikely(!attachment[i])) {
 702                         ret = -ENOMEM;
 703                         goto unwind;
 704                 }
 705
 706                 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
 707                          va + bo_size, vm);
 708
 709                 if (adev == bo_adev || (mem->domain == AMDGPU_GEM_DOMAIN_VRAM &&
 710                                         amdgpu_xgmi_same_hive(adev, bo_adev))) {
 711                         /* Mappings on the local GPU and VRAM mappings in the
 712                          * local hive share the original BO
 713                          */
 714                         attachment[i]->type = KFD_MEM_ATT_SHARED;
 715                         bo[i] = mem->bo;
 716                         drm_gem_object_get(&bo[i]->tbo.base);
 717                 } else if (i > 0) {
 718                         /* Multiple mappings on the same GPU share the BO */
 719                         attachment[i]->type = KFD_MEM_ATT_SHARED;
 720                         bo[i] = bo[0];
 721                         drm_gem_object_get(&bo[i]->tbo.base);
 722                 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
 723                         /* Create an SG BO to DMA-map userptrs on other GPUs */
 724                         attachment[i]->type = KFD_MEM_ATT_USERPTR;
 725                         ret = kfd_mem_attach_userptr(adev, mem, &bo[i]);
 726                         if (ret)
 727                                 goto unwind;
 728                 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT &&
 729                            mem->bo->tbo.type != ttm_bo_type_sg) {
 730                         /* GTT BOs use DMA-mapping ability of dynamic-attach
 731                          * DMA bufs. TODO: The same should work for VRAM on
 732                          * large-BAR GPUs.
 733                          */
 734                         attachment[i]->type = KFD_MEM_ATT_DMABUF;
 735                         ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
 736                         if (ret)
 737                                 goto unwind;
 738                 } else {
 739                         /* FIXME: Need to DMA-map other BO types:
 740                          * large-BAR VRAM, doorbells, MMIO remap
 741                          */
 742                         attachment[i]->type = KFD_MEM_ATT_SHARED;
 743                         bo[i] = mem->bo;
 744                         drm_gem_object_get(&bo[i]->tbo.base);
 745                 }
 746
 747                 /* Add BO to VM internal data structures */
 748                 attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
 749                 if (unlikely(!attachment[i]->bo_va)) {
 750                         ret = -ENOMEM;
 751                         pr_err("Failed to add BO object to VM. ret == %d\n",
 752                                ret);
 753                         goto unwind;
 754                 }
 755
 756                 attachment[i]->va = va;
 757                 attachment[i]->pte_flags = get_pte_flags(adev, mem);
 758                 attachment[i]->adev = adev;
 759                 list_add(&attachment[i]->list, &mem->attachments);
 760
 761                 va += bo_size;
 762         }
 763
 764         return 0;
 765
 766 unwind:
 767         for (; i >= 0; i--) {
 768                 if (!attachment[i])
 769                         continue;
 770                 if (attachment[i]->bo_va) {
 771                         amdgpu_vm_bo_rmv(adev, attachment[i]->bo_va);
 772                         list_del(&attachment[i]->list);
 773                 }
 774                 if (bo[i])
 775                         drm_gem_object_put(&bo[i]->tbo.base);
 776                 kfree(attachment[i]);
 777         }
 778         return ret;
 779 }
 780
 781 static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
 782 {
 783         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
 784
 785         pr_debug("\t remove VA 0x%llx in entry %p\n",
 786                         attachment->va, attachment);
 787         amdgpu_vm_bo_rmv(attachment->adev, attachment->bo_va);
 788         drm_gem_object_put(&bo->tbo.base);
 789         list_del(&attachment->list);
 790         kfree(attachment);
 791 }
 792
 793 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
 794                                 struct amdkfd_process_info *process_info,
 795                                 bool userptr)
 796 {
 797         struct ttm_validate_buffer *entry = &mem->validate_list;
 798         struct amdgpu_bo *bo = mem->bo;
 799
 800         INIT_LIST_HEAD(&entry->head);
 801         entry->num_shared = 1;
 802         entry->bo = &bo->tbo;
 803         mutex_lock(&process_info->lock);
 804         if (userptr)
 805                 list_add_tail(&entry->head, &process_info->userptr_valid_list);
 806         else
 807                 list_add_tail(&entry->head, &process_info->kfd_bo_list);
 808         mutex_unlock(&process_info->lock);
 809 }
 810
 811 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
 812                 struct amdkfd_process_info *process_info)
 813 {
 814         struct ttm_validate_buffer *bo_list_entry;
 815
 816         bo_list_entry = &mem->validate_list;
 817         mutex_lock(&process_info->lock);
 818         list_del(&bo_list_entry->head);
 819         mutex_unlock(&process_info->lock);
 820 }
 821
 822 /* Initializes user pages. It registers the MMU notifier and validates
 823  * the userptr BO in the GTT domain.
 824  *
 825  * The BO must already be on the userptr_valid_list. Otherwise an
 826  * eviction and restore may happen that leaves the new BO unmapped
 827  * with the user mode queues running.
 828  *
 829  * Takes the process_info->lock to protect against concurrent restore
 830  * workers.
 831  *
 832  * Returns 0 for success, negative errno for errors.
 833  */
 834 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr)
 835 {
 836         struct amdkfd_process_info *process_info = mem->process_info;
 837         struct amdgpu_bo *bo = mem->bo;
 838         struct ttm_operation_ctx ctx = { true, false };
 839         int ret = 0;
 840
 841         mutex_lock(&process_info->lock);
 842
 843         ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
 844         if (ret) {
 845                 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
 846                 goto out;
 847         }
 848
 849         ret = amdgpu_mn_register(bo, user_addr);
 850         if (ret) {
 851                 pr_err("%s: Failed to register MMU notifier: %d\n",
 852                        __func__, ret);
 853                 goto out;
 854         }
 855
 856         ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
 857         if (ret) {
 858                 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
 859                 goto unregister_out;
 860         }
 861
 862         ret = amdgpu_bo_reserve(bo, true);
 863         if (ret) {
 864                 pr_err("%s: Failed to reserve BO\n", __func__);
 865                 goto release_out;
 866         }
 867         amdgpu_bo_placement_from_domain(bo, mem->domain);
 868         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 869         if (ret)
 870                 pr_err("%s: failed to validate BO\n", __func__);
 871         amdgpu_bo_unreserve(bo);
 872
 873 release_out:
 874         amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
 875 unregister_out:
 876         if (ret)
 877                 amdgpu_mn_unregister(bo);
 878 out:
 879         mutex_unlock(&process_info->lock);
 880         return ret;
 881 }
 882
 883 /* Reserving a BO and its page table BOs must happen atomically to
 884  * avoid deadlocks. Some operations update multiple VMs at once. Track
 885  * all the reservation info in a context structure. Optionally a sync
 886  * object can track VM updates.
 887  */
 888 struct bo_vm_reservation_context {
 889         struct amdgpu_bo_list_entry kfd_bo; /* BO list entry for the KFD BO */
 890         unsigned int n_vms;                 /* Number of VMs reserved       */
 891         struct amdgpu_bo_list_entry *vm_pd; /* Array of VM BO list entries  */
 892         struct ww_acquire_ctx ticket;       /* Reservation ticket           */
 893         struct list_head list, duplicates;  /* BO lists                     */
 894         struct amdgpu_sync *sync;           /* Pointer to sync object       */
 895         bool reserved;                      /* Whether BOs are reserved     */
 896 };
 897
 898 enum bo_vm_match {
 899         BO_VM_NOT_MAPPED = 0,   /* Match VMs where a BO is not mapped */
 900         BO_VM_MAPPED,           /* Match VMs where a BO is mapped     */
 901         BO_VM_ALL,              /* Match all VMs a BO was added to    */
 902 };
 903
 904 /**
 905  * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
 906  * @mem: KFD BO structure.
 907  * @vm: the VM to reserve.
 908  * @ctx: the struct that will be used in unreserve_bo_and_vms().
 909  */
 910 static int reserve_bo_and_vm(struct kgd_mem *mem,
 911                               struct amdgpu_vm *vm,
 912                               struct bo_vm_reservation_context *ctx)
 913 {
 914         struct amdgpu_bo *bo = mem->bo;
 915         int ret;
 916
 917         WARN_ON(!vm);
 918
 919         ctx->reserved = false;
 920         ctx->n_vms = 1;
 921         ctx->sync = &mem->sync;
 922
 923         INIT_LIST_HEAD(&ctx->list);
 924         INIT_LIST_HEAD(&ctx->duplicates);
 925
 926         ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd), GFP_KERNEL);
 927         if (!ctx->vm_pd)
 928                 return -ENOMEM;
 929
 930         ctx->kfd_bo.priority = 0;
 931         ctx->kfd_bo.tv.bo = &bo->tbo;
 932         ctx->kfd_bo.tv.num_shared = 1;
 933         list_add(&ctx->kfd_bo.tv.head, &ctx->list);
 934
 935         amdgpu_vm_get_pd_bo(vm, &ctx->list, &ctx->vm_pd[0]);
 936
 937         ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
 938                                      false, &ctx->duplicates);
 939         if (ret) {
 940                 pr_err("Failed to reserve buffers in ttm.\n");
 941                 kfree(ctx->vm_pd);
 942                 ctx->vm_pd = NULL;
 943                 return ret;
 944         }
 945
 946         ctx->reserved = true;
 947         return 0;
 948 }
 949
 950 /**
 951  * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
 952  * @mem: KFD BO structure.
 953  * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
 954  * is used. Otherwise, a single VM associated with the BO.
 955  * @map_type: the mapping status that will be used to filter the VMs.
 956  * @ctx: the struct that will be used in unreserve_bo_and_vms().
 957  *
 958  * Returns 0 for success, negative for failure.
 959  */
 960 static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
 961                                 struct amdgpu_vm *vm, enum bo_vm_match map_type,
 962                                 struct bo_vm_reservation_context *ctx)
 963 {
 964         struct amdgpu_bo *bo = mem->bo;
 965         struct kfd_mem_attachment *entry;
 966         unsigned int i;
 967         int ret;
 968
 969         ctx->reserved = false;
 970         ctx->n_vms = 0;
 971         ctx->vm_pd = NULL;
 972         ctx->sync = &mem->sync;
 973
 974         INIT_LIST_HEAD(&ctx->list);
 975         INIT_LIST_HEAD(&ctx->duplicates);
 976
 977         list_for_each_entry(entry, &mem->attachments, list) {
 978                 if ((vm && vm != entry->bo_va->base.vm) ||
 979                         (entry->is_mapped != map_type
 980                         && map_type != BO_VM_ALL))
 981                         continue;
 982
 983                 ctx->n_vms++;
 984         }
 985
 986         if (ctx->n_vms != 0) {
 987                 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd),
 988                                      GFP_KERNEL);
 989                 if (!ctx->vm_pd)
 990                         return -ENOMEM;
 991         }
 992
 993         ctx->kfd_bo.priority = 0;
 994         ctx->kfd_bo.tv.bo = &bo->tbo;
 995         ctx->kfd_bo.tv.num_shared = 1;
 996         list_add(&ctx->kfd_bo.tv.head, &ctx->list);
 997
 998         i = 0;
 999         list_for_each_entry(entry, &mem->attachments, list) {
1000                 if ((vm && vm != entry->bo_va->base.vm) ||
1001                         (entry->is_mapped != map_type
1002                         && map_type != BO_VM_ALL))
1003                         continue;
1004
1005                 amdgpu_vm_get_pd_bo(entry->bo_va->base.vm, &ctx->list,
1006                                 &ctx->vm_pd[i]);
1007                 i++;
1008         }
1009
1010         ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
1011                                      false, &ctx->duplicates);
1012         if (ret) {
1013                 pr_err("Failed to reserve buffers in ttm.\n");
1014                 kfree(ctx->vm_pd);
1015                 ctx->vm_pd = NULL;
1016                 return ret;
1017         }
1018
1019         ctx->reserved = true;
1020         return 0;
1021 }
1022
1023 /**
1024  * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1025  * @ctx: Reservation context to unreserve
1026  * @wait: Optionally wait for a sync object representing pending VM updates
1027  * @intr: Whether the wait is interruptible
1028  *
1029  * Also frees any resources allocated in
1030  * reserve_bo_and_(cond_)vm(s). Returns the status from
1031  * amdgpu_sync_wait.
1032  */
1033 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1034                                  bool wait, bool intr)
1035 {
1036         int ret = 0;
1037
1038         if (wait)
1039                 ret = amdgpu_sync_wait(ctx->sync, intr);
1040
1041         if (ctx->reserved)
1042                 ttm_eu_backoff_reservation(&ctx->ticket, &ctx->list);
1043         kfree(ctx->vm_pd);
1044
1045         ctx->sync = NULL;
1046
1047         ctx->reserved = false;
1048         ctx->vm_pd = NULL;
1049
1050         return ret;
1051 }
1052
1053 static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1054                                 struct kfd_mem_attachment *entry,
1055                                 struct amdgpu_sync *sync)
1056 {
1057         struct amdgpu_bo_va *bo_va = entry->bo_va;
1058         struct amdgpu_device *adev = entry->adev;
1059         struct amdgpu_vm *vm = bo_va->base.vm;
1060
1061         amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1062
1063         amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1064
1065         amdgpu_sync_fence(sync, bo_va->last_pt_update);
1066
1067         kfd_mem_dmaunmap_attachment(mem, entry);
1068 }
1069
1070 static int update_gpuvm_pte(struct kgd_mem *mem,
1071                             struct kfd_mem_attachment *entry,
1072                             struct amdgpu_sync *sync)
1073 {
1074         struct amdgpu_bo_va *bo_va = entry->bo_va;
1075         struct amdgpu_device *adev = entry->adev;
1076         int ret;
1077
1078         ret = kfd_mem_dmamap_attachment(mem, entry);
1079         if (ret)
1080                 return ret;
1081
1082         /* Update the page tables  */
1083         ret = amdgpu_vm_bo_update(adev, bo_va, false);
1084         if (ret) {
1085                 pr_err("amdgpu_vm_bo_update failed\n");
1086                 return ret;
1087         }
1088
1089         return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1090 }
1091
1092 static int map_bo_to_gpuvm(struct kgd_mem *mem,
1093                            struct kfd_mem_attachment *entry,
1094                            struct amdgpu_sync *sync,
1095                            bool no_update_pte)
1096 {
1097         int ret;
1098
1099         /* Set virtual address for the allocation */
1100         ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1101                                amdgpu_bo_size(entry->bo_va->base.bo),
1102                                entry->pte_flags);
1103         if (ret) {
1104                 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1105                                 entry->va, ret);
1106                 return ret;
1107         }
1108
1109         if (no_update_pte)
1110                 return 0;
1111
1112         ret = update_gpuvm_pte(mem, entry, sync);
1113         if (ret) {
1114                 pr_err("update_gpuvm_pte() failed\n");
1115                 goto update_gpuvm_pte_failed;
1116         }
1117
1118         return 0;
1119
1120 update_gpuvm_pte_failed:
1121         unmap_bo_from_gpuvm(mem, entry, sync);
1122         return ret;
1123 }
1124
1125 static struct sg_table *create_doorbell_sg(uint64_t addr, uint32_t size)
1126 {
1127         struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
1128
1129         if (!sg)
1130                 return NULL;
1131         if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
1132                 kfree(sg);
1133                 return NULL;
1134         }
1135         sg->sgl->dma_address = addr;
1136         sg->sgl->length = size;
1137 #ifdef CONFIG_NEED_SG_DMA_LENGTH
1138         sg->sgl->dma_length = size;
1139 #endif
1140         return sg;
1141 }
1142
1143 static int process_validate_vms(struct amdkfd_process_info *process_info)
1144 {
1145         struct amdgpu_vm *peer_vm;
1146         int ret;
1147
1148         list_for_each_entry(peer_vm, &process_info->vm_list_head,
1149                             vm_list_node) {
1150                 ret = vm_validate_pt_pd_bos(peer_vm);
1151                 if (ret)
1152                         return ret;
1153         }
1154
1155         return 0;
1156 }
1157
1158 static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1159                                  struct amdgpu_sync *sync)
1160 {
1161         struct amdgpu_vm *peer_vm;
1162         int ret;
1163
1164         list_for_each_entry(peer_vm, &process_info->vm_list_head,
1165                             vm_list_node) {
1166                 struct amdgpu_bo *pd = peer_vm->root.base.bo;
1167
1168                 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1169                                        AMDGPU_SYNC_NE_OWNER,
1170                                        AMDGPU_FENCE_OWNER_KFD);
1171                 if (ret)
1172                         return ret;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int process_update_pds(struct amdkfd_process_info *process_info,
1179                               struct amdgpu_sync *sync)
1180 {
1181         struct amdgpu_vm *peer_vm;
1182         int ret;
1183
1184         list_for_each_entry(peer_vm, &process_info->vm_list_head,
1185                             vm_list_node) {
1186                 ret = vm_update_pds(peer_vm, sync);
1187                 if (ret)
1188                         return ret;
1189         }
1190
1191         return 0;
1192 }
1193
1194 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1195                        struct dma_fence **ef)
1196 {
1197         struct amdkfd_process_info *info = NULL;
1198         int ret;
1199
1200         if (!*process_info) {
1201                 info = kzalloc(sizeof(*info), GFP_KERNEL);
1202                 if (!info)
1203                         return -ENOMEM;
1204
1205                 mutex_init(&info->lock);
1206                 INIT_LIST_HEAD(&info->vm_list_head);
1207                 INIT_LIST_HEAD(&info->kfd_bo_list);
1208                 INIT_LIST_HEAD(&info->userptr_valid_list);
1209                 INIT_LIST_HEAD(&info->userptr_inval_list);
1210
1211                 info->eviction_fence =
1212                         amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1213                                                    current->mm,
1214                                                    NULL);
1215                 if (!info->eviction_fence) {
1216                         pr_err("Failed to create eviction fence\n");
1217                         ret = -ENOMEM;
1218                         goto create_evict_fence_fail;
1219                 }
1220
1221                 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1222                 atomic_set(&info->evicted_bos, 0);
1223                 INIT_DELAYED_WORK(&info->restore_userptr_work,
1224                                   amdgpu_amdkfd_restore_userptr_worker);
1225
1226                 *process_info = info;
1227                 *ef = dma_fence_get(&info->eviction_fence->base);
1228         }
1229
1230         vm->process_info = *process_info;
1231
1232         /* Validate page directory and attach eviction fence */
1233         ret = amdgpu_bo_reserve(vm->root.base.bo, true);
1234         if (ret)
1235                 goto reserve_pd_fail;
1236         ret = vm_validate_pt_pd_bos(vm);
1237         if (ret) {
1238                 pr_err("validate_pt_pd_bos() failed\n");
1239                 goto validate_pd_fail;
1240         }
1241         ret = amdgpu_bo_sync_wait(vm->root.base.bo,
1242                                   AMDGPU_FENCE_OWNER_KFD, false);
1243         if (ret)
1244                 goto wait_pd_fail;
1245         ret = dma_resv_reserve_shared(vm->root.base.bo->tbo.base.resv, 1);
1246         if (ret)
1247                 goto reserve_shared_fail;
1248         amdgpu_bo_fence(vm->root.base.bo,
1249                         &vm->process_info->eviction_fence->base, true);
1250         amdgpu_bo_unreserve(vm->root.base.bo);
1251
1252         /* Update process info */
1253         mutex_lock(&vm->process_info->lock);
1254         list_add_tail(&vm->vm_list_node,
1255                         &(vm->process_info->vm_list_head));
1256         vm->process_info->n_vms++;
1257         mutex_unlock(&vm->process_info->lock);
1258
1259         return 0;
1260
1261 reserve_shared_fail:
1262 wait_pd_fail:
1263 validate_pd_fail:
1264         amdgpu_bo_unreserve(vm->root.base.bo);
1265 reserve_pd_fail:
1266         vm->process_info = NULL;
1267         if (info) {
1268                 /* Two fence references: one in info and one in *ef */
1269                 dma_fence_put(&info->eviction_fence->base);
1270                 dma_fence_put(*ef);
1271                 *ef = NULL;
1272                 *process_info = NULL;
1273                 put_pid(info->pid);
1274 create_evict_fence_fail:
1275                 mutex_destroy(&info->lock);
1276                 kfree(info);
1277         }
1278         return ret;
1279 }
1280
1281 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
1282                                            struct file *filp, u32 pasid,
1283                                            void **process_info,
1284                                            struct dma_fence **ef)
1285 {
1286         struct amdgpu_device *adev = get_amdgpu_device(kgd);
1287         struct amdgpu_fpriv *drv_priv;
1288         struct amdgpu_vm *avm;
1289         int ret;
1290
1291         ret = amdgpu_file_to_fpriv(filp, &drv_priv);
1292         if (ret)
1293                 return ret;
1294         avm = &drv_priv->vm;
1295
1296         /* Already a compute VM? */
1297         if (avm->process_info)
1298                 return -EINVAL;
1299
1300         /* Convert VM into a compute VM */
1301         ret = amdgpu_vm_make_compute(adev, avm, pasid);
1302         if (ret)
1303                 return ret;
1304
1305         /* Initialize KFD part of the VM and process info */
1306         ret = init_kfd_vm(avm, process_info, ef);
1307         if (ret)
1308                 return ret;
1309
1310         amdgpu_vm_set_task_info(avm);
1311
1312         return 0;
1313 }
1314
1315 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1316                                     struct amdgpu_vm *vm)
1317 {
1318         struct amdkfd_process_info *process_info = vm->process_info;
1319         struct amdgpu_bo *pd = vm->root.base.bo;
1320
1321         if (!process_info)
1322                 return;
1323
1324         /* Release eviction fence from PD */
1325         amdgpu_bo_reserve(pd, false);
1326         amdgpu_bo_fence(pd, NULL, false);
1327         amdgpu_bo_unreserve(pd);
1328
1329         /* Update process info */
1330         mutex_lock(&process_info->lock);
1331         process_info->n_vms--;
1332         list_del(&vm->vm_list_node);
1333         mutex_unlock(&process_info->lock);
1334
1335         vm->process_info = NULL;
1336
1337         /* Release per-process resources when last compute VM is destroyed */
1338         if (!process_info->n_vms) {
1339                 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1340                 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1341                 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1342
1343                 dma_fence_put(&process_info->eviction_fence->base);
1344                 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1345                 put_pid(process_info->pid);
1346                 mutex_destroy(&process_info->lock);
1347                 kfree(process_info);
1348         }
1349 }
1350
1351 void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv)
1352 {
1353         struct amdgpu_device *adev = get_amdgpu_device(kgd);
1354         struct amdgpu_vm *avm;
1355
1356         if (WARN_ON(!kgd || !drm_priv))
1357                 return;
1358
1359         avm = drm_priv_to_vm(drm_priv);
1360
1361         pr_debug("Releasing process vm %p\n", avm);
1362
1363         /* The original pasid of amdgpu vm has already been
1364          * released during making a amdgpu vm to a compute vm
1365          * The current pasid is managed by kfd and will be
1366          * released on kfd process destroy. Set amdgpu pasid
1367          * to 0 to avoid duplicate release.
1368          */
1369         amdgpu_vm_release_compute(adev, avm);
1370 }
1371
1372 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1373 {
1374         struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1375         struct amdgpu_bo *pd = avm->root.base.bo;
1376         struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1377
1378         if (adev->asic_type < CHIP_VEGA10)
1379                 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1380         return avm->pd_phys_addr;
1381 }
1382
1383 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1384                 struct kgd_dev *kgd, uint64_t va, uint64_t size,
1385                 void *drm_priv, struct kgd_mem **mem,
1386                 uint64_t *offset, uint32_t flags)
1387 {
1388         struct amdgpu_device *adev = get_amdgpu_device(kgd);
1389         struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1390         enum ttm_bo_type bo_type = ttm_bo_type_device;
1391         struct sg_table *sg = NULL;
1392         uint64_t user_addr = 0;
1393         struct amdgpu_bo *bo;
1394         struct drm_gem_object *gobj;
1395         u32 domain, alloc_domain;
1396         u64 alloc_flags;
1397         int ret;
1398
1399         /*
1400          * Check on which domain to allocate BO
1401          */
1402         if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1403                 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1404                 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1405                 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1406                         AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED :
1407                         AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
1408         } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1409                 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1410                 alloc_flags = 0;
1411         } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1412                 domain = AMDGPU_GEM_DOMAIN_GTT;
1413                 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1414                 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1415                 if (!offset || !*offset)
1416                         return -EINVAL;
1417                 user_addr = untagged_addr(*offset);
1418         } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1419                         KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1420                 domain = AMDGPU_GEM_DOMAIN_GTT;
1421                 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1422                 bo_type = ttm_bo_type_sg;
1423                 alloc_flags = 0;
1424                 if (size > UINT_MAX)
1425                         return -EINVAL;
1426                 sg = create_doorbell_sg(*offset, size);
1427                 if (!sg)
1428                         return -ENOMEM;
1429         } else {
1430                 return -EINVAL;
1431         }
1432
1433         *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1434         if (!*mem) {
1435                 ret = -ENOMEM;
1436                 goto err;
1437         }
1438         INIT_LIST_HEAD(&(*mem)->attachments);
1439         mutex_init(&(*mem)->lock);
1440         (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1441
1442         /* Workaround for AQL queue wraparound bug. Map the same
1443          * memory twice. That means we only actually allocate half
1444          * the memory.
1445          */
1446         if ((*mem)->aql_queue)
1447                 size = size >> 1;
1448
1449         (*mem)->alloc_flags = flags;
1450
1451         amdgpu_sync_create(&(*mem)->sync);
1452
1453         ret = amdgpu_amdkfd_reserve_mem_limit(adev, size, alloc_domain, !!sg);
1454         if (ret) {
1455                 pr_debug("Insufficient memory\n");
1456                 goto err_reserve_limit;
1457         }
1458
1459         pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
1460                         va, size, domain_string(alloc_domain));
1461
1462         ret = amdgpu_gem_object_create(adev, size, 1, alloc_domain, alloc_flags,
1463                                        bo_type, NULL, &gobj);
1464         if (ret) {
1465                 pr_debug("Failed to create BO on domain %s. ret %d\n",
1466                          domain_string(alloc_domain), ret);
1467                 goto err_bo_create;
1468         }
1469         ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1470         if (ret) {
1471                 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1472                 goto err_node_allow;
1473         }
1474         bo = gem_to_amdgpu_bo(gobj);
1475         if (bo_type == ttm_bo_type_sg) {
1476                 bo->tbo.sg = sg;
1477                 bo->tbo.ttm->sg = sg;
1478         }
1479         bo->kfd_bo = *mem;
1480         (*mem)->bo = bo;
1481         if (user_addr)
1482                 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1483
1484         (*mem)->va = va;
1485         (*mem)->domain = domain;
1486         (*mem)->mapped_to_gpu_memory = 0;
1487         (*mem)->process_info = avm->process_info;
1488         add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1489
1490         if (user_addr) {
1491                 ret = init_user_pages(*mem, user_addr);
1492                 if (ret)
1493                         goto allocate_init_user_pages_failed;
1494         }
1495
1496         if (offset)
1497                 *offset = amdgpu_bo_mmap_offset(bo);
1498
1499         return 0;
1500
1501 allocate_init_user_pages_failed:
1502         remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1503         drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1504 err_node_allow:
1505         amdgpu_bo_unref(&bo);
1506         /* Don't unreserve system mem limit twice */
1507         goto err_reserve_limit;
1508 err_bo_create:
1509         unreserve_mem_limit(adev, size, alloc_domain, !!sg);
1510 err_reserve_limit:
1511         mutex_destroy(&(*mem)->lock);
1512         kfree(*mem);
1513 err:
1514         if (sg) {
1515                 sg_free_table(sg);
1516                 kfree(sg);
1517         }
1518         return ret;
1519 }
1520
1521 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1522                 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
1523                 uint64_t *size)
1524 {
1525         struct amdkfd_process_info *process_info = mem->process_info;
1526         unsigned long bo_size = mem->bo->tbo.base.size;
1527         struct kfd_mem_attachment *entry, *tmp;
1528         struct bo_vm_reservation_context ctx;
1529         struct ttm_validate_buffer *bo_list_entry;
1530         unsigned int mapped_to_gpu_memory;
1531         int ret;
1532         bool is_imported = false;
1533
1534         mutex_lock(&mem->lock);
1535         mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1536         is_imported = mem->is_imported;
1537         mutex_unlock(&mem->lock);
1538         /* lock is not needed after this, since mem is unused and will
1539          * be freed anyway
1540          */
1541
1542         if (mapped_to_gpu_memory > 0) {
1543                 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1544                                 mem->va, bo_size);
1545                 return -EBUSY;
1546         }
1547
1548         /* Make sure restore workers don't access the BO any more */
1549         bo_list_entry = &mem->validate_list;
1550         mutex_lock(&process_info->lock);
1551         list_del(&bo_list_entry->head);
1552         mutex_unlock(&process_info->lock);
1553
1554         /* No more MMU notifiers */
1555         amdgpu_mn_unregister(mem->bo);
1556
1557         ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1558         if (unlikely(ret))
1559                 return ret;
1560
1561         /* The eviction fence should be removed by the last unmap.
1562          * TODO: Log an error condition if the bo still has the eviction fence
1563          * attached
1564          */
1565         amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1566                                         process_info->eviction_fence);
1567         pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1568                 mem->va + bo_size * (1 + mem->aql_queue));
1569
1570         ret = unreserve_bo_and_vms(&ctx, false, false);
1571
1572         /* Remove from VM internal data structures */
1573         list_for_each_entry_safe(entry, tmp, &mem->attachments, list)
1574                 kfd_mem_detach(entry);
1575
1576         /* Free the sync object */
1577         amdgpu_sync_free(&mem->sync);
1578
1579         /* If the SG is not NULL, it's one we created for a doorbell or mmio
1580          * remap BO. We need to free it.
1581          */
1582         if (mem->bo->tbo.sg) {
1583                 sg_free_table(mem->bo->tbo.sg);
1584                 kfree(mem->bo->tbo.sg);
1585         }
1586
1587         /* Update the size of the BO being freed if it was allocated from
1588          * VRAM and is not imported.
1589          */
1590         if (size) {
1591                 if ((mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) &&
1592                     (!is_imported))
1593                         *size = bo_size;
1594                 else
1595                         *size = 0;
1596         }
1597
1598         /* Free the BO*/
1599         drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1600         if (mem->dmabuf)
1601                 dma_buf_put(mem->dmabuf);
1602         drm_gem_object_put(&mem->bo->tbo.base);
1603         mutex_destroy(&mem->lock);
1604         kfree(mem);
1605
1606         return ret;
1607 }
1608
1609 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1610                 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
1611 {
1612         struct amdgpu_device *adev = get_amdgpu_device(kgd);
1613         struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1614         int ret;
1615         struct amdgpu_bo *bo;
1616         uint32_t domain;
1617         struct kfd_mem_attachment *entry;
1618         struct bo_vm_reservation_context ctx;
1619         unsigned long bo_size;
1620         bool is_invalid_userptr = false;
1621
1622         bo = mem->bo;
1623         if (!bo) {
1624                 pr_err("Invalid BO when mapping memory to GPU\n");
1625                 return -EINVAL;
1626         }
1627
1628         /* Make sure restore is not running concurrently. Since we
1629          * don't map invalid userptr BOs, we rely on the next restore
1630          * worker to do the mapping
1631          */
1632         mutex_lock(&mem->process_info->lock);
1633
1634         /* Lock mmap-sem. If we find an invalid userptr BO, we can be
1635          * sure that the MMU notifier is no longer running
1636          * concurrently and the queues are actually stopped
1637          */
1638         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1639                 mmap_write_lock(current->mm);
1640                 is_invalid_userptr = atomic_read(&mem->invalid);
1641                 mmap_write_unlock(current->mm);
1642         }
1643
1644         mutex_lock(&mem->lock);
1645
1646         domain = mem->domain;
1647         bo_size = bo->tbo.base.size;
1648
1649         pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
1650                         mem->va,
1651                         mem->va + bo_size * (1 + mem->aql_queue),
1652                         avm, domain_string(domain));
1653
1654         if (!kfd_mem_is_attached(avm, mem)) {
1655                 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
1656                 if (ret)
1657                         goto out;
1658         }
1659
1660         ret = reserve_bo_and_vm(mem, avm, &ctx);
1661         if (unlikely(ret))
1662                 goto out;
1663
1664         /* Userptr can be marked as "not invalid", but not actually be
1665          * validated yet (still in the system domain). In that case
1666          * the queues are still stopped and we can leave mapping for
1667          * the next restore worker
1668          */
1669         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
1670             bo->tbo.mem.mem_type == TTM_PL_SYSTEM)
1671                 is_invalid_userptr = true;
1672
1673         ret = vm_validate_pt_pd_bos(avm);
1674         if (unlikely(ret))
1675                 goto out_unreserve;
1676
1677         if (mem->mapped_to_gpu_memory == 0 &&
1678             !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1679                 /* Validate BO only once. The eviction fence gets added to BO
1680                  * the first time it is mapped. Validate will wait for all
1681                  * background evictions to complete.
1682                  */
1683                 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
1684                 if (ret) {
1685                         pr_debug("Validate failed\n");
1686                         goto out_unreserve;
1687                 }
1688         }
1689
1690         list_for_each_entry(entry, &mem->attachments, list) {
1691                 if (entry->bo_va->base.vm != avm || entry->is_mapped)
1692                         continue;
1693
1694                 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
1695                          entry->va, entry->va + bo_size, entry);
1696
1697                 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
1698                                       is_invalid_userptr);
1699                 if (ret) {
1700                         pr_err("Failed to map bo to gpuvm\n");
1701                         goto out_unreserve;
1702                 }
1703
1704                 ret = vm_update_pds(avm, ctx.sync);
1705                 if (ret) {
1706                         pr_err("Failed to update page directories\n");
1707                         goto out_unreserve;
1708                 }
1709
1710                 entry->is_mapped = true;
1711                 mem->mapped_to_gpu_memory++;
1712                 pr_debug("\t INC mapping count %d\n",
1713                          mem->mapped_to_gpu_memory);
1714         }
1715
1716         if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
1717                 amdgpu_bo_fence(bo,
1718                                 &avm->process_info->eviction_fence->base,
1719                                 true);
1720         ret = unreserve_bo_and_vms(&ctx, false, false);
1721
1722         goto out;
1723
1724 out_unreserve:
1725         unreserve_bo_and_vms(&ctx, false, false);
1726 out:
1727         mutex_unlock(&mem->process_info->lock);
1728         mutex_unlock(&mem->lock);
1729         return ret;
1730 }
1731
1732 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1733                 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
1734 {
1735         struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1736         struct amdkfd_process_info *process_info = avm->process_info;
1737         unsigned long bo_size = mem->bo->tbo.base.size;
1738         struct kfd_mem_attachment *entry;
1739         struct bo_vm_reservation_context ctx;
1740         int ret;
1741
1742         mutex_lock(&mem->lock);
1743
1744         ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
1745         if (unlikely(ret))
1746                 goto out;
1747         /* If no VMs were reserved, it means the BO wasn't actually mapped */
1748         if (ctx.n_vms == 0) {
1749                 ret = -EINVAL;
1750                 goto unreserve_out;
1751         }
1752
1753         ret = vm_validate_pt_pd_bos(avm);
1754         if (unlikely(ret))
1755                 goto unreserve_out;
1756
1757         pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
1758                 mem->va,
1759                 mem->va + bo_size * (1 + mem->aql_queue),
1760                 avm);
1761
1762         list_for_each_entry(entry, &mem->attachments, list) {
1763                 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
1764                         continue;
1765
1766                 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
1767                          entry->va, entry->va + bo_size, entry);
1768
1769                 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
1770                 entry->is_mapped = false;
1771
1772                 mem->mapped_to_gpu_memory--;
1773                 pr_debug("\t DEC mapping count %d\n",
1774                          mem->mapped_to_gpu_memory);
1775         }
1776
1777         /* If BO is unmapped from all VMs, unfence it. It can be evicted if
1778          * required.
1779          */
1780         if (mem->mapped_to_gpu_memory == 0 &&
1781             !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
1782             !mem->bo->tbo.pin_count)
1783                 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1784                                                 process_info->eviction_fence);
1785
1786 unreserve_out:
1787         unreserve_bo_and_vms(&ctx, false, false);
1788 out:
1789         mutex_unlock(&mem->lock);
1790         return ret;
1791 }
1792
1793 int amdgpu_amdkfd_gpuvm_sync_memory(
1794                 struct kgd_dev *kgd, struct kgd_mem *mem, bool intr)
1795 {
1796         struct amdgpu_sync sync;
1797         int ret;
1798
1799         amdgpu_sync_create(&sync);
1800
1801         mutex_lock(&mem->lock);
1802         amdgpu_sync_clone(&mem->sync, &sync);
1803         mutex_unlock(&mem->lock);
1804
1805         ret = amdgpu_sync_wait(&sync, intr);
1806         amdgpu_sync_free(&sync);
1807         return ret;
1808 }
1809
1810 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
1811                 struct kgd_mem *mem, void **kptr, uint64_t *size)
1812 {
1813         int ret;
1814         struct amdgpu_bo *bo = mem->bo;
1815
1816         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1817                 pr_err("userptr can't be mapped to kernel\n");
1818                 return -EINVAL;
1819         }
1820
1821         /* delete kgd_mem from kfd_bo_list to avoid re-validating
1822          * this BO in BO's restoring after eviction.
1823          */
1824         mutex_lock(&mem->process_info->lock);
1825
1826         ret = amdgpu_bo_reserve(bo, true);
1827         if (ret) {
1828                 pr_err("Failed to reserve bo. ret %d\n", ret);
1829                 goto bo_reserve_failed;
1830         }
1831
1832         ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
1833         if (ret) {
1834                 pr_err("Failed to pin bo. ret %d\n", ret);
1835                 goto pin_failed;
1836         }
1837
1838         ret = amdgpu_bo_kmap(bo, kptr);
1839         if (ret) {
1840                 pr_err("Failed to map bo to kernel. ret %d\n", ret);
1841                 goto kmap_failed;
1842         }
1843
1844         amdgpu_amdkfd_remove_eviction_fence(
1845                 bo, mem->process_info->eviction_fence);
1846         list_del_init(&mem->validate_list.head);
1847
1848         if (size)
1849                 *size = amdgpu_bo_size(bo);
1850
1851         amdgpu_bo_unreserve(bo);
1852
1853         mutex_unlock(&mem->process_info->lock);
1854         return 0;
1855
1856 kmap_failed:
1857         amdgpu_bo_unpin(bo);
1858 pin_failed:
1859         amdgpu_bo_unreserve(bo);
1860 bo_reserve_failed:
1861         mutex_unlock(&mem->process_info->lock);
1862
1863         return ret;
1864 }
1865
1866 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
1867                                               struct kfd_vm_fault_info *mem)
1868 {
1869         struct amdgpu_device *adev;
1870
1871         adev = (struct amdgpu_device *)kgd;
1872         if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
1873                 *mem = *adev->gmc.vm_fault_info;
1874                 mb();
1875                 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1876         }
1877         return 0;
1878 }
1879
1880 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
1881                                       struct dma_buf *dma_buf,
1882                                       uint64_t va, void *drm_priv,
1883                                       struct kgd_mem **mem, uint64_t *size,
1884                                       uint64_t *mmap_offset)
1885 {
1886         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
1887         struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1888         struct drm_gem_object *obj;
1889         struct amdgpu_bo *bo;
1890         int ret;
1891
1892         if (dma_buf->ops != &amdgpu_dmabuf_ops)
1893                 /* Can't handle non-graphics buffers */
1894                 return -EINVAL;
1895
1896         obj = dma_buf->priv;
1897         if (drm_to_adev(obj->dev) != adev)
1898                 /* Can't handle buffers from other devices */
1899                 return -EINVAL;
1900
1901         bo = gem_to_amdgpu_bo(obj);
1902         if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
1903                                     AMDGPU_GEM_DOMAIN_GTT)))
1904                 /* Only VRAM and GTT BOs are supported */
1905                 return -EINVAL;
1906
1907         *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1908         if (!*mem)
1909                 return -ENOMEM;
1910
1911         ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
1912         if (ret) {
1913                 kfree(mem);
1914                 return ret;
1915         }
1916
1917         if (size)
1918                 *size = amdgpu_bo_size(bo);
1919
1920         if (mmap_offset)
1921                 *mmap_offset = amdgpu_bo_mmap_offset(bo);
1922
1923         INIT_LIST_HEAD(&(*mem)->attachments);
1924         mutex_init(&(*mem)->lock);
1925
1926         (*mem)->alloc_flags =
1927                 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
1928                 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
1929                 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
1930                 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
1931
1932         drm_gem_object_get(&bo->tbo.base);
1933         (*mem)->bo = bo;
1934         (*mem)->va = va;
1935         (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
1936                 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
1937         (*mem)->mapped_to_gpu_memory = 0;
1938         (*mem)->process_info = avm->process_info;
1939         add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
1940         amdgpu_sync_create(&(*mem)->sync);
1941         (*mem)->is_imported = true;
1942
1943         return 0;
1944 }
1945
1946 /* Evict a userptr BO by stopping the queues if necessary
1947  *
1948  * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
1949  * cannot do any memory allocations, and cannot take any locks that
1950  * are held elsewhere while allocating memory. Therefore this is as
1951  * simple as possible, using atomic counters.
1952  *
1953  * It doesn't do anything to the BO itself. The real work happens in
1954  * restore, where we get updated page addresses. This function only
1955  * ensures that GPU access to the BO is stopped.
1956  */
1957 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
1958                                 struct mm_struct *mm)
1959 {
1960         struct amdkfd_process_info *process_info = mem->process_info;
1961         int evicted_bos;
1962         int r = 0;
1963
1964         atomic_inc(&mem->invalid);
1965         evicted_bos = atomic_inc_return(&process_info->evicted_bos);
1966         if (evicted_bos == 1) {
1967                 /* First eviction, stop the queues */
1968                 r = kgd2kfd_quiesce_mm(mm);
1969                 if (r)
1970                         pr_err("Failed to quiesce KFD\n");
1971                 schedule_delayed_work(&process_info->restore_userptr_work,
1972                         msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
1973         }
1974
1975         return r;
1976 }
1977
1978 /* Update invalid userptr BOs
1979  *
1980  * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
1981  * userptr_inval_list and updates user pages for all BOs that have
1982  * been invalidated since their last update.
1983  */
1984 static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
1985                                      struct mm_struct *mm)
1986 {
1987         struct kgd_mem *mem, *tmp_mem;
1988         struct amdgpu_bo *bo;
1989         struct ttm_operation_ctx ctx = { false, false };
1990         int invalid, ret;
1991
1992         /* Move all invalidated BOs to the userptr_inval_list and
1993          * release their user pages by migration to the CPU domain
1994          */
1995         list_for_each_entry_safe(mem, tmp_mem,
1996                                  &process_info->userptr_valid_list,
1997                                  validate_list.head) {
1998                 if (!atomic_read(&mem->invalid))
1999                         continue; /* BO is still valid */
2000
2001                 bo = mem->bo;
2002
2003                 if (amdgpu_bo_reserve(bo, true))
2004                         return -EAGAIN;
2005                 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2006                 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2007                 amdgpu_bo_unreserve(bo);
2008                 if (ret) {
2009                         pr_err("%s: Failed to invalidate userptr BO\n",
2010                                __func__);
2011                         return -EAGAIN;
2012                 }
2013
2014                 list_move_tail(&mem->validate_list.head,
2015                                &process_info->userptr_inval_list);
2016         }
2017
2018         if (list_empty(&process_info->userptr_inval_list))
2019                 return 0; /* All evicted userptr BOs were freed */
2020
2021         /* Go through userptr_inval_list and update any invalid user_pages */
2022         list_for_each_entry(mem, &process_info->userptr_inval_list,
2023                             validate_list.head) {
2024                 invalid = atomic_read(&mem->invalid);
2025                 if (!invalid)
2026                         /* BO hasn't been invalidated since the last
2027                          * revalidation attempt. Keep its BO list.
2028                          */
2029                         continue;
2030
2031                 bo = mem->bo;
2032
2033                 /* Get updated user pages */
2034                 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
2035                 if (ret) {
2036                         pr_debug("%s: Failed to get user pages: %d\n",
2037                                 __func__, ret);
2038
2039                         /* Return error -EBUSY or -ENOMEM, retry restore */
2040                         return ret;
2041                 }
2042
2043                 /*
2044                  * FIXME: Cannot ignore the return code, must hold
2045                  * notifier_lock
2046                  */
2047                 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
2048
2049                 /* Mark the BO as valid unless it was invalidated
2050                  * again concurrently.
2051                  */
2052                 if (atomic_cmpxchg(&mem->invalid, invalid, 0) != invalid)
2053                         return -EAGAIN;
2054         }
2055
2056         return 0;
2057 }
2058
2059 /* Validate invalid userptr BOs
2060  *
2061  * Validates BOs on the userptr_inval_list, and moves them back to the
2062  * userptr_valid_list. Also updates GPUVM page tables with new page
2063  * addresses and waits for the page table updates to complete.
2064  */
2065 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2066 {
2067         struct amdgpu_bo_list_entry *pd_bo_list_entries;
2068         struct list_head resv_list, duplicates;
2069         struct ww_acquire_ctx ticket;
2070         struct amdgpu_sync sync;
2071
2072         struct amdgpu_vm *peer_vm;
2073         struct kgd_mem *mem, *tmp_mem;
2074         struct amdgpu_bo *bo;
2075         struct ttm_operation_ctx ctx = { false, false };
2076         int i, ret;
2077
2078         pd_bo_list_entries = kcalloc(process_info->n_vms,
2079                                      sizeof(struct amdgpu_bo_list_entry),
2080                                      GFP_KERNEL);
2081         if (!pd_bo_list_entries) {
2082                 pr_err("%s: Failed to allocate PD BO list entries\n", __func__);
2083                 ret = -ENOMEM;
2084                 goto out_no_mem;
2085         }
2086
2087         INIT_LIST_HEAD(&resv_list);
2088         INIT_LIST_HEAD(&duplicates);
2089
2090         /* Get all the page directory BOs that need to be reserved */
2091         i = 0;
2092         list_for_each_entry(peer_vm, &process_info->vm_list_head,
2093                             vm_list_node)
2094                 amdgpu_vm_get_pd_bo(peer_vm, &resv_list,
2095                                     &pd_bo_list_entries[i++]);
2096         /* Add the userptr_inval_list entries to resv_list */
2097         list_for_each_entry(mem, &process_info->userptr_inval_list,
2098                             validate_list.head) {
2099                 list_add_tail(&mem->resv_list.head, &resv_list);
2100                 mem->resv_list.bo = mem->validate_list.bo;
2101                 mem->resv_list.num_shared = mem->validate_list.num_shared;
2102         }
2103
2104         /* Reserve all BOs and page tables for validation */
2105         ret = ttm_eu_reserve_buffers(&ticket, &resv_list, false, &duplicates);
2106         WARN(!list_empty(&duplicates), "Duplicates should be empty");
2107         if (ret)
2108                 goto out_free;
2109
2110         amdgpu_sync_create(&sync);
2111
2112         ret = process_validate_vms(process_info);
2113         if (ret)
2114                 goto unreserve_out;
2115
2116         /* Validate BOs and update GPUVM page tables */
2117         list_for_each_entry_safe(mem, tmp_mem,
2118                                  &process_info->userptr_inval_list,
2119                                  validate_list.head) {
2120                 struct kfd_mem_attachment *attachment;
2121
2122                 bo = mem->bo;
2123
2124                 /* Validate the BO if we got user pages */
2125                 if (bo->tbo.ttm->pages[0]) {
2126                         amdgpu_bo_placement_from_domain(bo, mem->domain);
2127                         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2128                         if (ret) {
2129                                 pr_err("%s: failed to validate BO\n", __func__);
2130                                 goto unreserve_out;
2131                         }
2132                 }
2133
2134                 list_move_tail(&mem->validate_list.head,
2135                                &process_info->userptr_valid_list);
2136
2137                 /* Update mapping. If the BO was not validated
2138                  * (because we couldn't get user pages), this will
2139                  * clear the page table entries, which will result in
2140                  * VM faults if the GPU tries to access the invalid
2141                  * memory.
2142                  */
2143                 list_for_each_entry(attachment, &mem->attachments, list) {
2144                         if (!attachment->is_mapped)
2145                                 continue;
2146
2147                         kfd_mem_dmaunmap_attachment(mem, attachment);
2148                         ret = update_gpuvm_pte(mem, attachment, &sync);
2149                         if (ret) {
2150                                 pr_err("%s: update PTE failed\n", __func__);
2151                                 /* make sure this gets validated again */
2152                                 atomic_inc(&mem->invalid);
2153                                 goto unreserve_out;
2154                         }
2155                 }
2156         }
2157
2158         /* Update page directories */
2159         ret = process_update_pds(process_info, &sync);
2160
2161 unreserve_out:
2162         ttm_eu_backoff_reservation(&ticket, &resv_list);
2163         amdgpu_sync_wait(&sync, false);
2164         amdgpu_sync_free(&sync);
2165 out_free:
2166         kfree(pd_bo_list_entries);
2167 out_no_mem:
2168
2169         return ret;
2170 }
2171
2172 /* Worker callback to restore evicted userptr BOs
2173  *
2174  * Tries to update and validate all userptr BOs. If successful and no
2175  * concurrent evictions happened, the queues are restarted. Otherwise,
2176  * reschedule for another attempt later.
2177  */
2178 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2179 {
2180         struct delayed_work *dwork = to_delayed_work(work);
2181         struct amdkfd_process_info *process_info =
2182                 container_of(dwork, struct amdkfd_process_info,
2183                              restore_userptr_work);
2184         struct task_struct *usertask;
2185         struct mm_struct *mm;
2186         int evicted_bos;
2187
2188         evicted_bos = atomic_read(&process_info->evicted_bos);
2189         if (!evicted_bos)
2190                 return;
2191
2192         /* Reference task and mm in case of concurrent process termination */
2193         usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2194         if (!usertask)
2195                 return;
2196         mm = get_task_mm(usertask);
2197         if (!mm) {
2198                 put_task_struct(usertask);
2199                 return;
2200         }
2201
2202         mutex_lock(&process_info->lock);
2203
2204         if (update_invalid_user_pages(process_info, mm))
2205                 goto unlock_out;
2206         /* userptr_inval_list can be empty if all evicted userptr BOs
2207          * have been freed. In that case there is nothing to validate
2208          * and we can just restart the queues.
2209          */
2210         if (!list_empty(&process_info->userptr_inval_list)) {
2211                 if (atomic_read(&process_info->evicted_bos) != evicted_bos)
2212                         goto unlock_out; /* Concurrent eviction, try again */
2213
2214                 if (validate_invalid_user_pages(process_info))
2215                         goto unlock_out;
2216         }
2217         /* Final check for concurrent evicton and atomic update. If
2218          * another eviction happens after successful update, it will
2219          * be a first eviction that calls quiesce_mm. The eviction
2220          * reference counting inside KFD will handle this case.
2221          */
2222         if (atomic_cmpxchg(&process_info->evicted_bos, evicted_bos, 0) !=
2223             evicted_bos)
2224                 goto unlock_out;
2225         evicted_bos = 0;
2226         if (kgd2kfd_resume_mm(mm)) {
2227                 pr_err("%s: Failed to resume KFD\n", __func__);
2228                 /* No recovery from this failure. Probably the CP is
2229                  * hanging. No point trying again.
2230                  */
2231         }
2232
2233 unlock_out:
2234         mutex_unlock(&process_info->lock);
2235         mmput(mm);
2236         put_task_struct(usertask);
2237
2238         /* If validation failed, reschedule another attempt */
2239         if (evicted_bos)
2240                 schedule_delayed_work(&process_info->restore_userptr_work,
2241                         msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2242 }
2243
2244 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2245  *   KFD process identified by process_info
2246  *
2247  * @process_info: amdkfd_process_info of the KFD process
2248  *
2249  * After memory eviction, restore thread calls this function. The function
2250  * should be called when the Process is still valid. BO restore involves -
2251  *
2252  * 1.  Release old eviction fence and create new one
2253  * 2.  Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2254  * 3   Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2255  *     BOs that need to be reserved.
2256  * 4.  Reserve all the BOs
2257  * 5.  Validate of PD and PT BOs.
2258  * 6.  Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2259  * 7.  Add fence to all PD and PT BOs.
2260  * 8.  Unreserve all BOs
2261  */
2262 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
2263 {
2264         struct amdgpu_bo_list_entry *pd_bo_list;
2265         struct amdkfd_process_info *process_info = info;
2266         struct amdgpu_vm *peer_vm;
2267         struct kgd_mem *mem;
2268         struct bo_vm_reservation_context ctx;
2269         struct amdgpu_amdkfd_fence *new_fence;
2270         int ret = 0, i;
2271         struct list_head duplicate_save;
2272         struct amdgpu_sync sync_obj;
2273         unsigned long failed_size = 0;
2274         unsigned long total_size = 0;
2275
2276         INIT_LIST_HEAD(&duplicate_save);
2277         INIT_LIST_HEAD(&ctx.list);
2278         INIT_LIST_HEAD(&ctx.duplicates);
2279
2280         pd_bo_list = kcalloc(process_info->n_vms,
2281                              sizeof(struct amdgpu_bo_list_entry),
2282                              GFP_KERNEL);
2283         if (!pd_bo_list)
2284                 return -ENOMEM;
2285
2286         i = 0;
2287         mutex_lock(&process_info->lock);
2288         list_for_each_entry(peer_vm, &process_info->vm_list_head,
2289                         vm_list_node)
2290                 amdgpu_vm_get_pd_bo(peer_vm, &ctx.list, &pd_bo_list[i++]);
2291
2292         /* Reserve all BOs and page tables/directory. Add all BOs from
2293          * kfd_bo_list to ctx.list
2294          */
2295         list_for_each_entry(mem, &process_info->kfd_bo_list,
2296                             validate_list.head) {
2297
2298                 list_add_tail(&mem->resv_list.head, &ctx.list);
2299                 mem->resv_list.bo = mem->validate_list.bo;
2300                 mem->resv_list.num_shared = mem->validate_list.num_shared;
2301         }
2302
2303         ret = ttm_eu_reserve_buffers(&ctx.ticket, &ctx.list,
2304                                      false, &duplicate_save);
2305         if (ret) {
2306                 pr_debug("Memory eviction: TTM Reserve Failed. Try again\n");
2307                 goto ttm_reserve_fail;
2308         }
2309
2310         amdgpu_sync_create(&sync_obj);
2311
2312         /* Validate PDs and PTs */
2313         ret = process_validate_vms(process_info);
2314         if (ret)
2315                 goto validate_map_fail;
2316
2317         ret = process_sync_pds_resv(process_info, &sync_obj);
2318         if (ret) {
2319                 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2320                 goto validate_map_fail;
2321         }
2322
2323         /* Validate BOs and map them to GPUVM (update VM page tables). */
2324         list_for_each_entry(mem, &process_info->kfd_bo_list,
2325                             validate_list.head) {
2326
2327                 struct amdgpu_bo *bo = mem->bo;
2328                 uint32_t domain = mem->domain;
2329                 struct kfd_mem_attachment *attachment;
2330
2331                 total_size += amdgpu_bo_size(bo);
2332
2333                 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2334                 if (ret) {
2335                         pr_debug("Memory eviction: Validate BOs failed\n");
2336                         failed_size += amdgpu_bo_size(bo);
2337                         ret = amdgpu_amdkfd_bo_validate(bo,
2338                                                 AMDGPU_GEM_DOMAIN_GTT, false);
2339                         if (ret) {
2340                                 pr_debug("Memory eviction: Try again\n");
2341                                 goto validate_map_fail;
2342                         }
2343                 }
2344                 ret = amdgpu_sync_fence(&sync_obj, bo->tbo.moving);
2345                 if (ret) {
2346                         pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2347                         goto validate_map_fail;
2348                 }
2349                 list_for_each_entry(attachment, &mem->attachments, list) {
2350                         if (!attachment->is_mapped)
2351                                 continue;
2352
2353                         kfd_mem_dmaunmap_attachment(mem, attachment);
2354                         ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2355                         if (ret) {
2356                                 pr_debug("Memory eviction: update PTE failed. Try again\n");
2357                                 goto validate_map_fail;
2358                         }
2359                 }
2360         }
2361
2362         if (failed_size)
2363                 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2364
2365         /* Update page directories */
2366         ret = process_update_pds(process_info, &sync_obj);
2367         if (ret) {
2368                 pr_debug("Memory eviction: update PDs failed. Try again\n");
2369                 goto validate_map_fail;
2370         }
2371
2372         /* Wait for validate and PT updates to finish */
2373         amdgpu_sync_wait(&sync_obj, false);
2374
2375         /* Release old eviction fence and create new one, because fence only
2376          * goes from unsignaled to signaled, fence cannot be reused.
2377          * Use context and mm from the old fence.
2378          */
2379         new_fence = amdgpu_amdkfd_fence_create(
2380                                 process_info->eviction_fence->base.context,
2381                                 process_info->eviction_fence->mm,
2382                                 NULL);
2383         if (!new_fence) {
2384                 pr_err("Failed to create eviction fence\n");
2385                 ret = -ENOMEM;
2386                 goto validate_map_fail;
2387         }
2388         dma_fence_put(&process_info->eviction_fence->base);
2389         process_info->eviction_fence = new_fence;
2390         *ef = dma_fence_get(&new_fence->base);
2391
2392         /* Attach new eviction fence to all BOs */
2393         list_for_each_entry(mem, &process_info->kfd_bo_list,
2394                 validate_list.head)
2395                 amdgpu_bo_fence(mem->bo,
2396                         &process_info->eviction_fence->base, true);
2397
2398         /* Attach eviction fence to PD / PT BOs */
2399         list_for_each_entry(peer_vm, &process_info->vm_list_head,
2400                             vm_list_node) {
2401                 struct amdgpu_bo *bo = peer_vm->root.base.bo;
2402
2403                 amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true);
2404         }
2405
2406 validate_map_fail:
2407         ttm_eu_backoff_reservation(&ctx.ticket, &ctx.list);
2408         amdgpu_sync_free(&sync_obj);
2409 ttm_reserve_fail:
2410         mutex_unlock(&process_info->lock);
2411         kfree(pd_bo_list);
2412         return ret;
2413 }
2414
2415 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
2416 {
2417         struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2418         struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
2419         int ret;
2420
2421         if (!info || !gws)
2422                 return -EINVAL;
2423
2424         *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2425         if (!*mem)
2426                 return -ENOMEM;
2427
2428         mutex_init(&(*mem)->lock);
2429         INIT_LIST_HEAD(&(*mem)->attachments);
2430         (*mem)->bo = amdgpu_bo_ref(gws_bo);
2431         (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
2432         (*mem)->process_info = process_info;
2433         add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
2434         amdgpu_sync_create(&(*mem)->sync);
2435
2436
2437         /* Validate gws bo the first time it is added to process */
2438         mutex_lock(&(*mem)->process_info->lock);
2439         ret = amdgpu_bo_reserve(gws_bo, false);
2440         if (unlikely(ret)) {
2441                 pr_err("Reserve gws bo failed %d\n", ret);
2442                 goto bo_reservation_failure;
2443         }
2444
2445         ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
2446         if (ret) {
2447                 pr_err("GWS BO validate failed %d\n", ret);
2448                 goto bo_validation_failure;
2449         }
2450         /* GWS resource is shared b/t amdgpu and amdkfd
2451          * Add process eviction fence to bo so they can
2452          * evict each other.
2453          */
2454         ret = dma_resv_reserve_shared(gws_bo->tbo.base.resv, 1);
2455         if (ret)
2456                 goto reserve_shared_fail;
2457         amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true);
2458         amdgpu_bo_unreserve(gws_bo);
2459         mutex_unlock(&(*mem)->process_info->lock);
2460
2461         return ret;
2462
2463 reserve_shared_fail:
2464 bo_validation_failure:
2465         amdgpu_bo_unreserve(gws_bo);
2466 bo_reservation_failure:
2467         mutex_unlock(&(*mem)->process_info->lock);
2468         amdgpu_sync_free(&(*mem)->sync);
2469         remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
2470         amdgpu_bo_unref(&gws_bo);
2471         mutex_destroy(&(*mem)->lock);
2472         kfree(*mem);
2473         *mem = NULL;
2474         return ret;
2475 }
2476
2477 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
2478 {
2479         int ret;
2480         struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2481         struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
2482         struct amdgpu_bo *gws_bo = kgd_mem->bo;
2483
2484         /* Remove BO from process's validate list so restore worker won't touch
2485          * it anymore
2486          */
2487         remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
2488
2489         ret = amdgpu_bo_reserve(gws_bo, false);
2490         if (unlikely(ret)) {
2491                 pr_err("Reserve gws bo failed %d\n", ret);
2492                 //TODO add BO back to validate_list?
2493                 return ret;
2494         }
2495         amdgpu_amdkfd_remove_eviction_fence(gws_bo,
2496                         process_info->eviction_fence);
2497         amdgpu_bo_unreserve(gws_bo);
2498         amdgpu_sync_free(&kgd_mem->sync);
2499         amdgpu_bo_unref(&gws_bo);
2500         mutex_destroy(&kgd_mem->lock);
2501         kfree(mem);
2502         return 0;
2503 }
2504
2505 /* Returns GPU-specific tiling mode information */
2506 int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
2507                                 struct tile_config *config)
2508 {
2509         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
2510
2511         config->gb_addr_config = adev->gfx.config.gb_addr_config;
2512         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
2513         config->num_tile_configs =
2514                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2515         config->macro_tile_config_ptr =
2516                         adev->gfx.config.macrotile_mode_array;
2517         config->num_macro_tile_configs =
2518                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2519
2520         /* Those values are not set from GFX9 onwards */
2521         config->num_banks = adev->gfx.config.num_banks;
2522         config->num_ranks = adev->gfx.config.num_ranks;
2523
2524         return 0;
2525 }