2 * Copyright 2014-2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #include <linux/dma-buf.h>
23 #include <linux/list.h>
24 #include <linux/pagemap.h>
25 #include <linux/sched/mm.h>
26 #include <linux/sched/task.h>
28 #include "amdgpu_object.h"
29 #include "amdgpu_vm.h"
30 #include "amdgpu_amdkfd.h"
31 #include "amdgpu_dma_buf.h"
32 #include <uapi/linux/kfd_ioctl.h>
34 /* BO flag to indicate a KFD userptr BO */
35 #define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63)
37 /* Userptr restore delay, just long enough to allow consecutive VM
38 * changes to accumulate
40 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
42 /* Impose limit on how much memory KFD can use */
44 uint64_t max_system_mem_limit;
45 uint64_t max_ttm_mem_limit;
46 int64_t system_mem_used;
48 spinlock_t mem_limit_lock;
51 /* Struct used for amdgpu_amdkfd_bo_validate */
52 struct amdgpu_vm_parser {
57 static const char * const domain_bit_to_string[] = {
66 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
68 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
71 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
73 return (struct amdgpu_device *)kgd;
76 static bool check_if_add_bo_to_vm(struct amdgpu_vm *avm,
79 struct kfd_bo_va_list *entry;
81 list_for_each_entry(entry, &mem->bo_va_list, bo_list)
82 if (entry->bo_va->base.vm == avm)
88 /* Set memory usage limits. Current, limits are
89 * System (TTM + userptr) memory - 15/16th System RAM
90 * TTM memory - 3/8th System RAM
92 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
98 mem = si.totalram - si.totalhigh;
101 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
102 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
103 kfd_mem_limit.max_ttm_mem_limit = (mem >> 1) - (mem >> 3);
104 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
105 (kfd_mem_limit.max_system_mem_limit >> 20),
106 (kfd_mem_limit.max_ttm_mem_limit >> 20));
109 /* Estimate page table size needed to represent a given memory size
111 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
112 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
113 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
114 * for 2MB pages for TLB efficiency. However, small allocations and
115 * fragmented system memory still need some 4KB pages. We choose a
116 * compromise that should work in most cases without reserving too
117 * much memory for page tables unnecessarily (factor 16K, >> 14).
119 #define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)
121 static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
122 uint64_t size, u32 domain, bool sg)
124 uint64_t reserved_for_pt =
125 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
126 size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed;
129 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
130 sizeof(struct amdgpu_bo));
133 if (domain == AMDGPU_GEM_DOMAIN_GTT) {
135 system_mem_needed = acc_size + size;
136 ttm_mem_needed = acc_size + size;
137 } else if (domain == AMDGPU_GEM_DOMAIN_CPU && !sg) {
139 system_mem_needed = acc_size + size;
140 ttm_mem_needed = acc_size;
143 system_mem_needed = acc_size;
144 ttm_mem_needed = acc_size;
145 if (domain == AMDGPU_GEM_DOMAIN_VRAM)
149 spin_lock(&kfd_mem_limit.mem_limit_lock);
151 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
152 kfd_mem_limit.max_system_mem_limit) ||
153 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
154 kfd_mem_limit.max_ttm_mem_limit) ||
155 (adev->kfd.vram_used + vram_needed >
156 adev->gmc.real_vram_size - reserved_for_pt)) {
159 kfd_mem_limit.system_mem_used += system_mem_needed;
160 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
161 adev->kfd.vram_used += vram_needed;
164 spin_unlock(&kfd_mem_limit.mem_limit_lock);
168 static void unreserve_mem_limit(struct amdgpu_device *adev,
169 uint64_t size, u32 domain, bool sg)
173 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
174 sizeof(struct amdgpu_bo));
176 spin_lock(&kfd_mem_limit.mem_limit_lock);
177 if (domain == AMDGPU_GEM_DOMAIN_GTT) {
178 kfd_mem_limit.system_mem_used -= (acc_size + size);
179 kfd_mem_limit.ttm_mem_used -= (acc_size + size);
180 } else if (domain == AMDGPU_GEM_DOMAIN_CPU && !sg) {
181 kfd_mem_limit.system_mem_used -= (acc_size + size);
182 kfd_mem_limit.ttm_mem_used -= acc_size;
184 kfd_mem_limit.system_mem_used -= acc_size;
185 kfd_mem_limit.ttm_mem_used -= acc_size;
186 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
187 adev->kfd.vram_used -= size;
188 WARN_ONCE(adev->kfd.vram_used < 0,
189 "kfd VRAM memory accounting unbalanced");
192 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
193 "kfd system memory accounting unbalanced");
194 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
195 "kfd TTM memory accounting unbalanced");
197 spin_unlock(&kfd_mem_limit.mem_limit_lock);
200 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
202 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
203 u32 domain = bo->preferred_domains;
204 bool sg = (bo->preferred_domains == AMDGPU_GEM_DOMAIN_CPU);
206 if (bo->flags & AMDGPU_AMDKFD_USERPTR_BO) {
207 domain = AMDGPU_GEM_DOMAIN_CPU;
211 unreserve_mem_limit(adev, amdgpu_bo_size(bo), domain, sg);
215 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
216 * reservation object.
218 * @bo: [IN] Remove eviction fence(s) from this BO
219 * @ef: [IN] This eviction fence is removed if it
220 * is present in the shared list.
222 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
224 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
225 struct amdgpu_amdkfd_fence *ef)
227 struct dma_resv *resv = bo->tbo.base.resv;
228 struct dma_resv_list *old, *new;
229 unsigned int i, j, k;
234 old = dma_resv_get_list(resv);
238 new = kmalloc(offsetof(typeof(*new), shared[old->shared_max]),
243 /* Go through all the shared fences in the resevation object and sort
244 * the interesting ones to the end of the list.
246 for (i = 0, j = old->shared_count, k = 0; i < old->shared_count; ++i) {
249 f = rcu_dereference_protected(old->shared[i],
250 dma_resv_held(resv));
252 if (f->context == ef->base.context)
253 RCU_INIT_POINTER(new->shared[--j], f);
255 RCU_INIT_POINTER(new->shared[k++], f);
257 new->shared_max = old->shared_max;
258 new->shared_count = k;
260 /* Install the new fence list, seqcount provides the barriers */
262 write_seqcount_begin(&resv->seq);
263 RCU_INIT_POINTER(resv->fence, new);
264 write_seqcount_end(&resv->seq);
267 /* Drop the references to the removed fences or move them to ef_list */
268 for (i = j, k = 0; i < old->shared_count; ++i) {
271 f = rcu_dereference_protected(new->shared[i],
272 dma_resv_held(resv));
280 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
282 struct amdgpu_bo *root = bo;
283 struct amdgpu_vm_bo_base *vm_bo;
284 struct amdgpu_vm *vm;
285 struct amdkfd_process_info *info;
286 struct amdgpu_amdkfd_fence *ef;
289 /* we can always get vm_bo from root PD bo.*/
301 info = vm->process_info;
302 if (!info || !info->eviction_fence)
305 ef = container_of(dma_fence_get(&info->eviction_fence->base),
306 struct amdgpu_amdkfd_fence, base);
308 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
309 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
310 dma_resv_unlock(bo->tbo.base.resv);
312 dma_fence_put(&ef->base);
316 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
319 struct ttm_operation_ctx ctx = { false, false };
322 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
323 "Called with userptr BO"))
326 amdgpu_bo_placement_from_domain(bo, domain);
328 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
332 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
338 static int amdgpu_amdkfd_validate(void *param, struct amdgpu_bo *bo)
340 struct amdgpu_vm_parser *p = param;
342 return amdgpu_amdkfd_bo_validate(bo, p->domain, p->wait);
345 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
347 * Page directories are not updated here because huge page handling
348 * during page table updates can invalidate page directory entries
349 * again. Page directories are only updated after updating page
352 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
354 struct amdgpu_bo *pd = vm->root.base.bo;
355 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
356 struct amdgpu_vm_parser param;
359 param.domain = AMDGPU_GEM_DOMAIN_VRAM;
362 ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate,
365 pr_err("amdgpu: failed to validate PT BOs\n");
369 ret = amdgpu_amdkfd_validate(¶m, pd);
371 pr_err("amdgpu: failed to validate PD\n");
375 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
377 if (vm->use_cpu_for_update) {
378 ret = amdgpu_bo_kmap(pd, NULL);
380 pr_err("amdgpu: failed to kmap PD, ret=%d\n", ret);
388 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
390 struct amdgpu_bo *pd = vm->root.base.bo;
391 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
394 ret = amdgpu_vm_update_pdes(adev, vm, false);
398 return amdgpu_sync_fence(sync, vm->last_update, false);
401 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
403 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
404 bool coherent = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT;
405 uint32_t mapping_flags;
407 mapping_flags = AMDGPU_VM_PAGE_READABLE;
408 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
409 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
410 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
411 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
413 switch (adev->asic_type) {
415 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
417 mapping_flags |= coherent ?
418 AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
420 mapping_flags |= AMDGPU_VM_MTYPE_UC;
422 mapping_flags |= coherent ?
423 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
427 mapping_flags |= coherent ?
428 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
431 return amdgpu_gem_va_map_flags(adev, mapping_flags);
434 /* add_bo_to_vm - Add a BO to a VM
436 * Everything that needs to bo done only once when a BO is first added
437 * to a VM. It can later be mapped and unmapped many times without
438 * repeating these steps.
440 * 1. Allocate and initialize BO VA entry data structure
441 * 2. Add BO to the VM
442 * 3. Determine ASIC-specific PTE flags
443 * 4. Alloc page tables and directories if needed
444 * 4a. Validate new page tables and directories
446 static int add_bo_to_vm(struct amdgpu_device *adev, struct kgd_mem *mem,
447 struct amdgpu_vm *vm, bool is_aql,
448 struct kfd_bo_va_list **p_bo_va_entry)
451 struct kfd_bo_va_list *bo_va_entry;
452 struct amdgpu_bo *bo = mem->bo;
453 uint64_t va = mem->va;
454 struct list_head *list_bo_va = &mem->bo_va_list;
455 unsigned long bo_size = bo->tbo.mem.size;
458 pr_err("Invalid VA when adding BO to VM\n");
465 bo_va_entry = kzalloc(sizeof(*bo_va_entry), GFP_KERNEL);
469 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
472 /* Add BO to VM internal data structures*/
473 bo_va_entry->bo_va = amdgpu_vm_bo_add(adev, vm, bo);
474 if (!bo_va_entry->bo_va) {
476 pr_err("Failed to add BO object to VM. ret == %d\n",
481 bo_va_entry->va = va;
482 bo_va_entry->pte_flags = get_pte_flags(adev, mem);
483 bo_va_entry->kgd_dev = (void *)adev;
484 list_add(&bo_va_entry->bo_list, list_bo_va);
487 *p_bo_va_entry = bo_va_entry;
489 /* Allocate validate page tables if needed */
490 ret = vm_validate_pt_pd_bos(vm);
492 pr_err("validate_pt_pd_bos() failed\n");
499 amdgpu_vm_bo_rmv(adev, bo_va_entry->bo_va);
500 list_del(&bo_va_entry->bo_list);
506 static void remove_bo_from_vm(struct amdgpu_device *adev,
507 struct kfd_bo_va_list *entry, unsigned long size)
509 pr_debug("\t remove VA 0x%llx - 0x%llx in entry %p\n",
511 entry->va + size, entry);
512 amdgpu_vm_bo_rmv(adev, entry->bo_va);
513 list_del(&entry->bo_list);
517 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
518 struct amdkfd_process_info *process_info,
521 struct ttm_validate_buffer *entry = &mem->validate_list;
522 struct amdgpu_bo *bo = mem->bo;
524 INIT_LIST_HEAD(&entry->head);
525 entry->num_shared = 1;
526 entry->bo = &bo->tbo;
527 mutex_lock(&process_info->lock);
529 list_add_tail(&entry->head, &process_info->userptr_valid_list);
531 list_add_tail(&entry->head, &process_info->kfd_bo_list);
532 mutex_unlock(&process_info->lock);
535 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
536 struct amdkfd_process_info *process_info)
538 struct ttm_validate_buffer *bo_list_entry;
540 bo_list_entry = &mem->validate_list;
541 mutex_lock(&process_info->lock);
542 list_del(&bo_list_entry->head);
543 mutex_unlock(&process_info->lock);
546 /* Initializes user pages. It registers the MMU notifier and validates
547 * the userptr BO in the GTT domain.
549 * The BO must already be on the userptr_valid_list. Otherwise an
550 * eviction and restore may happen that leaves the new BO unmapped
551 * with the user mode queues running.
553 * Takes the process_info->lock to protect against concurrent restore
556 * Returns 0 for success, negative errno for errors.
558 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr)
560 struct amdkfd_process_info *process_info = mem->process_info;
561 struct amdgpu_bo *bo = mem->bo;
562 struct ttm_operation_ctx ctx = { true, false };
565 mutex_lock(&process_info->lock);
567 ret = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, user_addr, 0);
569 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
573 ret = amdgpu_mn_register(bo, user_addr);
575 pr_err("%s: Failed to register MMU notifier: %d\n",
580 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
582 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
586 ret = amdgpu_bo_reserve(bo, true);
588 pr_err("%s: Failed to reserve BO\n", __func__);
591 amdgpu_bo_placement_from_domain(bo, mem->domain);
592 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
594 pr_err("%s: failed to validate BO\n", __func__);
595 amdgpu_bo_unreserve(bo);
598 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
601 amdgpu_mn_unregister(bo);
603 mutex_unlock(&process_info->lock);
607 /* Reserving a BO and its page table BOs must happen atomically to
608 * avoid deadlocks. Some operations update multiple VMs at once. Track
609 * all the reservation info in a context structure. Optionally a sync
610 * object can track VM updates.
612 struct bo_vm_reservation_context {
613 struct amdgpu_bo_list_entry kfd_bo; /* BO list entry for the KFD BO */
614 unsigned int n_vms; /* Number of VMs reserved */
615 struct amdgpu_bo_list_entry *vm_pd; /* Array of VM BO list entries */
616 struct ww_acquire_ctx ticket; /* Reservation ticket */
617 struct list_head list, duplicates; /* BO lists */
618 struct amdgpu_sync *sync; /* Pointer to sync object */
619 bool reserved; /* Whether BOs are reserved */
623 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
624 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
625 BO_VM_ALL, /* Match all VMs a BO was added to */
629 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
630 * @mem: KFD BO structure.
631 * @vm: the VM to reserve.
632 * @ctx: the struct that will be used in unreserve_bo_and_vms().
634 static int reserve_bo_and_vm(struct kgd_mem *mem,
635 struct amdgpu_vm *vm,
636 struct bo_vm_reservation_context *ctx)
638 struct amdgpu_bo *bo = mem->bo;
643 ctx->reserved = false;
645 ctx->sync = &mem->sync;
647 INIT_LIST_HEAD(&ctx->list);
648 INIT_LIST_HEAD(&ctx->duplicates);
650 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd), GFP_KERNEL);
654 ctx->kfd_bo.priority = 0;
655 ctx->kfd_bo.tv.bo = &bo->tbo;
656 ctx->kfd_bo.tv.num_shared = 1;
657 list_add(&ctx->kfd_bo.tv.head, &ctx->list);
659 amdgpu_vm_get_pd_bo(vm, &ctx->list, &ctx->vm_pd[0]);
661 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
662 false, &ctx->duplicates);
664 ctx->reserved = true;
666 pr_err("Failed to reserve buffers in ttm\n");
675 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
676 * @mem: KFD BO structure.
677 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
678 * is used. Otherwise, a single VM associated with the BO.
679 * @map_type: the mapping status that will be used to filter the VMs.
680 * @ctx: the struct that will be used in unreserve_bo_and_vms().
682 * Returns 0 for success, negative for failure.
684 static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
685 struct amdgpu_vm *vm, enum bo_vm_match map_type,
686 struct bo_vm_reservation_context *ctx)
688 struct amdgpu_bo *bo = mem->bo;
689 struct kfd_bo_va_list *entry;
693 ctx->reserved = false;
696 ctx->sync = &mem->sync;
698 INIT_LIST_HEAD(&ctx->list);
699 INIT_LIST_HEAD(&ctx->duplicates);
701 list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
702 if ((vm && vm != entry->bo_va->base.vm) ||
703 (entry->is_mapped != map_type
704 && map_type != BO_VM_ALL))
710 if (ctx->n_vms != 0) {
711 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd),
717 ctx->kfd_bo.priority = 0;
718 ctx->kfd_bo.tv.bo = &bo->tbo;
719 ctx->kfd_bo.tv.num_shared = 1;
720 list_add(&ctx->kfd_bo.tv.head, &ctx->list);
723 list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
724 if ((vm && vm != entry->bo_va->base.vm) ||
725 (entry->is_mapped != map_type
726 && map_type != BO_VM_ALL))
729 amdgpu_vm_get_pd_bo(entry->bo_va->base.vm, &ctx->list,
734 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
735 false, &ctx->duplicates);
737 ctx->reserved = true;
739 pr_err("Failed to reserve buffers in ttm.\n");
750 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
751 * @ctx: Reservation context to unreserve
752 * @wait: Optionally wait for a sync object representing pending VM updates
753 * @intr: Whether the wait is interruptible
755 * Also frees any resources allocated in
756 * reserve_bo_and_(cond_)vm(s). Returns the status from
759 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
760 bool wait, bool intr)
765 ret = amdgpu_sync_wait(ctx->sync, intr);
768 ttm_eu_backoff_reservation(&ctx->ticket, &ctx->list);
773 ctx->reserved = false;
779 static int unmap_bo_from_gpuvm(struct amdgpu_device *adev,
780 struct kfd_bo_va_list *entry,
781 struct amdgpu_sync *sync)
783 struct amdgpu_bo_va *bo_va = entry->bo_va;
784 struct amdgpu_vm *vm = bo_va->base.vm;
786 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
788 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
790 amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
795 static int update_gpuvm_pte(struct amdgpu_device *adev,
796 struct kfd_bo_va_list *entry,
797 struct amdgpu_sync *sync)
800 struct amdgpu_bo_va *bo_va = entry->bo_va;
802 /* Update the page tables */
803 ret = amdgpu_vm_bo_update(adev, bo_va, false);
805 pr_err("amdgpu_vm_bo_update failed\n");
809 return amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
812 static int map_bo_to_gpuvm(struct amdgpu_device *adev,
813 struct kfd_bo_va_list *entry, struct amdgpu_sync *sync,
818 /* Set virtual address for the allocation */
819 ret = amdgpu_vm_bo_map(adev, entry->bo_va, entry->va, 0,
820 amdgpu_bo_size(entry->bo_va->base.bo),
823 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
831 ret = update_gpuvm_pte(adev, entry, sync);
833 pr_err("update_gpuvm_pte() failed\n");
834 goto update_gpuvm_pte_failed;
839 update_gpuvm_pte_failed:
840 unmap_bo_from_gpuvm(adev, entry, sync);
844 static struct sg_table *create_doorbell_sg(uint64_t addr, uint32_t size)
846 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
850 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
854 sg->sgl->dma_address = addr;
855 sg->sgl->length = size;
856 #ifdef CONFIG_NEED_SG_DMA_LENGTH
857 sg->sgl->dma_length = size;
862 static int process_validate_vms(struct amdkfd_process_info *process_info)
864 struct amdgpu_vm *peer_vm;
867 list_for_each_entry(peer_vm, &process_info->vm_list_head,
869 ret = vm_validate_pt_pd_bos(peer_vm);
877 static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
878 struct amdgpu_sync *sync)
880 struct amdgpu_vm *peer_vm;
883 list_for_each_entry(peer_vm, &process_info->vm_list_head,
885 struct amdgpu_bo *pd = peer_vm->root.base.bo;
887 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
888 AMDGPU_SYNC_NE_OWNER,
889 AMDGPU_FENCE_OWNER_KFD);
897 static int process_update_pds(struct amdkfd_process_info *process_info,
898 struct amdgpu_sync *sync)
900 struct amdgpu_vm *peer_vm;
903 list_for_each_entry(peer_vm, &process_info->vm_list_head,
905 ret = vm_update_pds(peer_vm, sync);
913 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
914 struct dma_fence **ef)
916 struct amdkfd_process_info *info = NULL;
919 if (!*process_info) {
920 info = kzalloc(sizeof(*info), GFP_KERNEL);
924 mutex_init(&info->lock);
925 INIT_LIST_HEAD(&info->vm_list_head);
926 INIT_LIST_HEAD(&info->kfd_bo_list);
927 INIT_LIST_HEAD(&info->userptr_valid_list);
928 INIT_LIST_HEAD(&info->userptr_inval_list);
930 info->eviction_fence =
931 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
933 if (!info->eviction_fence) {
934 pr_err("Failed to create eviction fence\n");
936 goto create_evict_fence_fail;
939 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
940 atomic_set(&info->evicted_bos, 0);
941 INIT_DELAYED_WORK(&info->restore_userptr_work,
942 amdgpu_amdkfd_restore_userptr_worker);
944 *process_info = info;
945 *ef = dma_fence_get(&info->eviction_fence->base);
948 vm->process_info = *process_info;
950 /* Validate page directory and attach eviction fence */
951 ret = amdgpu_bo_reserve(vm->root.base.bo, true);
953 goto reserve_pd_fail;
954 ret = vm_validate_pt_pd_bos(vm);
956 pr_err("validate_pt_pd_bos() failed\n");
957 goto validate_pd_fail;
959 ret = amdgpu_bo_sync_wait(vm->root.base.bo,
960 AMDGPU_FENCE_OWNER_KFD, false);
963 ret = dma_resv_reserve_shared(vm->root.base.bo->tbo.base.resv, 1);
965 goto reserve_shared_fail;
966 amdgpu_bo_fence(vm->root.base.bo,
967 &vm->process_info->eviction_fence->base, true);
968 amdgpu_bo_unreserve(vm->root.base.bo);
970 /* Update process info */
971 mutex_lock(&vm->process_info->lock);
972 list_add_tail(&vm->vm_list_node,
973 &(vm->process_info->vm_list_head));
974 vm->process_info->n_vms++;
975 mutex_unlock(&vm->process_info->lock);
982 amdgpu_bo_unreserve(vm->root.base.bo);
984 vm->process_info = NULL;
986 /* Two fence references: one in info and one in *ef */
987 dma_fence_put(&info->eviction_fence->base);
990 *process_info = NULL;
992 create_evict_fence_fail:
993 mutex_destroy(&info->lock);
999 int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, unsigned int pasid,
1000 void **vm, void **process_info,
1001 struct dma_fence **ef)
1003 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1004 struct amdgpu_vm *new_vm;
1007 new_vm = kzalloc(sizeof(*new_vm), GFP_KERNEL);
1011 /* Initialize AMDGPU part of the VM */
1012 ret = amdgpu_vm_init(adev, new_vm, AMDGPU_VM_CONTEXT_COMPUTE, pasid);
1014 pr_err("Failed init vm ret %d\n", ret);
1015 goto amdgpu_vm_init_fail;
1018 /* Initialize KFD part of the VM and process info */
1019 ret = init_kfd_vm(new_vm, process_info, ef);
1021 goto init_kfd_vm_fail;
1023 *vm = (void *) new_vm;
1028 amdgpu_vm_fini(adev, new_vm);
1029 amdgpu_vm_init_fail:
1034 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
1035 struct file *filp, unsigned int pasid,
1036 void **vm, void **process_info,
1037 struct dma_fence **ef)
1039 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1040 struct drm_file *drm_priv = filp->private_data;
1041 struct amdgpu_fpriv *drv_priv = drm_priv->driver_priv;
1042 struct amdgpu_vm *avm = &drv_priv->vm;
1045 /* Already a compute VM? */
1046 if (avm->process_info)
1049 /* Convert VM into a compute VM */
1050 ret = amdgpu_vm_make_compute(adev, avm, pasid);
1054 /* Initialize KFD part of the VM and process info */
1055 ret = init_kfd_vm(avm, process_info, ef);
1064 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1065 struct amdgpu_vm *vm)
1067 struct amdkfd_process_info *process_info = vm->process_info;
1068 struct amdgpu_bo *pd = vm->root.base.bo;
1073 /* Release eviction fence from PD */
1074 amdgpu_bo_reserve(pd, false);
1075 amdgpu_bo_fence(pd, NULL, false);
1076 amdgpu_bo_unreserve(pd);
1078 /* Update process info */
1079 mutex_lock(&process_info->lock);
1080 process_info->n_vms--;
1081 list_del(&vm->vm_list_node);
1082 mutex_unlock(&process_info->lock);
1084 vm->process_info = NULL;
1086 /* Release per-process resources when last compute VM is destroyed */
1087 if (!process_info->n_vms) {
1088 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1089 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1090 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1092 dma_fence_put(&process_info->eviction_fence->base);
1093 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1094 put_pid(process_info->pid);
1095 mutex_destroy(&process_info->lock);
1096 kfree(process_info);
1100 void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm)
1102 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1103 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1105 if (WARN_ON(!kgd || !vm))
1108 pr_debug("Destroying process vm %p\n", vm);
1110 /* Release the VM context */
1111 amdgpu_vm_fini(adev, avm);
1115 void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm)
1117 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1118 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1120 if (WARN_ON(!kgd || !vm))
1123 pr_debug("Releasing process vm %p\n", vm);
1125 /* The original pasid of amdgpu vm has already been
1126 * released during making a amdgpu vm to a compute vm
1127 * The current pasid is managed by kfd and will be
1128 * released on kfd process destroy. Set amdgpu pasid
1129 * to 0 to avoid duplicate release.
1131 amdgpu_vm_release_compute(adev, avm);
1134 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm)
1136 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1137 struct amdgpu_bo *pd = avm->root.base.bo;
1138 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1140 if (adev->asic_type < CHIP_VEGA10)
1141 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1142 return avm->pd_phys_addr;
1145 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1146 struct kgd_dev *kgd, uint64_t va, uint64_t size,
1147 void *vm, struct kgd_mem **mem,
1148 uint64_t *offset, uint32_t flags)
1150 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1151 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1152 enum ttm_bo_type bo_type = ttm_bo_type_device;
1153 struct sg_table *sg = NULL;
1154 uint64_t user_addr = 0;
1155 struct amdgpu_bo *bo;
1156 struct amdgpu_bo_param bp;
1157 u32 domain, alloc_domain;
1162 * Check on which domain to allocate BO
1164 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1165 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1166 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1167 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1168 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED :
1169 AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
1170 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1171 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1173 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1174 domain = AMDGPU_GEM_DOMAIN_GTT;
1175 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1177 if (!offset || !*offset)
1179 user_addr = untagged_addr(*offset);
1180 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1181 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1182 domain = AMDGPU_GEM_DOMAIN_GTT;
1183 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1184 bo_type = ttm_bo_type_sg;
1186 if (size > UINT_MAX)
1188 sg = create_doorbell_sg(*offset, size);
1195 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1200 INIT_LIST_HEAD(&(*mem)->bo_va_list);
1201 mutex_init(&(*mem)->lock);
1202 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1204 /* Workaround for AQL queue wraparound bug. Map the same
1205 * memory twice. That means we only actually allocate half
1208 if ((*mem)->aql_queue)
1211 (*mem)->alloc_flags = flags;
1213 amdgpu_sync_create(&(*mem)->sync);
1215 ret = amdgpu_amdkfd_reserve_mem_limit(adev, size, alloc_domain, !!sg);
1217 pr_debug("Insufficient system memory\n");
1218 goto err_reserve_limit;
1221 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
1222 va, size, domain_string(alloc_domain));
1224 memset(&bp, 0, sizeof(bp));
1227 bp.domain = alloc_domain;
1228 bp.flags = alloc_flags;
1231 ret = amdgpu_bo_create(adev, &bp, &bo);
1233 pr_debug("Failed to create BO on domain %s. ret %d\n",
1234 domain_string(alloc_domain), ret);
1237 if (bo_type == ttm_bo_type_sg) {
1239 bo->tbo.ttm->sg = sg;
1244 bo->flags |= AMDGPU_AMDKFD_USERPTR_BO;
1247 (*mem)->domain = domain;
1248 (*mem)->mapped_to_gpu_memory = 0;
1249 (*mem)->process_info = avm->process_info;
1250 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1253 ret = init_user_pages(*mem, user_addr);
1255 goto allocate_init_user_pages_failed;
1259 *offset = amdgpu_bo_mmap_offset(bo);
1263 allocate_init_user_pages_failed:
1264 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1265 amdgpu_bo_unref(&bo);
1266 /* Don't unreserve system mem limit twice */
1267 goto err_reserve_limit;
1269 unreserve_mem_limit(adev, size, alloc_domain, !!sg);
1271 mutex_destroy(&(*mem)->lock);
1281 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1282 struct kgd_dev *kgd, struct kgd_mem *mem)
1284 struct amdkfd_process_info *process_info = mem->process_info;
1285 unsigned long bo_size = mem->bo->tbo.mem.size;
1286 struct kfd_bo_va_list *entry, *tmp;
1287 struct bo_vm_reservation_context ctx;
1288 struct ttm_validate_buffer *bo_list_entry;
1291 mutex_lock(&mem->lock);
1293 if (mem->mapped_to_gpu_memory > 0) {
1294 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1296 mutex_unlock(&mem->lock);
1300 mutex_unlock(&mem->lock);
1301 /* lock is not needed after this, since mem is unused and will
1305 /* No more MMU notifiers */
1306 amdgpu_mn_unregister(mem->bo);
1308 /* Make sure restore workers don't access the BO any more */
1309 bo_list_entry = &mem->validate_list;
1310 mutex_lock(&process_info->lock);
1311 list_del(&bo_list_entry->head);
1312 mutex_unlock(&process_info->lock);
1314 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1318 /* The eviction fence should be removed by the last unmap.
1319 * TODO: Log an error condition if the bo still has the eviction fence
1322 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1323 process_info->eviction_fence);
1324 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1325 mem->va + bo_size * (1 + mem->aql_queue));
1327 /* Remove from VM internal data structures */
1328 list_for_each_entry_safe(entry, tmp, &mem->bo_va_list, bo_list)
1329 remove_bo_from_vm((struct amdgpu_device *)entry->kgd_dev,
1332 ret = unreserve_bo_and_vms(&ctx, false, false);
1334 /* Free the sync object */
1335 amdgpu_sync_free(&mem->sync);
1337 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1338 * remap BO. We need to free it.
1340 if (mem->bo->tbo.sg) {
1341 sg_free_table(mem->bo->tbo.sg);
1342 kfree(mem->bo->tbo.sg);
1346 amdgpu_bo_unref(&mem->bo);
1347 mutex_destroy(&mem->lock);
1353 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1354 struct kgd_dev *kgd, struct kgd_mem *mem, void *vm)
1356 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1357 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1359 struct amdgpu_bo *bo;
1361 struct kfd_bo_va_list *entry;
1362 struct bo_vm_reservation_context ctx;
1363 struct kfd_bo_va_list *bo_va_entry = NULL;
1364 struct kfd_bo_va_list *bo_va_entry_aql = NULL;
1365 unsigned long bo_size;
1366 bool is_invalid_userptr = false;
1370 pr_err("Invalid BO when mapping memory to GPU\n");
1374 /* Make sure restore is not running concurrently. Since we
1375 * don't map invalid userptr BOs, we rely on the next restore
1376 * worker to do the mapping
1378 mutex_lock(&mem->process_info->lock);
1380 /* Lock mmap-sem. If we find an invalid userptr BO, we can be
1381 * sure that the MMU notifier is no longer running
1382 * concurrently and the queues are actually stopped
1384 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1385 down_write(¤t->mm->mmap_sem);
1386 is_invalid_userptr = atomic_read(&mem->invalid);
1387 up_write(¤t->mm->mmap_sem);
1390 mutex_lock(&mem->lock);
1392 domain = mem->domain;
1393 bo_size = bo->tbo.mem.size;
1395 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
1397 mem->va + bo_size * (1 + mem->aql_queue),
1398 vm, domain_string(domain));
1400 ret = reserve_bo_and_vm(mem, vm, &ctx);
1404 /* Userptr can be marked as "not invalid", but not actually be
1405 * validated yet (still in the system domain). In that case
1406 * the queues are still stopped and we can leave mapping for
1407 * the next restore worker
1409 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
1410 bo->tbo.mem.mem_type == TTM_PL_SYSTEM)
1411 is_invalid_userptr = true;
1413 if (check_if_add_bo_to_vm(avm, mem)) {
1414 ret = add_bo_to_vm(adev, mem, avm, false,
1417 goto add_bo_to_vm_failed;
1418 if (mem->aql_queue) {
1419 ret = add_bo_to_vm(adev, mem, avm,
1420 true, &bo_va_entry_aql);
1422 goto add_bo_to_vm_failed_aql;
1425 ret = vm_validate_pt_pd_bos(avm);
1427 goto add_bo_to_vm_failed;
1430 if (mem->mapped_to_gpu_memory == 0 &&
1431 !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1432 /* Validate BO only once. The eviction fence gets added to BO
1433 * the first time it is mapped. Validate will wait for all
1434 * background evictions to complete.
1436 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
1438 pr_debug("Validate failed\n");
1439 goto map_bo_to_gpuvm_failed;
1443 list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
1444 if (entry->bo_va->base.vm == vm && !entry->is_mapped) {
1445 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
1446 entry->va, entry->va + bo_size,
1449 ret = map_bo_to_gpuvm(adev, entry, ctx.sync,
1450 is_invalid_userptr);
1452 pr_err("Failed to map bo to gpuvm\n");
1453 goto map_bo_to_gpuvm_failed;
1456 ret = vm_update_pds(vm, ctx.sync);
1458 pr_err("Failed to update page directories\n");
1459 goto map_bo_to_gpuvm_failed;
1462 entry->is_mapped = true;
1463 mem->mapped_to_gpu_memory++;
1464 pr_debug("\t INC mapping count %d\n",
1465 mem->mapped_to_gpu_memory);
1469 if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->pin_count)
1471 &avm->process_info->eviction_fence->base,
1473 ret = unreserve_bo_and_vms(&ctx, false, false);
1477 map_bo_to_gpuvm_failed:
1478 if (bo_va_entry_aql)
1479 remove_bo_from_vm(adev, bo_va_entry_aql, bo_size);
1480 add_bo_to_vm_failed_aql:
1482 remove_bo_from_vm(adev, bo_va_entry, bo_size);
1483 add_bo_to_vm_failed:
1484 unreserve_bo_and_vms(&ctx, false, false);
1486 mutex_unlock(&mem->process_info->lock);
1487 mutex_unlock(&mem->lock);
1491 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1492 struct kgd_dev *kgd, struct kgd_mem *mem, void *vm)
1494 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1495 struct amdkfd_process_info *process_info =
1496 ((struct amdgpu_vm *)vm)->process_info;
1497 unsigned long bo_size = mem->bo->tbo.mem.size;
1498 struct kfd_bo_va_list *entry;
1499 struct bo_vm_reservation_context ctx;
1502 mutex_lock(&mem->lock);
1504 ret = reserve_bo_and_cond_vms(mem, vm, BO_VM_MAPPED, &ctx);
1507 /* If no VMs were reserved, it means the BO wasn't actually mapped */
1508 if (ctx.n_vms == 0) {
1513 ret = vm_validate_pt_pd_bos((struct amdgpu_vm *)vm);
1517 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
1519 mem->va + bo_size * (1 + mem->aql_queue),
1522 list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
1523 if (entry->bo_va->base.vm == vm && entry->is_mapped) {
1524 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
1526 entry->va + bo_size,
1529 ret = unmap_bo_from_gpuvm(adev, entry, ctx.sync);
1531 entry->is_mapped = false;
1533 pr_err("failed to unmap VA 0x%llx\n",
1538 mem->mapped_to_gpu_memory--;
1539 pr_debug("\t DEC mapping count %d\n",
1540 mem->mapped_to_gpu_memory);
1544 /* If BO is unmapped from all VMs, unfence it. It can be evicted if
1547 if (mem->mapped_to_gpu_memory == 0 &&
1548 !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && !mem->bo->pin_count)
1549 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1550 process_info->eviction_fence);
1553 unreserve_bo_and_vms(&ctx, false, false);
1555 mutex_unlock(&mem->lock);
1559 int amdgpu_amdkfd_gpuvm_sync_memory(
1560 struct kgd_dev *kgd, struct kgd_mem *mem, bool intr)
1562 struct amdgpu_sync sync;
1565 amdgpu_sync_create(&sync);
1567 mutex_lock(&mem->lock);
1568 amdgpu_sync_clone(&mem->sync, &sync);
1569 mutex_unlock(&mem->lock);
1571 ret = amdgpu_sync_wait(&sync, intr);
1572 amdgpu_sync_free(&sync);
1576 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
1577 struct kgd_mem *mem, void **kptr, uint64_t *size)
1580 struct amdgpu_bo *bo = mem->bo;
1582 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1583 pr_err("userptr can't be mapped to kernel\n");
1587 /* delete kgd_mem from kfd_bo_list to avoid re-validating
1588 * this BO in BO's restoring after eviction.
1590 mutex_lock(&mem->process_info->lock);
1592 ret = amdgpu_bo_reserve(bo, true);
1594 pr_err("Failed to reserve bo. ret %d\n", ret);
1595 goto bo_reserve_failed;
1598 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
1600 pr_err("Failed to pin bo. ret %d\n", ret);
1604 ret = amdgpu_bo_kmap(bo, kptr);
1606 pr_err("Failed to map bo to kernel. ret %d\n", ret);
1610 amdgpu_amdkfd_remove_eviction_fence(
1611 bo, mem->process_info->eviction_fence);
1612 list_del_init(&mem->validate_list.head);
1615 *size = amdgpu_bo_size(bo);
1617 amdgpu_bo_unreserve(bo);
1619 mutex_unlock(&mem->process_info->lock);
1623 amdgpu_bo_unpin(bo);
1625 amdgpu_bo_unreserve(bo);
1627 mutex_unlock(&mem->process_info->lock);
1632 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
1633 struct kfd_vm_fault_info *mem)
1635 struct amdgpu_device *adev;
1637 adev = (struct amdgpu_device *)kgd;
1638 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
1639 *mem = *adev->gmc.vm_fault_info;
1641 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1646 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
1647 struct dma_buf *dma_buf,
1648 uint64_t va, void *vm,
1649 struct kgd_mem **mem, uint64_t *size,
1650 uint64_t *mmap_offset)
1652 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
1653 struct drm_gem_object *obj;
1654 struct amdgpu_bo *bo;
1655 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1657 if (dma_buf->ops != &amdgpu_dmabuf_ops)
1658 /* Can't handle non-graphics buffers */
1661 obj = dma_buf->priv;
1662 if (obj->dev->dev_private != adev)
1663 /* Can't handle buffers from other devices */
1666 bo = gem_to_amdgpu_bo(obj);
1667 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
1668 AMDGPU_GEM_DOMAIN_GTT)))
1669 /* Only VRAM and GTT BOs are supported */
1672 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1677 *size = amdgpu_bo_size(bo);
1680 *mmap_offset = amdgpu_bo_mmap_offset(bo);
1682 INIT_LIST_HEAD(&(*mem)->bo_va_list);
1683 mutex_init(&(*mem)->lock);
1685 (*mem)->alloc_flags =
1686 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
1687 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
1688 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
1689 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
1691 (*mem)->bo = amdgpu_bo_ref(bo);
1693 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
1694 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
1695 (*mem)->mapped_to_gpu_memory = 0;
1696 (*mem)->process_info = avm->process_info;
1697 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
1698 amdgpu_sync_create(&(*mem)->sync);
1703 /* Evict a userptr BO by stopping the queues if necessary
1705 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
1706 * cannot do any memory allocations, and cannot take any locks that
1707 * are held elsewhere while allocating memory. Therefore this is as
1708 * simple as possible, using atomic counters.
1710 * It doesn't do anything to the BO itself. The real work happens in
1711 * restore, where we get updated page addresses. This function only
1712 * ensures that GPU access to the BO is stopped.
1714 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
1715 struct mm_struct *mm)
1717 struct amdkfd_process_info *process_info = mem->process_info;
1721 atomic_inc(&mem->invalid);
1722 evicted_bos = atomic_inc_return(&process_info->evicted_bos);
1723 if (evicted_bos == 1) {
1724 /* First eviction, stop the queues */
1725 r = kgd2kfd_quiesce_mm(mm);
1727 pr_err("Failed to quiesce KFD\n");
1728 schedule_delayed_work(&process_info->restore_userptr_work,
1729 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
1735 /* Update invalid userptr BOs
1737 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
1738 * userptr_inval_list and updates user pages for all BOs that have
1739 * been invalidated since their last update.
1741 static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
1742 struct mm_struct *mm)
1744 struct kgd_mem *mem, *tmp_mem;
1745 struct amdgpu_bo *bo;
1746 struct ttm_operation_ctx ctx = { false, false };
1749 /* Move all invalidated BOs to the userptr_inval_list and
1750 * release their user pages by migration to the CPU domain
1752 list_for_each_entry_safe(mem, tmp_mem,
1753 &process_info->userptr_valid_list,
1754 validate_list.head) {
1755 if (!atomic_read(&mem->invalid))
1756 continue; /* BO is still valid */
1760 if (amdgpu_bo_reserve(bo, true))
1762 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
1763 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1764 amdgpu_bo_unreserve(bo);
1766 pr_err("%s: Failed to invalidate userptr BO\n",
1771 list_move_tail(&mem->validate_list.head,
1772 &process_info->userptr_inval_list);
1775 if (list_empty(&process_info->userptr_inval_list))
1776 return 0; /* All evicted userptr BOs were freed */
1778 /* Go through userptr_inval_list and update any invalid user_pages */
1779 list_for_each_entry(mem, &process_info->userptr_inval_list,
1780 validate_list.head) {
1781 invalid = atomic_read(&mem->invalid);
1783 /* BO hasn't been invalidated since the last
1784 * revalidation attempt. Keep its BO list.
1790 /* Get updated user pages */
1791 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
1793 pr_debug("%s: Failed to get user pages: %d\n",
1796 /* Return error -EBUSY or -ENOMEM, retry restore */
1801 * FIXME: Cannot ignore the return code, must hold
1804 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1806 /* Mark the BO as valid unless it was invalidated
1807 * again concurrently.
1809 if (atomic_cmpxchg(&mem->invalid, invalid, 0) != invalid)
1816 /* Validate invalid userptr BOs
1818 * Validates BOs on the userptr_inval_list, and moves them back to the
1819 * userptr_valid_list. Also updates GPUVM page tables with new page
1820 * addresses and waits for the page table updates to complete.
1822 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
1824 struct amdgpu_bo_list_entry *pd_bo_list_entries;
1825 struct list_head resv_list, duplicates;
1826 struct ww_acquire_ctx ticket;
1827 struct amdgpu_sync sync;
1829 struct amdgpu_vm *peer_vm;
1830 struct kgd_mem *mem, *tmp_mem;
1831 struct amdgpu_bo *bo;
1832 struct ttm_operation_ctx ctx = { false, false };
1835 pd_bo_list_entries = kcalloc(process_info->n_vms,
1836 sizeof(struct amdgpu_bo_list_entry),
1838 if (!pd_bo_list_entries) {
1839 pr_err("%s: Failed to allocate PD BO list entries\n", __func__);
1844 INIT_LIST_HEAD(&resv_list);
1845 INIT_LIST_HEAD(&duplicates);
1847 /* Get all the page directory BOs that need to be reserved */
1849 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1851 amdgpu_vm_get_pd_bo(peer_vm, &resv_list,
1852 &pd_bo_list_entries[i++]);
1853 /* Add the userptr_inval_list entries to resv_list */
1854 list_for_each_entry(mem, &process_info->userptr_inval_list,
1855 validate_list.head) {
1856 list_add_tail(&mem->resv_list.head, &resv_list);
1857 mem->resv_list.bo = mem->validate_list.bo;
1858 mem->resv_list.num_shared = mem->validate_list.num_shared;
1861 /* Reserve all BOs and page tables for validation */
1862 ret = ttm_eu_reserve_buffers(&ticket, &resv_list, false, &duplicates);
1863 WARN(!list_empty(&duplicates), "Duplicates should be empty");
1867 amdgpu_sync_create(&sync);
1869 ret = process_validate_vms(process_info);
1873 /* Validate BOs and update GPUVM page tables */
1874 list_for_each_entry_safe(mem, tmp_mem,
1875 &process_info->userptr_inval_list,
1876 validate_list.head) {
1877 struct kfd_bo_va_list *bo_va_entry;
1881 /* Validate the BO if we got user pages */
1882 if (bo->tbo.ttm->pages[0]) {
1883 amdgpu_bo_placement_from_domain(bo, mem->domain);
1884 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1886 pr_err("%s: failed to validate BO\n", __func__);
1891 list_move_tail(&mem->validate_list.head,
1892 &process_info->userptr_valid_list);
1894 /* Update mapping. If the BO was not validated
1895 * (because we couldn't get user pages), this will
1896 * clear the page table entries, which will result in
1897 * VM faults if the GPU tries to access the invalid
1900 list_for_each_entry(bo_va_entry, &mem->bo_va_list, bo_list) {
1901 if (!bo_va_entry->is_mapped)
1904 ret = update_gpuvm_pte((struct amdgpu_device *)
1905 bo_va_entry->kgd_dev,
1906 bo_va_entry, &sync);
1908 pr_err("%s: update PTE failed\n", __func__);
1909 /* make sure this gets validated again */
1910 atomic_inc(&mem->invalid);
1916 /* Update page directories */
1917 ret = process_update_pds(process_info, &sync);
1920 ttm_eu_backoff_reservation(&ticket, &resv_list);
1921 amdgpu_sync_wait(&sync, false);
1922 amdgpu_sync_free(&sync);
1924 kfree(pd_bo_list_entries);
1930 /* Worker callback to restore evicted userptr BOs
1932 * Tries to update and validate all userptr BOs. If successful and no
1933 * concurrent evictions happened, the queues are restarted. Otherwise,
1934 * reschedule for another attempt later.
1936 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
1938 struct delayed_work *dwork = to_delayed_work(work);
1939 struct amdkfd_process_info *process_info =
1940 container_of(dwork, struct amdkfd_process_info,
1941 restore_userptr_work);
1942 struct task_struct *usertask;
1943 struct mm_struct *mm;
1946 evicted_bos = atomic_read(&process_info->evicted_bos);
1950 /* Reference task and mm in case of concurrent process termination */
1951 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
1954 mm = get_task_mm(usertask);
1956 put_task_struct(usertask);
1960 mutex_lock(&process_info->lock);
1962 if (update_invalid_user_pages(process_info, mm))
1964 /* userptr_inval_list can be empty if all evicted userptr BOs
1965 * have been freed. In that case there is nothing to validate
1966 * and we can just restart the queues.
1968 if (!list_empty(&process_info->userptr_inval_list)) {
1969 if (atomic_read(&process_info->evicted_bos) != evicted_bos)
1970 goto unlock_out; /* Concurrent eviction, try again */
1972 if (validate_invalid_user_pages(process_info))
1975 /* Final check for concurrent evicton and atomic update. If
1976 * another eviction happens after successful update, it will
1977 * be a first eviction that calls quiesce_mm. The eviction
1978 * reference counting inside KFD will handle this case.
1980 if (atomic_cmpxchg(&process_info->evicted_bos, evicted_bos, 0) !=
1984 if (kgd2kfd_resume_mm(mm)) {
1985 pr_err("%s: Failed to resume KFD\n", __func__);
1986 /* No recovery from this failure. Probably the CP is
1987 * hanging. No point trying again.
1992 mutex_unlock(&process_info->lock);
1994 put_task_struct(usertask);
1996 /* If validation failed, reschedule another attempt */
1998 schedule_delayed_work(&process_info->restore_userptr_work,
1999 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2002 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2003 * KFD process identified by process_info
2005 * @process_info: amdkfd_process_info of the KFD process
2007 * After memory eviction, restore thread calls this function. The function
2008 * should be called when the Process is still valid. BO restore involves -
2010 * 1. Release old eviction fence and create new one
2011 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2012 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2013 * BOs that need to be reserved.
2014 * 4. Reserve all the BOs
2015 * 5. Validate of PD and PT BOs.
2016 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2017 * 7. Add fence to all PD and PT BOs.
2018 * 8. Unreserve all BOs
2020 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
2022 struct amdgpu_bo_list_entry *pd_bo_list;
2023 struct amdkfd_process_info *process_info = info;
2024 struct amdgpu_vm *peer_vm;
2025 struct kgd_mem *mem;
2026 struct bo_vm_reservation_context ctx;
2027 struct amdgpu_amdkfd_fence *new_fence;
2029 struct list_head duplicate_save;
2030 struct amdgpu_sync sync_obj;
2032 INIT_LIST_HEAD(&duplicate_save);
2033 INIT_LIST_HEAD(&ctx.list);
2034 INIT_LIST_HEAD(&ctx.duplicates);
2036 pd_bo_list = kcalloc(process_info->n_vms,
2037 sizeof(struct amdgpu_bo_list_entry),
2043 mutex_lock(&process_info->lock);
2044 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2046 amdgpu_vm_get_pd_bo(peer_vm, &ctx.list, &pd_bo_list[i++]);
2048 /* Reserve all BOs and page tables/directory. Add all BOs from
2049 * kfd_bo_list to ctx.list
2051 list_for_each_entry(mem, &process_info->kfd_bo_list,
2052 validate_list.head) {
2054 list_add_tail(&mem->resv_list.head, &ctx.list);
2055 mem->resv_list.bo = mem->validate_list.bo;
2056 mem->resv_list.num_shared = mem->validate_list.num_shared;
2059 ret = ttm_eu_reserve_buffers(&ctx.ticket, &ctx.list,
2060 false, &duplicate_save);
2062 pr_debug("Memory eviction: TTM Reserve Failed. Try again\n");
2063 goto ttm_reserve_fail;
2066 amdgpu_sync_create(&sync_obj);
2068 /* Validate PDs and PTs */
2069 ret = process_validate_vms(process_info);
2071 goto validate_map_fail;
2073 ret = process_sync_pds_resv(process_info, &sync_obj);
2075 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2076 goto validate_map_fail;
2079 /* Validate BOs and map them to GPUVM (update VM page tables). */
2080 list_for_each_entry(mem, &process_info->kfd_bo_list,
2081 validate_list.head) {
2083 struct amdgpu_bo *bo = mem->bo;
2084 uint32_t domain = mem->domain;
2085 struct kfd_bo_va_list *bo_va_entry;
2087 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2089 pr_debug("Memory eviction: Validate BOs failed. Try again\n");
2090 goto validate_map_fail;
2092 ret = amdgpu_sync_fence(&sync_obj, bo->tbo.moving, false);
2094 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2095 goto validate_map_fail;
2097 list_for_each_entry(bo_va_entry, &mem->bo_va_list,
2099 ret = update_gpuvm_pte((struct amdgpu_device *)
2100 bo_va_entry->kgd_dev,
2104 pr_debug("Memory eviction: update PTE failed. Try again\n");
2105 goto validate_map_fail;
2110 /* Update page directories */
2111 ret = process_update_pds(process_info, &sync_obj);
2113 pr_debug("Memory eviction: update PDs failed. Try again\n");
2114 goto validate_map_fail;
2117 /* Wait for validate and PT updates to finish */
2118 amdgpu_sync_wait(&sync_obj, false);
2120 /* Release old eviction fence and create new one, because fence only
2121 * goes from unsignaled to signaled, fence cannot be reused.
2122 * Use context and mm from the old fence.
2124 new_fence = amdgpu_amdkfd_fence_create(
2125 process_info->eviction_fence->base.context,
2126 process_info->eviction_fence->mm);
2128 pr_err("Failed to create eviction fence\n");
2130 goto validate_map_fail;
2132 dma_fence_put(&process_info->eviction_fence->base);
2133 process_info->eviction_fence = new_fence;
2134 *ef = dma_fence_get(&new_fence->base);
2136 /* Attach new eviction fence to all BOs */
2137 list_for_each_entry(mem, &process_info->kfd_bo_list,
2139 amdgpu_bo_fence(mem->bo,
2140 &process_info->eviction_fence->base, true);
2142 /* Attach eviction fence to PD / PT BOs */
2143 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2145 struct amdgpu_bo *bo = peer_vm->root.base.bo;
2147 amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true);
2151 ttm_eu_backoff_reservation(&ctx.ticket, &ctx.list);
2152 amdgpu_sync_free(&sync_obj);
2154 mutex_unlock(&process_info->lock);
2159 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
2161 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2162 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
2168 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2172 mutex_init(&(*mem)->lock);
2173 INIT_LIST_HEAD(&(*mem)->bo_va_list);
2174 (*mem)->bo = amdgpu_bo_ref(gws_bo);
2175 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
2176 (*mem)->process_info = process_info;
2177 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
2178 amdgpu_sync_create(&(*mem)->sync);
2181 /* Validate gws bo the first time it is added to process */
2182 mutex_lock(&(*mem)->process_info->lock);
2183 ret = amdgpu_bo_reserve(gws_bo, false);
2184 if (unlikely(ret)) {
2185 pr_err("Reserve gws bo failed %d\n", ret);
2186 goto bo_reservation_failure;
2189 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
2191 pr_err("GWS BO validate failed %d\n", ret);
2192 goto bo_validation_failure;
2194 /* GWS resource is shared b/t amdgpu and amdkfd
2195 * Add process eviction fence to bo so they can
2198 ret = dma_resv_reserve_shared(gws_bo->tbo.base.resv, 1);
2200 goto reserve_shared_fail;
2201 amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true);
2202 amdgpu_bo_unreserve(gws_bo);
2203 mutex_unlock(&(*mem)->process_info->lock);
2207 reserve_shared_fail:
2208 bo_validation_failure:
2209 amdgpu_bo_unreserve(gws_bo);
2210 bo_reservation_failure:
2211 mutex_unlock(&(*mem)->process_info->lock);
2212 amdgpu_sync_free(&(*mem)->sync);
2213 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
2214 amdgpu_bo_unref(&gws_bo);
2215 mutex_destroy(&(*mem)->lock);
2221 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
2224 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2225 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
2226 struct amdgpu_bo *gws_bo = kgd_mem->bo;
2228 /* Remove BO from process's validate list so restore worker won't touch
2231 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
2233 ret = amdgpu_bo_reserve(gws_bo, false);
2234 if (unlikely(ret)) {
2235 pr_err("Reserve gws bo failed %d\n", ret);
2236 //TODO add BO back to validate_list?
2239 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
2240 process_info->eviction_fence);
2241 amdgpu_bo_unreserve(gws_bo);
2242 amdgpu_sync_free(&kgd_mem->sync);
2243 amdgpu_bo_unref(&gws_bo);
2244 mutex_destroy(&kgd_mem->lock);
2249 /* Returns GPU-specific tiling mode information */
2250 int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
2251 struct tile_config *config)
2253 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
2255 config->gb_addr_config = adev->gfx.config.gb_addr_config;
2256 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
2257 config->num_tile_configs =
2258 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2259 config->macro_tile_config_ptr =
2260 adev->gfx.config.macrotile_mode_array;
2261 config->num_macro_tile_configs =
2262 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2264 /* Those values are not set from GFX9 onwards */
2265 config->num_banks = adev->gfx.config.num_banks;
2266 config->num_ranks = adev->gfx.config.num_ranks;