2 * Copyright 2014-2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #include <linux/dma-buf.h>
23 #include <linux/list.h>
24 #include <linux/pagemap.h>
25 #include <linux/sched/mm.h>
26 #include <linux/sched/task.h>
28 #include "amdgpu_object.h"
29 #include "amdgpu_gem.h"
30 #include "amdgpu_vm.h"
31 #include "amdgpu_amdkfd.h"
32 #include "amdgpu_dma_buf.h"
33 #include <uapi/linux/kfd_ioctl.h>
34 #include "amdgpu_xgmi.h"
36 /* Userptr restore delay, just long enough to allow consecutive VM
37 * changes to accumulate
39 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
41 /* Impose limit on how much memory KFD can use */
43 uint64_t max_system_mem_limit;
44 uint64_t max_ttm_mem_limit;
45 int64_t system_mem_used;
47 spinlock_t mem_limit_lock;
50 static const char * const domain_bit_to_string[] = {
59 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
61 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
63 static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
66 struct kfd_mem_attachment *entry;
68 list_for_each_entry(entry, &mem->attachments, list)
69 if (entry->bo_va->base.vm == avm)
75 /* Set memory usage limits. Current, limits are
76 * System (TTM + userptr) memory - 15/16th System RAM
77 * TTM memory - 3/8th System RAM
79 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
85 mem = si.freeram - si.freehigh;
88 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
89 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
90 kfd_mem_limit.max_ttm_mem_limit = (mem >> 1) - (mem >> 3);
91 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
92 (kfd_mem_limit.max_system_mem_limit >> 20),
93 (kfd_mem_limit.max_ttm_mem_limit >> 20));
96 void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
98 kfd_mem_limit.system_mem_used += size;
101 /* Estimate page table size needed to represent a given memory size
103 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
104 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
105 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
106 * for 2MB pages for TLB efficiency. However, small allocations and
107 * fragmented system memory still need some 4KB pages. We choose a
108 * compromise that should work in most cases without reserving too
109 * much memory for page tables unnecessarily (factor 16K, >> 14).
111 #define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)
113 static size_t amdgpu_amdkfd_acc_size(uint64_t size)
116 size *= sizeof(dma_addr_t) + sizeof(void *);
118 return __roundup_pow_of_two(sizeof(struct amdgpu_bo)) +
119 __roundup_pow_of_two(sizeof(struct ttm_tt)) +
124 * @amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
125 * of buffer including any reserved for control structures
127 * @adev: Device to which allocated BO belongs to
128 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
129 * equivalent to amdgpu_bo_size(BO)
130 * @alloc_flag: Flag used in allocating a BO as noted above
132 * Return: returns -ENOMEM in case of error, ZERO otherwise
134 static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
135 uint64_t size, u32 alloc_flag)
137 uint64_t reserved_for_pt =
138 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
139 size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed;
142 acc_size = amdgpu_amdkfd_acc_size(size);
145 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
146 system_mem_needed = acc_size + size;
147 ttm_mem_needed = acc_size + size;
148 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
149 system_mem_needed = acc_size;
150 ttm_mem_needed = acc_size;
152 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
153 system_mem_needed = acc_size + size;
154 ttm_mem_needed = acc_size;
155 } else if (alloc_flag &
156 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
157 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
158 system_mem_needed = acc_size;
159 ttm_mem_needed = acc_size;
161 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
165 spin_lock(&kfd_mem_limit.mem_limit_lock);
167 if (kfd_mem_limit.system_mem_used + system_mem_needed >
168 kfd_mem_limit.max_system_mem_limit)
169 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
171 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
172 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
173 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
174 kfd_mem_limit.max_ttm_mem_limit) ||
175 (adev->kfd.vram_used + vram_needed >
176 adev->gmc.real_vram_size - reserved_for_pt)) {
181 /* Update memory accounting by decreasing available system
182 * memory, TTM memory and GPU memory as computed above
184 adev->kfd.vram_used += vram_needed;
185 kfd_mem_limit.system_mem_used += system_mem_needed;
186 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
189 spin_unlock(&kfd_mem_limit.mem_limit_lock);
193 static void unreserve_mem_limit(struct amdgpu_device *adev,
194 uint64_t size, u32 alloc_flag)
198 acc_size = amdgpu_amdkfd_acc_size(size);
200 spin_lock(&kfd_mem_limit.mem_limit_lock);
202 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
203 kfd_mem_limit.system_mem_used -= (acc_size + size);
204 kfd_mem_limit.ttm_mem_used -= (acc_size + size);
205 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
206 kfd_mem_limit.system_mem_used -= acc_size;
207 kfd_mem_limit.ttm_mem_used -= acc_size;
208 adev->kfd.vram_used -= size;
209 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
210 kfd_mem_limit.system_mem_used -= (acc_size + size);
211 kfd_mem_limit.ttm_mem_used -= acc_size;
212 } else if (alloc_flag &
213 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
214 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
215 kfd_mem_limit.system_mem_used -= acc_size;
216 kfd_mem_limit.ttm_mem_used -= acc_size;
218 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
222 WARN_ONCE(adev->kfd.vram_used < 0,
223 "KFD VRAM memory accounting unbalanced");
224 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
225 "KFD TTM memory accounting unbalanced");
226 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
227 "KFD system memory accounting unbalanced");
230 spin_unlock(&kfd_mem_limit.mem_limit_lock);
233 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
235 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
236 u32 alloc_flags = bo->kfd_bo->alloc_flags;
237 u64 size = amdgpu_bo_size(bo);
239 unreserve_mem_limit(adev, size, alloc_flags);
244 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
245 * reservation object.
247 * @bo: [IN] Remove eviction fence(s) from this BO
248 * @ef: [IN] This eviction fence is removed if it
249 * is present in the shared list.
251 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
253 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
254 struct amdgpu_amdkfd_fence *ef)
256 struct dma_resv *resv = bo->tbo.base.resv;
257 struct dma_resv_list *old, *new;
258 unsigned int i, j, k;
263 old = dma_resv_shared_list(resv);
267 new = kmalloc(struct_size(new, shared, old->shared_max), GFP_KERNEL);
271 /* Go through all the shared fences in the resevation object and sort
272 * the interesting ones to the end of the list.
274 for (i = 0, j = old->shared_count, k = 0; i < old->shared_count; ++i) {
277 f = rcu_dereference_protected(old->shared[i],
278 dma_resv_held(resv));
280 if (f->context == ef->base.context)
281 RCU_INIT_POINTER(new->shared[--j], f);
283 RCU_INIT_POINTER(new->shared[k++], f);
285 new->shared_max = old->shared_max;
286 new->shared_count = k;
288 /* Install the new fence list, seqcount provides the barriers */
289 write_seqcount_begin(&resv->seq);
290 RCU_INIT_POINTER(resv->fence, new);
291 write_seqcount_end(&resv->seq);
293 /* Drop the references to the removed fences or move them to ef_list */
294 for (i = j; i < old->shared_count; ++i) {
297 f = rcu_dereference_protected(new->shared[i],
298 dma_resv_held(resv));
306 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
308 struct amdgpu_bo *root = bo;
309 struct amdgpu_vm_bo_base *vm_bo;
310 struct amdgpu_vm *vm;
311 struct amdkfd_process_info *info;
312 struct amdgpu_amdkfd_fence *ef;
315 /* we can always get vm_bo from root PD bo.*/
327 info = vm->process_info;
328 if (!info || !info->eviction_fence)
331 ef = container_of(dma_fence_get(&info->eviction_fence->base),
332 struct amdgpu_amdkfd_fence, base);
334 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
335 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
336 dma_resv_unlock(bo->tbo.base.resv);
338 dma_fence_put(&ef->base);
342 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
345 struct ttm_operation_ctx ctx = { false, false };
348 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
349 "Called with userptr BO"))
352 amdgpu_bo_placement_from_domain(bo, domain);
354 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
358 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
364 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
366 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
369 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
371 * Page directories are not updated here because huge page handling
372 * during page table updates can invalidate page directory entries
373 * again. Page directories are only updated after updating page
376 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
378 struct amdgpu_bo *pd = vm->root.bo;
379 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
382 ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
384 pr_err("failed to validate PT BOs\n");
388 ret = amdgpu_amdkfd_validate_vm_bo(NULL, pd);
390 pr_err("failed to validate PD\n");
394 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
396 if (vm->use_cpu_for_update) {
397 ret = amdgpu_bo_kmap(pd, NULL);
399 pr_err("failed to kmap PD, ret=%d\n", ret);
407 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
409 struct amdgpu_bo *pd = vm->root.bo;
410 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
413 ret = amdgpu_vm_update_pdes(adev, vm, false);
417 return amdgpu_sync_fence(sync, vm->last_update);
420 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
422 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
423 bool coherent = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT;
424 bool uncached = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED;
425 uint32_t mapping_flags;
429 mapping_flags = AMDGPU_VM_PAGE_READABLE;
430 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
431 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
432 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
433 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
435 switch (adev->asic_type) {
437 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
439 mapping_flags |= coherent ?
440 AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
442 mapping_flags |= coherent ?
443 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
445 mapping_flags |= coherent ?
446 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
450 if (coherent && uncached) {
451 if (adev->gmc.xgmi.connected_to_cpu ||
452 !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM))
454 mapping_flags |= AMDGPU_VM_MTYPE_UC;
455 } else if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
456 if (bo_adev == adev) {
457 mapping_flags |= coherent ?
458 AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
459 if (adev->gmc.xgmi.connected_to_cpu)
462 mapping_flags |= coherent ?
463 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
464 if (amdgpu_xgmi_same_hive(adev, bo_adev))
469 mapping_flags |= coherent ?
470 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
474 mapping_flags |= coherent ?
475 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
478 pte_flags = amdgpu_gem_va_map_flags(adev, mapping_flags);
479 pte_flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
485 kfd_mem_dmamap_userptr(struct kgd_mem *mem,
486 struct kfd_mem_attachment *attachment)
488 enum dma_data_direction direction =
489 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
490 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
491 struct ttm_operation_ctx ctx = {.interruptible = true};
492 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
493 struct amdgpu_device *adev = attachment->adev;
494 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
495 struct ttm_tt *ttm = bo->tbo.ttm;
498 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
499 if (unlikely(!ttm->sg))
502 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
505 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
506 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
508 (u64)ttm->num_pages << PAGE_SHIFT,
513 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
517 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm->dma_address,
520 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
521 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
528 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
530 pr_err("DMA map userptr failed: %d\n", ret);
531 sg_free_table(ttm->sg);
539 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
541 struct ttm_operation_ctx ctx = {.interruptible = true};
542 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
544 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
545 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
549 kfd_mem_dmamap_attachment(struct kgd_mem *mem,
550 struct kfd_mem_attachment *attachment)
552 switch (attachment->type) {
553 case KFD_MEM_ATT_SHARED:
555 case KFD_MEM_ATT_USERPTR:
556 return kfd_mem_dmamap_userptr(mem, attachment);
557 case KFD_MEM_ATT_DMABUF:
558 return kfd_mem_dmamap_dmabuf(attachment);
566 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
567 struct kfd_mem_attachment *attachment)
569 enum dma_data_direction direction =
570 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
571 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
572 struct ttm_operation_ctx ctx = {.interruptible = false};
573 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
574 struct amdgpu_device *adev = attachment->adev;
575 struct ttm_tt *ttm = bo->tbo.ttm;
577 if (unlikely(!ttm->sg))
580 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
581 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
583 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
584 sg_free_table(ttm->sg);
590 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
592 struct ttm_operation_ctx ctx = {.interruptible = true};
593 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
595 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
596 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
600 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
601 struct kfd_mem_attachment *attachment)
603 switch (attachment->type) {
604 case KFD_MEM_ATT_SHARED:
606 case KFD_MEM_ATT_USERPTR:
607 kfd_mem_dmaunmap_userptr(mem, attachment);
609 case KFD_MEM_ATT_DMABUF:
610 kfd_mem_dmaunmap_dmabuf(attachment);
618 kfd_mem_attach_userptr(struct amdgpu_device *adev, struct kgd_mem *mem,
619 struct amdgpu_bo **bo)
621 unsigned long bo_size = mem->bo->tbo.base.size;
622 struct drm_gem_object *gobj;
625 ret = amdgpu_bo_reserve(mem->bo, false);
629 ret = amdgpu_gem_object_create(adev, bo_size, 1,
630 AMDGPU_GEM_DOMAIN_CPU,
631 AMDGPU_GEM_CREATE_PREEMPTIBLE,
632 ttm_bo_type_sg, mem->bo->tbo.base.resv,
634 amdgpu_bo_unreserve(mem->bo);
638 *bo = gem_to_amdgpu_bo(gobj);
639 (*bo)->parent = amdgpu_bo_ref(mem->bo);
645 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
646 struct amdgpu_bo **bo)
648 struct drm_gem_object *gobj;
652 mem->dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base,
653 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
655 if (IS_ERR(mem->dmabuf)) {
656 ret = PTR_ERR(mem->dmabuf);
662 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
664 return PTR_ERR(gobj);
666 *bo = gem_to_amdgpu_bo(gobj);
667 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
668 (*bo)->parent = amdgpu_bo_ref(mem->bo);
673 /* kfd_mem_attach - Add a BO to a VM
675 * Everything that needs to bo done only once when a BO is first added
676 * to a VM. It can later be mapped and unmapped many times without
677 * repeating these steps.
679 * 0. Create BO for DMA mapping, if needed
680 * 1. Allocate and initialize BO VA entry data structure
681 * 2. Add BO to the VM
682 * 3. Determine ASIC-specific PTE flags
683 * 4. Alloc page tables and directories if needed
684 * 4a. Validate new page tables and directories
686 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
687 struct amdgpu_vm *vm, bool is_aql)
689 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
690 unsigned long bo_size = mem->bo->tbo.base.size;
691 uint64_t va = mem->va;
692 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
693 struct amdgpu_bo *bo[2] = {NULL, NULL};
697 pr_err("Invalid VA when adding BO to VM\n");
701 for (i = 0; i <= is_aql; i++) {
702 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
703 if (unlikely(!attachment[i])) {
708 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
711 if (adev == bo_adev || (mem->domain == AMDGPU_GEM_DOMAIN_VRAM &&
712 amdgpu_xgmi_same_hive(adev, bo_adev))) {
713 /* Mappings on the local GPU and VRAM mappings in the
714 * local hive share the original BO
716 attachment[i]->type = KFD_MEM_ATT_SHARED;
718 drm_gem_object_get(&bo[i]->tbo.base);
720 /* Multiple mappings on the same GPU share the BO */
721 attachment[i]->type = KFD_MEM_ATT_SHARED;
723 drm_gem_object_get(&bo[i]->tbo.base);
724 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
725 /* Create an SG BO to DMA-map userptrs on other GPUs */
726 attachment[i]->type = KFD_MEM_ATT_USERPTR;
727 ret = kfd_mem_attach_userptr(adev, mem, &bo[i]);
730 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT &&
731 mem->bo->tbo.type != ttm_bo_type_sg) {
732 /* GTT BOs use DMA-mapping ability of dynamic-attach
733 * DMA bufs. TODO: The same should work for VRAM on
736 attachment[i]->type = KFD_MEM_ATT_DMABUF;
737 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
741 /* FIXME: Need to DMA-map other BO types:
742 * large-BAR VRAM, doorbells, MMIO remap
744 attachment[i]->type = KFD_MEM_ATT_SHARED;
746 drm_gem_object_get(&bo[i]->tbo.base);
749 /* Add BO to VM internal data structures */
750 ret = amdgpu_bo_reserve(bo[i], false);
752 pr_debug("Unable to reserve BO during memory attach");
755 attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
756 amdgpu_bo_unreserve(bo[i]);
757 if (unlikely(!attachment[i]->bo_va)) {
759 pr_err("Failed to add BO object to VM. ret == %d\n",
763 attachment[i]->va = va;
764 attachment[i]->pte_flags = get_pte_flags(adev, mem);
765 attachment[i]->adev = adev;
766 list_add(&attachment[i]->list, &mem->attachments);
774 for (; i >= 0; i--) {
777 if (attachment[i]->bo_va) {
778 amdgpu_bo_reserve(bo[i], true);
779 amdgpu_vm_bo_rmv(adev, attachment[i]->bo_va);
780 amdgpu_bo_unreserve(bo[i]);
781 list_del(&attachment[i]->list);
784 drm_gem_object_put(&bo[i]->tbo.base);
785 kfree(attachment[i]);
790 static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
792 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
794 pr_debug("\t remove VA 0x%llx in entry %p\n",
795 attachment->va, attachment);
796 amdgpu_vm_bo_rmv(attachment->adev, attachment->bo_va);
797 drm_gem_object_put(&bo->tbo.base);
798 list_del(&attachment->list);
802 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
803 struct amdkfd_process_info *process_info,
806 struct ttm_validate_buffer *entry = &mem->validate_list;
807 struct amdgpu_bo *bo = mem->bo;
809 INIT_LIST_HEAD(&entry->head);
810 entry->num_shared = 1;
811 entry->bo = &bo->tbo;
812 mutex_lock(&process_info->lock);
814 list_add_tail(&entry->head, &process_info->userptr_valid_list);
816 list_add_tail(&entry->head, &process_info->kfd_bo_list);
817 mutex_unlock(&process_info->lock);
820 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
821 struct amdkfd_process_info *process_info)
823 struct ttm_validate_buffer *bo_list_entry;
825 bo_list_entry = &mem->validate_list;
826 mutex_lock(&process_info->lock);
827 list_del(&bo_list_entry->head);
828 mutex_unlock(&process_info->lock);
831 /* Initializes user pages. It registers the MMU notifier and validates
832 * the userptr BO in the GTT domain.
834 * The BO must already be on the userptr_valid_list. Otherwise an
835 * eviction and restore may happen that leaves the new BO unmapped
836 * with the user mode queues running.
838 * Takes the process_info->lock to protect against concurrent restore
841 * Returns 0 for success, negative errno for errors.
843 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr)
845 struct amdkfd_process_info *process_info = mem->process_info;
846 struct amdgpu_bo *bo = mem->bo;
847 struct ttm_operation_ctx ctx = { true, false };
850 mutex_lock(&process_info->lock);
852 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
854 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
858 ret = amdgpu_mn_register(bo, user_addr);
860 pr_err("%s: Failed to register MMU notifier: %d\n",
865 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
867 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
871 ret = amdgpu_bo_reserve(bo, true);
873 pr_err("%s: Failed to reserve BO\n", __func__);
876 amdgpu_bo_placement_from_domain(bo, mem->domain);
877 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
879 pr_err("%s: failed to validate BO\n", __func__);
880 amdgpu_bo_unreserve(bo);
883 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
886 amdgpu_mn_unregister(bo);
888 mutex_unlock(&process_info->lock);
892 /* Reserving a BO and its page table BOs must happen atomically to
893 * avoid deadlocks. Some operations update multiple VMs at once. Track
894 * all the reservation info in a context structure. Optionally a sync
895 * object can track VM updates.
897 struct bo_vm_reservation_context {
898 struct amdgpu_bo_list_entry kfd_bo; /* BO list entry for the KFD BO */
899 unsigned int n_vms; /* Number of VMs reserved */
900 struct amdgpu_bo_list_entry *vm_pd; /* Array of VM BO list entries */
901 struct ww_acquire_ctx ticket; /* Reservation ticket */
902 struct list_head list, duplicates; /* BO lists */
903 struct amdgpu_sync *sync; /* Pointer to sync object */
904 bool reserved; /* Whether BOs are reserved */
908 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
909 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
910 BO_VM_ALL, /* Match all VMs a BO was added to */
914 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
915 * @mem: KFD BO structure.
916 * @vm: the VM to reserve.
917 * @ctx: the struct that will be used in unreserve_bo_and_vms().
919 static int reserve_bo_and_vm(struct kgd_mem *mem,
920 struct amdgpu_vm *vm,
921 struct bo_vm_reservation_context *ctx)
923 struct amdgpu_bo *bo = mem->bo;
928 ctx->reserved = false;
930 ctx->sync = &mem->sync;
932 INIT_LIST_HEAD(&ctx->list);
933 INIT_LIST_HEAD(&ctx->duplicates);
935 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd), GFP_KERNEL);
939 ctx->kfd_bo.priority = 0;
940 ctx->kfd_bo.tv.bo = &bo->tbo;
941 ctx->kfd_bo.tv.num_shared = 1;
942 list_add(&ctx->kfd_bo.tv.head, &ctx->list);
944 amdgpu_vm_get_pd_bo(vm, &ctx->list, &ctx->vm_pd[0]);
946 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
947 false, &ctx->duplicates);
949 pr_err("Failed to reserve buffers in ttm.\n");
955 ctx->reserved = true;
960 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
961 * @mem: KFD BO structure.
962 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
963 * is used. Otherwise, a single VM associated with the BO.
964 * @map_type: the mapping status that will be used to filter the VMs.
965 * @ctx: the struct that will be used in unreserve_bo_and_vms().
967 * Returns 0 for success, negative for failure.
969 static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
970 struct amdgpu_vm *vm, enum bo_vm_match map_type,
971 struct bo_vm_reservation_context *ctx)
973 struct amdgpu_bo *bo = mem->bo;
974 struct kfd_mem_attachment *entry;
978 ctx->reserved = false;
981 ctx->sync = &mem->sync;
983 INIT_LIST_HEAD(&ctx->list);
984 INIT_LIST_HEAD(&ctx->duplicates);
986 list_for_each_entry(entry, &mem->attachments, list) {
987 if ((vm && vm != entry->bo_va->base.vm) ||
988 (entry->is_mapped != map_type
989 && map_type != BO_VM_ALL))
995 if (ctx->n_vms != 0) {
996 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd),
1002 ctx->kfd_bo.priority = 0;
1003 ctx->kfd_bo.tv.bo = &bo->tbo;
1004 ctx->kfd_bo.tv.num_shared = 1;
1005 list_add(&ctx->kfd_bo.tv.head, &ctx->list);
1008 list_for_each_entry(entry, &mem->attachments, list) {
1009 if ((vm && vm != entry->bo_va->base.vm) ||
1010 (entry->is_mapped != map_type
1011 && map_type != BO_VM_ALL))
1014 amdgpu_vm_get_pd_bo(entry->bo_va->base.vm, &ctx->list,
1019 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
1020 false, &ctx->duplicates);
1022 pr_err("Failed to reserve buffers in ttm.\n");
1028 ctx->reserved = true;
1033 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1034 * @ctx: Reservation context to unreserve
1035 * @wait: Optionally wait for a sync object representing pending VM updates
1036 * @intr: Whether the wait is interruptible
1038 * Also frees any resources allocated in
1039 * reserve_bo_and_(cond_)vm(s). Returns the status from
1042 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1043 bool wait, bool intr)
1048 ret = amdgpu_sync_wait(ctx->sync, intr);
1051 ttm_eu_backoff_reservation(&ctx->ticket, &ctx->list);
1056 ctx->reserved = false;
1062 static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1063 struct kfd_mem_attachment *entry,
1064 struct amdgpu_sync *sync)
1066 struct amdgpu_bo_va *bo_va = entry->bo_va;
1067 struct amdgpu_device *adev = entry->adev;
1068 struct amdgpu_vm *vm = bo_va->base.vm;
1070 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1072 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1074 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1076 kfd_mem_dmaunmap_attachment(mem, entry);
1079 static int update_gpuvm_pte(struct kgd_mem *mem,
1080 struct kfd_mem_attachment *entry,
1081 struct amdgpu_sync *sync,
1084 struct amdgpu_bo_va *bo_va = entry->bo_va;
1085 struct amdgpu_device *adev = entry->adev;
1088 ret = kfd_mem_dmamap_attachment(mem, entry);
1092 /* Update the page tables */
1093 ret = amdgpu_vm_bo_update(adev, bo_va, false, table_freed);
1095 pr_err("amdgpu_vm_bo_update failed\n");
1099 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1102 static int map_bo_to_gpuvm(struct kgd_mem *mem,
1103 struct kfd_mem_attachment *entry,
1104 struct amdgpu_sync *sync,
1110 /* Set virtual address for the allocation */
1111 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1112 amdgpu_bo_size(entry->bo_va->base.bo),
1115 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1123 ret = update_gpuvm_pte(mem, entry, sync, table_freed);
1125 pr_err("update_gpuvm_pte() failed\n");
1126 goto update_gpuvm_pte_failed;
1131 update_gpuvm_pte_failed:
1132 unmap_bo_from_gpuvm(mem, entry, sync);
1136 static struct sg_table *create_doorbell_sg(uint64_t addr, uint32_t size)
1138 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
1142 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
1146 sg->sgl->dma_address = addr;
1147 sg->sgl->length = size;
1148 #ifdef CONFIG_NEED_SG_DMA_LENGTH
1149 sg->sgl->dma_length = size;
1154 static int process_validate_vms(struct amdkfd_process_info *process_info)
1156 struct amdgpu_vm *peer_vm;
1159 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1161 ret = vm_validate_pt_pd_bos(peer_vm);
1169 static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1170 struct amdgpu_sync *sync)
1172 struct amdgpu_vm *peer_vm;
1175 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1177 struct amdgpu_bo *pd = peer_vm->root.bo;
1179 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1180 AMDGPU_SYNC_NE_OWNER,
1181 AMDGPU_FENCE_OWNER_KFD);
1189 static int process_update_pds(struct amdkfd_process_info *process_info,
1190 struct amdgpu_sync *sync)
1192 struct amdgpu_vm *peer_vm;
1195 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1197 ret = vm_update_pds(peer_vm, sync);
1205 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1206 struct dma_fence **ef)
1208 struct amdkfd_process_info *info = NULL;
1211 if (!*process_info) {
1212 info = kzalloc(sizeof(*info), GFP_KERNEL);
1216 mutex_init(&info->lock);
1217 INIT_LIST_HEAD(&info->vm_list_head);
1218 INIT_LIST_HEAD(&info->kfd_bo_list);
1219 INIT_LIST_HEAD(&info->userptr_valid_list);
1220 INIT_LIST_HEAD(&info->userptr_inval_list);
1222 info->eviction_fence =
1223 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1226 if (!info->eviction_fence) {
1227 pr_err("Failed to create eviction fence\n");
1229 goto create_evict_fence_fail;
1232 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1233 atomic_set(&info->evicted_bos, 0);
1234 INIT_DELAYED_WORK(&info->restore_userptr_work,
1235 amdgpu_amdkfd_restore_userptr_worker);
1237 *process_info = info;
1238 *ef = dma_fence_get(&info->eviction_fence->base);
1241 vm->process_info = *process_info;
1243 /* Validate page directory and attach eviction fence */
1244 ret = amdgpu_bo_reserve(vm->root.bo, true);
1246 goto reserve_pd_fail;
1247 ret = vm_validate_pt_pd_bos(vm);
1249 pr_err("validate_pt_pd_bos() failed\n");
1250 goto validate_pd_fail;
1252 ret = amdgpu_bo_sync_wait(vm->root.bo,
1253 AMDGPU_FENCE_OWNER_KFD, false);
1256 ret = dma_resv_reserve_shared(vm->root.bo->tbo.base.resv, 1);
1258 goto reserve_shared_fail;
1259 amdgpu_bo_fence(vm->root.bo,
1260 &vm->process_info->eviction_fence->base, true);
1261 amdgpu_bo_unreserve(vm->root.bo);
1263 /* Update process info */
1264 mutex_lock(&vm->process_info->lock);
1265 list_add_tail(&vm->vm_list_node,
1266 &(vm->process_info->vm_list_head));
1267 vm->process_info->n_vms++;
1268 mutex_unlock(&vm->process_info->lock);
1272 reserve_shared_fail:
1275 amdgpu_bo_unreserve(vm->root.bo);
1277 vm->process_info = NULL;
1279 /* Two fence references: one in info and one in *ef */
1280 dma_fence_put(&info->eviction_fence->base);
1283 *process_info = NULL;
1285 create_evict_fence_fail:
1286 mutex_destroy(&info->lock);
1293 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1294 * @bo: Handle of buffer object being pinned
1295 * @domain: Domain into which BO should be pinned
1297 * - USERPTR BOs are UNPINNABLE and will return error
1298 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1299 * PIN count incremented. It is valid to PIN a BO multiple times
1301 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1303 static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1307 ret = amdgpu_bo_reserve(bo, false);
1311 ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1313 pr_err("Error in Pinning BO to domain: %d\n", domain);
1315 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1316 amdgpu_bo_unreserve(bo);
1322 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1323 * @bo: Handle of buffer object being unpinned
1325 * - Is a illegal request for USERPTR BOs and is ignored
1326 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1327 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1329 static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1333 ret = amdgpu_bo_reserve(bo, false);
1337 amdgpu_bo_unpin(bo);
1338 amdgpu_bo_unreserve(bo);
1341 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1342 struct file *filp, u32 pasid,
1343 void **process_info,
1344 struct dma_fence **ef)
1346 struct amdgpu_fpriv *drv_priv;
1347 struct amdgpu_vm *avm;
1350 ret = amdgpu_file_to_fpriv(filp, &drv_priv);
1353 avm = &drv_priv->vm;
1355 /* Already a compute VM? */
1356 if (avm->process_info)
1359 /* Free the original amdgpu allocated pasid,
1360 * will be replaced with kfd allocated pasid.
1363 amdgpu_pasid_free(avm->pasid);
1364 amdgpu_vm_set_pasid(adev, avm, 0);
1367 /* Convert VM into a compute VM */
1368 ret = amdgpu_vm_make_compute(adev, avm);
1372 ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1375 /* Initialize KFD part of the VM and process info */
1376 ret = init_kfd_vm(avm, process_info, ef);
1380 amdgpu_vm_set_task_info(avm);
1385 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1386 struct amdgpu_vm *vm)
1388 struct amdkfd_process_info *process_info = vm->process_info;
1389 struct amdgpu_bo *pd = vm->root.bo;
1394 /* Release eviction fence from PD */
1395 amdgpu_bo_reserve(pd, false);
1396 amdgpu_bo_fence(pd, NULL, false);
1397 amdgpu_bo_unreserve(pd);
1399 /* Update process info */
1400 mutex_lock(&process_info->lock);
1401 process_info->n_vms--;
1402 list_del(&vm->vm_list_node);
1403 mutex_unlock(&process_info->lock);
1405 vm->process_info = NULL;
1407 /* Release per-process resources when last compute VM is destroyed */
1408 if (!process_info->n_vms) {
1409 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1410 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1411 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1413 dma_fence_put(&process_info->eviction_fence->base);
1414 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1415 put_pid(process_info->pid);
1416 mutex_destroy(&process_info->lock);
1417 kfree(process_info);
1421 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1424 struct amdgpu_vm *avm;
1426 if (WARN_ON(!adev || !drm_priv))
1429 avm = drm_priv_to_vm(drm_priv);
1431 pr_debug("Releasing process vm %p\n", avm);
1433 /* The original pasid of amdgpu vm has already been
1434 * released during making a amdgpu vm to a compute vm
1435 * The current pasid is managed by kfd and will be
1436 * released on kfd process destroy. Set amdgpu pasid
1437 * to 0 to avoid duplicate release.
1439 amdgpu_vm_release_compute(adev, avm);
1442 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1444 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1445 struct amdgpu_bo *pd = avm->root.bo;
1446 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1448 if (adev->asic_type < CHIP_VEGA10)
1449 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1450 return avm->pd_phys_addr;
1453 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1454 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1455 void *drm_priv, struct kgd_mem **mem,
1456 uint64_t *offset, uint32_t flags)
1458 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1459 enum ttm_bo_type bo_type = ttm_bo_type_device;
1460 struct sg_table *sg = NULL;
1461 uint64_t user_addr = 0;
1462 struct amdgpu_bo *bo;
1463 struct drm_gem_object *gobj = NULL;
1464 u32 domain, alloc_domain;
1469 * Check on which domain to allocate BO
1471 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1472 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1473 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1474 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1475 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1476 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1477 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1479 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1480 domain = AMDGPU_GEM_DOMAIN_GTT;
1481 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1482 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1483 if (!offset || !*offset)
1485 user_addr = untagged_addr(*offset);
1486 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1487 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1488 domain = AMDGPU_GEM_DOMAIN_GTT;
1489 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1490 bo_type = ttm_bo_type_sg;
1492 if (size > UINT_MAX)
1494 sg = create_doorbell_sg(*offset, size);
1501 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1506 INIT_LIST_HEAD(&(*mem)->attachments);
1507 mutex_init(&(*mem)->lock);
1508 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1510 /* Workaround for AQL queue wraparound bug. Map the same
1511 * memory twice. That means we only actually allocate half
1514 if ((*mem)->aql_queue)
1517 (*mem)->alloc_flags = flags;
1519 amdgpu_sync_create(&(*mem)->sync);
1521 ret = amdgpu_amdkfd_reserve_mem_limit(adev, size, flags);
1523 pr_debug("Insufficient memory\n");
1524 goto err_reserve_limit;
1527 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
1528 va, size, domain_string(alloc_domain));
1530 ret = amdgpu_gem_object_create(adev, size, 1, alloc_domain, alloc_flags,
1531 bo_type, NULL, &gobj);
1533 pr_debug("Failed to create BO on domain %s. ret %d\n",
1534 domain_string(alloc_domain), ret);
1537 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1539 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1540 goto err_node_allow;
1542 bo = gem_to_amdgpu_bo(gobj);
1543 if (bo_type == ttm_bo_type_sg) {
1545 bo->tbo.ttm->sg = sg;
1550 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1553 (*mem)->domain = domain;
1554 (*mem)->mapped_to_gpu_memory = 0;
1555 (*mem)->process_info = avm->process_info;
1556 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1559 ret = init_user_pages(*mem, user_addr);
1561 goto allocate_init_user_pages_failed;
1565 *offset = amdgpu_bo_mmap_offset(bo);
1567 if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1568 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1569 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1571 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1574 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1575 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1580 allocate_init_user_pages_failed:
1581 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1583 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1585 /* Don't unreserve system mem limit twice */
1586 goto err_reserve_limit;
1588 unreserve_mem_limit(adev, size, flags);
1590 mutex_destroy(&(*mem)->lock);
1592 drm_gem_object_put(gobj);
1603 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1604 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1607 struct amdkfd_process_info *process_info = mem->process_info;
1608 unsigned long bo_size = mem->bo->tbo.base.size;
1609 struct kfd_mem_attachment *entry, *tmp;
1610 struct bo_vm_reservation_context ctx;
1611 struct ttm_validate_buffer *bo_list_entry;
1612 unsigned int mapped_to_gpu_memory;
1614 bool is_imported = false;
1616 mutex_lock(&mem->lock);
1618 /* Unpin MMIO/DOORBELL BO's that were pinnned during allocation */
1619 if (mem->alloc_flags &
1620 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1621 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1622 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1625 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1626 is_imported = mem->is_imported;
1627 mutex_unlock(&mem->lock);
1628 /* lock is not needed after this, since mem is unused and will
1632 if (mapped_to_gpu_memory > 0) {
1633 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1638 /* Make sure restore workers don't access the BO any more */
1639 bo_list_entry = &mem->validate_list;
1640 mutex_lock(&process_info->lock);
1641 list_del(&bo_list_entry->head);
1642 mutex_unlock(&process_info->lock);
1644 /* No more MMU notifiers */
1645 amdgpu_mn_unregister(mem->bo);
1647 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1651 /* The eviction fence should be removed by the last unmap.
1652 * TODO: Log an error condition if the bo still has the eviction fence
1655 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1656 process_info->eviction_fence);
1657 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1658 mem->va + bo_size * (1 + mem->aql_queue));
1660 /* Remove from VM internal data structures */
1661 list_for_each_entry_safe(entry, tmp, &mem->attachments, list)
1662 kfd_mem_detach(entry);
1664 ret = unreserve_bo_and_vms(&ctx, false, false);
1666 /* Free the sync object */
1667 amdgpu_sync_free(&mem->sync);
1669 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1670 * remap BO. We need to free it.
1672 if (mem->bo->tbo.sg) {
1673 sg_free_table(mem->bo->tbo.sg);
1674 kfree(mem->bo->tbo.sg);
1677 /* Update the size of the BO being freed if it was allocated from
1678 * VRAM and is not imported.
1681 if ((mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) &&
1689 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1691 dma_buf_put(mem->dmabuf);
1692 mutex_destroy(&mem->lock);
1694 /* If this releases the last reference, it will end up calling
1695 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1696 * this needs to be the last call here.
1698 drm_gem_object_put(&mem->bo->tbo.base);
1703 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1704 struct amdgpu_device *adev, struct kgd_mem *mem,
1705 void *drm_priv, bool *table_freed)
1707 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1709 struct amdgpu_bo *bo;
1711 struct kfd_mem_attachment *entry;
1712 struct bo_vm_reservation_context ctx;
1713 unsigned long bo_size;
1714 bool is_invalid_userptr = false;
1718 pr_err("Invalid BO when mapping memory to GPU\n");
1722 /* Make sure restore is not running concurrently. Since we
1723 * don't map invalid userptr BOs, we rely on the next restore
1724 * worker to do the mapping
1726 mutex_lock(&mem->process_info->lock);
1728 /* Lock mmap-sem. If we find an invalid userptr BO, we can be
1729 * sure that the MMU notifier is no longer running
1730 * concurrently and the queues are actually stopped
1732 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1733 mmap_write_lock(current->mm);
1734 is_invalid_userptr = atomic_read(&mem->invalid);
1735 mmap_write_unlock(current->mm);
1738 mutex_lock(&mem->lock);
1740 domain = mem->domain;
1741 bo_size = bo->tbo.base.size;
1743 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
1745 mem->va + bo_size * (1 + mem->aql_queue),
1746 avm, domain_string(domain));
1748 if (!kfd_mem_is_attached(avm, mem)) {
1749 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
1754 ret = reserve_bo_and_vm(mem, avm, &ctx);
1758 /* Userptr can be marked as "not invalid", but not actually be
1759 * validated yet (still in the system domain). In that case
1760 * the queues are still stopped and we can leave mapping for
1761 * the next restore worker
1763 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
1764 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
1765 is_invalid_userptr = true;
1767 ret = vm_validate_pt_pd_bos(avm);
1771 if (mem->mapped_to_gpu_memory == 0 &&
1772 !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1773 /* Validate BO only once. The eviction fence gets added to BO
1774 * the first time it is mapped. Validate will wait for all
1775 * background evictions to complete.
1777 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
1779 pr_debug("Validate failed\n");
1784 list_for_each_entry(entry, &mem->attachments, list) {
1785 if (entry->bo_va->base.vm != avm || entry->is_mapped)
1788 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
1789 entry->va, entry->va + bo_size, entry);
1791 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
1792 is_invalid_userptr, table_freed);
1794 pr_err("Failed to map bo to gpuvm\n");
1798 ret = vm_update_pds(avm, ctx.sync);
1800 pr_err("Failed to update page directories\n");
1804 entry->is_mapped = true;
1805 mem->mapped_to_gpu_memory++;
1806 pr_debug("\t INC mapping count %d\n",
1807 mem->mapped_to_gpu_memory);
1810 if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
1812 &avm->process_info->eviction_fence->base,
1814 ret = unreserve_bo_and_vms(&ctx, false, false);
1816 /* Only apply no TLB flush on Aldebaran to
1817 * workaround regressions on other Asics.
1819 if (table_freed && (adev->asic_type != CHIP_ALDEBARAN))
1820 *table_freed = true;
1825 unreserve_bo_and_vms(&ctx, false, false);
1827 mutex_unlock(&mem->process_info->lock);
1828 mutex_unlock(&mem->lock);
1832 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1833 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
1835 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1836 struct amdkfd_process_info *process_info = avm->process_info;
1837 unsigned long bo_size = mem->bo->tbo.base.size;
1838 struct kfd_mem_attachment *entry;
1839 struct bo_vm_reservation_context ctx;
1842 mutex_lock(&mem->lock);
1844 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
1847 /* If no VMs were reserved, it means the BO wasn't actually mapped */
1848 if (ctx.n_vms == 0) {
1853 ret = vm_validate_pt_pd_bos(avm);
1857 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
1859 mem->va + bo_size * (1 + mem->aql_queue),
1862 list_for_each_entry(entry, &mem->attachments, list) {
1863 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
1866 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
1867 entry->va, entry->va + bo_size, entry);
1869 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
1870 entry->is_mapped = false;
1872 mem->mapped_to_gpu_memory--;
1873 pr_debug("\t DEC mapping count %d\n",
1874 mem->mapped_to_gpu_memory);
1877 /* If BO is unmapped from all VMs, unfence it. It can be evicted if
1880 if (mem->mapped_to_gpu_memory == 0 &&
1881 !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
1882 !mem->bo->tbo.pin_count)
1883 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1884 process_info->eviction_fence);
1887 unreserve_bo_and_vms(&ctx, false, false);
1889 mutex_unlock(&mem->lock);
1893 int amdgpu_amdkfd_gpuvm_sync_memory(
1894 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
1896 struct amdgpu_sync sync;
1899 amdgpu_sync_create(&sync);
1901 mutex_lock(&mem->lock);
1902 amdgpu_sync_clone(&mem->sync, &sync);
1903 mutex_unlock(&mem->lock);
1905 ret = amdgpu_sync_wait(&sync, intr);
1906 amdgpu_sync_free(&sync);
1910 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct amdgpu_device *adev,
1911 struct kgd_mem *mem, void **kptr, uint64_t *size)
1914 struct amdgpu_bo *bo = mem->bo;
1916 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1917 pr_err("userptr can't be mapped to kernel\n");
1921 /* delete kgd_mem from kfd_bo_list to avoid re-validating
1922 * this BO in BO's restoring after eviction.
1924 mutex_lock(&mem->process_info->lock);
1926 ret = amdgpu_bo_reserve(bo, true);
1928 pr_err("Failed to reserve bo. ret %d\n", ret);
1929 goto bo_reserve_failed;
1932 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
1934 pr_err("Failed to pin bo. ret %d\n", ret);
1938 ret = amdgpu_bo_kmap(bo, kptr);
1940 pr_err("Failed to map bo to kernel. ret %d\n", ret);
1944 amdgpu_amdkfd_remove_eviction_fence(
1945 bo, mem->process_info->eviction_fence);
1946 list_del_init(&mem->validate_list.head);
1949 *size = amdgpu_bo_size(bo);
1951 amdgpu_bo_unreserve(bo);
1953 mutex_unlock(&mem->process_info->lock);
1957 amdgpu_bo_unpin(bo);
1959 amdgpu_bo_unreserve(bo);
1961 mutex_unlock(&mem->process_info->lock);
1966 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct amdgpu_device *adev,
1967 struct kgd_mem *mem)
1969 struct amdgpu_bo *bo = mem->bo;
1971 amdgpu_bo_reserve(bo, true);
1972 amdgpu_bo_kunmap(bo);
1973 amdgpu_bo_unpin(bo);
1974 amdgpu_bo_unreserve(bo);
1977 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
1978 struct kfd_vm_fault_info *mem)
1980 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
1981 *mem = *adev->gmc.vm_fault_info;
1983 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1988 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
1989 struct dma_buf *dma_buf,
1990 uint64_t va, void *drm_priv,
1991 struct kgd_mem **mem, uint64_t *size,
1992 uint64_t *mmap_offset)
1994 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1995 struct drm_gem_object *obj;
1996 struct amdgpu_bo *bo;
1999 if (dma_buf->ops != &amdgpu_dmabuf_ops)
2000 /* Can't handle non-graphics buffers */
2003 obj = dma_buf->priv;
2004 if (drm_to_adev(obj->dev) != adev)
2005 /* Can't handle buffers from other devices */
2008 bo = gem_to_amdgpu_bo(obj);
2009 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2010 AMDGPU_GEM_DOMAIN_GTT)))
2011 /* Only VRAM and GTT BOs are supported */
2014 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2018 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2025 *size = amdgpu_bo_size(bo);
2028 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2030 INIT_LIST_HEAD(&(*mem)->attachments);
2031 mutex_init(&(*mem)->lock);
2033 (*mem)->alloc_flags =
2034 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2035 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2036 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2037 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2039 drm_gem_object_get(&bo->tbo.base);
2042 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2043 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2044 (*mem)->mapped_to_gpu_memory = 0;
2045 (*mem)->process_info = avm->process_info;
2046 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2047 amdgpu_sync_create(&(*mem)->sync);
2048 (*mem)->is_imported = true;
2053 /* Evict a userptr BO by stopping the queues if necessary
2055 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2056 * cannot do any memory allocations, and cannot take any locks that
2057 * are held elsewhere while allocating memory. Therefore this is as
2058 * simple as possible, using atomic counters.
2060 * It doesn't do anything to the BO itself. The real work happens in
2061 * restore, where we get updated page addresses. This function only
2062 * ensures that GPU access to the BO is stopped.
2064 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
2065 struct mm_struct *mm)
2067 struct amdkfd_process_info *process_info = mem->process_info;
2071 atomic_inc(&mem->invalid);
2072 evicted_bos = atomic_inc_return(&process_info->evicted_bos);
2073 if (evicted_bos == 1) {
2074 /* First eviction, stop the queues */
2075 r = kgd2kfd_quiesce_mm(mm);
2077 pr_err("Failed to quiesce KFD\n");
2078 schedule_delayed_work(&process_info->restore_userptr_work,
2079 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2085 /* Update invalid userptr BOs
2087 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2088 * userptr_inval_list and updates user pages for all BOs that have
2089 * been invalidated since their last update.
2091 static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2092 struct mm_struct *mm)
2094 struct kgd_mem *mem, *tmp_mem;
2095 struct amdgpu_bo *bo;
2096 struct ttm_operation_ctx ctx = { false, false };
2099 /* Move all invalidated BOs to the userptr_inval_list and
2100 * release their user pages by migration to the CPU domain
2102 list_for_each_entry_safe(mem, tmp_mem,
2103 &process_info->userptr_valid_list,
2104 validate_list.head) {
2105 if (!atomic_read(&mem->invalid))
2106 continue; /* BO is still valid */
2110 if (amdgpu_bo_reserve(bo, true))
2112 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2113 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2114 amdgpu_bo_unreserve(bo);
2116 pr_err("%s: Failed to invalidate userptr BO\n",
2121 list_move_tail(&mem->validate_list.head,
2122 &process_info->userptr_inval_list);
2125 if (list_empty(&process_info->userptr_inval_list))
2126 return 0; /* All evicted userptr BOs were freed */
2128 /* Go through userptr_inval_list and update any invalid user_pages */
2129 list_for_each_entry(mem, &process_info->userptr_inval_list,
2130 validate_list.head) {
2131 invalid = atomic_read(&mem->invalid);
2133 /* BO hasn't been invalidated since the last
2134 * revalidation attempt. Keep its BO list.
2140 /* Get updated user pages */
2141 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
2143 pr_debug("Failed %d to get user pages\n", ret);
2145 /* Return -EFAULT bad address error as success. It will
2146 * fail later with a VM fault if the GPU tries to access
2147 * it. Better than hanging indefinitely with stalled
2150 * Return other error -EBUSY or -ENOMEM to retry restore
2157 * FIXME: Cannot ignore the return code, must hold
2160 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
2163 /* Mark the BO as valid unless it was invalidated
2164 * again concurrently.
2166 if (atomic_cmpxchg(&mem->invalid, invalid, 0) != invalid)
2173 /* Validate invalid userptr BOs
2175 * Validates BOs on the userptr_inval_list, and moves them back to the
2176 * userptr_valid_list. Also updates GPUVM page tables with new page
2177 * addresses and waits for the page table updates to complete.
2179 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2181 struct amdgpu_bo_list_entry *pd_bo_list_entries;
2182 struct list_head resv_list, duplicates;
2183 struct ww_acquire_ctx ticket;
2184 struct amdgpu_sync sync;
2186 struct amdgpu_vm *peer_vm;
2187 struct kgd_mem *mem, *tmp_mem;
2188 struct amdgpu_bo *bo;
2189 struct ttm_operation_ctx ctx = { false, false };
2192 pd_bo_list_entries = kcalloc(process_info->n_vms,
2193 sizeof(struct amdgpu_bo_list_entry),
2195 if (!pd_bo_list_entries) {
2196 pr_err("%s: Failed to allocate PD BO list entries\n", __func__);
2201 INIT_LIST_HEAD(&resv_list);
2202 INIT_LIST_HEAD(&duplicates);
2204 /* Get all the page directory BOs that need to be reserved */
2206 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2208 amdgpu_vm_get_pd_bo(peer_vm, &resv_list,
2209 &pd_bo_list_entries[i++]);
2210 /* Add the userptr_inval_list entries to resv_list */
2211 list_for_each_entry(mem, &process_info->userptr_inval_list,
2212 validate_list.head) {
2213 list_add_tail(&mem->resv_list.head, &resv_list);
2214 mem->resv_list.bo = mem->validate_list.bo;
2215 mem->resv_list.num_shared = mem->validate_list.num_shared;
2218 /* Reserve all BOs and page tables for validation */
2219 ret = ttm_eu_reserve_buffers(&ticket, &resv_list, false, &duplicates);
2220 WARN(!list_empty(&duplicates), "Duplicates should be empty");
2224 amdgpu_sync_create(&sync);
2226 ret = process_validate_vms(process_info);
2230 /* Validate BOs and update GPUVM page tables */
2231 list_for_each_entry_safe(mem, tmp_mem,
2232 &process_info->userptr_inval_list,
2233 validate_list.head) {
2234 struct kfd_mem_attachment *attachment;
2238 /* Validate the BO if we got user pages */
2239 if (bo->tbo.ttm->pages[0]) {
2240 amdgpu_bo_placement_from_domain(bo, mem->domain);
2241 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2243 pr_err("%s: failed to validate BO\n", __func__);
2248 list_move_tail(&mem->validate_list.head,
2249 &process_info->userptr_valid_list);
2251 /* Update mapping. If the BO was not validated
2252 * (because we couldn't get user pages), this will
2253 * clear the page table entries, which will result in
2254 * VM faults if the GPU tries to access the invalid
2257 list_for_each_entry(attachment, &mem->attachments, list) {
2258 if (!attachment->is_mapped)
2261 kfd_mem_dmaunmap_attachment(mem, attachment);
2262 ret = update_gpuvm_pte(mem, attachment, &sync, NULL);
2264 pr_err("%s: update PTE failed\n", __func__);
2265 /* make sure this gets validated again */
2266 atomic_inc(&mem->invalid);
2272 /* Update page directories */
2273 ret = process_update_pds(process_info, &sync);
2276 ttm_eu_backoff_reservation(&ticket, &resv_list);
2277 amdgpu_sync_wait(&sync, false);
2278 amdgpu_sync_free(&sync);
2280 kfree(pd_bo_list_entries);
2286 /* Worker callback to restore evicted userptr BOs
2288 * Tries to update and validate all userptr BOs. If successful and no
2289 * concurrent evictions happened, the queues are restarted. Otherwise,
2290 * reschedule for another attempt later.
2292 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2294 struct delayed_work *dwork = to_delayed_work(work);
2295 struct amdkfd_process_info *process_info =
2296 container_of(dwork, struct amdkfd_process_info,
2297 restore_userptr_work);
2298 struct task_struct *usertask;
2299 struct mm_struct *mm;
2302 evicted_bos = atomic_read(&process_info->evicted_bos);
2306 /* Reference task and mm in case of concurrent process termination */
2307 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2310 mm = get_task_mm(usertask);
2312 put_task_struct(usertask);
2316 mutex_lock(&process_info->lock);
2318 if (update_invalid_user_pages(process_info, mm))
2320 /* userptr_inval_list can be empty if all evicted userptr BOs
2321 * have been freed. In that case there is nothing to validate
2322 * and we can just restart the queues.
2324 if (!list_empty(&process_info->userptr_inval_list)) {
2325 if (atomic_read(&process_info->evicted_bos) != evicted_bos)
2326 goto unlock_out; /* Concurrent eviction, try again */
2328 if (validate_invalid_user_pages(process_info))
2331 /* Final check for concurrent evicton and atomic update. If
2332 * another eviction happens after successful update, it will
2333 * be a first eviction that calls quiesce_mm. The eviction
2334 * reference counting inside KFD will handle this case.
2336 if (atomic_cmpxchg(&process_info->evicted_bos, evicted_bos, 0) !=
2340 if (kgd2kfd_resume_mm(mm)) {
2341 pr_err("%s: Failed to resume KFD\n", __func__);
2342 /* No recovery from this failure. Probably the CP is
2343 * hanging. No point trying again.
2348 mutex_unlock(&process_info->lock);
2350 put_task_struct(usertask);
2352 /* If validation failed, reschedule another attempt */
2354 schedule_delayed_work(&process_info->restore_userptr_work,
2355 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2358 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2359 * KFD process identified by process_info
2361 * @process_info: amdkfd_process_info of the KFD process
2363 * After memory eviction, restore thread calls this function. The function
2364 * should be called when the Process is still valid. BO restore involves -
2366 * 1. Release old eviction fence and create new one
2367 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2368 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2369 * BOs that need to be reserved.
2370 * 4. Reserve all the BOs
2371 * 5. Validate of PD and PT BOs.
2372 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2373 * 7. Add fence to all PD and PT BOs.
2374 * 8. Unreserve all BOs
2376 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
2378 struct amdgpu_bo_list_entry *pd_bo_list;
2379 struct amdkfd_process_info *process_info = info;
2380 struct amdgpu_vm *peer_vm;
2381 struct kgd_mem *mem;
2382 struct bo_vm_reservation_context ctx;
2383 struct amdgpu_amdkfd_fence *new_fence;
2385 struct list_head duplicate_save;
2386 struct amdgpu_sync sync_obj;
2387 unsigned long failed_size = 0;
2388 unsigned long total_size = 0;
2390 INIT_LIST_HEAD(&duplicate_save);
2391 INIT_LIST_HEAD(&ctx.list);
2392 INIT_LIST_HEAD(&ctx.duplicates);
2394 pd_bo_list = kcalloc(process_info->n_vms,
2395 sizeof(struct amdgpu_bo_list_entry),
2401 mutex_lock(&process_info->lock);
2402 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2404 amdgpu_vm_get_pd_bo(peer_vm, &ctx.list, &pd_bo_list[i++]);
2406 /* Reserve all BOs and page tables/directory. Add all BOs from
2407 * kfd_bo_list to ctx.list
2409 list_for_each_entry(mem, &process_info->kfd_bo_list,
2410 validate_list.head) {
2412 list_add_tail(&mem->resv_list.head, &ctx.list);
2413 mem->resv_list.bo = mem->validate_list.bo;
2414 mem->resv_list.num_shared = mem->validate_list.num_shared;
2417 ret = ttm_eu_reserve_buffers(&ctx.ticket, &ctx.list,
2418 false, &duplicate_save);
2420 pr_debug("Memory eviction: TTM Reserve Failed. Try again\n");
2421 goto ttm_reserve_fail;
2424 amdgpu_sync_create(&sync_obj);
2426 /* Validate PDs and PTs */
2427 ret = process_validate_vms(process_info);
2429 goto validate_map_fail;
2431 ret = process_sync_pds_resv(process_info, &sync_obj);
2433 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2434 goto validate_map_fail;
2437 /* Validate BOs and map them to GPUVM (update VM page tables). */
2438 list_for_each_entry(mem, &process_info->kfd_bo_list,
2439 validate_list.head) {
2441 struct amdgpu_bo *bo = mem->bo;
2442 uint32_t domain = mem->domain;
2443 struct kfd_mem_attachment *attachment;
2445 total_size += amdgpu_bo_size(bo);
2447 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2449 pr_debug("Memory eviction: Validate BOs failed\n");
2450 failed_size += amdgpu_bo_size(bo);
2451 ret = amdgpu_amdkfd_bo_validate(bo,
2452 AMDGPU_GEM_DOMAIN_GTT, false);
2454 pr_debug("Memory eviction: Try again\n");
2455 goto validate_map_fail;
2458 ret = amdgpu_sync_fence(&sync_obj, bo->tbo.moving);
2460 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2461 goto validate_map_fail;
2463 list_for_each_entry(attachment, &mem->attachments, list) {
2464 if (!attachment->is_mapped)
2467 kfd_mem_dmaunmap_attachment(mem, attachment);
2468 ret = update_gpuvm_pte(mem, attachment, &sync_obj, NULL);
2470 pr_debug("Memory eviction: update PTE failed. Try again\n");
2471 goto validate_map_fail;
2477 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2479 /* Update page directories */
2480 ret = process_update_pds(process_info, &sync_obj);
2482 pr_debug("Memory eviction: update PDs failed. Try again\n");
2483 goto validate_map_fail;
2486 /* Wait for validate and PT updates to finish */
2487 amdgpu_sync_wait(&sync_obj, false);
2489 /* Release old eviction fence and create new one, because fence only
2490 * goes from unsignaled to signaled, fence cannot be reused.
2491 * Use context and mm from the old fence.
2493 new_fence = amdgpu_amdkfd_fence_create(
2494 process_info->eviction_fence->base.context,
2495 process_info->eviction_fence->mm,
2498 pr_err("Failed to create eviction fence\n");
2500 goto validate_map_fail;
2502 dma_fence_put(&process_info->eviction_fence->base);
2503 process_info->eviction_fence = new_fence;
2504 *ef = dma_fence_get(&new_fence->base);
2506 /* Attach new eviction fence to all BOs */
2507 list_for_each_entry(mem, &process_info->kfd_bo_list,
2509 amdgpu_bo_fence(mem->bo,
2510 &process_info->eviction_fence->base, true);
2512 /* Attach eviction fence to PD / PT BOs */
2513 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2515 struct amdgpu_bo *bo = peer_vm->root.bo;
2517 amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true);
2521 ttm_eu_backoff_reservation(&ctx.ticket, &ctx.list);
2522 amdgpu_sync_free(&sync_obj);
2524 mutex_unlock(&process_info->lock);
2529 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
2531 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2532 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
2538 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2542 mutex_init(&(*mem)->lock);
2543 INIT_LIST_HEAD(&(*mem)->attachments);
2544 (*mem)->bo = amdgpu_bo_ref(gws_bo);
2545 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
2546 (*mem)->process_info = process_info;
2547 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
2548 amdgpu_sync_create(&(*mem)->sync);
2551 /* Validate gws bo the first time it is added to process */
2552 mutex_lock(&(*mem)->process_info->lock);
2553 ret = amdgpu_bo_reserve(gws_bo, false);
2554 if (unlikely(ret)) {
2555 pr_err("Reserve gws bo failed %d\n", ret);
2556 goto bo_reservation_failure;
2559 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
2561 pr_err("GWS BO validate failed %d\n", ret);
2562 goto bo_validation_failure;
2564 /* GWS resource is shared b/t amdgpu and amdkfd
2565 * Add process eviction fence to bo so they can
2568 ret = dma_resv_reserve_shared(gws_bo->tbo.base.resv, 1);
2570 goto reserve_shared_fail;
2571 amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true);
2572 amdgpu_bo_unreserve(gws_bo);
2573 mutex_unlock(&(*mem)->process_info->lock);
2577 reserve_shared_fail:
2578 bo_validation_failure:
2579 amdgpu_bo_unreserve(gws_bo);
2580 bo_reservation_failure:
2581 mutex_unlock(&(*mem)->process_info->lock);
2582 amdgpu_sync_free(&(*mem)->sync);
2583 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
2584 amdgpu_bo_unref(&gws_bo);
2585 mutex_destroy(&(*mem)->lock);
2591 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
2594 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2595 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
2596 struct amdgpu_bo *gws_bo = kgd_mem->bo;
2598 /* Remove BO from process's validate list so restore worker won't touch
2601 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
2603 ret = amdgpu_bo_reserve(gws_bo, false);
2604 if (unlikely(ret)) {
2605 pr_err("Reserve gws bo failed %d\n", ret);
2606 //TODO add BO back to validate_list?
2609 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
2610 process_info->eviction_fence);
2611 amdgpu_bo_unreserve(gws_bo);
2612 amdgpu_sync_free(&kgd_mem->sync);
2613 amdgpu_bo_unref(&gws_bo);
2614 mutex_destroy(&kgd_mem->lock);
2619 /* Returns GPU-specific tiling mode information */
2620 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
2621 struct tile_config *config)
2623 config->gb_addr_config = adev->gfx.config.gb_addr_config;
2624 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
2625 config->num_tile_configs =
2626 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2627 config->macro_tile_config_ptr =
2628 adev->gfx.config.macrotile_mode_array;
2629 config->num_macro_tile_configs =
2630 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2632 /* Those values are not set from GFX9 onwards */
2633 config->num_banks = adev->gfx.config.num_banks;
2634 config->num_ranks = adev->gfx.config.num_ranks;