2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #include <linux/mmu_context.h>
24 #include "amdgpu_amdkfd.h"
25 #include "gc/gc_10_3_0_offset.h"
26 #include "gc/gc_10_3_0_sh_mask.h"
27 #include "oss/osssys_5_0_0_offset.h"
28 #include "oss/osssys_5_0_0_sh_mask.h"
29 #include "soc15_common.h"
30 #include "v10_structs.h"
34 enum hqd_dequeue_request_type {
41 static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
42 uint32_t queue, uint32_t vmid)
44 mutex_lock(&adev->srbm_mutex);
45 nv_grbm_select(adev, mec, pipe, queue, vmid);
48 static void unlock_srbm(struct amdgpu_device *adev)
50 nv_grbm_select(adev, 0, 0, 0, 0);
51 mutex_unlock(&adev->srbm_mutex);
54 static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
57 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
58 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
60 lock_srbm(adev, mec, pipe, queue_id, 0);
63 static uint64_t get_queue_mask(struct amdgpu_device *adev,
64 uint32_t pipe_id, uint32_t queue_id)
66 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
72 static void release_queue(struct amdgpu_device *adev)
77 static void program_sh_mem_settings_v10_3(struct amdgpu_device *adev, uint32_t vmid,
78 uint32_t sh_mem_config,
79 uint32_t sh_mem_ape1_base,
80 uint32_t sh_mem_ape1_limit,
81 uint32_t sh_mem_bases)
83 lock_srbm(adev, 0, 0, 0, vmid);
85 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
86 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
87 /* APE1 no longer exists on GFX9 */
92 /* ATC is defeatured on Sienna_Cichlid */
93 static int set_pasid_vmid_mapping_v10_3(struct amdgpu_device *adev, unsigned int pasid,
96 uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;
98 /* Mapping vmid to pasid also for IH block */
99 pr_debug("mapping vmid %d -> pasid %d in IH block for GFX client\n",
101 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, value);
106 static int init_interrupts_v10_3(struct amdgpu_device *adev, uint32_t pipe_id)
111 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
112 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
114 lock_srbm(adev, mec, pipe, 0, 0);
116 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
117 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
118 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
125 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
126 unsigned int engine_id,
127 unsigned int queue_id)
129 uint32_t sdma_engine_reg_base = 0;
130 uint32_t sdma_rlc_reg_offset;
135 "Invalid sdma engine id (%d), using engine id 0\n",
139 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
140 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
143 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
144 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
147 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
148 mmSDMA2_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
151 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
152 mmSDMA3_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
156 sdma_rlc_reg_offset = sdma_engine_reg_base
157 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
159 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
160 queue_id, sdma_rlc_reg_offset);
162 return sdma_rlc_reg_offset;
165 static inline struct v10_compute_mqd *get_mqd(void *mqd)
167 return (struct v10_compute_mqd *)mqd;
170 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
172 return (struct v10_sdma_mqd *)mqd;
175 static int hqd_load_v10_3(struct amdgpu_device *adev, void *mqd,
176 uint32_t pipe_id, uint32_t queue_id,
177 uint32_t __user *wptr, uint32_t wptr_shift,
178 uint32_t wptr_mask, struct mm_struct *mm)
180 struct v10_compute_mqd *m;
182 uint32_t reg, hqd_base, data;
186 pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
187 acquire_queue(adev, pipe_id, queue_id);
189 /* HIQ is set during driver init period with vmid set to 0*/
190 if (m->cp_hqd_vmid == 0) {
191 uint32_t value, mec, pipe;
193 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
194 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
196 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
197 mec, pipe, queue_id);
198 value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
199 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
200 ((mec << 5) | (pipe << 3) | queue_id | 0x80));
201 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value);
204 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
205 mqd_hqd = &m->cp_mqd_base_addr_lo;
206 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
209 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
210 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
213 /* Activate doorbell logic before triggering WPTR poll. */
214 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
215 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
216 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
219 /* Don't read wptr with get_user because the user
220 * context may not be accessible (if this function
221 * runs in a work queue). Instead trigger a one-shot
222 * polling read from memory in the CP. This assumes
223 * that wptr is GPU-accessible in the queue's VMID via
224 * ATC or SVM. WPTR==RPTR before starting the poll so
225 * the CP starts fetching new commands from the right
228 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit
229 * tricky. Assume that the queue didn't overflow. The
230 * number of valid bits in the 32-bit RPTR depends on
231 * the queue size. The remaining bits are taken from
232 * the saved 64-bit WPTR. If the WPTR wrapped, add the
235 uint32_t queue_size =
236 2 << REG_GET_FIELD(m->cp_hqd_pq_control,
237 CP_HQD_PQ_CONTROL, QUEUE_SIZE);
238 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
240 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr)
241 guessed_wptr += queue_size;
242 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
243 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
245 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
246 lower_32_bits(guessed_wptr));
247 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
248 upper_32_bits(guessed_wptr));
249 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
250 lower_32_bits((uint64_t)wptr));
251 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
252 upper_32_bits((uint64_t)wptr));
253 pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
254 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
255 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
256 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
259 /* Start the EOP fetcher */
260 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
261 REG_SET_FIELD(m->cp_hqd_eop_rptr,
262 CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
264 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
265 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
272 static int hiq_mqd_load_v10_3(struct amdgpu_device *adev, void *mqd,
273 uint32_t pipe_id, uint32_t queue_id,
274 uint32_t doorbell_off)
276 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
277 struct v10_compute_mqd *m;
283 acquire_queue(adev, pipe_id, queue_id);
285 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
286 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
288 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
289 mec, pipe, queue_id);
291 spin_lock(&adev->gfx.kiq.ring_lock);
292 r = amdgpu_ring_alloc(kiq_ring, 7);
294 pr_err("Failed to alloc KIQ (%d).\n", r);
298 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
299 amdgpu_ring_write(kiq_ring,
300 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
301 PACKET3_MAP_QUEUES_VMID(m->cp_hqd_vmid) | /* VMID */
302 PACKET3_MAP_QUEUES_QUEUE(queue_id) |
303 PACKET3_MAP_QUEUES_PIPE(pipe) |
304 PACKET3_MAP_QUEUES_ME((mec - 1)) |
305 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
306 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
307 PACKET3_MAP_QUEUES_ENGINE_SEL(1) | /* engine_sel: hiq */
308 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
309 amdgpu_ring_write(kiq_ring,
310 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(doorbell_off));
311 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
312 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
313 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
314 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
315 amdgpu_ring_commit(kiq_ring);
318 spin_unlock(&adev->gfx.kiq.ring_lock);
324 static int hqd_dump_v10_3(struct amdgpu_device *adev,
325 uint32_t pipe_id, uint32_t queue_id,
326 uint32_t (**dump)[2], uint32_t *n_regs)
329 #define HQD_N_REGS 56
330 #define DUMP_REG(addr) do { \
331 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
333 (*dump)[i][0] = (addr) << 2; \
334 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \
337 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
341 acquire_queue(adev, pipe_id, queue_id);
343 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
344 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
349 WARN_ON_ONCE(i != HQD_N_REGS);
355 static int hqd_sdma_load_v10_3(struct amdgpu_device *adev, void *mqd,
356 uint32_t __user *wptr, struct mm_struct *mm)
358 struct v10_sdma_mqd *m;
359 uint32_t sdma_rlc_reg_offset;
360 unsigned long end_jiffies;
363 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
365 m = get_sdma_mqd(mqd);
366 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
369 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
370 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
372 end_jiffies = msecs_to_jiffies(2000) + jiffies;
374 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
375 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
377 if (time_after(jiffies, end_jiffies)) {
378 pr_err("SDMA RLC not idle in %s\n", __func__);
381 usleep_range(500, 1000);
384 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
385 m->sdmax_rlcx_doorbell_offset);
387 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
389 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
390 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
391 m->sdmax_rlcx_rb_rptr);
392 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
393 m->sdmax_rlcx_rb_rptr_hi);
395 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
396 if (read_user_wptr(mm, wptr64, data64)) {
397 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
398 lower_32_bits(data64));
399 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
400 upper_32_bits(data64));
402 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
403 m->sdmax_rlcx_rb_rptr);
404 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
405 m->sdmax_rlcx_rb_rptr_hi);
407 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
409 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
410 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
411 m->sdmax_rlcx_rb_base_hi);
412 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
413 m->sdmax_rlcx_rb_rptr_addr_lo);
414 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
415 m->sdmax_rlcx_rb_rptr_addr_hi);
417 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
419 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
424 static int hqd_sdma_dump_v10_3(struct amdgpu_device *adev,
425 uint32_t engine_id, uint32_t queue_id,
426 uint32_t (**dump)[2], uint32_t *n_regs)
428 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
429 engine_id, queue_id);
432 #define HQD_N_REGS (19+6+7+12)
434 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
438 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
439 DUMP_REG(sdma_rlc_reg_offset + reg);
440 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
441 DUMP_REG(sdma_rlc_reg_offset + reg);
442 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
443 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
444 DUMP_REG(sdma_rlc_reg_offset + reg);
445 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
446 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
447 DUMP_REG(sdma_rlc_reg_offset + reg);
449 WARN_ON_ONCE(i != HQD_N_REGS);
455 static bool hqd_is_occupied_v10_3(struct amdgpu_device *adev,
456 uint64_t queue_address, uint32_t pipe_id,
463 acquire_queue(adev, pipe_id, queue_id);
464 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
466 low = lower_32_bits(queue_address >> 8);
467 high = upper_32_bits(queue_address >> 8);
469 if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
470 high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
477 static bool hqd_sdma_is_occupied_v10_3(struct amdgpu_device *adev,
480 struct v10_sdma_mqd *m;
481 uint32_t sdma_rlc_reg_offset;
482 uint32_t sdma_rlc_rb_cntl;
484 m = get_sdma_mqd(mqd);
485 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
488 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
490 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
496 static int hqd_destroy_v10_3(struct amdgpu_device *adev, void *mqd,
497 enum kfd_preempt_type reset_type,
498 unsigned int utimeout, uint32_t pipe_id,
501 enum hqd_dequeue_request_type type;
502 unsigned long end_jiffies;
504 struct v10_compute_mqd *m = get_mqd(mqd);
506 acquire_queue(adev, pipe_id, queue_id);
508 if (m->cp_hqd_vmid == 0)
509 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
511 switch (reset_type) {
512 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
515 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
518 case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE:
526 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
528 end_jiffies = (utimeout * HZ / 1000) + jiffies;
530 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
531 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
533 if (time_after(jiffies, end_jiffies)) {
534 pr_err("cp queue pipe %d queue %d preemption failed\n",
539 usleep_range(500, 1000);
546 static int hqd_sdma_destroy_v10_3(struct amdgpu_device *adev, void *mqd,
547 unsigned int utimeout)
549 struct v10_sdma_mqd *m;
550 uint32_t sdma_rlc_reg_offset;
552 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
554 m = get_sdma_mqd(mqd);
555 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
558 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
559 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
560 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
563 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
564 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
566 if (time_after(jiffies, end_jiffies)) {
567 pr_err("SDMA RLC not idle in %s\n", __func__);
570 usleep_range(500, 1000);
573 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
574 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
575 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
576 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
578 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
579 m->sdmax_rlcx_rb_rptr_hi =
580 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
586 static int address_watch_disable_v10_3(struct amdgpu_device *adev)
591 static int address_watch_execute_v10_3(struct amdgpu_device *adev,
592 unsigned int watch_point_id,
600 static int wave_control_execute_v10_3(struct amdgpu_device *adev,
601 uint32_t gfx_index_val,
606 mutex_lock(&adev->grbm_idx_mutex);
608 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
609 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
611 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
612 INSTANCE_BROADCAST_WRITES, 1);
613 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
614 SA_BROADCAST_WRITES, 1);
615 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
616 SE_BROADCAST_WRITES, 1);
618 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
619 mutex_unlock(&adev->grbm_idx_mutex);
624 static uint32_t address_watch_get_offset_v10_3(struct amdgpu_device *adev,
625 unsigned int watch_point_id,
626 unsigned int reg_offset)
631 static void set_vm_context_page_table_base_v10_3(struct amdgpu_device *adev,
632 uint32_t vmid, uint64_t page_table_base)
634 /* SDMA is on gfxhub as well for Navi1* series */
635 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
638 static void program_trap_handler_settings_v10_3(struct amdgpu_device *adev,
639 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)
641 lock_srbm(adev, 0, 0, 0, vmid);
644 * Program TBA registers
646 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
647 lower_32_bits(tba_addr >> 8));
648 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
649 upper_32_bits(tba_addr >> 8) |
650 (1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT));
653 * Program TMA registers
655 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
656 lower_32_bits(tma_addr >> 8));
657 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
658 upper_32_bits(tma_addr >> 8));
664 uint32_t enable_debug_trap_v10_3(struct amdgpu_device *adev,
665 uint32_t trap_debug_wave_launch_mode,
669 uint32_t orig_wave_cntl_value;
670 uint32_t orig_stall_vmid;
672 mutex_lock(&adev->grbm_idx_mutex);
674 orig_wave_cntl_value = RREG32(SOC15_REG_OFFSET(GC,
676 mmSPI_GDBG_WAVE_CNTL));
677 orig_stall_vmid = REG_GET_FIELD(orig_wave_cntl_value,
681 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
682 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
685 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
687 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), orig_stall_vmid);
689 mutex_unlock(&adev->grbm_idx_mutex);
694 uint32_t disable_debug_trap_v10_3(struct amdgpu_device *adev)
696 mutex_lock(&adev->grbm_idx_mutex);
698 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
700 mutex_unlock(&adev->grbm_idx_mutex);
705 uint32_t set_wave_launch_trap_override_v10_3(struct amdgpu_device *adev,
706 uint32_t trap_override,
711 mutex_lock(&adev->grbm_idx_mutex);
713 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
714 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
715 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
718 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK,
720 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK,
721 REPLACE, trap_override);
722 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
724 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
725 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 0);
726 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
728 mutex_unlock(&adev->grbm_idx_mutex);
733 uint32_t set_wave_launch_mode_v10_3(struct amdgpu_device *adev,
734 uint8_t wave_launch_mode,
741 is_stall_mode = (wave_launch_mode == 4);
742 is_mode_set = (wave_launch_mode != 0 && wave_launch_mode != 4);
744 mutex_lock(&adev->grbm_idx_mutex);
746 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,
747 VMID_MASK, is_mode_set ? 1 << vmid : 0);
748 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,
749 MODE, is_mode_set ? wave_launch_mode : 0);
750 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data);
752 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
753 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL,
754 STALL_VMID, is_stall_mode ? 1 << vmid : 0);
755 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL,
756 STALL_RA, is_stall_mode ? 1 : 0);
757 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
759 mutex_unlock(&adev->grbm_idx_mutex);
764 /* kgd_get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values
765 * The values read are:
766 * ib_offload_wait_time -- Wait Count for Indirect Buffer Offloads.
767 * atomic_offload_wait_time -- Wait Count for L2 and GDS Atomics Offloads.
768 * wrm_offload_wait_time -- Wait Count for WAIT_REG_MEM Offloads.
769 * gws_wait_time -- Wait Count for Global Wave Syncs.
770 * que_sleep_wait_time -- Wait Count for Dequeue Retry.
771 * sch_wave_wait_time -- Wait Count for Scheduling Wave Message.
772 * sem_rearm_wait_time -- Wait Count for Semaphore re-arm.
773 * deq_retry_wait_time -- Wait Count for Global Wave Syncs.
775 void get_iq_wait_times_v10_3(struct amdgpu_device *adev,
776 uint32_t *wait_times)
779 *wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
782 void build_grace_period_packet_info_v10_3(struct amdgpu_device *adev,
784 uint32_t grace_period,
785 uint32_t *reg_offset,
788 *reg_data = wait_times;
790 *reg_data = REG_SET_FIELD(*reg_data,
795 *reg_offset = mmCP_IQ_WAIT_TIME2;
799 const struct kfd2kgd_calls gfx_v10_3_kfd2kgd = {
800 .program_sh_mem_settings = program_sh_mem_settings_v10_3,
801 .set_pasid_vmid_mapping = set_pasid_vmid_mapping_v10_3,
802 .init_interrupts = init_interrupts_v10_3,
803 .hqd_load = hqd_load_v10_3,
804 .hiq_mqd_load = hiq_mqd_load_v10_3,
805 .hqd_sdma_load = hqd_sdma_load_v10_3,
806 .hqd_dump = hqd_dump_v10_3,
807 .hqd_sdma_dump = hqd_sdma_dump_v10_3,
808 .hqd_is_occupied = hqd_is_occupied_v10_3,
809 .hqd_sdma_is_occupied = hqd_sdma_is_occupied_v10_3,
810 .hqd_destroy = hqd_destroy_v10_3,
811 .hqd_sdma_destroy = hqd_sdma_destroy_v10_3,
812 .address_watch_disable = address_watch_disable_v10_3,
813 .address_watch_execute = address_watch_execute_v10_3,
814 .wave_control_execute = wave_control_execute_v10_3,
815 .address_watch_get_offset = address_watch_get_offset_v10_3,
816 .get_atc_vmid_pasid_mapping_info = NULL,
817 .set_vm_context_page_table_base = set_vm_context_page_table_base_v10_3,
818 .program_trap_handler_settings = program_trap_handler_settings_v10_3,
820 .enable_debug_trap = enable_debug_trap_v10_3,
821 .disable_debug_trap = disable_debug_trap_v10_3,
822 .set_wave_launch_trap_override = set_wave_launch_trap_override_v10_3,
823 .set_wave_launch_mode = set_wave_launch_mode_v10_3,
824 .get_iq_wait_times = get_iq_wait_times_v10_3,
825 .build_grace_period_packet_info = build_grace_period_packet_info_v10_3,