2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
35 #define pr_fmt(fmt) "amdgpu: " fmt
41 #define dev_fmt(fmt) "amdgpu: " fmt
43 #include "amdgpu_ctx.h"
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
53 #include <linux/aer.h>
55 #include <drm/ttm/ttm_bo_api.h>
56 #include <drm/ttm/ttm_bo_driver.h>
57 #include <drm/ttm/ttm_placement.h>
58 #include <drm/ttm/ttm_module.h>
59 #include <drm/ttm/ttm_execbuf_util.h>
61 #include <drm/amdgpu_drm.h>
62 #include <drm/drm_gem.h>
63 #include <drm/drm_ioctl.h>
64 #include <drm/gpu_scheduler.h>
66 #include <kgd_kfd_interface.h>
67 #include "dm_pp_interface.h"
68 #include "kgd_pp_interface.h"
70 #include "amd_shared.h"
71 #include "amdgpu_mode.h"
72 #include "amdgpu_ih.h"
73 #include "amdgpu_irq.h"
74 #include "amdgpu_ucode.h"
75 #include "amdgpu_ttm.h"
76 #include "amdgpu_psp.h"
77 #include "amdgpu_gds.h"
78 #include "amdgpu_sync.h"
79 #include "amdgpu_ring.h"
80 #include "amdgpu_vm.h"
81 #include "amdgpu_dpm.h"
82 #include "amdgpu_acp.h"
83 #include "amdgpu_uvd.h"
84 #include "amdgpu_vce.h"
85 #include "amdgpu_vcn.h"
86 #include "amdgpu_jpeg.h"
87 #include "amdgpu_mn.h"
88 #include "amdgpu_gmc.h"
89 #include "amdgpu_gfx.h"
90 #include "amdgpu_sdma.h"
91 #include "amdgpu_nbio.h"
92 #include "amdgpu_dm.h"
93 #include "amdgpu_virt.h"
94 #include "amdgpu_csa.h"
95 #include "amdgpu_gart.h"
96 #include "amdgpu_debugfs.h"
97 #include "amdgpu_job.h"
98 #include "amdgpu_bo_list.h"
99 #include "amdgpu_gem.h"
100 #include "amdgpu_doorbell.h"
101 #include "amdgpu_amdkfd.h"
102 #include "amdgpu_smu.h"
103 #include "amdgpu_discovery.h"
104 #include "amdgpu_mes.h"
105 #include "amdgpu_umc.h"
106 #include "amdgpu_mmhub.h"
107 #include "amdgpu_gfxhub.h"
108 #include "amdgpu_df.h"
109 #include "amdgpu_smuio.h"
111 #define MAX_GPU_INSTANCE 16
113 struct amdgpu_gpu_instance
115 struct amdgpu_device *adev;
116 int mgpu_fan_enabled;
119 struct amdgpu_mgpu_info
121 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
128 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
131 * Modules parameters.
133 extern int amdgpu_modeset;
134 extern int amdgpu_vram_limit;
135 extern int amdgpu_vis_vram_limit;
136 extern int amdgpu_gart_size;
137 extern int amdgpu_gtt_size;
138 extern int amdgpu_moverate;
139 extern int amdgpu_benchmarking;
140 extern int amdgpu_testing;
141 extern int amdgpu_audio;
142 extern int amdgpu_disp_priority;
143 extern int amdgpu_hw_i2c;
144 extern int amdgpu_pcie_gen2;
145 extern int amdgpu_msi;
146 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
147 extern int amdgpu_dpm;
148 extern int amdgpu_fw_load_type;
149 extern int amdgpu_aspm;
150 extern int amdgpu_runtime_pm;
151 extern uint amdgpu_ip_block_mask;
152 extern int amdgpu_bapm;
153 extern int amdgpu_deep_color;
154 extern int amdgpu_vm_size;
155 extern int amdgpu_vm_block_size;
156 extern int amdgpu_vm_fragment_size;
157 extern int amdgpu_vm_fault_stop;
158 extern int amdgpu_vm_debug;
159 extern int amdgpu_vm_update_mode;
160 extern int amdgpu_exp_hw_support;
161 extern int amdgpu_dc;
162 extern int amdgpu_sched_jobs;
163 extern int amdgpu_sched_hw_submission;
164 extern uint amdgpu_pcie_gen_cap;
165 extern uint amdgpu_pcie_lane_cap;
166 extern uint amdgpu_cg_mask;
167 extern uint amdgpu_pg_mask;
168 extern uint amdgpu_sdma_phase_quantum;
169 extern char *amdgpu_disable_cu;
170 extern char *amdgpu_virtual_display;
171 extern uint amdgpu_pp_feature_mask;
172 extern uint amdgpu_force_long_training;
173 extern int amdgpu_job_hang_limit;
174 extern int amdgpu_lbpw;
175 extern int amdgpu_compute_multipipe;
176 extern int amdgpu_gpu_recovery;
177 extern int amdgpu_emu_mode;
178 extern uint amdgpu_smu_memory_pool_size;
179 extern uint amdgpu_dc_feature_mask;
180 extern uint amdgpu_dc_debug_mask;
181 extern uint amdgpu_dm_abm_level;
182 extern struct amdgpu_mgpu_info mgpu_info;
183 extern int amdgpu_ras_enable;
184 extern uint amdgpu_ras_mask;
185 extern int amdgpu_bad_page_threshold;
186 extern int amdgpu_async_gfx_ring;
187 extern int amdgpu_mcbp;
188 extern int amdgpu_discovery;
189 extern int amdgpu_mes;
190 extern int amdgpu_noretry;
191 extern int amdgpu_force_asic_type;
192 #ifdef CONFIG_HSA_AMD
193 extern int sched_policy;
194 extern bool debug_evictions;
195 extern bool no_system_mem_limit;
197 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
198 static const bool __maybe_unused debug_evictions; /* = false */
199 static const bool __maybe_unused no_system_mem_limit;
202 extern int amdgpu_tmz;
203 extern int amdgpu_reset_method;
205 #ifdef CONFIG_DRM_AMDGPU_SI
206 extern int amdgpu_si_support;
208 #ifdef CONFIG_DRM_AMDGPU_CIK
209 extern int amdgpu_cik_support;
211 extern int amdgpu_num_kcq;
213 #define AMDGPU_VM_MAX_NUM_CTX 4096
214 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
215 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
216 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
217 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
218 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
219 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
220 #define AMDGPUFB_CONN_LIMIT 4
221 #define AMDGPU_BIOS_NUM_SCRATCH 16
223 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
225 /* hard reset data */
226 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
229 #define AMDGPU_RESET_GFX (1 << 0)
230 #define AMDGPU_RESET_COMPUTE (1 << 1)
231 #define AMDGPU_RESET_DMA (1 << 2)
232 #define AMDGPU_RESET_CP (1 << 3)
233 #define AMDGPU_RESET_GRBM (1 << 4)
234 #define AMDGPU_RESET_DMA1 (1 << 5)
235 #define AMDGPU_RESET_RLC (1 << 6)
236 #define AMDGPU_RESET_SEM (1 << 7)
237 #define AMDGPU_RESET_IH (1 << 8)
238 #define AMDGPU_RESET_VMC (1 << 9)
239 #define AMDGPU_RESET_MC (1 << 10)
240 #define AMDGPU_RESET_DISPLAY (1 << 11)
241 #define AMDGPU_RESET_UVD (1 << 12)
242 #define AMDGPU_RESET_VCE (1 << 13)
243 #define AMDGPU_RESET_VCE1 (1 << 14)
245 /* max cursor sizes (in pixels) */
246 #define CIK_CURSOR_WIDTH 128
247 #define CIK_CURSOR_HEIGHT 128
249 struct amdgpu_device;
251 struct amdgpu_cs_parser;
253 struct amdgpu_irq_src;
255 struct amdgpu_bo_va_mapping;
257 struct kfd_vm_fault_info;
258 struct amdgpu_hive_info;
261 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
262 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
263 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
264 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
265 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
266 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
267 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
268 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
269 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
270 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
275 enum amdgpu_thermal_irq {
276 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
277 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
279 AMDGPU_THERMAL_IRQ_LAST
282 enum amdgpu_kiq_irq {
283 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
284 AMDGPU_CP_KIQ_IRQ_LAST
287 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
288 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
289 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
291 int amdgpu_device_ip_set_clockgating_state(void *dev,
292 enum amd_ip_block_type block_type,
293 enum amd_clockgating_state state);
294 int amdgpu_device_ip_set_powergating_state(void *dev,
295 enum amd_ip_block_type block_type,
296 enum amd_powergating_state state);
297 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
299 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
300 enum amd_ip_block_type block_type);
301 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
302 enum amd_ip_block_type block_type);
304 #define AMDGPU_MAX_IP_NUM 16
306 struct amdgpu_ip_block_status {
310 bool late_initialized;
314 struct amdgpu_ip_block_version {
315 const enum amd_ip_block_type type;
319 const struct amd_ip_funcs *funcs;
322 #define HW_REV(_Major, _Minor, _Rev) \
323 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
325 struct amdgpu_ip_block {
326 struct amdgpu_ip_block_status status;
327 const struct amdgpu_ip_block_version *version;
330 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
331 enum amd_ip_block_type type,
332 u32 major, u32 minor);
334 struct amdgpu_ip_block *
335 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
336 enum amd_ip_block_type type);
338 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
339 const struct amdgpu_ip_block_version *ip_block_version);
344 bool amdgpu_get_bios(struct amdgpu_device *adev);
345 bool amdgpu_read_bios(struct amdgpu_device *adev);
351 #define AMDGPU_MAX_PPLL 3
353 struct amdgpu_clock {
354 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
355 struct amdgpu_pll spll;
356 struct amdgpu_pll mpll;
358 uint32_t default_mclk;
359 uint32_t default_sclk;
360 uint32_t default_dispclk;
361 uint32_t current_dispclk;
363 uint32_t max_pixel_clock;
366 /* sub-allocation manager, it has to be protected by another lock.
367 * By conception this is an helper for other part of the driver
368 * like the indirect buffer or semaphore, which both have their
371 * Principe is simple, we keep a list of sub allocation in offset
372 * order (first entry has offset == 0, last entry has the highest
375 * When allocating new object we first check if there is room at
376 * the end total_size - (last_object_offset + last_object_size) >=
377 * alloc_size. If so we allocate new object there.
379 * When there is not enough room at the end, we start waiting for
380 * each sub object until we reach object_offset+object_size >=
381 * alloc_size, this object then become the sub object we return.
383 * Alignment can't be bigger than page size.
385 * Hole are not considered for allocation to keep things simple.
386 * Assumption is that there won't be hole (all object on same
390 #define AMDGPU_SA_NUM_FENCE_LISTS 32
392 struct amdgpu_sa_manager {
393 wait_queue_head_t wq;
394 struct amdgpu_bo *bo;
395 struct list_head *hole;
396 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
397 struct list_head olist;
405 /* sub-allocation buffer */
406 struct amdgpu_sa_bo {
407 struct list_head olist;
408 struct list_head flist;
409 struct amdgpu_sa_manager *manager;
412 struct dma_fence *fence;
415 int amdgpu_fence_slab_init(void);
416 void amdgpu_fence_slab_fini(void);
422 struct amdgpu_flip_work {
423 struct delayed_work flip_work;
424 struct work_struct unpin_work;
425 struct amdgpu_device *adev;
429 struct drm_pending_vblank_event *event;
430 struct amdgpu_bo *old_abo;
431 struct dma_fence *excl;
432 unsigned shared_count;
433 struct dma_fence **shared;
434 struct dma_fence_cb cb;
444 struct amdgpu_sa_bo *sa_bo;
451 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
454 * file private structure
457 struct amdgpu_fpriv {
459 struct amdgpu_bo_va *prt_va;
460 struct amdgpu_bo_va *csa_va;
461 struct mutex bo_list_lock;
462 struct idr bo_list_handles;
463 struct amdgpu_ctx_mgr ctx_mgr;
466 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
468 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
470 enum amdgpu_ib_pool_type pool,
471 struct amdgpu_ib *ib);
472 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
473 struct dma_fence *f);
474 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
475 struct amdgpu_ib *ibs, struct amdgpu_job *job,
476 struct dma_fence **f);
477 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
478 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
479 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
484 struct amdgpu_cs_chunk {
490 struct amdgpu_cs_post_dep {
491 struct drm_syncobj *syncobj;
492 struct dma_fence_chain *chain;
496 struct amdgpu_cs_parser {
497 struct amdgpu_device *adev;
498 struct drm_file *filp;
499 struct amdgpu_ctx *ctx;
503 struct amdgpu_cs_chunk *chunks;
505 /* scheduler job object */
506 struct amdgpu_job *job;
507 struct drm_sched_entity *entity;
510 struct ww_acquire_ctx ticket;
511 struct amdgpu_bo_list *bo_list;
512 struct amdgpu_mn *mn;
513 struct amdgpu_bo_list_entry vm_pd;
514 struct list_head validated;
515 struct dma_fence *fence;
516 uint64_t bytes_moved_threshold;
517 uint64_t bytes_moved_vis_threshold;
518 uint64_t bytes_moved;
519 uint64_t bytes_moved_vis;
522 struct amdgpu_bo_list_entry uf_entry;
524 unsigned num_post_deps;
525 struct amdgpu_cs_post_dep *post_deps;
528 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
529 uint32_t ib_idx, int idx)
531 return p->job->ibs[ib_idx].ptr[idx];
534 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
535 uint32_t ib_idx, int idx,
538 p->job->ibs[ib_idx].ptr[idx] = value;
544 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
547 struct amdgpu_bo *wb_obj;
548 volatile uint32_t *wb;
550 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
551 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
554 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
555 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
560 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
566 void amdgpu_test_moves(struct amdgpu_device *adev);
569 * ASIC specific register table accessible by UMD
571 struct amdgpu_allowed_register_entry {
576 enum amd_reset_method {
577 AMD_RESET_METHOD_LEGACY = 0,
578 AMD_RESET_METHOD_MODE0,
579 AMD_RESET_METHOD_MODE1,
580 AMD_RESET_METHOD_MODE2,
581 AMD_RESET_METHOD_BACO
585 * ASIC specific functions.
587 struct amdgpu_asic_funcs {
588 bool (*read_disabled_bios)(struct amdgpu_device *adev);
589 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
590 u8 *bios, u32 length_bytes);
591 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
592 u32 sh_num, u32 reg_offset, u32 *value);
593 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
594 int (*reset)(struct amdgpu_device *adev);
595 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
596 /* get the reference clock */
597 u32 (*get_xclk)(struct amdgpu_device *adev);
598 /* MM block clocks */
599 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
600 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
601 /* static power management */
602 int (*get_pcie_lanes)(struct amdgpu_device *adev);
603 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
604 /* get config memsize register */
605 u32 (*get_config_memsize)(struct amdgpu_device *adev);
606 /* flush hdp write queue */
607 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
608 /* invalidate hdp read cache */
609 void (*invalidate_hdp)(struct amdgpu_device *adev,
610 struct amdgpu_ring *ring);
611 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev);
612 /* check if the asic needs a full reset of if soft reset will work */
613 bool (*need_full_reset)(struct amdgpu_device *adev);
614 /* initialize doorbell layout for specific asic*/
615 void (*init_doorbell_index)(struct amdgpu_device *adev);
616 /* PCIe bandwidth usage */
617 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
619 /* do we need to reset the asic at init time (e.g., kexec) */
620 bool (*need_reset_on_init)(struct amdgpu_device *adev);
621 /* PCIe replay counter */
622 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
623 /* device supports BACO */
624 bool (*supports_baco)(struct amdgpu_device *adev);
625 /* pre asic_init quirks */
626 void (*pre_asic_init)(struct amdgpu_device *adev);
627 /* enter/exit umd stable pstate */
628 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
634 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
635 struct drm_file *filp);
637 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
638 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
639 struct drm_file *filp);
640 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
641 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
642 struct drm_file *filp);
644 /* VRAM scratch page for HDP bug, default vram page */
645 struct amdgpu_vram_scratch {
646 struct amdgpu_bo *robj;
647 volatile uint32_t *ptr;
654 struct amdgpu_atcs_functions {
662 struct amdgpu_atcs_functions functions;
668 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
669 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
672 * Core structure, functions and helpers.
674 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
675 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
677 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
678 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
680 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
681 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
683 struct amdgpu_mmio_remap {
685 resource_size_t bus_addr;
688 /* Define the HW IP blocks will be used in driver , add more if necessary */
689 enum amd_hw_ip_block_type {
707 JPEG_HWIP = VCN_HWIP,
722 #define HWIP_MAX_INSTANCE 8
724 struct amd_powerplay {
726 const struct amd_pm_funcs *pp_funcs;
729 /* polaris10 kickers */
730 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
736 ((did == 0x6FDF) && \
741 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
745 /* polaris11 kickers */
746 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
749 ((did == 0x67FF) && \
754 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
757 /* polaris12 kickers */
758 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
763 ((did == 0x6981) && \
768 #define AMDGPU_RESET_MAGIC_NUM 64
769 #define AMDGPU_MAX_DF_PERFMONS 4
770 struct amdgpu_device {
772 struct pci_dev *pdev;
773 struct drm_device ddev;
775 #ifdef CONFIG_DRM_AMD_ACP
776 struct amdgpu_acp acp;
778 struct amdgpu_hive_info *hive;
780 enum amd_asic_type asic_type;
783 uint32_t external_rev_id;
785 unsigned long apu_flags;
787 const struct amdgpu_asic_funcs *asic_funcs;
791 struct notifier_block acpi_nb;
792 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
793 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
794 unsigned debugfs_count;
795 #if defined(CONFIG_DEBUG_FS)
796 struct dentry *debugfs_preempt;
797 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
799 struct amdgpu_atif *atif;
800 struct amdgpu_atcs atcs;
801 struct mutex srbm_mutex;
802 /* GRBM index mutex. Protects concurrent access to GRBM index */
803 struct mutex grbm_idx_mutex;
804 struct dev_pm_domain vga_pm_domain;
805 bool have_disp_power_ref;
806 bool have_atomics_support;
812 uint32_t bios_scratch_reg_offset;
813 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
815 /* Register/doorbell mmio */
816 resource_size_t rmmio_base;
817 resource_size_t rmmio_size;
819 /* protects concurrent MM_INDEX/DATA based register access */
820 spinlock_t mmio_idx_lock;
821 struct amdgpu_mmio_remap rmmio_remap;
822 /* protects concurrent SMC based register access */
823 spinlock_t smc_idx_lock;
824 amdgpu_rreg_t smc_rreg;
825 amdgpu_wreg_t smc_wreg;
826 /* protects concurrent PCIE register access */
827 spinlock_t pcie_idx_lock;
828 amdgpu_rreg_t pcie_rreg;
829 amdgpu_wreg_t pcie_wreg;
830 amdgpu_rreg_t pciep_rreg;
831 amdgpu_wreg_t pciep_wreg;
832 amdgpu_rreg64_t pcie_rreg64;
833 amdgpu_wreg64_t pcie_wreg64;
834 /* protects concurrent UVD register access */
835 spinlock_t uvd_ctx_idx_lock;
836 amdgpu_rreg_t uvd_ctx_rreg;
837 amdgpu_wreg_t uvd_ctx_wreg;
838 /* protects concurrent DIDT register access */
839 spinlock_t didt_idx_lock;
840 amdgpu_rreg_t didt_rreg;
841 amdgpu_wreg_t didt_wreg;
842 /* protects concurrent gc_cac register access */
843 spinlock_t gc_cac_idx_lock;
844 amdgpu_rreg_t gc_cac_rreg;
845 amdgpu_wreg_t gc_cac_wreg;
846 /* protects concurrent se_cac register access */
847 spinlock_t se_cac_idx_lock;
848 amdgpu_rreg_t se_cac_rreg;
849 amdgpu_wreg_t se_cac_wreg;
850 /* protects concurrent ENDPOINT (audio) register access */
851 spinlock_t audio_endpt_idx_lock;
852 amdgpu_block_rreg_t audio_endpt_rreg;
853 amdgpu_block_wreg_t audio_endpt_wreg;
854 void __iomem *rio_mem;
855 resource_size_t rio_mem_size;
856 struct amdgpu_doorbell doorbell;
859 struct amdgpu_clock clock;
862 struct amdgpu_gmc gmc;
863 struct amdgpu_gart gart;
864 dma_addr_t dummy_page_addr;
865 struct amdgpu_vm_manager vm_manager;
866 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
869 /* memory management */
870 struct amdgpu_mman mman;
871 struct amdgpu_vram_scratch vram_scratch;
873 atomic64_t num_bytes_moved;
874 atomic64_t num_evictions;
875 atomic64_t num_vram_cpu_page_faults;
876 atomic_t gpu_reset_counter;
877 atomic_t vram_lost_counter;
879 /* data for buffer migration throttling */
883 s64 accum_us; /* accumulated microseconds */
884 s64 accum_us_vis; /* for visible VRAM */
889 bool enable_virtual_display;
890 struct amdgpu_mode_info mode_info;
891 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
892 struct work_struct hotplug_work;
893 struct amdgpu_irq_src crtc_irq;
894 struct amdgpu_irq_src vupdate_irq;
895 struct amdgpu_irq_src pageflip_irq;
896 struct amdgpu_irq_src hpd_irq;
901 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
903 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
904 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
907 struct amdgpu_irq irq;
910 struct amd_powerplay powerplay;
911 bool pp_force_state_enabled;
914 struct smu_context smu;
922 struct amdgpu_nbio nbio;
925 struct amdgpu_smuio smuio;
928 struct amdgpu_mmhub mmhub;
931 struct amdgpu_gfxhub gfxhub;
934 struct amdgpu_gfx gfx;
937 struct amdgpu_sdma sdma;
940 struct amdgpu_uvd uvd;
943 struct amdgpu_vce vce;
946 struct amdgpu_vcn vcn;
949 struct amdgpu_jpeg jpeg;
952 struct amdgpu_firmware firmware;
955 struct psp_context psp;
958 struct amdgpu_gds gds;
961 struct amdgpu_kfd_dev kfd;
964 struct amdgpu_umc umc;
966 /* display related functionality */
967 struct amdgpu_display_manager dm;
971 struct amdgpu_mes mes;
976 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
978 struct mutex mn_lock;
979 DECLARE_HASHTABLE(mn_hash, 7);
981 /* tracking pinned memory */
982 atomic64_t vram_pin_size;
983 atomic64_t visible_pin_size;
984 atomic64_t gart_pin_size;
986 /* soc15 register offset based on ip, instance and segment */
987 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
989 /* delayed work_func for deferring clockgating during resume */
990 struct delayed_work delayed_init_work;
992 struct amdgpu_virt virt;
994 /* link all shadow bo */
995 struct list_head shadow_list;
996 struct mutex shadow_list_lock;
998 /* record hw reset is performed */
1000 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1006 atomic_t in_gpu_reset;
1007 enum pp_mp1_state mp1_state;
1008 struct rw_semaphore reset_sem;
1009 struct amdgpu_doorbell_index doorbell_index;
1011 struct mutex notifier_lock;
1014 struct work_struct xgmi_reset_work;
1019 long compute_timeout;
1022 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1024 /* enable runtime pm on the device */
1029 bool ucode_sysfs_en;
1031 /* Chip product information */
1032 char product_number[16];
1033 char product_name[32];
1036 struct amdgpu_autodump autodump;
1038 atomic_t throttling_logging_enabled;
1039 struct ratelimit_state throttling_logging_rs;
1040 uint32_t ras_features;
1042 bool in_pci_err_recovery;
1043 struct pci_saved_state *pci_state;
1046 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1048 return container_of(ddev, struct amdgpu_device, ddev);
1051 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1056 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1058 return container_of(bdev, struct amdgpu_device, mman.bdev);
1061 int amdgpu_device_init(struct amdgpu_device *adev,
1063 void amdgpu_device_fini(struct amdgpu_device *adev);
1064 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1066 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1067 uint32_t *buf, size_t size, bool write);
1068 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1069 uint32_t reg, uint32_t acc_flags);
1070 void amdgpu_device_wreg(struct amdgpu_device *adev,
1071 uint32_t reg, uint32_t v,
1072 uint32_t acc_flags);
1073 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1074 uint32_t reg, uint32_t v);
1075 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1076 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1078 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1079 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1081 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1082 u32 pcie_index, u32 pcie_data,
1084 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1085 u32 pcie_index, u32 pcie_data,
1087 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1088 u32 pcie_index, u32 pcie_data,
1089 u32 reg_addr, u32 reg_data);
1090 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1091 u32 pcie_index, u32 pcie_data,
1092 u32 reg_addr, u64 reg_data);
1094 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1095 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1097 int emu_soc_asic_init(struct amdgpu_device *adev);
1100 * Registers read & write functions.
1102 #define AMDGPU_REGS_NO_KIQ (1<<1)
1104 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1105 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1107 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1108 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1110 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1111 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1113 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1114 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1115 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1116 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1117 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1118 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1119 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1120 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1121 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1122 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1123 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1124 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1125 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1126 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1127 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1128 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1129 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1130 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1131 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1132 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1133 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1134 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1135 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1136 #define WREG32_P(reg, val, mask) \
1138 uint32_t tmp_ = RREG32(reg); \
1140 tmp_ |= ((val) & ~(mask)); \
1141 WREG32(reg, tmp_); \
1143 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1144 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1145 #define WREG32_PLL_P(reg, val, mask) \
1147 uint32_t tmp_ = RREG32_PLL(reg); \
1149 tmp_ |= ((val) & ~(mask)); \
1150 WREG32_PLL(reg, tmp_); \
1153 #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1155 u32 tmp = RREG32_SMC(_Reg); \
1157 tmp |= ((_Val) & ~(_Mask)); \
1158 WREG32_SMC(_Reg, tmp); \
1161 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1162 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1163 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1165 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1166 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1168 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1169 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1170 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1172 #define REG_GET_FIELD(value, reg, field) \
1173 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1175 #define WREG32_FIELD(reg, field, val) \
1176 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1178 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1179 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1184 #define RBIOS8(i) (adev->bios[i])
1185 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1186 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1191 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1192 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1193 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1194 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1195 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1196 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1197 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1198 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1199 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1200 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1201 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1202 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1203 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1204 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1205 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1206 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1207 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1208 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1209 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1210 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1211 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1212 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1213 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1214 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1216 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1218 /* Common functions */
1219 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1220 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1221 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1222 struct amdgpu_job* job);
1223 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1224 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1226 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1228 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1229 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1230 const u32 *registers,
1231 const u32 array_size);
1233 bool amdgpu_device_supports_boco(struct drm_device *dev);
1234 bool amdgpu_device_supports_baco(struct drm_device *dev);
1235 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1236 struct amdgpu_device *peer_adev);
1237 int amdgpu_device_baco_enter(struct drm_device *dev);
1238 int amdgpu_device_baco_exit(struct drm_device *dev);
1241 #if defined(CONFIG_VGA_SWITCHEROO)
1242 void amdgpu_register_atpx_handler(void);
1243 void amdgpu_unregister_atpx_handler(void);
1244 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1245 bool amdgpu_is_atpx_hybrid(void);
1246 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1247 bool amdgpu_has_atpx(void);
1249 static inline void amdgpu_register_atpx_handler(void) {}
1250 static inline void amdgpu_unregister_atpx_handler(void) {}
1251 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1252 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1253 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1254 static inline bool amdgpu_has_atpx(void) { return false; }
1257 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1258 void *amdgpu_atpx_get_dhandle(void);
1260 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1266 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1267 extern const int amdgpu_max_kms_ioctl;
1269 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1270 void amdgpu_driver_unload_kms(struct drm_device *dev);
1271 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1272 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1273 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1274 struct drm_file *file_priv);
1275 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1276 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1277 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1278 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1279 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1280 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1281 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1285 * functions used by amdgpu_encoder.c
1287 struct amdgpu_afmt_acr {
1301 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1304 #if defined(CONFIG_ACPI)
1305 int amdgpu_acpi_init(struct amdgpu_device *adev);
1306 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1307 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1308 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1309 u8 perf_req, bool advertise);
1310 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1312 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1313 struct amdgpu_dm_backlight_caps *caps);
1314 bool amdgpu_acpi_is_s0ix_supported(void);
1316 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1317 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1318 static inline bool amdgpu_acpi_is_s0ix_supported(void) { return false; }
1321 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1322 uint64_t addr, struct amdgpu_bo **bo,
1323 struct amdgpu_bo_va_mapping **mapping);
1325 #if defined(CONFIG_DRM_AMD_DC)
1326 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1328 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1332 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1333 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1335 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1336 pci_channel_state_t state);
1337 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1338 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1339 void amdgpu_pci_resume(struct pci_dev *pdev);
1341 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1342 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1344 #include "amdgpu_object.h"
1346 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1348 return adev->gmc.tmz_enabled;
1351 static inline int amdgpu_in_reset(struct amdgpu_device *adev)
1353 return atomic_read(&adev->in_gpu_reset);