2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
35 #define pr_fmt(fmt) "amdgpu: " fmt
41 #define dev_fmt(fmt) "amdgpu: " fmt
43 #include "amdgpu_ctx.h"
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
53 #include <linux/aer.h>
55 #include <drm/ttm/ttm_bo_api.h>
56 #include <drm/ttm/ttm_bo_driver.h>
57 #include <drm/ttm/ttm_placement.h>
58 #include <drm/ttm/ttm_execbuf_util.h>
60 #include <drm/amdgpu_drm.h>
61 #include <drm/drm_gem.h>
62 #include <drm/drm_ioctl.h>
63 #include <drm/gpu_scheduler.h>
65 #include <kgd_kfd_interface.h>
66 #include "dm_pp_interface.h"
67 #include "kgd_pp_interface.h"
69 #include "amd_shared.h"
70 #include "amdgpu_mode.h"
71 #include "amdgpu_ih.h"
72 #include "amdgpu_irq.h"
73 #include "amdgpu_ucode.h"
74 #include "amdgpu_ttm.h"
75 #include "amdgpu_psp.h"
76 #include "amdgpu_gds.h"
77 #include "amdgpu_sync.h"
78 #include "amdgpu_ring.h"
79 #include "amdgpu_vm.h"
80 #include "amdgpu_dpm.h"
81 #include "amdgpu_acp.h"
82 #include "amdgpu_uvd.h"
83 #include "amdgpu_vce.h"
84 #include "amdgpu_vcn.h"
85 #include "amdgpu_jpeg.h"
86 #include "amdgpu_mn.h"
87 #include "amdgpu_gmc.h"
88 #include "amdgpu_gfx.h"
89 #include "amdgpu_sdma.h"
90 #include "amdgpu_nbio.h"
91 #include "amdgpu_hdp.h"
92 #include "amdgpu_dm.h"
93 #include "amdgpu_virt.h"
94 #include "amdgpu_csa.h"
95 #include "amdgpu_gart.h"
96 #include "amdgpu_debugfs.h"
97 #include "amdgpu_job.h"
98 #include "amdgpu_bo_list.h"
99 #include "amdgpu_gem.h"
100 #include "amdgpu_doorbell.h"
101 #include "amdgpu_amdkfd.h"
102 #include "amdgpu_smu.h"
103 #include "amdgpu_discovery.h"
104 #include "amdgpu_mes.h"
105 #include "amdgpu_umc.h"
106 #include "amdgpu_mmhub.h"
107 #include "amdgpu_gfxhub.h"
108 #include "amdgpu_df.h"
109 #include "amdgpu_smuio.h"
110 #include "amdgpu_fdinfo.h"
112 #define MAX_GPU_INSTANCE 16
114 struct amdgpu_gpu_instance
116 struct amdgpu_device *adev;
117 int mgpu_fan_enabled;
120 struct amdgpu_mgpu_info
122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
128 /* delayed reset_func for XGMI configuration if necessary */
129 struct delayed_work delayed_reset_work;
133 struct amdgpu_watchdog_timer
135 bool timeout_fatal_disable;
136 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
139 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
142 * Modules parameters.
144 extern int amdgpu_modeset;
145 extern int amdgpu_vram_limit;
146 extern int amdgpu_vis_vram_limit;
147 extern int amdgpu_gart_size;
148 extern int amdgpu_gtt_size;
149 extern int amdgpu_moverate;
150 extern int amdgpu_benchmarking;
151 extern int amdgpu_testing;
152 extern int amdgpu_audio;
153 extern int amdgpu_disp_priority;
154 extern int amdgpu_hw_i2c;
155 extern int amdgpu_pcie_gen2;
156 extern int amdgpu_msi;
157 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
158 extern int amdgpu_dpm;
159 extern int amdgpu_fw_load_type;
160 extern int amdgpu_aspm;
161 extern int amdgpu_runtime_pm;
162 extern uint amdgpu_ip_block_mask;
163 extern int amdgpu_bapm;
164 extern int amdgpu_deep_color;
165 extern int amdgpu_vm_size;
166 extern int amdgpu_vm_block_size;
167 extern int amdgpu_vm_fragment_size;
168 extern int amdgpu_vm_fault_stop;
169 extern int amdgpu_vm_debug;
170 extern int amdgpu_vm_update_mode;
171 extern int amdgpu_exp_hw_support;
172 extern int amdgpu_dc;
173 extern int amdgpu_sched_jobs;
174 extern int amdgpu_sched_hw_submission;
175 extern uint amdgpu_pcie_gen_cap;
176 extern uint amdgpu_pcie_lane_cap;
177 extern uint amdgpu_cg_mask;
178 extern uint amdgpu_pg_mask;
179 extern uint amdgpu_sdma_phase_quantum;
180 extern char *amdgpu_disable_cu;
181 extern char *amdgpu_virtual_display;
182 extern uint amdgpu_pp_feature_mask;
183 extern uint amdgpu_force_long_training;
184 extern int amdgpu_job_hang_limit;
185 extern int amdgpu_lbpw;
186 extern int amdgpu_compute_multipipe;
187 extern int amdgpu_gpu_recovery;
188 extern int amdgpu_emu_mode;
189 extern uint amdgpu_smu_memory_pool_size;
190 extern int amdgpu_smu_pptable_id;
191 extern uint amdgpu_dc_feature_mask;
192 extern uint amdgpu_freesync_vid_mode;
193 extern uint amdgpu_dc_debug_mask;
194 extern uint amdgpu_dm_abm_level;
195 extern int amdgpu_backlight;
196 extern struct amdgpu_mgpu_info mgpu_info;
197 extern int amdgpu_ras_enable;
198 extern uint amdgpu_ras_mask;
199 extern int amdgpu_bad_page_threshold;
200 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
201 extern int amdgpu_async_gfx_ring;
202 extern int amdgpu_mcbp;
203 extern int amdgpu_discovery;
204 extern int amdgpu_mes;
205 extern int amdgpu_noretry;
206 extern int amdgpu_force_asic_type;
207 #ifdef CONFIG_HSA_AMD
208 extern int sched_policy;
209 extern bool debug_evictions;
210 extern bool no_system_mem_limit;
212 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
213 static const bool __maybe_unused debug_evictions; /* = false */
214 static const bool __maybe_unused no_system_mem_limit;
217 extern int amdgpu_tmz;
218 extern int amdgpu_reset_method;
220 #ifdef CONFIG_DRM_AMDGPU_SI
221 extern int amdgpu_si_support;
223 #ifdef CONFIG_DRM_AMDGPU_CIK
224 extern int amdgpu_cik_support;
226 extern int amdgpu_num_kcq;
228 #define AMDGPU_VM_MAX_NUM_CTX 4096
229 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
230 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
231 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
232 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
233 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
234 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
235 #define AMDGPUFB_CONN_LIMIT 4
236 #define AMDGPU_BIOS_NUM_SCRATCH 16
238 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
240 /* hard reset data */
241 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
244 #define AMDGPU_RESET_GFX (1 << 0)
245 #define AMDGPU_RESET_COMPUTE (1 << 1)
246 #define AMDGPU_RESET_DMA (1 << 2)
247 #define AMDGPU_RESET_CP (1 << 3)
248 #define AMDGPU_RESET_GRBM (1 << 4)
249 #define AMDGPU_RESET_DMA1 (1 << 5)
250 #define AMDGPU_RESET_RLC (1 << 6)
251 #define AMDGPU_RESET_SEM (1 << 7)
252 #define AMDGPU_RESET_IH (1 << 8)
253 #define AMDGPU_RESET_VMC (1 << 9)
254 #define AMDGPU_RESET_MC (1 << 10)
255 #define AMDGPU_RESET_DISPLAY (1 << 11)
256 #define AMDGPU_RESET_UVD (1 << 12)
257 #define AMDGPU_RESET_VCE (1 << 13)
258 #define AMDGPU_RESET_VCE1 (1 << 14)
260 /* max cursor sizes (in pixels) */
261 #define CIK_CURSOR_WIDTH 128
262 #define CIK_CURSOR_HEIGHT 128
264 struct amdgpu_device;
266 struct amdgpu_cs_parser;
268 struct amdgpu_irq_src;
270 struct amdgpu_bo_va_mapping;
271 struct kfd_vm_fault_info;
272 struct amdgpu_hive_info;
273 struct amdgpu_reset_context;
274 struct amdgpu_reset_control;
277 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
278 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
279 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
280 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
281 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
282 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
283 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
284 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
285 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
286 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
291 enum amdgpu_thermal_irq {
292 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
293 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
295 AMDGPU_THERMAL_IRQ_LAST
298 enum amdgpu_kiq_irq {
299 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
300 AMDGPU_CP_KIQ_IRQ_LAST
303 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
304 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
305 #define MAX_KIQ_REG_TRY 1000
307 int amdgpu_device_ip_set_clockgating_state(void *dev,
308 enum amd_ip_block_type block_type,
309 enum amd_clockgating_state state);
310 int amdgpu_device_ip_set_powergating_state(void *dev,
311 enum amd_ip_block_type block_type,
312 enum amd_powergating_state state);
313 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
315 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
316 enum amd_ip_block_type block_type);
317 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
318 enum amd_ip_block_type block_type);
320 #define AMDGPU_MAX_IP_NUM 16
322 struct amdgpu_ip_block_status {
326 bool late_initialized;
330 struct amdgpu_ip_block_version {
331 const enum amd_ip_block_type type;
335 const struct amd_ip_funcs *funcs;
338 #define HW_REV(_Major, _Minor, _Rev) \
339 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
341 struct amdgpu_ip_block {
342 struct amdgpu_ip_block_status status;
343 const struct amdgpu_ip_block_version *version;
346 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
347 enum amd_ip_block_type type,
348 u32 major, u32 minor);
350 struct amdgpu_ip_block *
351 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
352 enum amd_ip_block_type type);
354 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
355 const struct amdgpu_ip_block_version *ip_block_version);
360 bool amdgpu_get_bios(struct amdgpu_device *adev);
361 bool amdgpu_read_bios(struct amdgpu_device *adev);
367 #define AMDGPU_MAX_PPLL 3
369 struct amdgpu_clock {
370 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
371 struct amdgpu_pll spll;
372 struct amdgpu_pll mpll;
374 uint32_t default_mclk;
375 uint32_t default_sclk;
376 uint32_t default_dispclk;
377 uint32_t current_dispclk;
379 uint32_t max_pixel_clock;
382 /* sub-allocation manager, it has to be protected by another lock.
383 * By conception this is an helper for other part of the driver
384 * like the indirect buffer or semaphore, which both have their
387 * Principe is simple, we keep a list of sub allocation in offset
388 * order (first entry has offset == 0, last entry has the highest
391 * When allocating new object we first check if there is room at
392 * the end total_size - (last_object_offset + last_object_size) >=
393 * alloc_size. If so we allocate new object there.
395 * When there is not enough room at the end, we start waiting for
396 * each sub object until we reach object_offset+object_size >=
397 * alloc_size, this object then become the sub object we return.
399 * Alignment can't be bigger than page size.
401 * Hole are not considered for allocation to keep things simple.
402 * Assumption is that there won't be hole (all object on same
406 #define AMDGPU_SA_NUM_FENCE_LISTS 32
408 struct amdgpu_sa_manager {
409 wait_queue_head_t wq;
410 struct amdgpu_bo *bo;
411 struct list_head *hole;
412 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
413 struct list_head olist;
421 /* sub-allocation buffer */
422 struct amdgpu_sa_bo {
423 struct list_head olist;
424 struct list_head flist;
425 struct amdgpu_sa_manager *manager;
428 struct dma_fence *fence;
431 int amdgpu_fence_slab_init(void);
432 void amdgpu_fence_slab_fini(void);
438 struct amdgpu_flip_work {
439 struct delayed_work flip_work;
440 struct work_struct unpin_work;
441 struct amdgpu_device *adev;
445 struct drm_pending_vblank_event *event;
446 struct amdgpu_bo *old_abo;
447 struct dma_fence *excl;
448 unsigned shared_count;
449 struct dma_fence **shared;
450 struct dma_fence_cb cb;
460 struct amdgpu_sa_bo *sa_bo;
467 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
470 * file private structure
473 struct amdgpu_fpriv {
475 struct amdgpu_bo_va *prt_va;
476 struct amdgpu_bo_va *csa_va;
477 struct mutex bo_list_lock;
478 struct idr bo_list_handles;
479 struct amdgpu_ctx_mgr ctx_mgr;
482 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
484 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
486 enum amdgpu_ib_pool_type pool,
487 struct amdgpu_ib *ib);
488 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
489 struct dma_fence *f);
490 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
491 struct amdgpu_ib *ibs, struct amdgpu_job *job,
492 struct dma_fence **f);
493 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
494 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
495 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
500 struct amdgpu_cs_chunk {
506 struct amdgpu_cs_post_dep {
507 struct drm_syncobj *syncobj;
508 struct dma_fence_chain *chain;
512 struct amdgpu_cs_parser {
513 struct amdgpu_device *adev;
514 struct drm_file *filp;
515 struct amdgpu_ctx *ctx;
519 struct amdgpu_cs_chunk *chunks;
521 /* scheduler job object */
522 struct amdgpu_job *job;
523 struct drm_sched_entity *entity;
526 struct ww_acquire_ctx ticket;
527 struct amdgpu_bo_list *bo_list;
528 struct amdgpu_mn *mn;
529 struct amdgpu_bo_list_entry vm_pd;
530 struct list_head validated;
531 struct dma_fence *fence;
532 uint64_t bytes_moved_threshold;
533 uint64_t bytes_moved_vis_threshold;
534 uint64_t bytes_moved;
535 uint64_t bytes_moved_vis;
538 struct amdgpu_bo_list_entry uf_entry;
540 unsigned num_post_deps;
541 struct amdgpu_cs_post_dep *post_deps;
544 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
545 uint32_t ib_idx, int idx)
547 return p->job->ibs[ib_idx].ptr[idx];
550 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
551 uint32_t ib_idx, int idx,
554 p->job->ibs[ib_idx].ptr[idx] = value;
560 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
563 struct amdgpu_bo *wb_obj;
564 volatile uint32_t *wb;
566 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
567 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
570 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
571 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
576 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
582 void amdgpu_test_moves(struct amdgpu_device *adev);
585 * ASIC specific register table accessible by UMD
587 struct amdgpu_allowed_register_entry {
592 enum amd_reset_method {
593 AMD_RESET_METHOD_NONE = -1,
594 AMD_RESET_METHOD_LEGACY = 0,
595 AMD_RESET_METHOD_MODE0,
596 AMD_RESET_METHOD_MODE1,
597 AMD_RESET_METHOD_MODE2,
598 AMD_RESET_METHOD_BACO,
599 AMD_RESET_METHOD_PCI,
602 struct amdgpu_video_codec_info {
606 u32 max_pixels_per_frame;
610 struct amdgpu_video_codecs {
611 const u32 codec_count;
612 const struct amdgpu_video_codec_info *codec_array;
616 * ASIC specific functions.
618 struct amdgpu_asic_funcs {
619 bool (*read_disabled_bios)(struct amdgpu_device *adev);
620 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
621 u8 *bios, u32 length_bytes);
622 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
623 u32 sh_num, u32 reg_offset, u32 *value);
624 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
625 int (*reset)(struct amdgpu_device *adev);
626 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
627 /* get the reference clock */
628 u32 (*get_xclk)(struct amdgpu_device *adev);
629 /* MM block clocks */
630 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
631 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
632 /* static power management */
633 int (*get_pcie_lanes)(struct amdgpu_device *adev);
634 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
635 /* get config memsize register */
636 u32 (*get_config_memsize)(struct amdgpu_device *adev);
637 /* flush hdp write queue */
638 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
639 /* invalidate hdp read cache */
640 void (*invalidate_hdp)(struct amdgpu_device *adev,
641 struct amdgpu_ring *ring);
642 /* check if the asic needs a full reset of if soft reset will work */
643 bool (*need_full_reset)(struct amdgpu_device *adev);
644 /* initialize doorbell layout for specific asic*/
645 void (*init_doorbell_index)(struct amdgpu_device *adev);
646 /* PCIe bandwidth usage */
647 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
649 /* do we need to reset the asic at init time (e.g., kexec) */
650 bool (*need_reset_on_init)(struct amdgpu_device *adev);
651 /* PCIe replay counter */
652 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
653 /* device supports BACO */
654 bool (*supports_baco)(struct amdgpu_device *adev);
655 /* pre asic_init quirks */
656 void (*pre_asic_init)(struct amdgpu_device *adev);
657 /* enter/exit umd stable pstate */
658 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
659 /* query video codecs */
660 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
661 const struct amdgpu_video_codecs **codecs);
667 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
668 struct drm_file *filp);
670 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
671 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
672 struct drm_file *filp);
673 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
674 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
675 struct drm_file *filp);
677 /* VRAM scratch page for HDP bug, default vram page */
678 struct amdgpu_vram_scratch {
679 struct amdgpu_bo *robj;
680 volatile uint32_t *ptr;
687 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
688 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
691 * Core structure, functions and helpers.
693 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
694 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
696 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
697 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
699 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
700 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
702 struct amdgpu_mmio_remap {
704 resource_size_t bus_addr;
707 /* Define the HW IP blocks will be used in driver , add more if necessary */
708 enum amd_hw_ip_block_type {
726 JPEG_HWIP = VCN_HWIP,
741 #define HWIP_MAX_INSTANCE 8
743 struct amd_powerplay {
745 const struct amd_pm_funcs *pp_funcs;
748 /* polaris10 kickers */
749 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
755 ((did == 0x6FDF) && \
760 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
764 /* polaris11 kickers */
765 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
768 ((did == 0x67FF) && \
773 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
776 /* polaris12 kickers */
777 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
782 ((did == 0x6981) && \
787 #define AMDGPU_RESET_MAGIC_NUM 64
788 #define AMDGPU_MAX_DF_PERFMONS 4
789 struct amdgpu_device {
791 struct pci_dev *pdev;
792 struct drm_device ddev;
794 #ifdef CONFIG_DRM_AMD_ACP
795 struct amdgpu_acp acp;
797 struct amdgpu_hive_info *hive;
799 enum amd_asic_type asic_type;
802 uint32_t external_rev_id;
804 unsigned long apu_flags;
806 const struct amdgpu_asic_funcs *asic_funcs;
810 struct notifier_block acpi_nb;
811 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
812 struct debugfs_blob_wrapper debugfs_vbios_blob;
813 struct mutex srbm_mutex;
814 /* GRBM index mutex. Protects concurrent access to GRBM index */
815 struct mutex grbm_idx_mutex;
816 struct dev_pm_domain vga_pm_domain;
817 bool have_disp_power_ref;
818 bool have_atomics_support;
824 uint32_t bios_scratch_reg_offset;
825 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
827 /* Register/doorbell mmio */
828 resource_size_t rmmio_base;
829 resource_size_t rmmio_size;
831 /* protects concurrent MM_INDEX/DATA based register access */
832 spinlock_t mmio_idx_lock;
833 struct amdgpu_mmio_remap rmmio_remap;
834 /* protects concurrent SMC based register access */
835 spinlock_t smc_idx_lock;
836 amdgpu_rreg_t smc_rreg;
837 amdgpu_wreg_t smc_wreg;
838 /* protects concurrent PCIE register access */
839 spinlock_t pcie_idx_lock;
840 amdgpu_rreg_t pcie_rreg;
841 amdgpu_wreg_t pcie_wreg;
842 amdgpu_rreg_t pciep_rreg;
843 amdgpu_wreg_t pciep_wreg;
844 amdgpu_rreg64_t pcie_rreg64;
845 amdgpu_wreg64_t pcie_wreg64;
846 /* protects concurrent UVD register access */
847 spinlock_t uvd_ctx_idx_lock;
848 amdgpu_rreg_t uvd_ctx_rreg;
849 amdgpu_wreg_t uvd_ctx_wreg;
850 /* protects concurrent DIDT register access */
851 spinlock_t didt_idx_lock;
852 amdgpu_rreg_t didt_rreg;
853 amdgpu_wreg_t didt_wreg;
854 /* protects concurrent gc_cac register access */
855 spinlock_t gc_cac_idx_lock;
856 amdgpu_rreg_t gc_cac_rreg;
857 amdgpu_wreg_t gc_cac_wreg;
858 /* protects concurrent se_cac register access */
859 spinlock_t se_cac_idx_lock;
860 amdgpu_rreg_t se_cac_rreg;
861 amdgpu_wreg_t se_cac_wreg;
862 /* protects concurrent ENDPOINT (audio) register access */
863 spinlock_t audio_endpt_idx_lock;
864 amdgpu_block_rreg_t audio_endpt_rreg;
865 amdgpu_block_wreg_t audio_endpt_wreg;
866 struct amdgpu_doorbell doorbell;
869 struct amdgpu_clock clock;
872 struct amdgpu_gmc gmc;
873 struct amdgpu_gart gart;
874 dma_addr_t dummy_page_addr;
875 struct amdgpu_vm_manager vm_manager;
876 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
879 /* memory management */
880 struct amdgpu_mman mman;
881 struct amdgpu_vram_scratch vram_scratch;
883 atomic64_t num_bytes_moved;
884 atomic64_t num_evictions;
885 atomic64_t num_vram_cpu_page_faults;
886 atomic_t gpu_reset_counter;
887 atomic_t vram_lost_counter;
889 /* data for buffer migration throttling */
893 s64 accum_us; /* accumulated microseconds */
894 s64 accum_us_vis; /* for visible VRAM */
899 bool enable_virtual_display;
900 struct amdgpu_mode_info mode_info;
901 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
902 struct work_struct hotplug_work;
903 struct amdgpu_irq_src crtc_irq;
904 struct amdgpu_irq_src vline0_irq;
905 struct amdgpu_irq_src vupdate_irq;
906 struct amdgpu_irq_src pageflip_irq;
907 struct amdgpu_irq_src hpd_irq;
908 struct amdgpu_irq_src dmub_trace_irq;
909 struct amdgpu_irq_src dmub_outbox_irq;
914 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
916 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
917 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
920 struct amdgpu_irq irq;
923 struct amd_powerplay powerplay;
924 bool pp_force_state_enabled;
927 struct smu_context smu;
935 struct amdgpu_nbio nbio;
938 struct amdgpu_hdp hdp;
941 struct amdgpu_smuio smuio;
944 struct amdgpu_mmhub mmhub;
947 struct amdgpu_gfxhub gfxhub;
950 struct amdgpu_gfx gfx;
953 struct amdgpu_sdma sdma;
956 struct amdgpu_uvd uvd;
959 struct amdgpu_vce vce;
962 struct amdgpu_vcn vcn;
965 struct amdgpu_jpeg jpeg;
968 struct amdgpu_firmware firmware;
971 struct psp_context psp;
974 struct amdgpu_gds gds;
977 struct amdgpu_kfd_dev kfd;
980 struct amdgpu_umc umc;
982 /* display related functionality */
983 struct amdgpu_display_manager dm;
987 struct amdgpu_mes mes;
992 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
993 uint32_t harvest_ip_mask;
995 struct mutex mn_lock;
996 DECLARE_HASHTABLE(mn_hash, 7);
998 /* tracking pinned memory */
999 atomic64_t vram_pin_size;
1000 atomic64_t visible_pin_size;
1001 atomic64_t gart_pin_size;
1003 /* soc15 register offset based on ip, instance and segment */
1004 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1006 /* delayed work_func for deferring clockgating during resume */
1007 struct delayed_work delayed_init_work;
1009 struct amdgpu_virt virt;
1011 /* link all shadow bo */
1012 struct list_head shadow_list;
1013 struct mutex shadow_list_lock;
1015 /* record hw reset is performed */
1017 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1025 atomic_t in_gpu_reset;
1026 enum pp_mp1_state mp1_state;
1027 struct rw_semaphore reset_sem;
1028 struct amdgpu_doorbell_index doorbell_index;
1030 struct mutex notifier_lock;
1033 struct work_struct xgmi_reset_work;
1034 struct list_head reset_list;
1039 long compute_timeout;
1042 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1044 /* enable runtime pm on the device */
1050 bool ucode_sysfs_en;
1052 /* Chip product information */
1053 char product_number[16];
1054 char product_name[32];
1057 struct amdgpu_autodump autodump;
1059 atomic_t throttling_logging_enabled;
1060 struct ratelimit_state throttling_logging_rs;
1061 uint32_t ras_hw_enabled;
1062 uint32_t ras_enabled;
1064 bool in_pci_err_recovery;
1065 struct pci_saved_state *pci_state;
1067 struct amdgpu_reset_control *reset_cntl;
1070 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1072 return container_of(ddev, struct amdgpu_device, ddev);
1075 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1080 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1082 return container_of(bdev, struct amdgpu_device, mman.bdev);
1085 int amdgpu_device_init(struct amdgpu_device *adev,
1087 void amdgpu_device_fini(struct amdgpu_device *adev);
1088 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1090 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1091 uint32_t *buf, size_t size, bool write);
1092 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1093 uint32_t reg, uint32_t acc_flags);
1094 void amdgpu_device_wreg(struct amdgpu_device *adev,
1095 uint32_t reg, uint32_t v,
1096 uint32_t acc_flags);
1097 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1098 uint32_t reg, uint32_t v);
1099 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1100 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1102 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1103 u32 pcie_index, u32 pcie_data,
1105 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1106 u32 pcie_index, u32 pcie_data,
1108 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1109 u32 pcie_index, u32 pcie_data,
1110 u32 reg_addr, u32 reg_data);
1111 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1112 u32 pcie_index, u32 pcie_data,
1113 u32 reg_addr, u64 reg_data);
1115 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1116 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1118 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1119 struct amdgpu_reset_context *reset_context);
1121 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1122 struct amdgpu_reset_context *reset_context);
1124 int emu_soc_asic_init(struct amdgpu_device *adev);
1127 * Registers read & write functions.
1129 #define AMDGPU_REGS_NO_KIQ (1<<1)
1130 #define AMDGPU_REGS_RLC (1<<2)
1132 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1133 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1135 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1136 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1138 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1139 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1141 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1142 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1143 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1144 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1145 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1146 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1147 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1148 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1149 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1150 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1151 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1152 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1153 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1154 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1155 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1156 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1157 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1158 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1159 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1160 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1161 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1162 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1163 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1164 #define WREG32_P(reg, val, mask) \
1166 uint32_t tmp_ = RREG32(reg); \
1168 tmp_ |= ((val) & ~(mask)); \
1169 WREG32(reg, tmp_); \
1171 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1172 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1173 #define WREG32_PLL_P(reg, val, mask) \
1175 uint32_t tmp_ = RREG32_PLL(reg); \
1177 tmp_ |= ((val) & ~(mask)); \
1178 WREG32_PLL(reg, tmp_); \
1181 #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1183 u32 tmp = RREG32_SMC(_Reg); \
1185 tmp |= ((_Val) & ~(_Mask)); \
1186 WREG32_SMC(_Reg, tmp); \
1189 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1191 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1192 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1194 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1195 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1196 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1198 #define REG_GET_FIELD(value, reg, field) \
1199 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1201 #define WREG32_FIELD(reg, field, val) \
1202 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1204 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1205 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1210 #define RBIOS8(i) (adev->bios[i])
1211 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1212 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1217 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1218 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1219 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1220 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1221 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1222 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1223 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1224 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1225 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1226 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1227 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1228 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1229 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1230 #define amdgpu_asic_flush_hdp(adev, r) \
1231 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1232 #define amdgpu_asic_invalidate_hdp(adev, r) \
1233 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r)))
1234 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1235 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1236 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1237 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1238 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1239 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1240 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1241 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1242 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1243 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1245 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1247 /* Common functions */
1248 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1249 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1250 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1251 struct amdgpu_job* job);
1252 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1253 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1254 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1256 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1258 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1259 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1260 const u32 *registers,
1261 const u32 array_size);
1263 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1264 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1265 bool amdgpu_device_supports_px(struct drm_device *dev);
1266 bool amdgpu_device_supports_boco(struct drm_device *dev);
1267 bool amdgpu_device_supports_baco(struct drm_device *dev);
1268 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1269 struct amdgpu_device *peer_adev);
1270 int amdgpu_device_baco_enter(struct drm_device *dev);
1271 int amdgpu_device_baco_exit(struct drm_device *dev);
1274 #if defined(CONFIG_VGA_SWITCHEROO)
1275 void amdgpu_register_atpx_handler(void);
1276 void amdgpu_unregister_atpx_handler(void);
1277 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1278 bool amdgpu_is_atpx_hybrid(void);
1279 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1280 bool amdgpu_has_atpx(void);
1282 static inline void amdgpu_register_atpx_handler(void) {}
1283 static inline void amdgpu_unregister_atpx_handler(void) {}
1284 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1285 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1286 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1287 static inline bool amdgpu_has_atpx(void) { return false; }
1290 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1291 void *amdgpu_atpx_get_dhandle(void);
1293 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1299 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1300 extern const int amdgpu_max_kms_ioctl;
1302 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1303 void amdgpu_driver_unload_kms(struct drm_device *dev);
1304 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1305 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1306 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1307 struct drm_file *file_priv);
1308 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1309 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1310 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1311 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1312 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1313 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1314 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1316 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1317 struct drm_file *filp);
1320 * functions used by amdgpu_encoder.c
1322 struct amdgpu_afmt_acr {
1336 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1339 #if defined(CONFIG_ACPI)
1340 int amdgpu_acpi_init(struct amdgpu_device *adev);
1341 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1342 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1343 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1344 u8 perf_req, bool advertise);
1345 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1347 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1348 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev);
1349 void amdgpu_acpi_detect(void);
1351 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1352 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1353 static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; }
1354 static inline void amdgpu_acpi_detect(void) { }
1357 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1358 uint64_t addr, struct amdgpu_bo **bo,
1359 struct amdgpu_bo_va_mapping **mapping);
1361 #if defined(CONFIG_DRM_AMD_DC)
1362 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1364 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1368 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1369 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1371 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1372 pci_channel_state_t state);
1373 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1374 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1375 void amdgpu_pci_resume(struct pci_dev *pdev);
1377 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1378 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1380 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1382 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1383 enum amd_clockgating_state state);
1384 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1385 enum amd_powergating_state state);
1387 #include "amdgpu_object.h"
1389 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1391 return adev->gmc.tmz_enabled;
1394 static inline int amdgpu_in_reset(struct amdgpu_device *adev)
1396 return atomic_read(&adev->in_gpu_reset);