1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Whiskey Cove PMIC GPIO Driver
5 * This driver is written based on gpio-crystalcove.c
7 * Copyright (C) 2016 Intel Corporation. All rights reserved.
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/mfd/intel_soc_pmic.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/seq_file.h>
20 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
24 * Each pin has one output control register and one input control register.
26 #define BANK0_NR_PINS 7
27 #define BANK1_NR_PINS 4
28 #define BANK2_NR_PINS 2
29 #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
30 #define WCOVE_VGPIO_NUM 94
31 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
32 #define GPIO_OUT_CTRL_BASE 0x4e44
33 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
34 #define GPIO_IN_CTRL_BASE 0x4e51
37 * GPIO interrupts are organized in two groups:
38 * Group 0: Bank 0 pins (Pin 0 - 6)
39 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
40 * Each group has two registers (one bit per pin): status and mask.
42 #define GROUP0_NR_IRQS 7
43 #define GROUP1_NR_IRQS 6
44 #define IRQ_MASK_BASE 0x4e19
45 #define IRQ_STATUS_BASE 0x4e0b
46 #define GPIO_IRQ0_MASK GENMASK(6, 0)
47 #define GPIO_IRQ1_MASK GENMASK(5, 0)
48 #define UPDATE_IRQ_TYPE BIT(0)
49 #define UPDATE_IRQ_MASK BIT(1)
51 #define CTLI_INTCNT_DIS (0 << 1)
52 #define CTLI_INTCNT_NE (1 << 1)
53 #define CTLI_INTCNT_PE (2 << 1)
54 #define CTLI_INTCNT_BE (3 << 1)
56 #define CTLO_DIR_IN (0 << 5)
57 #define CTLO_DIR_OUT (1 << 5)
59 #define CTLO_DRV_MASK (1 << 4)
60 #define CTLO_DRV_OD (0 << 4)
61 #define CTLO_DRV_CMOS (1 << 4)
63 #define CTLO_DRV_REN (1 << 3)
65 #define CTLO_RVAL_2KDOWN (0 << 1)
66 #define CTLO_RVAL_2KUP (1 << 1)
67 #define CTLO_RVAL_50KDOWN (2 << 1)
68 #define CTLO_RVAL_50KUP (3 << 1)
70 #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
71 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
81 * struct wcove_gpio - Whiskey Cove GPIO controller
82 * @buslock: for bus lock/sync and unlock.
83 * @chip: the abstract gpio_chip structure.
84 * @dev: the gpio device
85 * @regmap: the regmap from the parent device.
86 * @regmap_irq_chip: the regmap of the gpio irq chip.
87 * @update: pending IRQ setting update, to be written to the chip upon unlock.
88 * @intcnt: the Interrupt Detect value to be written.
89 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
93 struct gpio_chip chip;
95 struct regmap *regmap;
96 struct regmap_irq_chip_data *regmap_irq_chip;
102 static inline int to_reg(int gpio, enum ctrl_register reg_type)
106 if (gpio >= WCOVE_GPIO_NUM)
109 if (reg_type == CTRL_IN)
110 reg = GPIO_IN_CTRL_BASE + gpio;
112 reg = GPIO_OUT_CTRL_BASE + gpio;
117 static inline int to_ireg(int gpio, enum ctrl_register type, unsigned int *mask)
119 unsigned int reg = type == IRQ_STATUS ? IRQ_STATUS_BASE : IRQ_MASK_BASE;
121 if (gpio < GROUP0_NR_IRQS) {
126 *mask = BIT(gpio - GROUP0_NR_IRQS);
132 static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
134 unsigned int mask, reg = to_ireg(gpio, IRQ_MASK, &mask);
136 if (wg->set_irq_mask)
137 regmap_set_bits(wg->regmap, reg, mask);
139 regmap_clear_bits(wg->regmap, reg, mask);
142 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
144 int reg = to_reg(gpio, CTRL_IN);
149 regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
152 static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
154 struct wcove_gpio *wg = gpiochip_get_data(chip);
155 int reg = to_reg(gpio, CTRL_OUT);
160 return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
163 static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
166 struct wcove_gpio *wg = gpiochip_get_data(chip);
167 int reg = to_reg(gpio, CTRL_OUT);
172 return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
175 static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
177 struct wcove_gpio *wg = gpiochip_get_data(chip);
179 int ret, reg = to_reg(gpio, CTRL_OUT);
182 return GPIO_LINE_DIRECTION_OUT;
184 ret = regmap_read(wg->regmap, reg, &val);
188 if (val & CTLO_DIR_OUT)
189 return GPIO_LINE_DIRECTION_OUT;
191 return GPIO_LINE_DIRECTION_IN;
194 static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
196 struct wcove_gpio *wg = gpiochip_get_data(chip);
198 int ret, reg = to_reg(gpio, CTRL_IN);
203 ret = regmap_read(wg->regmap, reg, &val);
210 static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
212 struct wcove_gpio *wg = gpiochip_get_data(chip);
213 int reg = to_reg(gpio, CTRL_OUT);
219 regmap_set_bits(wg->regmap, reg, 1);
221 regmap_clear_bits(wg->regmap, reg, 1);
224 static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
225 unsigned long config)
227 struct wcove_gpio *wg = gpiochip_get_data(chip);
228 int reg = to_reg(gpio, CTRL_OUT);
233 switch (pinconf_to_config_param(config)) {
234 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
235 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
237 case PIN_CONFIG_DRIVE_PUSH_PULL:
238 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
247 static int wcove_irq_type(struct irq_data *data, unsigned int type)
249 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
250 struct wcove_gpio *wg = gpiochip_get_data(chip);
252 if (data->hwirq >= WCOVE_GPIO_NUM)
257 wg->intcnt = CTLI_INTCNT_DIS;
259 case IRQ_TYPE_EDGE_BOTH:
260 wg->intcnt = CTLI_INTCNT_BE;
262 case IRQ_TYPE_EDGE_RISING:
263 wg->intcnt = CTLI_INTCNT_PE;
265 case IRQ_TYPE_EDGE_FALLING:
266 wg->intcnt = CTLI_INTCNT_NE;
272 wg->update |= UPDATE_IRQ_TYPE;
277 static void wcove_bus_lock(struct irq_data *data)
279 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
280 struct wcove_gpio *wg = gpiochip_get_data(chip);
282 mutex_lock(&wg->buslock);
285 static void wcove_bus_sync_unlock(struct irq_data *data)
287 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
288 struct wcove_gpio *wg = gpiochip_get_data(chip);
289 int gpio = data->hwirq;
291 if (wg->update & UPDATE_IRQ_TYPE)
292 wcove_update_irq_ctrl(wg, gpio);
293 if (wg->update & UPDATE_IRQ_MASK)
294 wcove_update_irq_mask(wg, gpio);
297 mutex_unlock(&wg->buslock);
300 static void wcove_irq_unmask(struct irq_data *data)
302 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
303 struct wcove_gpio *wg = gpiochip_get_data(chip);
305 if (data->hwirq >= WCOVE_GPIO_NUM)
308 wg->set_irq_mask = false;
309 wg->update |= UPDATE_IRQ_MASK;
312 static void wcove_irq_mask(struct irq_data *data)
314 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
315 struct wcove_gpio *wg = gpiochip_get_data(chip);
317 if (data->hwirq >= WCOVE_GPIO_NUM)
320 wg->set_irq_mask = true;
321 wg->update |= UPDATE_IRQ_MASK;
324 static struct irq_chip wcove_irqchip = {
325 .name = "Whiskey Cove",
326 .irq_mask = wcove_irq_mask,
327 .irq_unmask = wcove_irq_unmask,
328 .irq_set_type = wcove_irq_type,
329 .irq_bus_lock = wcove_bus_lock,
330 .irq_bus_sync_unlock = wcove_bus_sync_unlock,
333 static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
335 struct wcove_gpio *wg = (struct wcove_gpio *)data;
336 unsigned int virq, gpio;
337 unsigned long pending;
340 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
341 dev_err(wg->dev, "Failed to read irq status register\n");
345 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
349 /* Iterate until no interrupt is pending */
351 /* One iteration is for all pending bits */
352 for_each_set_bit(gpio, &pending, WCOVE_GPIO_NUM) {
353 unsigned int mask, reg = to_ireg(gpio, IRQ_STATUS, &mask);
355 virq = irq_find_mapping(wg->chip.irq.domain, gpio);
356 handle_nested_irq(virq);
357 regmap_set_bits(wg->regmap, reg, mask);
361 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
362 dev_err(wg->dev, "Failed to read irq status\n");
366 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
372 static void wcove_gpio_dbg_show(struct seq_file *s,
373 struct gpio_chip *chip)
375 unsigned int ctlo, ctli, irq_mask, irq_status;
376 struct wcove_gpio *wg = gpiochip_get_data(chip);
377 int gpio, mask, ret = 0;
379 for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
380 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
381 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
382 ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask);
383 ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status);
385 pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
389 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
390 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
391 ctli & 0x1 ? "hi" : "lo",
392 ctli & CTLI_INTCNT_NE ? "fall" : " ",
393 ctli & CTLI_INTCNT_PE ? "rise" : " ",
395 irq_mask & mask ? "mask " : "unmask",
396 irq_status & mask ? "pending" : " ");
400 static int wcove_gpio_probe(struct platform_device *pdev)
402 struct intel_soc_pmic *pmic;
403 struct wcove_gpio *wg;
406 struct gpio_irq_chip *girq;
409 * This gpio platform device is created by a mfd device (see
410 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
411 * shared by all sub-devices created by the mfd device, the regmap
412 * pointer for instance, is stored as driver data of the mfd device
415 pmic = dev_get_drvdata(pdev->dev.parent);
419 irq = platform_get_irq(pdev, 0);
425 wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
429 wg->regmap_irq_chip = pmic->irq_chip_data;
431 platform_set_drvdata(pdev, wg);
433 mutex_init(&wg->buslock);
434 wg->chip.label = KBUILD_MODNAME;
435 wg->chip.direction_input = wcove_gpio_dir_in;
436 wg->chip.direction_output = wcove_gpio_dir_out;
437 wg->chip.get_direction = wcove_gpio_get_direction;
438 wg->chip.get = wcove_gpio_get;
439 wg->chip.set = wcove_gpio_set;
440 wg->chip.set_config = wcove_gpio_set_config;
442 wg->chip.ngpio = WCOVE_VGPIO_NUM;
443 wg->chip.can_sleep = true;
444 wg->chip.parent = pdev->dev.parent;
445 wg->chip.dbg_show = wcove_gpio_dbg_show;
447 wg->regmap = pmic->regmap;
449 virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
451 dev_err(dev, "Failed to get virq by irq %d\n", irq);
455 girq = &wg->chip.irq;
456 girq->chip = &wcove_irqchip;
457 /* This will let us handle the parent IRQ in the driver */
458 girq->parent_handler = NULL;
459 girq->num_parents = 0;
460 girq->parents = NULL;
461 girq->default_type = IRQ_TYPE_NONE;
462 girq->handler = handle_simple_irq;
463 girq->threaded = true;
465 ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler,
466 IRQF_ONESHOT, pdev->name, wg);
468 dev_err(dev, "Failed to request irq %d\n", virq);
472 ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
474 dev_err(dev, "Failed to add gpiochip: %d\n", ret);
478 /* Enable GPIO0 interrupts */
479 ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 0, GPIO_IRQ0_MASK);
483 /* Enable GPIO1 interrupts */
484 ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK);
492 * Whiskey Cove PMIC itself is a analog device(but with digital control
493 * interface) providing power management support for other devices in
494 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
496 static struct platform_driver wcove_gpio_driver = {
498 .name = "bxt_wcove_gpio",
500 .probe = wcove_gpio_probe,
503 module_platform_driver(wcove_gpio_driver);
505 MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
506 MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
507 MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
508 MODULE_LICENSE("GPL v2");
509 MODULE_ALIAS("platform:bxt_wcove_gpio");