1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2017 NVIDIA Corporation
5 * Author: Thierry Reding <treding@nvidia.com>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
15 #include <dt-bindings/gpio/tegra186-gpio.h>
16 #include <dt-bindings/gpio/tegra194-gpio.h>
18 /* security registers */
19 #define TEGRA186_GPIO_CTL_SCR 0x0c
20 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
21 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
23 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
25 /* control registers */
26 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
27 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
28 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
29 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
30 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
35 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
36 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
38 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
39 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
41 #define TEGRA186_GPIO_INPUT 0x08
42 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
44 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
45 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
47 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
48 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
50 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
52 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
54 struct tegra_gpio_port {
61 struct tegra186_pin_range {
66 struct tegra_gpio_soc {
67 const struct tegra_gpio_port *ports;
68 unsigned int num_ports;
70 unsigned int instance;
72 const struct tegra186_pin_range *pin_ranges;
73 unsigned int num_pin_ranges;
78 struct gpio_chip gpio;
83 const struct tegra_gpio_soc *soc;
89 static const struct tegra_gpio_port *
90 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
92 unsigned int start = 0, i;
94 for (i = 0; i < gpio->soc->num_ports; i++) {
95 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
97 if (*pin >= start && *pin < start + port->pins) {
108 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
111 const struct tegra_gpio_port *port;
114 port = tegra186_gpio_get_port(gpio, &pin);
118 offset = port->bank * 0x1000 + port->port * 0x200;
120 return gpio->base + offset + pin * 0x20;
123 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
126 struct tegra_gpio *gpio = gpiochip_get_data(chip);
130 base = tegra186_gpio_get_base(gpio, offset);
131 if (WARN_ON(base == NULL))
134 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
135 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
136 return GPIO_LINE_DIRECTION_OUT;
138 return GPIO_LINE_DIRECTION_IN;
141 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
144 struct tegra_gpio *gpio = gpiochip_get_data(chip);
148 base = tegra186_gpio_get_base(gpio, offset);
149 if (WARN_ON(base == NULL))
152 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
153 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
154 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
156 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
157 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
158 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
159 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
164 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
165 unsigned int offset, int level)
167 struct tegra_gpio *gpio = gpiochip_get_data(chip);
171 /* configure output level first */
172 chip->set(chip, offset, level);
174 base = tegra186_gpio_get_base(gpio, offset);
175 if (WARN_ON(base == NULL))
178 /* set the direction */
179 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
180 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
181 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
183 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
184 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
185 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
186 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
191 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
193 struct tegra_gpio *gpio = gpiochip_get_data(chip);
197 base = tegra186_gpio_get_base(gpio, offset);
198 if (WARN_ON(base == NULL))
201 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
202 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
203 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
205 value = readl(base + TEGRA186_GPIO_INPUT);
207 return value & BIT(0);
210 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
213 struct tegra_gpio *gpio = gpiochip_get_data(chip);
217 base = tegra186_gpio_get_base(gpio, offset);
218 if (WARN_ON(base == NULL))
221 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
223 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
225 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
227 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
230 static int tegra186_gpio_set_config(struct gpio_chip *chip,
232 unsigned long config)
234 struct tegra_gpio *gpio = gpiochip_get_data(chip);
238 base = tegra186_gpio_get_base(gpio, offset);
242 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
245 debounce = pinconf_to_config_argument(config);
248 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
251 if (debounce > 255000)
254 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
256 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
257 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
259 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
260 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
261 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
266 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
268 struct tegra_gpio *gpio = gpiochip_get_data(chip);
269 struct pinctrl_dev *pctldev;
270 struct device_node *np;
274 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
277 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
281 pctldev = of_pinctrl_get(np);
284 return -EPROBE_DEFER;
286 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
287 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
288 const char *group = gpio->soc->pin_ranges[i].group;
293 if (port >= gpio->soc->num_ports) {
294 dev_warn(chip->parent, "invalid port %u for %s\n",
299 for (j = 0; j < port; j++)
300 pin += gpio->soc->ports[j].pins;
302 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
310 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
311 const struct of_phandle_args *spec,
314 struct tegra_gpio *gpio = gpiochip_get_data(chip);
315 unsigned int port, pin, i, offset = 0;
317 if (WARN_ON(chip->of_gpio_n_cells < 2))
320 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
323 port = spec->args[0] / 8;
324 pin = spec->args[0] % 8;
326 if (port >= gpio->soc->num_ports) {
327 dev_err(chip->parent, "invalid port number: %u\n", port);
331 for (i = 0; i < port; i++)
332 offset += gpio->soc->ports[i].pins;
335 *flags = spec->args[1];
340 static void tegra186_irq_ack(struct irq_data *data)
342 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
345 base = tegra186_gpio_get_base(gpio, data->hwirq);
346 if (WARN_ON(base == NULL))
349 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
352 static void tegra186_irq_mask(struct irq_data *data)
354 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
358 base = tegra186_gpio_get_base(gpio, data->hwirq);
359 if (WARN_ON(base == NULL))
362 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
363 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
364 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
367 static void tegra186_irq_unmask(struct irq_data *data)
369 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
373 base = tegra186_gpio_get_base(gpio, data->hwirq);
374 if (WARN_ON(base == NULL))
377 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
378 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
379 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
382 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
384 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
388 base = tegra186_gpio_get_base(gpio, data->hwirq);
389 if (WARN_ON(base == NULL))
392 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
393 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
394 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
396 switch (type & IRQ_TYPE_SENSE_MASK) {
400 case IRQ_TYPE_EDGE_RISING:
401 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
402 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
405 case IRQ_TYPE_EDGE_FALLING:
406 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
409 case IRQ_TYPE_EDGE_BOTH:
410 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
413 case IRQ_TYPE_LEVEL_HIGH:
414 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
415 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
418 case IRQ_TYPE_LEVEL_LOW:
419 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
426 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
428 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
429 irq_set_handler_locked(data, handle_level_irq);
431 irq_set_handler_locked(data, handle_edge_irq);
433 if (data->parent_data)
434 return irq_chip_set_type_parent(data, type);
439 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
441 if (data->parent_data)
442 return irq_chip_set_wake_parent(data, on);
447 static void tegra186_gpio_irq(struct irq_desc *desc)
449 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
450 struct irq_domain *domain = gpio->gpio.irq.domain;
451 struct irq_chip *chip = irq_desc_get_chip(desc);
452 unsigned int parent = irq_desc_get_irq(desc);
453 unsigned int i, offset = 0;
455 chained_irq_enter(chip, desc);
457 for (i = 0; i < gpio->soc->num_ports; i++) {
458 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
463 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
465 /* skip ports that are not associated with this bank */
466 if (parent != gpio->irq[port->bank])
469 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
471 for_each_set_bit(pin, &value, port->pins) {
472 int ret = generic_handle_domain_irq(domain, offset + pin);
473 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
477 offset += port->pins;
480 chained_irq_exit(chip, desc);
483 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
484 struct irq_fwspec *fwspec,
485 unsigned long *hwirq,
488 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
489 unsigned int port, pin, i, offset = 0;
491 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
494 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
497 port = fwspec->param[0] / 8;
498 pin = fwspec->param[0] % 8;
500 if (port >= gpio->soc->num_ports)
503 for (i = 0; i < port; i++)
504 offset += gpio->soc->ports[i].pins;
506 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
507 *hwirq = offset + pin;
512 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
513 unsigned int parent_hwirq,
514 unsigned int parent_type)
516 struct tegra_gpio *gpio = gpiochip_get_data(chip);
517 struct irq_fwspec *fwspec;
519 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
523 fwspec->fwnode = chip->irq.parent_domain->fwnode;
524 fwspec->param_count = 3;
525 fwspec->param[0] = gpio->soc->instance;
526 fwspec->param[1] = parent_hwirq;
527 fwspec->param[2] = parent_type;
532 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
535 unsigned int *parent_hwirq,
536 unsigned int *parent_type)
538 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
544 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
547 struct tegra_gpio *gpio = gpiochip_get_data(chip);
550 for (i = 0; i < gpio->soc->num_ports; i++) {
551 if (offset < gpio->soc->ports[i].pins)
554 offset -= gpio->soc->ports[i].pins;
557 return offset + i * 8;
560 static const struct of_device_id tegra186_pmc_of_match[] = {
561 { .compatible = "nvidia,tegra186-pmc" },
562 { .compatible = "nvidia,tegra194-pmc" },
566 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
571 for (i = 0; i < gpio->soc->num_ports; i++) {
572 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
573 unsigned int offset, p = port->port;
576 base = gpio->secure + port->bank * 0x1000 + 0x800;
578 value = readl(base + TEGRA186_GPIO_CTL_SCR);
581 * For controllers that haven't been locked down yet, make
582 * sure to program the default interrupt route mapping.
584 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
585 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
586 for (j = 0; j < 8; j++) {
587 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
589 value = readl(base + offset);
590 value = BIT(port->pins) - 1;
591 writel(value, base + offset);
597 static int tegra186_gpio_probe(struct platform_device *pdev)
599 unsigned int i, j, offset;
600 struct gpio_irq_chip *irq;
601 struct tegra_gpio *gpio;
602 struct device_node *np;
606 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
610 gpio->soc = of_device_get_match_data(&pdev->dev);
612 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
613 if (IS_ERR(gpio->secure))
614 return PTR_ERR(gpio->secure);
616 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
617 if (IS_ERR(gpio->base))
618 return PTR_ERR(gpio->base);
620 err = platform_irq_count(pdev);
626 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
631 for (i = 0; i < gpio->num_irq; i++) {
632 err = platform_get_irq(pdev, i);
639 gpio->gpio.label = gpio->soc->name;
640 gpio->gpio.parent = &pdev->dev;
642 gpio->gpio.request = gpiochip_generic_request;
643 gpio->gpio.free = gpiochip_generic_free;
644 gpio->gpio.get_direction = tegra186_gpio_get_direction;
645 gpio->gpio.direction_input = tegra186_gpio_direction_input;
646 gpio->gpio.direction_output = tegra186_gpio_direction_output;
647 gpio->gpio.get = tegra186_gpio_get;
648 gpio->gpio.set = tegra186_gpio_set;
649 gpio->gpio.set_config = tegra186_gpio_set_config;
650 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
652 gpio->gpio.base = -1;
654 for (i = 0; i < gpio->soc->num_ports; i++)
655 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
657 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
658 sizeof(*names), GFP_KERNEL);
662 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
663 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
666 for (j = 0; j < port->pins; j++) {
667 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
668 "P%s.%02x", port->name, j);
672 names[offset + j] = name;
675 offset += port->pins;
678 gpio->gpio.names = (const char * const *)names;
680 gpio->gpio.of_node = pdev->dev.of_node;
681 gpio->gpio.of_gpio_n_cells = 2;
682 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
684 gpio->intc.name = pdev->dev.of_node->name;
685 gpio->intc.irq_ack = tegra186_irq_ack;
686 gpio->intc.irq_mask = tegra186_irq_mask;
687 gpio->intc.irq_unmask = tegra186_irq_unmask;
688 gpio->intc.irq_set_type = tegra186_irq_set_type;
689 gpio->intc.irq_set_wake = tegra186_irq_set_wake;
691 irq = &gpio->gpio.irq;
692 irq->chip = &gpio->intc;
693 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
694 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
695 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
696 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
697 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
698 irq->handler = handle_simple_irq;
699 irq->default_type = IRQ_TYPE_NONE;
700 irq->parent_handler = tegra186_gpio_irq;
701 irq->parent_handler_data = gpio;
702 irq->num_parents = gpio->num_irq;
703 irq->parents = gpio->irq;
705 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
707 irq->parent_domain = irq_find_host(np);
710 if (!irq->parent_domain)
711 return -EPROBE_DEFER;
714 tegra186_gpio_init_route_mapping(gpio);
716 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
717 sizeof(*irq->map), GFP_KERNEL);
721 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
722 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
724 for (j = 0; j < port->pins; j++)
725 irq->map[offset + j] = irq->parents[port->bank];
727 offset += port->pins;
730 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
733 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
734 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
741 static const struct tegra_gpio_port tegra186_main_ports[] = {
742 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
743 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
744 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
745 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
746 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
747 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
748 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
749 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
750 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
751 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
752 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
753 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
754 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
755 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
756 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
757 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
758 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
759 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
760 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
761 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
762 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
763 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
764 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
767 static const struct tegra_gpio_soc tegra186_main_soc = {
768 .num_ports = ARRAY_SIZE(tegra186_main_ports),
769 .ports = tegra186_main_ports,
770 .name = "tegra186-gpio",
774 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
775 [TEGRA186_AON_GPIO_PORT_##_name] = { \
782 static const struct tegra_gpio_port tegra186_aon_ports[] = {
783 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
784 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
785 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
786 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
787 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
788 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
789 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
790 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
793 static const struct tegra_gpio_soc tegra186_aon_soc = {
794 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
795 .ports = tegra186_aon_ports,
796 .name = "tegra186-gpio-aon",
800 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
801 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
808 static const struct tegra_gpio_port tegra194_main_ports[] = {
809 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
810 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
811 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
812 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
813 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
814 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
815 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
816 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
817 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
818 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
819 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
820 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
821 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
822 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
823 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
824 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
825 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
826 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
827 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
828 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
829 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
830 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
831 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
832 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
833 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
834 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
835 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
836 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
839 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
840 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
841 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
844 static const struct tegra_gpio_soc tegra194_main_soc = {
845 .num_ports = ARRAY_SIZE(tegra194_main_ports),
846 .ports = tegra194_main_ports,
847 .name = "tegra194-gpio",
849 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
850 .pin_ranges = tegra194_main_pin_ranges,
851 .pinmux = "nvidia,tegra194-pinmux",
854 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
855 [TEGRA194_AON_GPIO_PORT_##_name] = { \
862 static const struct tegra_gpio_port tegra194_aon_ports[] = {
863 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
864 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
865 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
866 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
867 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
870 static const struct tegra_gpio_soc tegra194_aon_soc = {
871 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
872 .ports = tegra194_aon_ports,
873 .name = "tegra194-gpio-aon",
877 static const struct of_device_id tegra186_gpio_of_match[] = {
879 .compatible = "nvidia,tegra186-gpio",
880 .data = &tegra186_main_soc
882 .compatible = "nvidia,tegra186-gpio-aon",
883 .data = &tegra186_aon_soc
885 .compatible = "nvidia,tegra194-gpio",
886 .data = &tegra194_main_soc
888 .compatible = "nvidia,tegra194-gpio-aon",
889 .data = &tegra194_aon_soc
894 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
896 static struct platform_driver tegra186_gpio_driver = {
898 .name = "tegra186-gpio",
899 .of_match_table = tegra186_gpio_of_match,
901 .probe = tegra186_gpio_probe,
903 module_platform_driver(tegra186_gpio_driver);
905 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
906 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
907 MODULE_LICENSE("GPL v2");