1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2017 NVIDIA Corporation
5 * Author: Thierry Reding <treding@nvidia.com>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
15 #include <dt-bindings/gpio/tegra186-gpio.h>
16 #include <dt-bindings/gpio/tegra194-gpio.h>
18 /* security registers */
19 #define TEGRA186_GPIO_CTL_SCR 0x0c
20 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
21 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
23 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
25 /* control registers */
26 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
27 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
28 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
29 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
30 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
35 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
37 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
38 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
40 #define TEGRA186_GPIO_INPUT 0x08
41 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
43 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
44 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
46 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
47 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
49 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
51 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
53 struct tegra_gpio_port {
60 struct tegra_gpio_soc {
61 const struct tegra_gpio_port *ports;
62 unsigned int num_ports;
64 unsigned int instance;
68 struct gpio_chip gpio;
73 const struct tegra_gpio_soc *soc;
79 static const struct tegra_gpio_port *
80 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
82 unsigned int start = 0, i;
84 for (i = 0; i < gpio->soc->num_ports; i++) {
85 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
87 if (*pin >= start && *pin < start + port->pins) {
98 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
101 const struct tegra_gpio_port *port;
104 port = tegra186_gpio_get_port(gpio, &pin);
108 offset = port->bank * 0x1000 + port->port * 0x200;
110 return gpio->base + offset + pin * 0x20;
113 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
116 struct tegra_gpio *gpio = gpiochip_get_data(chip);
120 base = tegra186_gpio_get_base(gpio, offset);
121 if (WARN_ON(base == NULL))
124 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
125 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
126 return GPIO_LINE_DIRECTION_OUT;
128 return GPIO_LINE_DIRECTION_IN;
131 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
134 struct tegra_gpio *gpio = gpiochip_get_data(chip);
138 base = tegra186_gpio_get_base(gpio, offset);
139 if (WARN_ON(base == NULL))
142 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
143 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
144 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
146 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
147 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
148 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
149 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
154 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
155 unsigned int offset, int level)
157 struct tegra_gpio *gpio = gpiochip_get_data(chip);
161 /* configure output level first */
162 chip->set(chip, offset, level);
164 base = tegra186_gpio_get_base(gpio, offset);
165 if (WARN_ON(base == NULL))
168 /* set the direction */
169 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
170 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
171 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
173 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
174 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
175 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
176 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
181 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
183 struct tegra_gpio *gpio = gpiochip_get_data(chip);
187 base = tegra186_gpio_get_base(gpio, offset);
188 if (WARN_ON(base == NULL))
191 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
192 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
193 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
195 value = readl(base + TEGRA186_GPIO_INPUT);
197 return value & BIT(0);
200 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
203 struct tegra_gpio *gpio = gpiochip_get_data(chip);
207 base = tegra186_gpio_get_base(gpio, offset);
208 if (WARN_ON(base == NULL))
211 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
213 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
215 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
217 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
220 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
221 const struct of_phandle_args *spec,
224 struct tegra_gpio *gpio = gpiochip_get_data(chip);
225 unsigned int port, pin, i, offset = 0;
227 if (WARN_ON(chip->of_gpio_n_cells < 2))
230 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
233 port = spec->args[0] / 8;
234 pin = spec->args[0] % 8;
236 if (port >= gpio->soc->num_ports) {
237 dev_err(chip->parent, "invalid port number: %u\n", port);
241 for (i = 0; i < port; i++)
242 offset += gpio->soc->ports[i].pins;
245 *flags = spec->args[1];
250 static void tegra186_irq_ack(struct irq_data *data)
252 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
255 base = tegra186_gpio_get_base(gpio, data->hwirq);
256 if (WARN_ON(base == NULL))
259 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
262 static void tegra186_irq_mask(struct irq_data *data)
264 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
268 base = tegra186_gpio_get_base(gpio, data->hwirq);
269 if (WARN_ON(base == NULL))
272 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
273 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
274 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
277 static void tegra186_irq_unmask(struct irq_data *data)
279 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
283 base = tegra186_gpio_get_base(gpio, data->hwirq);
284 if (WARN_ON(base == NULL))
287 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
288 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
289 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
292 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
294 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
298 base = tegra186_gpio_get_base(gpio, data->hwirq);
299 if (WARN_ON(base == NULL))
302 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
303 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
304 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
306 switch (type & IRQ_TYPE_SENSE_MASK) {
310 case IRQ_TYPE_EDGE_RISING:
311 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
312 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
315 case IRQ_TYPE_EDGE_FALLING:
316 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
319 case IRQ_TYPE_EDGE_BOTH:
320 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
323 case IRQ_TYPE_LEVEL_HIGH:
324 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
325 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
328 case IRQ_TYPE_LEVEL_LOW:
329 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
336 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
338 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
339 irq_set_handler_locked(data, handle_level_irq);
341 irq_set_handler_locked(data, handle_edge_irq);
343 return irq_chip_set_type_parent(data, type);
346 static void tegra186_gpio_irq(struct irq_desc *desc)
348 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
349 struct irq_domain *domain = gpio->gpio.irq.domain;
350 struct irq_chip *chip = irq_desc_get_chip(desc);
351 unsigned int parent = irq_desc_get_irq(desc);
352 unsigned int i, offset = 0;
354 chained_irq_enter(chip, desc);
356 for (i = 0; i < gpio->soc->num_ports; i++) {
357 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
358 unsigned int pin, irq;
362 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
364 /* skip ports that are not associated with this bank */
365 if (parent != gpio->irq[port->bank])
368 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
370 for_each_set_bit(pin, &value, port->pins) {
371 irq = irq_find_mapping(domain, offset + pin);
372 if (WARN_ON(irq == 0))
375 generic_handle_irq(irq);
379 offset += port->pins;
382 chained_irq_exit(chip, desc);
385 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
386 struct irq_fwspec *fwspec,
387 unsigned long *hwirq,
390 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
391 unsigned int port, pin, i, offset = 0;
393 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
396 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
399 port = fwspec->param[0] / 8;
400 pin = fwspec->param[0] % 8;
402 if (port >= gpio->soc->num_ports)
405 for (i = 0; i < port; i++)
406 offset += gpio->soc->ports[i].pins;
408 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
409 *hwirq = offset + pin;
414 static void tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
415 struct irq_fwspec *fwspec,
416 unsigned int parent_hwirq,
417 unsigned int parent_type)
419 struct tegra_gpio *gpio = gpiochip_get_data(chip);
421 fwspec->param_count = 3;
422 fwspec->param[0] = gpio->soc->instance;
423 fwspec->param[1] = parent_hwirq;
424 fwspec->param[2] = parent_type;
427 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
430 unsigned int *parent_hwirq,
431 unsigned int *parent_type)
433 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
439 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
442 struct tegra_gpio *gpio = gpiochip_get_data(chip);
445 for (i = 0; i < gpio->soc->num_ports; i++) {
446 if (offset < gpio->soc->ports[i].pins)
449 offset -= gpio->soc->ports[i].pins;
452 return offset + i * 8;
455 static const struct of_device_id tegra186_pmc_of_match[] = {
456 { .compatible = "nvidia,tegra186-pmc" },
457 { .compatible = "nvidia,tegra194-pmc" },
461 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
466 for (i = 0; i < gpio->soc->num_ports; i++) {
467 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
468 unsigned int offset, p = port->port;
471 base = gpio->secure + port->bank * 0x1000 + 0x800;
473 value = readl(base + TEGRA186_GPIO_CTL_SCR);
476 * For controllers that haven't been locked down yet, make
477 * sure to program the default interrupt route mapping.
479 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
480 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
481 for (j = 0; j < 8; j++) {
482 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
484 value = readl(base + offset);
485 value = BIT(port->pins) - 1;
486 writel(value, base + offset);
492 static int tegra186_gpio_probe(struct platform_device *pdev)
494 unsigned int i, j, offset;
495 struct gpio_irq_chip *irq;
496 struct tegra_gpio *gpio;
497 struct device_node *np;
501 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
505 gpio->soc = of_device_get_match_data(&pdev->dev);
507 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
508 if (IS_ERR(gpio->secure))
509 return PTR_ERR(gpio->secure);
511 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
512 if (IS_ERR(gpio->base))
513 return PTR_ERR(gpio->base);
515 err = platform_irq_count(pdev);
521 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
526 for (i = 0; i < gpio->num_irq; i++) {
527 err = platform_get_irq(pdev, i);
534 gpio->gpio.label = gpio->soc->name;
535 gpio->gpio.parent = &pdev->dev;
537 gpio->gpio.get_direction = tegra186_gpio_get_direction;
538 gpio->gpio.direction_input = tegra186_gpio_direction_input;
539 gpio->gpio.direction_output = tegra186_gpio_direction_output;
540 gpio->gpio.get = tegra186_gpio_get,
541 gpio->gpio.set = tegra186_gpio_set;
543 gpio->gpio.base = -1;
545 for (i = 0; i < gpio->soc->num_ports; i++)
546 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
548 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
549 sizeof(*names), GFP_KERNEL);
553 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
554 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
557 for (j = 0; j < port->pins; j++) {
558 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
559 "P%s.%02x", port->name, j);
563 names[offset + j] = name;
566 offset += port->pins;
569 gpio->gpio.names = (const char * const *)names;
571 gpio->gpio.of_node = pdev->dev.of_node;
572 gpio->gpio.of_gpio_n_cells = 2;
573 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
575 gpio->intc.name = pdev->dev.of_node->name;
576 gpio->intc.irq_ack = tegra186_irq_ack;
577 gpio->intc.irq_mask = tegra186_irq_mask;
578 gpio->intc.irq_unmask = tegra186_irq_unmask;
579 gpio->intc.irq_set_type = tegra186_irq_set_type;
580 gpio->intc.irq_set_wake = irq_chip_set_wake_parent;
582 irq = &gpio->gpio.irq;
583 irq->chip = &gpio->intc;
584 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
585 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
586 irq->populate_parent_fwspec = tegra186_gpio_populate_parent_fwspec;
587 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
588 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
589 irq->handler = handle_simple_irq;
590 irq->default_type = IRQ_TYPE_NONE;
591 irq->parent_handler = tegra186_gpio_irq;
592 irq->parent_handler_data = gpio;
593 irq->num_parents = gpio->num_irq;
594 irq->parents = gpio->irq;
596 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
598 irq->parent_domain = irq_find_host(np);
601 if (!irq->parent_domain)
602 return -EPROBE_DEFER;
605 tegra186_gpio_init_route_mapping(gpio);
607 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
608 sizeof(*irq->map), GFP_KERNEL);
612 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
613 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
615 for (j = 0; j < port->pins; j++)
616 irq->map[offset + j] = irq->parents[port->bank];
618 offset += port->pins;
621 platform_set_drvdata(pdev, gpio);
623 err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
630 static int tegra186_gpio_remove(struct platform_device *pdev)
635 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
636 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
643 static const struct tegra_gpio_port tegra186_main_ports[] = {
644 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
645 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
646 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
647 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
648 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
649 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
650 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
651 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
652 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
653 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
654 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
655 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
656 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
657 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
658 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
659 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
660 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
661 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
662 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
663 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
664 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
665 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
666 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
669 static const struct tegra_gpio_soc tegra186_main_soc = {
670 .num_ports = ARRAY_SIZE(tegra186_main_ports),
671 .ports = tegra186_main_ports,
672 .name = "tegra186-gpio",
676 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
677 [TEGRA186_AON_GPIO_PORT_##_name] = { \
684 static const struct tegra_gpio_port tegra186_aon_ports[] = {
685 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
686 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
687 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
688 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
689 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
690 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
691 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
692 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
695 static const struct tegra_gpio_soc tegra186_aon_soc = {
696 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
697 .ports = tegra186_aon_ports,
698 .name = "tegra186-gpio-aon",
702 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
703 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
710 static const struct tegra_gpio_port tegra194_main_ports[] = {
711 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
712 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
713 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
714 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
715 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
716 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
717 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
718 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
719 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
720 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
721 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
722 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
723 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
724 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
725 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
726 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
727 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
728 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
729 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
730 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
731 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
732 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
733 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
734 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
735 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
736 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
737 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
738 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
741 static const struct tegra_gpio_soc tegra194_main_soc = {
742 .num_ports = ARRAY_SIZE(tegra194_main_ports),
743 .ports = tegra194_main_ports,
744 .name = "tegra194-gpio",
748 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
749 [TEGRA194_AON_GPIO_PORT_##_name] = { \
756 static const struct tegra_gpio_port tegra194_aon_ports[] = {
757 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
758 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
759 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
760 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
761 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
764 static const struct tegra_gpio_soc tegra194_aon_soc = {
765 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
766 .ports = tegra194_aon_ports,
767 .name = "tegra194-gpio-aon",
771 static const struct of_device_id tegra186_gpio_of_match[] = {
773 .compatible = "nvidia,tegra186-gpio",
774 .data = &tegra186_main_soc
776 .compatible = "nvidia,tegra186-gpio-aon",
777 .data = &tegra186_aon_soc
779 .compatible = "nvidia,tegra194-gpio",
780 .data = &tegra194_main_soc
782 .compatible = "nvidia,tegra194-gpio-aon",
783 .data = &tegra194_aon_soc
789 static struct platform_driver tegra186_gpio_driver = {
791 .name = "tegra186-gpio",
792 .of_match_table = tegra186_gpio_of_match,
794 .probe = tegra186_gpio_probe,
795 .remove = tegra186_gpio_remove,
797 module_platform_driver(tegra186_gpio_driver);
799 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
800 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
801 MODULE_LICENSE("GPL v2");