1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2017 NVIDIA Corporation
5 * Author: Thierry Reding <treding@nvidia.com>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
15 #include <dt-bindings/gpio/tegra186-gpio.h>
16 #include <dt-bindings/gpio/tegra194-gpio.h>
17 #include <dt-bindings/gpio/tegra234-gpio.h>
18 #include <dt-bindings/gpio/tegra241-gpio.h>
20 /* security registers */
21 #define TEGRA186_GPIO_CTL_SCR 0x0c
22 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
23 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
25 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
27 /* control registers */
28 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
29 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
30 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
35 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
36 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
37 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
38 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
40 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
41 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
43 #define TEGRA186_GPIO_INPUT 0x08
44 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
46 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
47 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
49 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
50 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
52 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
54 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
56 struct tegra_gpio_port {
63 struct tegra186_pin_range {
68 struct tegra_gpio_soc {
69 const struct tegra_gpio_port *ports;
70 unsigned int num_ports;
72 unsigned int instance;
74 unsigned int num_irqs_per_bank;
76 const struct tegra186_pin_range *pin_ranges;
77 unsigned int num_pin_ranges;
82 struct gpio_chip gpio;
86 const struct tegra_gpio_soc *soc;
87 unsigned int num_irqs_per_bank;
88 unsigned int num_banks;
94 static const struct tegra_gpio_port *
95 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
97 unsigned int start = 0, i;
99 for (i = 0; i < gpio->soc->num_ports; i++) {
100 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
102 if (*pin >= start && *pin < start + port->pins) {
113 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
116 const struct tegra_gpio_port *port;
119 port = tegra186_gpio_get_port(gpio, &pin);
123 offset = port->bank * 0x1000 + port->port * 0x200;
125 return gpio->base + offset + pin * 0x20;
128 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
131 struct tegra_gpio *gpio = gpiochip_get_data(chip);
135 base = tegra186_gpio_get_base(gpio, offset);
136 if (WARN_ON(base == NULL))
139 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
140 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
141 return GPIO_LINE_DIRECTION_OUT;
143 return GPIO_LINE_DIRECTION_IN;
146 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
149 struct tegra_gpio *gpio = gpiochip_get_data(chip);
153 base = tegra186_gpio_get_base(gpio, offset);
154 if (WARN_ON(base == NULL))
157 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
158 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
159 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
161 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
162 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
163 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
164 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
169 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
170 unsigned int offset, int level)
172 struct tegra_gpio *gpio = gpiochip_get_data(chip);
176 /* configure output level first */
177 chip->set(chip, offset, level);
179 base = tegra186_gpio_get_base(gpio, offset);
180 if (WARN_ON(base == NULL))
183 /* set the direction */
184 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
185 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
186 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
188 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
189 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
190 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
191 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
196 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
198 struct tegra_gpio *gpio = gpiochip_get_data(chip);
202 base = tegra186_gpio_get_base(gpio, offset);
203 if (WARN_ON(base == NULL))
206 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
207 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
208 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
210 value = readl(base + TEGRA186_GPIO_INPUT);
212 return value & BIT(0);
215 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
218 struct tegra_gpio *gpio = gpiochip_get_data(chip);
222 base = tegra186_gpio_get_base(gpio, offset);
223 if (WARN_ON(base == NULL))
226 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
228 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
230 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
232 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
235 static int tegra186_gpio_set_config(struct gpio_chip *chip,
237 unsigned long config)
239 struct tegra_gpio *gpio = gpiochip_get_data(chip);
243 base = tegra186_gpio_get_base(gpio, offset);
247 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
250 debounce = pinconf_to_config_argument(config);
253 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
256 if (debounce > 255000)
259 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
261 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
262 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
264 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
265 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
266 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
271 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
273 struct tegra_gpio *gpio = gpiochip_get_data(chip);
274 struct pinctrl_dev *pctldev;
275 struct device_node *np;
279 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
282 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
286 pctldev = of_pinctrl_get(np);
289 return -EPROBE_DEFER;
291 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
292 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
293 const char *group = gpio->soc->pin_ranges[i].group;
298 if (port >= gpio->soc->num_ports) {
299 dev_warn(chip->parent, "invalid port %u for %s\n",
304 for (j = 0; j < port; j++)
305 pin += gpio->soc->ports[j].pins;
307 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
315 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
316 const struct of_phandle_args *spec,
319 struct tegra_gpio *gpio = gpiochip_get_data(chip);
320 unsigned int port, pin, i, offset = 0;
322 if (WARN_ON(chip->of_gpio_n_cells < 2))
325 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
328 port = spec->args[0] / 8;
329 pin = spec->args[0] % 8;
331 if (port >= gpio->soc->num_ports) {
332 dev_err(chip->parent, "invalid port number: %u\n", port);
336 for (i = 0; i < port; i++)
337 offset += gpio->soc->ports[i].pins;
340 *flags = spec->args[1];
345 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
347 static void tegra186_irq_ack(struct irq_data *data)
349 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
350 struct tegra_gpio *gpio = to_tegra_gpio(gc);
353 base = tegra186_gpio_get_base(gpio, data->hwirq);
354 if (WARN_ON(base == NULL))
357 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
360 static void tegra186_irq_mask(struct irq_data *data)
362 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
363 struct tegra_gpio *gpio = to_tegra_gpio(gc);
367 base = tegra186_gpio_get_base(gpio, data->hwirq);
368 if (WARN_ON(base == NULL))
371 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
372 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
373 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
375 gpiochip_disable_irq(&gpio->gpio, data->hwirq);
378 static void tegra186_irq_unmask(struct irq_data *data)
380 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
381 struct tegra_gpio *gpio = to_tegra_gpio(gc);
385 base = tegra186_gpio_get_base(gpio, data->hwirq);
386 if (WARN_ON(base == NULL))
389 gpiochip_enable_irq(&gpio->gpio, data->hwirq);
391 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
392 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
393 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
396 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
398 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
399 struct tegra_gpio *gpio = to_tegra_gpio(gc);
403 base = tegra186_gpio_get_base(gpio, data->hwirq);
404 if (WARN_ON(base == NULL))
407 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
408 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
409 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
411 switch (type & IRQ_TYPE_SENSE_MASK) {
415 case IRQ_TYPE_EDGE_RISING:
416 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
417 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
420 case IRQ_TYPE_EDGE_FALLING:
421 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
424 case IRQ_TYPE_EDGE_BOTH:
425 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
428 case IRQ_TYPE_LEVEL_HIGH:
429 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
430 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
433 case IRQ_TYPE_LEVEL_LOW:
434 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
441 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
443 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
444 irq_set_handler_locked(data, handle_level_irq);
446 irq_set_handler_locked(data, handle_edge_irq);
448 if (data->parent_data)
449 return irq_chip_set_type_parent(data, type);
454 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
456 if (data->parent_data)
457 return irq_chip_set_wake_parent(data, on);
462 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
464 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
466 seq_printf(p, dev_name(gc->parent));
469 static const struct irq_chip tegra186_gpio_irq_chip = {
470 .irq_ack = tegra186_irq_ack,
471 .irq_mask = tegra186_irq_mask,
472 .irq_unmask = tegra186_irq_unmask,
473 .irq_set_type = tegra186_irq_set_type,
474 .irq_set_wake = tegra186_irq_set_wake,
475 .irq_print_chip = tegra186_irq_print_chip,
476 .flags = IRQCHIP_IMMUTABLE,
477 GPIOCHIP_IRQ_RESOURCE_HELPERS,
480 static void tegra186_gpio_irq(struct irq_desc *desc)
482 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
483 struct irq_domain *domain = gpio->gpio.irq.domain;
484 struct irq_chip *chip = irq_desc_get_chip(desc);
485 unsigned int parent = irq_desc_get_irq(desc);
486 unsigned int i, j, offset = 0;
488 chained_irq_enter(chip, desc);
490 for (i = 0; i < gpio->soc->num_ports; i++) {
491 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
496 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
498 /* skip ports that are not associated with this bank */
499 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
500 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
504 if (j == gpio->num_irqs_per_bank)
507 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
509 for_each_set_bit(pin, &value, port->pins) {
510 int ret = generic_handle_domain_irq(domain, offset + pin);
511 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
515 offset += port->pins;
518 chained_irq_exit(chip, desc);
521 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
522 struct irq_fwspec *fwspec,
523 unsigned long *hwirq,
526 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
527 unsigned int port, pin, i, offset = 0;
529 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
532 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
535 port = fwspec->param[0] / 8;
536 pin = fwspec->param[0] % 8;
538 if (port >= gpio->soc->num_ports)
541 for (i = 0; i < port; i++)
542 offset += gpio->soc->ports[i].pins;
544 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
545 *hwirq = offset + pin;
550 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
551 unsigned int parent_hwirq,
552 unsigned int parent_type)
554 struct tegra_gpio *gpio = gpiochip_get_data(chip);
555 struct irq_fwspec *fwspec;
557 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
561 fwspec->fwnode = chip->irq.parent_domain->fwnode;
562 fwspec->param_count = 3;
563 fwspec->param[0] = gpio->soc->instance;
564 fwspec->param[1] = parent_hwirq;
565 fwspec->param[2] = parent_type;
570 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
573 unsigned int *parent_hwirq,
574 unsigned int *parent_type)
576 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
582 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
585 struct tegra_gpio *gpio = gpiochip_get_data(chip);
588 for (i = 0; i < gpio->soc->num_ports; i++) {
589 if (offset < gpio->soc->ports[i].pins)
592 offset -= gpio->soc->ports[i].pins;
595 return offset + i * 8;
598 static const struct of_device_id tegra186_pmc_of_match[] = {
599 { .compatible = "nvidia,tegra186-pmc" },
600 { .compatible = "nvidia,tegra194-pmc" },
604 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
606 struct device *dev = gpio->gpio.parent;
610 for (i = 0; i < gpio->soc->num_ports; i++) {
611 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
612 unsigned int offset, p = port->port;
615 base = gpio->secure + port->bank * 0x1000 + 0x800;
617 value = readl(base + TEGRA186_GPIO_CTL_SCR);
620 * For controllers that haven't been locked down yet, make
621 * sure to program the default interrupt route mapping.
623 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
624 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
626 * On Tegra194 and later, each pin can be routed to one or more
629 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
630 dev_dbg(dev, "programming default interrupt routing for port %s\n",
633 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
636 * By default we only want to route GPIO pins to IRQ 0. This works
637 * only under the assumption that we're running as the host kernel
638 * and hence all GPIO pins are owned by Linux.
640 * For cases where Linux is the guest OS, the hypervisor will have
641 * to configure the interrupt routing and pass only the valid
642 * interrupts via device tree.
645 value = readl(base + offset);
646 value = BIT(port->pins) - 1;
647 writel(value, base + offset);
654 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
656 struct device *dev = gpio->gpio.parent;
658 if (gpio->num_irq > gpio->num_banks) {
659 if (gpio->num_irq % gpio->num_banks != 0)
663 if (gpio->num_irq < gpio->num_banks)
666 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
668 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
674 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
675 gpio->num_irq, gpio->num_banks);
679 static int tegra186_gpio_probe(struct platform_device *pdev)
681 unsigned int i, j, offset;
682 struct gpio_irq_chip *irq;
683 struct tegra_gpio *gpio;
684 struct device_node *np;
688 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
692 gpio->soc = device_get_match_data(&pdev->dev);
693 gpio->gpio.label = gpio->soc->name;
694 gpio->gpio.parent = &pdev->dev;
696 /* count the number of banks in the controller */
697 for (i = 0; i < gpio->soc->num_ports; i++)
698 if (gpio->soc->ports[i].bank > gpio->num_banks)
699 gpio->num_banks = gpio->soc->ports[i].bank;
703 /* get register apertures */
704 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
705 if (IS_ERR(gpio->secure)) {
706 gpio->secure = devm_platform_ioremap_resource(pdev, 0);
707 if (IS_ERR(gpio->secure))
708 return PTR_ERR(gpio->secure);
711 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
712 if (IS_ERR(gpio->base)) {
713 gpio->base = devm_platform_ioremap_resource(pdev, 1);
714 if (IS_ERR(gpio->base))
715 return PTR_ERR(gpio->base);
718 err = platform_irq_count(pdev);
724 err = tegra186_gpio_irqs_per_bank(gpio);
728 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
733 for (i = 0; i < gpio->num_irq; i++) {
734 err = platform_get_irq(pdev, i);
741 gpio->gpio.request = gpiochip_generic_request;
742 gpio->gpio.free = gpiochip_generic_free;
743 gpio->gpio.get_direction = tegra186_gpio_get_direction;
744 gpio->gpio.direction_input = tegra186_gpio_direction_input;
745 gpio->gpio.direction_output = tegra186_gpio_direction_output;
746 gpio->gpio.get = tegra186_gpio_get;
747 gpio->gpio.set = tegra186_gpio_set;
748 gpio->gpio.set_config = tegra186_gpio_set_config;
749 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
751 gpio->gpio.base = -1;
753 for (i = 0; i < gpio->soc->num_ports; i++)
754 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
756 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
757 sizeof(*names), GFP_KERNEL);
761 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
762 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
765 for (j = 0; j < port->pins; j++) {
766 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
767 "P%s.%02x", port->name, j);
771 names[offset + j] = name;
774 offset += port->pins;
777 gpio->gpio.names = (const char * const *)names;
779 #if defined(CONFIG_OF_GPIO)
780 gpio->gpio.of_gpio_n_cells = 2;
781 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
782 #endif /* CONFIG_OF_GPIO */
784 irq = &gpio->gpio.irq;
785 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
786 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
787 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
788 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
789 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
790 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
791 irq->handler = handle_simple_irq;
792 irq->default_type = IRQ_TYPE_NONE;
793 irq->parent_handler = tegra186_gpio_irq;
794 irq->parent_handler_data = gpio;
795 irq->num_parents = gpio->num_irq;
798 * To simplify things, use a single interrupt per bank for now. Some
799 * chips support up to 8 interrupts per bank, which can be useful to
800 * distribute the load and decrease the processing latency for GPIOs
801 * but it also requires a more complicated interrupt routing than we
804 if (gpio->num_irqs_per_bank > 1) {
805 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
806 sizeof(*irq->parents), GFP_KERNEL);
810 for (i = 0; i < gpio->num_banks; i++)
811 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
813 irq->num_parents = gpio->num_banks;
815 irq->num_parents = gpio->num_irq;
816 irq->parents = gpio->irq;
819 if (gpio->soc->num_irqs_per_bank > 1)
820 tegra186_gpio_init_route_mapping(gpio);
822 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
824 irq->parent_domain = irq_find_host(np);
827 if (!irq->parent_domain)
828 return -EPROBE_DEFER;
831 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
832 sizeof(*irq->map), GFP_KERNEL);
836 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
837 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
839 for (j = 0; j < port->pins; j++)
840 irq->map[offset + j] = irq->parents[port->bank];
842 offset += port->pins;
845 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
848 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
849 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
856 static const struct tegra_gpio_port tegra186_main_ports[] = {
857 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
858 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
859 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
860 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
861 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
862 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
863 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
864 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
865 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
866 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
867 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
868 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
869 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
870 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
871 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
872 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
873 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
874 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
875 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
876 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
877 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
878 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
879 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
882 static const struct tegra_gpio_soc tegra186_main_soc = {
883 .num_ports = ARRAY_SIZE(tegra186_main_ports),
884 .ports = tegra186_main_ports,
885 .name = "tegra186-gpio",
887 .num_irqs_per_bank = 1,
890 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
891 [TEGRA186_AON_GPIO_PORT_##_name] = { \
898 static const struct tegra_gpio_port tegra186_aon_ports[] = {
899 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
900 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
901 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
902 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
903 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
904 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
905 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
906 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
909 static const struct tegra_gpio_soc tegra186_aon_soc = {
910 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
911 .ports = tegra186_aon_ports,
912 .name = "tegra186-gpio-aon",
914 .num_irqs_per_bank = 1,
917 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
918 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
925 static const struct tegra_gpio_port tegra194_main_ports[] = {
926 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
927 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
928 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
929 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
930 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
931 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
932 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
933 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
934 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
935 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
936 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
937 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
938 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
939 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
940 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
941 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
942 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
943 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
944 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
945 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
946 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
947 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
948 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
949 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
950 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
951 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
952 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
953 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
956 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
957 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
958 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
961 static const struct tegra_gpio_soc tegra194_main_soc = {
962 .num_ports = ARRAY_SIZE(tegra194_main_ports),
963 .ports = tegra194_main_ports,
964 .name = "tegra194-gpio",
966 .num_irqs_per_bank = 8,
967 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
968 .pin_ranges = tegra194_main_pin_ranges,
969 .pinmux = "nvidia,tegra194-pinmux",
972 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
973 [TEGRA194_AON_GPIO_PORT_##_name] = { \
980 static const struct tegra_gpio_port tegra194_aon_ports[] = {
981 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
982 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
983 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
984 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
985 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
988 static const struct tegra_gpio_soc tegra194_aon_soc = {
989 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
990 .ports = tegra194_aon_ports,
991 .name = "tegra194-gpio-aon",
993 .num_irqs_per_bank = 8,
996 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
997 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
1004 static const struct tegra_gpio_port tegra234_main_ports[] = {
1005 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1006 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1007 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1008 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1009 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1010 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1011 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1012 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1013 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1014 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1015 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1016 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1017 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1018 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1019 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1020 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1021 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1022 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1023 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1024 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1025 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1026 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1027 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1028 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1029 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1032 static const struct tegra_gpio_soc tegra234_main_soc = {
1033 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1034 .ports = tegra234_main_ports,
1035 .name = "tegra234-gpio",
1037 .num_irqs_per_bank = 8,
1040 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1041 [TEGRA234_AON_GPIO_PORT_##_name] = { \
1048 static const struct tegra_gpio_port tegra234_aon_ports[] = {
1049 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1050 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1051 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1052 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1053 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1054 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1057 static const struct tegra_gpio_soc tegra234_aon_soc = {
1058 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1059 .ports = tegra234_aon_ports,
1060 .name = "tegra234-gpio-aon",
1062 .num_irqs_per_bank = 8,
1065 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1066 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
1073 static const struct tegra_gpio_port tegra241_main_ports[] = {
1074 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1075 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1076 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1077 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1078 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1079 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1080 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1081 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1082 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1083 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1084 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1087 static const struct tegra_gpio_soc tegra241_main_soc = {
1088 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1089 .ports = tegra241_main_ports,
1090 .name = "tegra241-gpio",
1092 .num_irqs_per_bank = 8,
1095 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1096 [TEGRA241_AON_GPIO_PORT_##_name] = { \
1103 static const struct tegra_gpio_port tegra241_aon_ports[] = {
1104 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1105 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1108 static const struct tegra_gpio_soc tegra241_aon_soc = {
1109 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1110 .ports = tegra241_aon_ports,
1111 .name = "tegra241-gpio-aon",
1113 .num_irqs_per_bank = 8,
1116 static const struct of_device_id tegra186_gpio_of_match[] = {
1118 .compatible = "nvidia,tegra186-gpio",
1119 .data = &tegra186_main_soc
1121 .compatible = "nvidia,tegra186-gpio-aon",
1122 .data = &tegra186_aon_soc
1124 .compatible = "nvidia,tegra194-gpio",
1125 .data = &tegra194_main_soc
1127 .compatible = "nvidia,tegra194-gpio-aon",
1128 .data = &tegra194_aon_soc
1130 .compatible = "nvidia,tegra234-gpio",
1131 .data = &tegra234_main_soc
1133 .compatible = "nvidia,tegra234-gpio-aon",
1134 .data = &tegra234_aon_soc
1139 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1141 static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1142 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1143 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1144 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1145 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1146 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1147 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1150 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1152 static struct platform_driver tegra186_gpio_driver = {
1154 .name = "tegra186-gpio",
1155 .of_match_table = tegra186_gpio_of_match,
1156 .acpi_match_table = tegra186_gpio_acpi_match,
1158 .probe = tegra186_gpio_probe,
1160 module_platform_driver(tegra186_gpio_driver);
1162 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1163 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1164 MODULE_LICENSE("GPL v2");