1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2022 NVIDIA Corporation
5 * Author: Thierry Reding <treding@nvidia.com>
6 * Dipen Patel <dpatel@nvidia.com>
9 #include <linux/gpio/driver.h>
10 #include <linux/hte.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/seq_file.h>
18 #include <dt-bindings/gpio/tegra186-gpio.h>
19 #include <dt-bindings/gpio/tegra194-gpio.h>
20 #include <dt-bindings/gpio/tegra234-gpio.h>
21 #include <dt-bindings/gpio/tegra241-gpio.h>
23 /* security registers */
24 #define TEGRA186_GPIO_CTL_SCR 0x0c
25 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
26 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
28 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
30 /* control registers */
31 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
32 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
33 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
35 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
36 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
37 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
38 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
39 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
40 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
41 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
42 #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
44 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
45 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
47 #define TEGRA186_GPIO_INPUT 0x08
48 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
50 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
51 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
53 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
54 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
56 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
58 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
60 struct tegra_gpio_port {
67 struct tegra186_pin_range {
72 struct tegra_gpio_soc {
73 const struct tegra_gpio_port *ports;
74 unsigned int num_ports;
76 unsigned int instance;
78 unsigned int num_irqs_per_bank;
80 const struct tegra186_pin_range *pin_ranges;
81 unsigned int num_pin_ranges;
87 struct gpio_chip gpio;
91 const struct tegra_gpio_soc *soc;
92 unsigned int num_irqs_per_bank;
93 unsigned int num_banks;
99 static const struct tegra_gpio_port *
100 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
102 unsigned int start = 0, i;
104 for (i = 0; i < gpio->soc->num_ports; i++) {
105 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
107 if (*pin >= start && *pin < start + port->pins) {
118 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
121 const struct tegra_gpio_port *port;
124 port = tegra186_gpio_get_port(gpio, &pin);
128 offset = port->bank * 0x1000 + port->port * 0x200;
130 return gpio->base + offset + pin * 0x20;
133 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
136 struct tegra_gpio *gpio = gpiochip_get_data(chip);
140 base = tegra186_gpio_get_base(gpio, offset);
141 if (WARN_ON(base == NULL))
144 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
145 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
146 return GPIO_LINE_DIRECTION_OUT;
148 return GPIO_LINE_DIRECTION_IN;
151 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
154 struct tegra_gpio *gpio = gpiochip_get_data(chip);
158 base = tegra186_gpio_get_base(gpio, offset);
159 if (WARN_ON(base == NULL))
162 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
163 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
164 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
166 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
167 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
168 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
169 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
174 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
175 unsigned int offset, int level)
177 struct tegra_gpio *gpio = gpiochip_get_data(chip);
181 /* configure output level first */
182 chip->set(chip, offset, level);
184 base = tegra186_gpio_get_base(gpio, offset);
185 if (WARN_ON(base == NULL))
188 /* set the direction */
189 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
190 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
191 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
193 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
194 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
195 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
196 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
201 #define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
203 static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
206 struct tegra_gpio *gpio;
213 gpio = gpiochip_get_data(gc);
217 base = tegra186_gpio_get_base(gpio, offset);
218 if (WARN_ON(base == NULL))
221 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
222 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
224 if (flags == HTE_BOTH_EDGES) {
225 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
226 } else if (flags == HTE_RISING_EDGE_TS) {
227 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
228 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
229 } else if (flags == HTE_FALLING_EDGE_TS) {
230 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
233 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
238 static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
241 struct tegra_gpio *gpio;
248 gpio = gpiochip_get_data(gc);
252 base = tegra186_gpio_get_base(gpio, offset);
253 if (WARN_ON(base == NULL))
256 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
257 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
258 if (flags == HTE_BOTH_EDGES) {
259 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
260 } else if (flags == HTE_RISING_EDGE_TS) {
261 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
262 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
263 } else if (flags == HTE_FALLING_EDGE_TS) {
264 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
266 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
271 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
273 struct tegra_gpio *gpio = gpiochip_get_data(chip);
277 base = tegra186_gpio_get_base(gpio, offset);
278 if (WARN_ON(base == NULL))
281 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
282 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
283 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
285 value = readl(base + TEGRA186_GPIO_INPUT);
287 return value & BIT(0);
290 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
293 struct tegra_gpio *gpio = gpiochip_get_data(chip);
297 base = tegra186_gpio_get_base(gpio, offset);
298 if (WARN_ON(base == NULL))
301 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
303 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
305 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
307 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
310 static int tegra186_gpio_set_config(struct gpio_chip *chip,
312 unsigned long config)
314 struct tegra_gpio *gpio = gpiochip_get_data(chip);
318 base = tegra186_gpio_get_base(gpio, offset);
322 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
325 debounce = pinconf_to_config_argument(config);
328 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
331 if (debounce > 255000)
334 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
336 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
337 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
339 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
340 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
341 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
346 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
348 struct tegra_gpio *gpio = gpiochip_get_data(chip);
349 struct pinctrl_dev *pctldev;
350 struct device_node *np;
354 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
357 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
361 pctldev = of_pinctrl_get(np);
364 return -EPROBE_DEFER;
366 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
367 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
368 const char *group = gpio->soc->pin_ranges[i].group;
373 if (port >= gpio->soc->num_ports) {
374 dev_warn(chip->parent, "invalid port %u for %s\n",
379 for (j = 0; j < port; j++)
380 pin += gpio->soc->ports[j].pins;
382 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
390 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
391 const struct of_phandle_args *spec,
394 struct tegra_gpio *gpio = gpiochip_get_data(chip);
395 unsigned int port, pin, i, offset = 0;
397 if (WARN_ON(chip->of_gpio_n_cells < 2))
400 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
403 port = spec->args[0] / 8;
404 pin = spec->args[0] % 8;
406 if (port >= gpio->soc->num_ports) {
407 dev_err(chip->parent, "invalid port number: %u\n", port);
411 for (i = 0; i < port; i++)
412 offset += gpio->soc->ports[i].pins;
415 *flags = spec->args[1];
420 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
422 static void tegra186_irq_ack(struct irq_data *data)
424 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
425 struct tegra_gpio *gpio = to_tegra_gpio(gc);
428 base = tegra186_gpio_get_base(gpio, data->hwirq);
429 if (WARN_ON(base == NULL))
432 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
435 static void tegra186_irq_mask(struct irq_data *data)
437 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
438 struct tegra_gpio *gpio = to_tegra_gpio(gc);
442 base = tegra186_gpio_get_base(gpio, data->hwirq);
443 if (WARN_ON(base == NULL))
446 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
447 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
448 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
450 gpiochip_disable_irq(&gpio->gpio, data->hwirq);
453 static void tegra186_irq_unmask(struct irq_data *data)
455 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
456 struct tegra_gpio *gpio = to_tegra_gpio(gc);
460 base = tegra186_gpio_get_base(gpio, data->hwirq);
461 if (WARN_ON(base == NULL))
464 gpiochip_enable_irq(&gpio->gpio, data->hwirq);
466 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
467 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
468 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
471 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
473 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
474 struct tegra_gpio *gpio = to_tegra_gpio(gc);
478 base = tegra186_gpio_get_base(gpio, data->hwirq);
479 if (WARN_ON(base == NULL))
482 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
483 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
484 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
486 switch (type & IRQ_TYPE_SENSE_MASK) {
490 case IRQ_TYPE_EDGE_RISING:
491 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
492 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
495 case IRQ_TYPE_EDGE_FALLING:
496 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
499 case IRQ_TYPE_EDGE_BOTH:
500 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
503 case IRQ_TYPE_LEVEL_HIGH:
504 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
505 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
508 case IRQ_TYPE_LEVEL_LOW:
509 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
516 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
518 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
519 irq_set_handler_locked(data, handle_level_irq);
521 irq_set_handler_locked(data, handle_edge_irq);
523 if (data->parent_data)
524 return irq_chip_set_type_parent(data, type);
529 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
531 if (data->parent_data)
532 return irq_chip_set_wake_parent(data, on);
537 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
539 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
541 seq_printf(p, dev_name(gc->parent));
544 static const struct irq_chip tegra186_gpio_irq_chip = {
545 .irq_ack = tegra186_irq_ack,
546 .irq_mask = tegra186_irq_mask,
547 .irq_unmask = tegra186_irq_unmask,
548 .irq_set_type = tegra186_irq_set_type,
549 .irq_set_wake = tegra186_irq_set_wake,
550 .irq_print_chip = tegra186_irq_print_chip,
551 .flags = IRQCHIP_IMMUTABLE,
552 GPIOCHIP_IRQ_RESOURCE_HELPERS,
555 static void tegra186_gpio_irq(struct irq_desc *desc)
557 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
558 struct irq_domain *domain = gpio->gpio.irq.domain;
559 struct irq_chip *chip = irq_desc_get_chip(desc);
560 unsigned int parent = irq_desc_get_irq(desc);
561 unsigned int i, j, offset = 0;
563 chained_irq_enter(chip, desc);
565 for (i = 0; i < gpio->soc->num_ports; i++) {
566 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
571 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
573 /* skip ports that are not associated with this bank */
574 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
575 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
579 if (j == gpio->num_irqs_per_bank)
582 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
584 for_each_set_bit(pin, &value, port->pins) {
585 int ret = generic_handle_domain_irq(domain, offset + pin);
586 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
590 offset += port->pins;
593 chained_irq_exit(chip, desc);
596 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
597 struct irq_fwspec *fwspec,
598 unsigned long *hwirq,
601 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
602 unsigned int port, pin, i, offset = 0;
604 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
607 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
610 port = fwspec->param[0] / 8;
611 pin = fwspec->param[0] % 8;
613 if (port >= gpio->soc->num_ports)
616 for (i = 0; i < port; i++)
617 offset += gpio->soc->ports[i].pins;
619 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
620 *hwirq = offset + pin;
625 static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
626 union gpio_irq_fwspec *gfwspec,
627 unsigned int parent_hwirq,
628 unsigned int parent_type)
630 struct tegra_gpio *gpio = gpiochip_get_data(chip);
631 struct irq_fwspec *fwspec = &gfwspec->fwspec;
633 fwspec->fwnode = chip->irq.parent_domain->fwnode;
634 fwspec->param_count = 3;
635 fwspec->param[0] = gpio->soc->instance;
636 fwspec->param[1] = parent_hwirq;
637 fwspec->param[2] = parent_type;
642 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
645 unsigned int *parent_hwirq,
646 unsigned int *parent_type)
648 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
654 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
657 struct tegra_gpio *gpio = gpiochip_get_data(chip);
660 for (i = 0; i < gpio->soc->num_ports; i++) {
661 if (offset < gpio->soc->ports[i].pins)
664 offset -= gpio->soc->ports[i].pins;
667 return offset + i * 8;
670 static const struct of_device_id tegra186_pmc_of_match[] = {
671 { .compatible = "nvidia,tegra186-pmc" },
672 { .compatible = "nvidia,tegra194-pmc" },
676 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
678 struct device *dev = gpio->gpio.parent;
682 for (i = 0; i < gpio->soc->num_ports; i++) {
683 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
684 unsigned int offset, p = port->port;
687 base = gpio->secure + port->bank * 0x1000 + 0x800;
689 value = readl(base + TEGRA186_GPIO_CTL_SCR);
692 * For controllers that haven't been locked down yet, make
693 * sure to program the default interrupt route mapping.
695 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
696 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
698 * On Tegra194 and later, each pin can be routed to one or more
701 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
702 dev_dbg(dev, "programming default interrupt routing for port %s\n",
705 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
708 * By default we only want to route GPIO pins to IRQ 0. This works
709 * only under the assumption that we're running as the host kernel
710 * and hence all GPIO pins are owned by Linux.
712 * For cases where Linux is the guest OS, the hypervisor will have
713 * to configure the interrupt routing and pass only the valid
714 * interrupts via device tree.
717 value = readl(base + offset);
718 value = BIT(port->pins) - 1;
719 writel(value, base + offset);
726 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
728 struct device *dev = gpio->gpio.parent;
730 if (gpio->num_irq > gpio->num_banks) {
731 if (gpio->num_irq % gpio->num_banks != 0)
735 if (gpio->num_irq < gpio->num_banks)
738 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
740 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
746 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
747 gpio->num_irq, gpio->num_banks);
751 static int tegra186_gpio_probe(struct platform_device *pdev)
753 unsigned int i, j, offset;
754 struct gpio_irq_chip *irq;
755 struct tegra_gpio *gpio;
756 struct device_node *np;
760 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
764 gpio->soc = device_get_match_data(&pdev->dev);
765 gpio->gpio.label = gpio->soc->name;
766 gpio->gpio.parent = &pdev->dev;
768 /* count the number of banks in the controller */
769 for (i = 0; i < gpio->soc->num_ports; i++)
770 if (gpio->soc->ports[i].bank > gpio->num_banks)
771 gpio->num_banks = gpio->soc->ports[i].bank;
775 /* get register apertures */
776 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
777 if (IS_ERR(gpio->secure)) {
778 gpio->secure = devm_platform_ioremap_resource(pdev, 0);
779 if (IS_ERR(gpio->secure))
780 return PTR_ERR(gpio->secure);
783 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
784 if (IS_ERR(gpio->base)) {
785 gpio->base = devm_platform_ioremap_resource(pdev, 1);
786 if (IS_ERR(gpio->base))
787 return PTR_ERR(gpio->base);
790 err = platform_irq_count(pdev);
796 err = tegra186_gpio_irqs_per_bank(gpio);
800 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
805 for (i = 0; i < gpio->num_irq; i++) {
806 err = platform_get_irq(pdev, i);
813 gpio->gpio.request = gpiochip_generic_request;
814 gpio->gpio.free = gpiochip_generic_free;
815 gpio->gpio.get_direction = tegra186_gpio_get_direction;
816 gpio->gpio.direction_input = tegra186_gpio_direction_input;
817 gpio->gpio.direction_output = tegra186_gpio_direction_output;
818 gpio->gpio.get = tegra186_gpio_get;
819 gpio->gpio.set = tegra186_gpio_set;
820 gpio->gpio.set_config = tegra186_gpio_set_config;
821 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
822 if (gpio->soc->has_gte) {
823 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
824 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
827 gpio->gpio.base = -1;
829 for (i = 0; i < gpio->soc->num_ports; i++)
830 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
832 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
833 sizeof(*names), GFP_KERNEL);
837 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
838 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
841 for (j = 0; j < port->pins; j++) {
842 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
843 "P%s.%02x", port->name, j);
847 names[offset + j] = name;
850 offset += port->pins;
853 gpio->gpio.names = (const char * const *)names;
855 #if defined(CONFIG_OF_GPIO)
856 gpio->gpio.of_gpio_n_cells = 2;
857 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
858 #endif /* CONFIG_OF_GPIO */
860 irq = &gpio->gpio.irq;
861 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
862 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
863 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
864 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
865 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
866 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
867 irq->handler = handle_simple_irq;
868 irq->default_type = IRQ_TYPE_NONE;
869 irq->parent_handler = tegra186_gpio_irq;
870 irq->parent_handler_data = gpio;
871 irq->num_parents = gpio->num_irq;
874 * To simplify things, use a single interrupt per bank for now. Some
875 * chips support up to 8 interrupts per bank, which can be useful to
876 * distribute the load and decrease the processing latency for GPIOs
877 * but it also requires a more complicated interrupt routing than we
880 if (gpio->num_irqs_per_bank > 1) {
881 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
882 sizeof(*irq->parents), GFP_KERNEL);
886 for (i = 0; i < gpio->num_banks; i++)
887 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
889 irq->num_parents = gpio->num_banks;
891 irq->num_parents = gpio->num_irq;
892 irq->parents = gpio->irq;
895 if (gpio->soc->num_irqs_per_bank > 1)
896 tegra186_gpio_init_route_mapping(gpio);
898 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
900 irq->parent_domain = irq_find_host(np);
903 if (!irq->parent_domain)
904 return -EPROBE_DEFER;
907 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
908 sizeof(*irq->map), GFP_KERNEL);
912 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
913 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
915 for (j = 0; j < port->pins; j++)
916 irq->map[offset + j] = irq->parents[port->bank];
918 offset += port->pins;
921 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
924 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
925 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
932 static const struct tegra_gpio_port tegra186_main_ports[] = {
933 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
934 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
935 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
936 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
937 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
938 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
939 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
940 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
941 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
942 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
943 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
944 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
945 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
946 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
947 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
948 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
949 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
950 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
951 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
952 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
953 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
954 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
955 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
958 static const struct tegra_gpio_soc tegra186_main_soc = {
959 .num_ports = ARRAY_SIZE(tegra186_main_ports),
960 .ports = tegra186_main_ports,
961 .name = "tegra186-gpio",
963 .num_irqs_per_bank = 1,
966 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
967 [TEGRA186_AON_GPIO_PORT_##_name] = { \
974 static const struct tegra_gpio_port tegra186_aon_ports[] = {
975 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
976 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
977 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
978 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
979 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
980 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
981 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
982 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
985 static const struct tegra_gpio_soc tegra186_aon_soc = {
986 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
987 .ports = tegra186_aon_ports,
988 .name = "tegra186-gpio-aon",
990 .num_irqs_per_bank = 1,
993 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
994 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
1001 static const struct tegra_gpio_port tegra194_main_ports[] = {
1002 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
1003 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
1004 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
1005 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
1006 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
1007 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
1008 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
1009 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
1010 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
1011 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
1012 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
1013 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
1014 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
1015 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
1016 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
1017 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
1018 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
1019 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
1020 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
1021 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
1022 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
1023 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
1024 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
1025 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
1026 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
1027 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
1028 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
1029 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
1032 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
1033 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
1034 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
1037 static const struct tegra_gpio_soc tegra194_main_soc = {
1038 .num_ports = ARRAY_SIZE(tegra194_main_ports),
1039 .ports = tegra194_main_ports,
1040 .name = "tegra194-gpio",
1042 .num_irqs_per_bank = 8,
1043 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
1044 .pin_ranges = tegra194_main_pin_ranges,
1045 .pinmux = "nvidia,tegra194-pinmux",
1048 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1049 [TEGRA194_AON_GPIO_PORT_##_name] = { \
1056 static const struct tegra_gpio_port tegra194_aon_ports[] = {
1057 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
1058 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
1059 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1060 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
1061 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
1064 static const struct tegra_gpio_soc tegra194_aon_soc = {
1065 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
1066 .ports = tegra194_aon_ports,
1067 .name = "tegra194-gpio-aon",
1069 .num_irqs_per_bank = 8,
1073 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1074 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
1081 static const struct tegra_gpio_port tegra234_main_ports[] = {
1082 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1083 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1084 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1085 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1086 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1087 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1088 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1089 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1090 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1091 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1092 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1093 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1094 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1095 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1096 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1097 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1098 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1099 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1100 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1101 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1102 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1103 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1104 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1105 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1106 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1109 static const struct tegra_gpio_soc tegra234_main_soc = {
1110 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1111 .ports = tegra234_main_ports,
1112 .name = "tegra234-gpio",
1114 .num_irqs_per_bank = 8,
1117 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1118 [TEGRA234_AON_GPIO_PORT_##_name] = { \
1125 static const struct tegra_gpio_port tegra234_aon_ports[] = {
1126 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1127 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1128 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1129 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1130 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1131 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1134 static const struct tegra_gpio_soc tegra234_aon_soc = {
1135 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1136 .ports = tegra234_aon_ports,
1137 .name = "tegra234-gpio-aon",
1139 .num_irqs_per_bank = 8,
1142 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1143 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
1150 static const struct tegra_gpio_port tegra241_main_ports[] = {
1151 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1152 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1153 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1154 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1155 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1156 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1157 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1158 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1159 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1160 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1161 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1164 static const struct tegra_gpio_soc tegra241_main_soc = {
1165 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1166 .ports = tegra241_main_ports,
1167 .name = "tegra241-gpio",
1169 .num_irqs_per_bank = 8,
1172 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1173 [TEGRA241_AON_GPIO_PORT_##_name] = { \
1180 static const struct tegra_gpio_port tegra241_aon_ports[] = {
1181 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1182 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1185 static const struct tegra_gpio_soc tegra241_aon_soc = {
1186 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1187 .ports = tegra241_aon_ports,
1188 .name = "tegra241-gpio-aon",
1190 .num_irqs_per_bank = 8,
1193 static const struct of_device_id tegra186_gpio_of_match[] = {
1195 .compatible = "nvidia,tegra186-gpio",
1196 .data = &tegra186_main_soc
1198 .compatible = "nvidia,tegra186-gpio-aon",
1199 .data = &tegra186_aon_soc
1201 .compatible = "nvidia,tegra194-gpio",
1202 .data = &tegra194_main_soc
1204 .compatible = "nvidia,tegra194-gpio-aon",
1205 .data = &tegra194_aon_soc
1207 .compatible = "nvidia,tegra234-gpio",
1208 .data = &tegra234_main_soc
1210 .compatible = "nvidia,tegra234-gpio-aon",
1211 .data = &tegra234_aon_soc
1216 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1218 static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1219 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1220 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1221 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1222 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1223 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1224 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1227 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1229 static struct platform_driver tegra186_gpio_driver = {
1231 .name = "tegra186-gpio",
1232 .of_match_table = tegra186_gpio_of_match,
1233 .acpi_match_table = tegra186_gpio_acpi_match,
1235 .probe = tegra186_gpio_probe,
1237 module_platform_driver(tegra186_gpio_driver);
1239 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1240 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1241 MODULE_LICENSE("GPL v2");